Delay compensation circuit and compensation method thereof

Abstract

The application provides a delay compensation circuit and a compensation method thereof, which are applied to an endoscope and comprise an image acquisition unit and an image processing unit, the image acquisition unit is connected with the image processing unit through a transmission line, the delay compensation circuit further comprises a delay timer, the image processing unit sends a clock signal CLK to the image acquisition unit, the image acquisition unit feeds back an analog image signal VOUT to the image processing unit, delay parameters of the delay timer are set based on delay data of the transmission line, and the delay timer delays the clock signal CLK or delays the analog image signal VOUT based on the delay parameters, so that the image acquisition unit and the image processing unit are synchronized in signals. The delay compensation circuit and the compensation method thereof can solve the problem that the image quality is affected due to the delay of the transmission line and optimize the image quality.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of endoscopes, and in particular to a delay compensation circuit for an endoscope and a compensation method thereof. BACKGROUND

[0002] An endoscope is a commonly used medical instrument, which is composed of a bendable part, a light source and a set of lenses. It is introduced into the human body through natural orifices or small incisions made by surgery, and can be used to directly observe changes in the relevant parts when introduced into the organ to be examined.

[0003] Due to the rapid development of endoscopes, the size of image sensors is becoming smaller to meet the needs of various surgical procedures and minimally invasive procedures. As the size gradually decreases, image sensors cannot integrate all components within the image sensor chip. For example, some image sensors do not integrate analog-to-digital converters and other components, but are separated into two chips and connected through a cable, which increases the length of signal transmission and causes signal delay, thereby affecting image quality. The quality of the image directly affects the use effect of the endoscope.

[0004] Therefore, it is necessary to provide a delay compensation circuit for an endoscope and a compensation method thereof to solve the above problems. SUMMARY

[0005] The purpose of the present application is to provide a delay compensation circuit that can solve the problem of affecting image quality due to transmission line delay and optimize image quality.

[0006] To achieve the above purpose, the present application provides a delay compensation circuit applied to an endoscope, which comprises an image acquisition unit and an image processing unit, the image acquisition unit is connected with the image processing unit through a transmission line, the delay compensation circuit further comprises a delay timer, the image processing unit sends a clock signal CLK to the image acquisition unit, the image acquisition unit feeds back an analog image signal VOUT to the image processing unit, the delay parameter of the delay timer is set based on the delay data of the transmission line, and the delay timer delays the clock signal CLK or the analog image signal VOUT based on the delay parameter, so that the image acquisition unit and the image processing unit are synchronized.

[0007] As a further improvement of the present application, the clock signal CLK is delayed by the delay of the delay device and output as a delayed clock signal CLK1, the image acquisition unit receives the delayed clock signal CLK1 and outputs a timing-synchronized synchronous analog image signal VOUT1, the synchronous analog image signal VOUT1 is delayed by the delay of the transmission line and output as a line-delayed analog image signal VOUT2, and the line-delayed analog image signal VOUT2 is synchronized with the clock signal CLK.

[0008] As a further improvement of the present application, the clock signal CLK is delayed by the delay of the transmission line and output as a line-delayed clock signal CLK2, the image processing unit receives the line-delayed clock signal CLK2 and outputs a timing-synchronized synchronous analog image signal VOUT3, the synchronous analog image signal VOUT3 is delayed by the delay of the transmission line and output as a second line-delayed analog image signal VOUT4, the second line-delayed analog image signal VOUT4 is further delayed by the delay of the delay device and output as a delayed analog image signal VOUT5, and the delayed analog image signal VOUT5 is synchronized with the clock signal CLK.

[0009] As a further improvement of the present application, the delay device is arranged on the transmission line, or the delay device is integrated on the image acquisition unit or the image processing unit.

[0010] As a further improvement of the present application, the delay device is a single-chip microcomputer which increases the delay by the working clock.

[0011] As a further improvement of the present application, the delay device is a delay-adjustable flip-flop.

[0012] Another object of the present application is to provide a delay compensation method applied to the above-mentioned delay compensation circuit.

[0013] To achieve the above object, the present application provides a delay compensation method applied to the above-mentioned delay compensation circuit, which comprises the following steps:

[0014] S1: calculating or measuring the delay data of the transmission line;

[0015] S2: calculating and setting the delay parameter of the delay device based on the delay data of the transmission line and the period of the clock signal CLK / the analog image signal VOUT;

[0016] S3: comparing whether the image acquisition unit and the image processing unit are signal-synchronized;

[0017] S4: If the image acquisition unit and the image processing unit are not synchronized, adjust the delay parameter of the delay timer until the signals are synchronized.

[0018] As a further improvement of the present application, the method for measuring the delay data of the transmission line in step S1 comprises comparing the rising or falling edges of the clock signal CLK or the analog image signal VOUT.

[0019] As a further improvement of the present application, the measuring tool for measuring the delay data of the transmission line in step S1 comprises an oscilloscope, an FPGA, a single-chip microcomputer, or a TDC chip.

[0020] As a further improvement of the present application, the method for comparing whether the image acquisition unit and the image processing unit are synchronized in step S3 comprises checking the image quality effect of the endoscope, or measuring whether the signal delay of the clock signal CLK and the analog image signal VOUT meets the acquisition timing.

[0021] The present application has the beneficial effect that the delay compensation circuit and the compensation method thereof can compensate for the delay caused by the transmission line by setting a delay timer between the image acquisition unit and the image processing unit connected by the transmission line, and setting the delay parameter of the delay timer through the delay data of the transmission line, so as to realize the signal synchronization of the image acquisition unit and the image processing unit without phase difference, and solve the image problems such as stripes, waves, color abnormalities, etc. caused by delay, and optimize the image quality. BRIEF DESCRIPTION OF DRAWINGS

[0022] Figure 1 is a structural block diagram of the delay compensation circuit of the preferred embodiment of the present application.

[0023] Figure 2 is a timing diagram of the image acquisition unit and the image processing unit of an embodiment of the present application.

[0024] Figure 3 is a timing diagram of the image acquisition unit and the image processing unit of another embodiment of the present application.

[0025] Figure 4 is a delay diagram of the delay timer being a monostable trigger of the present application.

[0026] Figure 5 is a delay diagram of the delay timer being a bistable trigger of the present application.

[0027] Figure 6 is a flowchart of the delay compensation method of the present application. DETAILED DESCRIPTION

[0028] In order to make the objects, technical solutions and advantages of the present application clearer, the present application will be described in detail below with reference to the drawings and specific embodiments.

[0029] It should be noted that, in order not to obscure the present application due to unnecessary details, only structures and / or processing steps closely related to the solutions of the present application are shown in the drawings, and other details not closely related to the present application are omitted.

[0030] In addition, it should also be noted that the term "comprise", "include" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such a process, method, article or device.

[0031] Please refer to Figures 1-5 As shown in the drawings, the present application provides a delay compensation circuit, which is applied to an endoscope, especially to a discrete image sensor arranged in the endoscope, for compensating the delay of the discrete image sensor caused by the transmission line 30, so as to avoid the influence of signal delay on image quality.

[0032] Please refer to Figure 1 As shown in the drawings, the delay compensation circuit includes an image acquisition unit 10 and an image processing unit 20 connected by a transmission line 30, and a delay timer 40 arranged between the image acquisition unit 10 and the image processing unit 20. The image acquisition unit 10 includes a photoelectric converter and other modules, the image processing unit 20 includes an analog-to-digital converter (ADC) and other modules, and the image acquisition unit 10 and the image processing unit 20 are connected by the transmission line 30, and the delay timer 40 is arranged on the transmission line 30. Among them, the image acquisition unit 10 is used to convert the optical signal into an analog electrical signal, and the analog electrical signal is transmitted to the image processing unit 20 through the transmission line 30 and enters the analog-to-digital converter for analog-to-digital conversion. By increasing the delay timer 40 between the image processing chip and the image acquisition chip, the delay caused by the transmission line 30 is compensated, and the image quality is improved.

[0033] It should be noted that, in the present embodiment, the delay timer 40 is arranged on the transmission line 30, and in other embodiments, the delay timer 40 is also integrated on the image acquisition unit 10 or the image processing unit 20, which is not limited by the present application.

[0034] The transmission line 30 at least includes a clock signal CLK, an analog image signal VOUT and other signals. The clock signal CLK is sent from the image processing unit 20 to the image acquisition unit 10, and is used for timing synchronization between the image processing unit 20 and the image acquisition unit 10, so as to ensure that the image acquisition unit 10 and the image processing unit 20 work at the same frequency. The analog image signal VOUT is the analog image data output by the image acquisition unit 10, and is sent from the image acquisition unit 10 to the image processing unit 20. When the transmission line 30 is relatively long, for example, when the transmission line 30 is longer than 1 m, the delay of the transmission of the clock signal CLK and the analog image signal VOUT will exceed (1 m+1 m) / (2x10 8 m / s) = 30 ns. In addition, since the image acquisition unit 10 uses a line scanning mode to acquire data, i.e., the data of the same line is sent continuously, the delay of the transmission line 30 will cause the analog image signal VOUT and the clock signal CLK, which should be synchronized, to have a phase difference (see Figure 2 ), so that the analog-to-digital conversion of the image processing unit 20 is offset, and the image quality is poor.

[0035] By adding a delay timer 40 between the image processing chip and the image acquisition chip, setting the delay parameter of the delay timer 40 based on the delay data of the transmission line 30, and delaying the clock signal CLK or the analog image signal VOUT based on the delay parameter, the image acquisition unit 10 and the image processing unit 20 are synchronized, and there is no phase difference, so that the image problems caused by the delay, such as image stripes, waves, color abnormalities, etc., are solved, and the image quality is optimized.

[0036] Please refer to Figure 2 In an embodiment of the present application, the synchronization between the analog image signal VOUT and the clock signal CLK is achieved by delaying the clock signal CLK.

[0037] In particular, the delay data Td of the transmission line 30 is calculated or measured by a delay measurement tool. The delay parameter TC of the delay timer 40 is set based on the delay data Td of the transmission line 30. When the image processing unit 20 sends the clock signal CLK to the image acquisition unit 10, the clock signal CLK is delayed by the delay timer 40 and output as a delayed clock signal CLK1, i.e. the clock signal CLK is delayed by the delay timer 40 and reaches the image acquisition unit 10 as the delayed clock signal CLK1. The image acquisition unit 10 outputs a time-synchronized synchronized analog image signal VOUT1 after receiving the delayed clock signal CLK1, and the synchronized analog image signal VOUT1 is output as a line-delayed analog image signal VOUT2 after being delayed by the transmission line 30. That is, the synchronized analog image signal VOUT1 and the line-delayed analog image signal VOUT2 are both output signals generated based on the delayed clock signal CLK1. Since the sum of the delay data Td of the transmission line 30 and the delay parameter TC of the delay timer 40 is at least one period of the clock signal CLK, the line-delayed analog image signal VOUT2 is finally synchronized with the clock signal CLK after being delayed by the delay timer 40 and the transmission line 30, and the delay compensation is achieved.

[0038] Referring to Figure 3 In another embodiment of the present application, the synchronization of the analog image signal VOUT and the clock signal CLK is achieved by delaying the analog image signal VOUT, as shown in the figure.

[0039] In particular, the delay of the transmission line 30 is calculated or measured by a delay measurement tool. The delay parameter TC of the delay timer 40 is set based on the delay data Td of the transmission line 30. When the image processing unit 20 sends the clock signal CLK to the image acquisition unit 10, the clock signal CLK is delayed by the transmission line 30 and output as a line-delayed clock signal CLK2. That is, the clock signal CLK is delayed by the transmission line 30 and reaches the image acquisition unit 10 as the line-delayed clock signal CLK2. The image processing unit 20 outputs a time-synchronized synchronized analog image signal VOUT3 after receiving the line-delayed clock signal CLK2, and the synchronized analog image signal VOUT3 is output as a secondary line-delayed analog image signal VOUT4 after being delayed by the transmission line 30, and the secondary line-delayed analog image signal VOUT4 is output as a delayed analog image signal VOUT5 after being delayed by the delay timer 40. The delayed analog image signal VOUT5 is synchronized with the clock signal CLK, and the delay compensation is achieved.

[0040] Further, in the present embodiment, the delay timer 40 can be implemented by increasing the delay time of the working clock of a single-chip microcomputer. Alternatively, the delay timer 40 can be implemented by using the main frequency clock of an FPGA to generate the required delay time. Of course, in other embodiments, the delay timer 40 can also be a delay-adjustable flip-flop. For example, the flip-flop can be a monostable flip-flop or a bistable flip-flop or other delay-adjustable flip-flop.

[0041] Referring to Figure 4 When the delay timer 40 is a monostable flip-flop, as shown in the figure, when the rising edge signal is received at the input end (INPUT), a pulse with adjustable width is output at the output end (OUTPUT), and the adjustment of the delay parameter is realized by adjusting the width of the pulse.

[0042] Referring to Figure 5 When the delay timer 40 is a bistable flip-flop, as shown in the figure, the clock signal CLK enters the first monostable flip-flop to generate a forward pulse OUTPUT1 with adjustable pulse width, and the forward pulse OUTPUT1 enters the second monostable flip-flop after passing through the NOT gate to generate a forward pulse OUTPUT2 with adjustable pulse width, so as to realize the setting of the delay parameter.

[0043] Referring to Figure 6 and in combination with Figures 2-3 The present application provides a delay compensation method applied to the above-mentioned delay compensation circuit, and the delay compensation method comprises the following steps:

[0044] S1: calculating or measuring the delay data of the transmission line 30;

[0045] S2: based on the delay data of the transmission line 30 and the period of the clock signal CLK / the analog image signal VOUT, calculating and setting the delay parameter of the delay timer 40;

[0046] S3: comparing whether the image acquisition unit 10 and the image processing unit 20 are signal-synchronized;

[0047] S4: if the image acquisition unit 10 and the image processing unit 20 are not signal-synchronized, adjusting the delay parameter of the delay timer 40 until signal-synchronization.

[0048] Specifically, the delay data of the transmission line 30 in step S1 can be obtained by calculation. The transmission speed of an electric signal on an electronic line is about V=2x10 8 m / s, and the delay data Td=L / V of the transmission line 30 can be calculated according to the length L of the transmission line 30.

[0049] Alternatively, the delay data of the transmission line 30 in step S1 can be obtained by measurement. The measurement method includes measuring the time difference of the clock signal CLK and the delay of the analog image signal VOUT using a measurement tool. At this time, the rising edge or the falling edge or other valid data of the clock signal CLK or the analog image signal VOUT can be compared.

[0050] Further, the measurement tool of the delay data of the transmission line 30 in step S1 includes but is not limited to an oscilloscope, an FPGA, a single-chip microcomputer, and a TDC chip. By measuring the line delay data Td between the analog image signal VOUT and the clock signal CLK, it can be known that Td = cd = de (see Figure 3

[0051] Please refer to Figure 2 Fig. 2, in step S2, based on the delay data Td of the transmission line 30 and the period T of the clock signal CLK, the method for calculating and setting the delay parameter of the delay device 40 is as follows: since the clock signal CLK is a square wave signal with a frequency of F, its period T = 1 / F, then the delay parameter TC of the delay device 40 = ab = T-bc = T-cd = T-de.

[0052] When the delay device 40 is not added and the delay parameter is not set, the delay of the clock signal CLK through the transmission line 30 becomes the line delay clock signal CLK3, at this time, the image acquisition unit 10 receives the line delay clock signal CLK3 and outputs the delay synchronization analog image signal VOUT6 which is synchronous with the timing thereof, the delay synchronization analog image signal VOUT6 is delayed through the transmission line 30 and outputs the secondary line delay analog image signal VOUT7, the secondary line delay analog image signal VOUT7 has a phase difference with the clock signal CLK, which affects the image quality.

[0053] When the delay device 40 is added and the delay parameter TC = ab is set, the first pulse of the clock signal CLK is delayed through the delay device 40 from a to b (CLK1), CLK1 is a delayed clock signal. At this time, the image acquisition unit 10 receives the delayed clock signal CLK1 and outputs the synchronization analog image signal VOUT1 which is synchronous with the timing thereof, the synchronization analog image signal VOUT1 is delayed through the transmission line 30 (Td = bc) and outputs the line delay analog image signal VOUT2, finally, the line delay analog image signal VOUT2 is synchronous with the clock signal CLK, realizing delay compensation, no phase difference, and improving the image quality.

[0054] Please refer to Figure 3 Fig. 2, in step S2, based on the delay data Td of the transmission line 30 and the period T of the clock signal CLK, the method for calculating and setting the delay parameter of the delay device 40 is as follows: ​

[0055] Since the analog image signal VOUT refers to a digital signal or an analog and digital mixed signal (analog-digital mixed), and the analog image signal VOUT is also a signal with rising and falling edges, the method for setting the delay parameter TC of the delay timer 40 is similar to the method for setting the delay parameter TC of the delay timer 40 on the clock signal CLK, the delay parameter TC = ab = T-bc = T-cd = T-de.

[0056] Please refer to Figure 3 As shown, the definition "D" represents the rising edge of the analog image signal VOUT. When the image processing unit 20 sends the clock signal CLK to the image acquisition unit 10, the clock signal CLK is delayed (Td = de) through the transmission line 30 and output as a line-delayed clock signal CLK2. That is, the clock signal CLK reaches the image acquisition unit 10 as a line-delayed clock signal CLK2 after being delayed through the transmission line 30. After the image processing unit 20 receives the line-delayed clock signal CLK2, a timing-synchronized synchronous analog image signal VOUT3 is output, which should be a second line-delayed analog image signal VOUT4 when it reaches the image processing unit 20 after being delayed (Td = de) through the transmission line 30. The second line-delayed analog image signal VOUT4 then enters the delay timer 40 and outputs a delayed analog image signal VOUT5 after being delayed through the delay timer 40. That is, the delayed analog image signal VOUT5 is delayed by ef based on the line-delayed analog image signal VOUT4, so that the delayed analog image signal VOUT5 is synchronized with the clock signal CLK, achieving delay compensation.

[0057] Further, the method for comparing whether the image acquisition unit 10 and the image processing unit 20 are signal-synchronized in step S3 includes checking the image quality effect of the endoscope, or measuring whether the signal delay of the clock signal CLK and the analog image signal VOUT meets the acquisition timing.

[0058] In step S4, if the image acquisition unit 10 and the image processing unit 20 are not signal-synchronized, the delay parameter of the delay timer 40 is fine-tuned until the analog image signal VOUT and the clock signal CLK are synchronized.

[0059] Through the above delay compensation method, the delay difference between the analog image signal VOUT and the clock signal CLK can be adaptively measured, and the delay parameter of the delay timer 40 can be dynamically adjusted, so that the batch-produced discrete image sensor no longer has strict requirements for the consistency of the transmission line 30, and can be adjusted and calibrated in an adaptive manner, reducing the production consistency requirement and process difficulty, and improving the production efficiency.

[0060] In summary, the delay compensation circuit and the compensation method thereof can set the delay timer 40 between the image acquisition unit 10 and the image processing unit 20 connected by the transmission line 30, and set the delay parameter of the delay timer 40 through the delay data of the transmission line 30, so as to compensate the delay caused by the transmission line 30, realize the signal synchronization of the image acquisition unit 10 and the image processing unit 20, have no phase difference, solve the image problems such as image stripes, corrugations, color abnormalities and the like caused by the delay, and optimize the image quality.

[0061] The above examples are only used to illustrate the technical solutions of the present application and not limit the present application. Although the present application has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present application can be modified or replaced equivalently without departing from the spirit and scope of the technical solutions of the present application.

Claims

1. A delay compensation circuit, applied to an endoscope, characterized in that: The system includes an image acquisition unit and an image processing unit, which are connected via a transmission line. The delay compensation circuit also includes a delay unit. The image processing unit sends a clock signal CLK to the image acquisition unit and feeds back an analog image signal VOUT to the image processing unit. The delay parameters of the delay unit are set based on the delay data of the transmission line. The delay unit delays either the clock signal CLK or the analog image signal VOUT based on the delay parameters, thereby synchronizing the signals of the image acquisition unit and the image processing unit. The delay unit is a delay-adjustable trigger, and the delay parameters are dynamically set by adaptively measuring the delay difference between the analog image signal VOUT and the clock signal CLK.

2. The delay compensation circuit according to claim 1, characterized in that: The clock signal CLK is delayed by the delay unit and output as a delayed clock signal CLK1. After receiving the delayed clock signal CLK1, the image acquisition unit outputs a timing-synchronized analog image signal VOUT1. The synchronous analog image signal VOUT1 is delayed by the transmission line and outputs a line-delayed analog image signal VOUT2. The line-delayed analog image signal VOUT2 is synchronized with the clock signal CLK.

3. The delay compensation circuit according to claim 1, characterized in that: The clock signal CLK is delayed by the transmission line to output a line-delayed clock signal CLK2. After receiving the line-delayed clock signal CLK2, the image processing unit outputs a timing-synchronized analog image signal VOUT3. The synchronous analog image signal VOUT3 is delayed by the transmission line to output a secondary line-delayed analog image signal VOUT4. The secondary line-delayed analog image signal VOUT4 is further delayed by the delay unit to output a delayed analog image signal VOUT5. The delayed analog image signal VOUT5 is synchronized with the clock signal CLK.

4. The delay compensation circuit according to any one of claims 1 to 3, characterized in that: The delay device is disposed on the transmission line, or the delay device is integrated into the image acquisition unit or the image processing unit.

5. A delay compensation method, characterized in that: The delay compensation method, applied to the delay compensation circuit according to any one of claims 1 to 4, comprises the following steps: S1: Calculate or measure the delay data of the transmission line; S2: Based on the delay data of the transmission line and the period of the clock signal CLK / the analog image signal VOUT, calculate and set the delay parameters of the delay device; S3: Compare whether the image acquisition unit and the image processing unit are synchronized; S4: If the signals of the image acquisition unit and the image processing unit are not synchronized, adjust the delay parameter of the delay unit until the signals are synchronized.

6. The delay compensation method according to claim 5, characterized in that: The method for measuring the delay data of the transmission line in step S1 includes comparing the rising or falling edge of the clock signal CLK or the analog image signal VOUT.

7. The delay compensation method according to claim 5, characterized in that: The measurement tools for the delay data of the transmission line in step S1 include oscilloscopes, FPGAs, microcontrollers, and TDC chips.

8. The delay compensation method according to claim 5, characterized in that: The method for comparing whether the image acquisition unit and the image processing unit are signal synchronized in step S3 includes: checking the image quality of the endoscope, or measuring whether the signal delay of the clock signal CLK and the analog image signal VOUT conforms to the acquisition timing.

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