A SoC chip multi-version verification method, device and equipment

Abstract

A method, device and equipment for multi-version verification of SoC chips, the method comprising: S1. setting random variables; S2. constraining the random variables, and selecting a register of the design to be tested according to the value of the random variables; S3. passing the value of the random variables to the top level of verification, and connecting different interfaces of the design to be tested according to the value of the random variables and the constraint conditions; S4. delivering the stimulus to the register of the design to be tested through the corresponding interface according to the value of the random variables. The method, device and equipment for multi-version verification of SoC chips provided by the present invention, by setting random variables, implement multiple versions of testing according to different values ​​of the random variables, and the verification platform constructed only needs to be compiled once to implement verification of functions for different versions of the SoC chip, effectively solving the problem that the verification platform construction of existing multi-version SoC chips needs to be constructed for multiple platforms for verification separately, which is not flexible and inconvenient to maintain.

Description

Technical Field

[0001] The present invention belongs to the field of chip verification technology, and specifically relates to a multi-version verification method, device and equipment for a SoC chip. Background Art

[0002] With the development of large-scale integrated circuits (SOCs), SoCs are integrating an increasing number of IP modules, leading to increasing chip complexity and integration, and increasingly stringent verification requirements. Currently, different versions of SoC chips are often implemented during design. This means that while the chip design may have the same external pinout, the pin functionality, interface protocols, and internal functions may differ. Verification requires the creation of separate verification platforms based on the different functional versions. This inflexible and inconvenient verification platform setup is difficult to maintain. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a SoC chip multi-version verification method, a SoC chip multi-version verification device and a SoC chip multi-version verification equipment to address the problem that the existing multi-version SoC chip verification requires the construction of multiple platforms for verification separately, which is not flexible enough and inconvenient to maintain.

[0004] In a first aspect, the present invention provides a multi-version verification method for a SoC chip, comprising the following steps:

[0005] S1. Set random variables;

[0006] S2 constrains the random variable and selects the design register to be tested according to the value of the random variable;

[0007] S3. The value of the random variable is passed to the verification top layer, and the different interfaces of the design to be tested are connected according to the value of the random variable and the constraints;

[0008] S4. According to the value of the random variable, the stimulus is transmitted to the register of the design to be tested through the corresponding interface.

[0009] As a further improvement of the present invention, before step S1, the step further includes establishing a register model, wherein the register model includes a verification code corresponding to the design to be tested, and the verification code contains all information of the registers of the design to be tested.

[0010] As a further improvement of the present invention, step S3 further includes:

[0011] Drive the SoC chip pins to select the corresponding verification version according to the value of the random variable;

[0012] According to the value of the random variable, the verification environment is driven to select the corresponding interface component to connect with the chip pin.

[0013] As a further improvement of the present invention, step S4 further includes:

[0014] Selecting a corresponding interface component according to the value of the random variable, the interface component sends the stimulus to the corresponding SoC chip pin in the timing format of the corresponding interface of the SoC chip;

[0015] Send stimulus from the corresponding SoC chip pin to the corresponding interface inside the SoC chip;

[0016] The stimulus is sent to the corresponding register of the design under test from the corresponding interface inside the SoC chip to perform write and read operations on the register of the design under test.

[0017] As a further improvement of the present invention, fun_sel is used to represent the random variable. When fun_sel=0, the first verification version interface is selected to access the design register to be tested, the register model is connected to the first interface component corresponding to the first verification version interface, and the first interface component is connected to the first verification version interface; when fun_sel=1, the second verification version interface is selected to access the design register to be tested, the register model is connected to the second interface component corresponding to the second verification version interface, and the second interface component is connected to the second verification version interface.

[0018] As a further improvement of the present invention, the first verification version interface and the second verification version interface are any interface, including but not limited to a JTAG interface, a SW interface, an I2C interface, an AXI interface, an AHB interface, etc.

[0019] As a further improvement of the present invention, the first verification version interface and the second verification version interface are of different interface types.

[0020] In a second aspect, the present invention further provides a SoC chip multi-version verification device, comprising: a setting module for setting random variables;

[0021] A constraint module, configured to constrain the random variable and select a design register to be tested according to the value of the random variable;

[0022] A connection module, used to pass the value of the random variable to the verification top layer and connect different interfaces of the design to be tested according to the value of the random variable and the constraint conditions;

[0023] The sending module is used to transmit the stimulus to the register of the design to be tested through the corresponding interface according to the value of the random variable.

[0024] In the third aspect, the present invention also provides a SoC chip multi-version verification device, which includes: at least two excitation models, each excitation model corresponding to an interface; the at least two excitation models send excitation according to the corresponding interface protocol, so that the SoC chip multi-version verification device executes the SoC chip multi-version verification method described in any of the above embodiments.

[0025] The present invention provides a multi-version verification method for SoC chips. By setting random variables, the method implements the testing of multiple functional versions of the SoC chip according to different values ​​of the random variables. The verification platform only needs to be compiled once to verify the functions of different versions of the SoC chip. This effectively solves the problem that the verification platform construction of existing multi-version SoC chip verification requires the construction of multiple platforms for separate verification, which is not flexible and inconvenient to maintain.

[0026] The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only part of the embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0028] Figure 1 A flow chart of a multi-version verification method for a SoC chip provided by an embodiment of the present invention;

[0029] Figure 2 A schematic diagram of a multi-version verification interface connection for a SoC chip provided by an embodiment of the present invention;

[0030] Figure 3 A structural block diagram of a multi-version verification device for a SoC chip provided by an embodiment of the present invention;

[0031] Figure 4 A schematic diagram of the structure of a multi-version verification device for a SoC chip provided by an embodiment of the present invention.

[0032] The meanings of the reference numerals in the accompanying drawings are:

[0033] 200-design under test; 201-first verification version interface; 202-second verification version interface; 203-first interface component; 204-second interface component; 205-design under test register; 301-setting module; 302-constraint module; 303-connection module; 304-sending module; 401-stimulus model 1; 402-stimulus model 2. DETAILED DESCRIPTION

[0034] In order to make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in combination with the drawings and specific embodiments in the embodiments of the present invention, and the present invention will be further described in detail. It should be understood that the embodiments described herein are only used to explain the present invention and are part of the embodiments of the present invention, not all of the embodiments. That is, the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. The implementation method covers the features of multiple specific embodiments and the method steps and their sequence for constructing and operating these specific embodiments. However, other specific embodiments can also be used to achieve the same or equal functions and step sequences. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0035] First, let’s explain the terms involved in this application:

[0036] SoC chip: refers to System on Chip, also known as System on Chip, which is an integrated circuit with a dedicated purpose. It contains all the contents of a complete system and embedded software. The hardware components include: core, registers, peripheral interfaces, buses, interrupt modules, clock modules, etc.

[0037] Design under test: referred to as (DUT), the design under test in this solution is the SoC chip under test.

[0038] Interface: refers to the communication interface, which is a set of standard-defined interface protocols designed to enable data communication between the host and slave devices.

[0039] Different versions are often implemented in the current SoC chip design process. That is, the chip design has the same external pins, but there are different versions in terms of pin functions, interface protocols, and internal functions. For verification, different versions of verification platforms need to be established according to different functional versions for separate verification. This verification platform is not flexible enough and is not convenient to maintain.

[0040] In order to solve the problem that the existing multi-version SoC chip verification requires the construction of multiple platforms for verification, which is not flexible and inconvenient to maintain, an embodiment of the present invention provides a multi-version SoC chip verification method. Figure 1 A flow chart of a multi-version verification method for a SoC chip provided by an embodiment of the present invention is shown as follows: Figure 1 As shown, this embodiment provides a multi-version verification method for a SoC chip, including the following steps:

[0041] S1. Set up random variables.

[0042] The present embodiment provides a multi-version verification method for a SoC chip, which realizes verification of functions of different versions of the SoC chip by setting random variables to distinguish different functional versions of the SoC chip to be verified. Based on this, the setting of the random variables matches the number of functional versions of the SoC chip to be verified. Preferably, before step S1, it also includes setting a verification environment based on the UVM platform, the verification environment including a register model and interface components of different versions of the design to be tested. Specifically, the register model is a verification code written corresponding to the register of the design to be tested, and the verification code contains various information of the register of the design to be tested. The interface component is a verification code corresponding to the interface of different versions of the design to be tested. It can send incentives for the interface protocols of the different versions of the interface of the design to be tested, and cooperate with the register model to send incentives for the register of the design to be tested.

[0043] It can be understood that by setting random variables to distinguish different functional versions of the SoC chip to be verified, the constructed verification platform only needs to be compiled once to verify the functions of different versions of the SoC chip.

[0044] S2. Constrain the random variable and select the design register to be tested according to the value of the random variable.

[0045] As an embodiment of the present invention, for different functional versions of the SoC chip, the design to be tested includes multiple interfaces with different protocols, all of which can access the internal registers of the chip. Based on this, the random variable is constrained, and the design register to be tested is selected according to the value of the random variable. Specifically, if there are two functional versions of the SoC chip that need to be verified, the values ​​of the random variable can be set to 0 and 1. When the value of the random variable is 0, it means that the external chip can only access the design register to be tested through the version 0 interface; when the value of the random variable is 1, it means that the external chip can only access the design register to be tested through the version 1 interface. If there are three functional versions of the SoC chip that need to be verified, the values ​​of the random variable can be set to 0, 1, and 2. When the value of the random variable is 0, it means that the external chip can only access the design register to be tested through the version 0 interface; when the value of the random variable is 1, it means that the external chip can only access the design register to be tested through the version 1 interface; when the value of the random variable is 2, it means that the external chip can only access the design register to be tested through the version 2 interface, and so on.

[0046] By adopting this solution, the functions of different versions of SoC chips can be verified according to the different values ​​of random variables, which effectively solves the problem that the existing multi-version SoC chip verification requires the construction of multiple platforms for separate verification, and the verification platform construction is not flexible and inconvenient to maintain.

[0047] S3. Pass the value of the random variable to the top level of verification, and connect different interfaces of the design to be tested according to the value of the random variable and the constraint conditions.

[0048] Preferably, step S3 further includes: driving the SoC chip pins to select the corresponding verification version based on the value of the random variable; and driving the verification environment to select the corresponding interface component to connect to the chip pins based on the value of the random variable. Specifically, as one embodiment of the present invention, when verifying the function of the SoC chip, the value of the random variable that distinguishes the different functional versions of the SoC chip is first passed to the top verification layer. At the top verification layer, the different pins and interfaces of the design under test are connected based on the value of the random variable that distinguishes the functional versions. The value passed by the random variable drives the chip pins, allowing the chip to select the corresponding functional version. On the other hand, the value passed by the random variable also allows the verification environment to select the corresponding interface component to connect to the chip pins. Assume that the chip's internal registers can be accessed through pins A and B of the chip, with A being the input and B being the output. When the random variable takes the value of 0, the interface component of control version 0 is connected to pins A and B; when the random variable takes the value of 1, the interface component of control version 1 is connected to pins A and B.

[0049] S4. According to the value of the random variable, the stimulus is transmitted to the register of the design to be tested through the corresponding interface.

[0050] Preferably, step S4 also includes: selecting a corresponding interface component according to the value of the random variable, the interface component sending the stimulus to the corresponding SoC chip pin in the timing format of the corresponding interface of the SoC chip; sending the stimulus from the corresponding SoC chip pin to the corresponding interface inside the SoC chip; sending the stimulus from the corresponding interface inside the SoC chip to the corresponding design register to be tested, thereby realizing the write and read operations of the design register to be tested. Specifically, as an embodiment of the present invention, if version 0 is required for testing, the value of the random variable is constrained to be 0 in the test case, the write and read stimulus is passed to the interface component corresponding to version 0, and then the stimulus is sent to the inside of the chip in the timing format of interface 0, thereby realizing the write and read operations of the register. Specifically, the stimulus sent by the interface component of version 0 first reaches the chip pin, then from the chip pin to the corresponding interface 0 inside the chip, and then from the interface 0 inside the chip to the design register to be tested. If version 1 is required for testing, constrain the value of the random variable to 1 in the test case, pass the write and read stimuli to the interface component of version 1, and then send the stimuli to the inside of the chip in the timing format of interface 1, so as to realize the write and read operations of the register. Specifically, the stimuli sent by the interface component corresponding to version 1 first reach the chip pin, then from the chip pin to the corresponding interface 1 inside the chip, and then from interface 1 inside the chip to the design register to be tested.

[0051] The present invention provides a multi-version verification method for SoC chips. By setting random variables, the functional tests of multiple versions of the SoC chip are implemented according to different values ​​of the random variables. The constructed verification platform only needs to be compiled once to verify the functions of different versions of the SoC chip. This effectively solves the problem that when verifying the functions of different versions of multi-version SoC chips, multiple platforms need to be built to verify the functions of different versions of the SoC chip separately, which exists in the existing problem that the verification platform construction is not flexible and inconvenient to maintain.

[0052] Figure 2 This is a schematic diagram of a multi-version verification interface connection for a SoC chip provided by the present invention, such as Figure 2 As shown, an embodiment of the present invention also provides a multi-version verification system for a SoC chip, which includes: a first verification version interface 201 and a second verification version interface 202. The first verification version interface 201 and the second verification version interface 202 have different interface protocols, but both can access the internal registers of the SoC chip, that is, the design register 205 to be tested here, but only one of the two version interfaces can be connected to the SoC chip pin, that is, only one interface can be used from the inside of the SoC chip; a register model, which is a verification code corresponding to the design to be tested 200, and the verification code contains all information of the design register 205 to be tested; a first interface component 203, which is a verification code corresponding to the first verification version interface 201, and is used to send stimulus for the interface protocol of the first verification version interface 201; a second interface component 204, which is a verification code corresponding to the second verification version interface 202, and is used to send stimulus for the interface protocol of the second verification version interface 202; and a random variable, which is used to select an interface for accessing the design register 205 to be tested. Preferably, the first interface component 203 and the second interface component 204 are further configured to cooperate with the register model to send stimulus to the design register under test 205 .

[0053] Please continue to refer to Figure 2As an embodiment of the present invention, fun_sel is used to represent the random variable, that is, fun_sel is used as a special pin of the SoC chip to distinguish the SoC chip version. It should be noted that the SoC chip version may be distinguished by multiple pins or according to the value of fun_sel or other methods. In this embodiment, the distinction is explained in terms of one pin. The principles of other situations are consistent with the scheme of this embodiment. Specifically, when fun_sel takes a value of 0, it means that the chip can only access the design register 205 to be tested through the first verification version interface 201 outside the chip, the register model is connected to the first interface component 203, and the first interface component 203 is connected to the first verification version interface 201. Further, when fun_sel takes a value of 1, it means that the chip can only access the design register to be tested through the second verification version interface 202 outside the chip, the register model is connected to the second interface component 204, and the second interface component 204 is connected to the second verification version interface 202.

[0054] As an embodiment of the present invention, specifically, assuming that the register model is reg_model, model is an instance of the register model, the first interface component 203 is if0_bus_env, and reg_env0 is used as an instance of the first interface component 203; the second interface component 204 is if1_bus_env, and reg_env1 is used as an instance of the second interface component 204. If fun_sel==0, then model is passed to the first interface component reg_env0 using uvm_config_db::set(), and reg_env0 obtains model using uvm_config_db::get(); if fun_sel==1, then model is passed to the second interface component reg_env1 using uvm_config_db::set(), and reg_env1 obtains model using uvm_config_db::get().

[0055] As an embodiment of the present invention, it should be noted that the value passed by the random variable fun_sel drives the chip pins on the one hand, allowing the chip to select the corresponding version, and on the other hand, the value passed by the random variable fun_sel also allows the verification environment to select the corresponding interface component to connect to the chip pins. Assume that the design register 205 to be tested can be accessed through the pins A and B of the chip, A is the input, and B is the output. When the random variable fun_sel is 0, bufif0 is used to control the first interface component 203 corresponding to the first verification version interface 201 to be connected to pins A and pin B; when fun_sel is 1, bufif1 is used to control the second interface component 204 corresponding to the second verification version interface 202 to be connected to pins A and pin B.

[0056] Preferably, if it is necessary to test the first version, the value of the random variable is constrained to 0 in the test case, and the write and read stimuli are passed to the first interface component 203 corresponding to the first version, and then the stimuli are sent to the chip in the timing format of the first verification version interface 201, thereby achieving the write and read operations of the design register 205 to be tested. Specifically, the stimuli sent by the first interface component 203 corresponding to the first version first reach the chip pins, then from the chip pins reach the corresponding first verification version interface 201 inside the chip, and then from the first verification version interface 201 inside the chip reach the design register 205 to be tested. If it is necessary to test the second version, the value of the random variable is constrained to 1 in the test case, and the write and read stimuli are passed to the second interface component 204 corresponding to the second version, and then the stimuli are sent to the chip in the timing format of the second verification version interface 202, thereby achieving the write and read operations of the design register 205 to be tested.

[0057] Specifically, as an embodiment of the present invention, assuming that a register inside the chip is SOC_REG0, the write stimulus format generated for register SOC_REG0 in the test case is this.model.SOC_REG0.write(status,wdata); the read stimulus format is this.model.SOC_REG0.read(status,rdata). If the first version needs to be tested, constrain fun_sel==0 in the test case. After the interface component is selected, the write and read stimuli generated will be transmitted to the first interface component. After the interface is selected, the first interface component 203 will send the stimulus to the inside of the chip in the timing format of the first verification version interface 201, thereby performing the write and read operations of the timing register. The data sent by the first interface component 203 reaches the chip pin, the stimulus reaches the first verification version interface 201 inside the chip from the chip pin, and the stimulus reaches the design register to be tested 205 from the first verification version interface 201 inside the chip. If you need to test the second version, constrain fun_sel==1 in the test case. The write and read stimuli generated after the interface component is selected will be passed to the second interface component 204. After the interface is selected, the second interface component 204 will send the stimulus to the inside of the chip in the timing format of the second verification version interface 202, thereby performing the write and read operations of the timing register. The stimulus sent by the second interface component 204 reaches the chip pin, and the stimulus reaches the second verification version interface 202 inside the chip from the chip pin, and the stimulus reaches the register from the internal version interface of the chip.

[0058] In this embodiment, users can set random variable parameters, register models, and interface components according to their needs and in a free combination of classified iterations of different products and versions. It has component-based management, flexible configuration, and flexible parameter modification.

[0059] As an embodiment of the present invention, the first verification version interface and the second verification version interface are any type of interface, including but not limited to JTAG interface, SW interface, I2C interface, AXI interface, AHB interface, etc., wherein the interface types of the first verification version interface and the second verification version interface are different.

[0060] Based on the above-mentioned SoC chip multi-version verification method, an embodiment of the present invention further provides a SoC chip multi-version verification device, Figure 3 A structural block diagram of a multi-version verification device for a SoC chip provided by an embodiment of the present invention is shown as follows: Figure 3 As shown, the SoC chip multi-version verification device includes the following modules:

[0061] Setting module 301, used for setting random variables;

[0062] Preferably, the random variable is used to distinguish different functional versions of the SoC chip to be verified, so as to realize verification of functions of different versions of the SoC chip.

[0063] It should be noted that if there are two SoC chip function versions that need to be verified, the setting module 301 can set the values ​​of the random variable to 0 and 1; if there are three SoC chip function versions that need to be verified, the setting module 301 can set the values ​​of the random variable to 0, 1, 2, and so on.

[0064] A constraint module 302 is used to constrain the random variable and select the design register to be tested according to the value of the random variable;

[0065] It should be noted that if there are two SoC chip functional versions that need to be verified, and the setting module 301 sets the values ​​of the random variable to 0 and 1, then when the random variable takes the value of 0, the constraint module 302 is used to restrict the chip's external access to the design register 205 to the first verification version interface 201; when the random variable takes the value of 1, the constraint module 302 is used to restrict the chip's external access to the design register 205 to the second verification version interface 202. If there are three SoC chip functional versions that need to be verified, and the setting module 301 sets the values ​​of the random variable to 0, 1, and 2, then when the random variable takes the value of 0, the constraint module 302 is used to restrict the chip's external access to the design register 205 to the first verification version interface 201; when the random variable takes the value of 1, the constraint module 302 is used to restrict the chip's external access to the design register 205 to the second verification version interface 202; when the random variable takes the value of 2, the constraint module is used to restrict the chip's external access to the design register 205 to the third version interface, and so on.

[0066] The connection module 303 is used to pass the value of the random variable to the verification top layer and connect different interfaces of the design under test according to the value of the random variable and the constraint conditions;

[0067] As one embodiment of the present invention, specifically, when verifying the functionality of a SoC chip, connection module 303 first transmits the value of a random variable that distinguishes different functional versions of the SoC chip to the top level verification layer. The top level verification layer then connects different pins and interfaces of the design under test based on the value of the random variable that distinguishes the functional versions. It should be noted that the value transmitted by the random variable not only drives the chip pins, allowing the chip to select the corresponding functional version, but also enables the verification environment to select the corresponding interface component to connect to the chip pins.

[0068] The sending module 304 is configured to transmit the stimulus to the register of the design to be tested through the corresponding interface according to the value of the random variable.

[0069] As an embodiment of the present invention, it should be noted that after the connection module 303 selects the corresponding interface component according to the value of the random variable, the sending module 304 sends the stimulus to the corresponding SoC chip pin in the timing format of the corresponding interface of the SoC chip through the interface component; then sends the stimulus from the corresponding SoC chip pin to the corresponding interface inside the SoC chip; then sends the stimulus from the corresponding interface inside the SoC chip to the corresponding design register to be tested 205, thereby realizing the write and read operations of the design register to be tested 205.

[0070] For other details about how the modules in the SoC chip multi-version verification device implement the above technical solution, please refer to the description of the SoC chip multi-version verification method provided in the above invention embodiment, which will not be repeated here.

[0071] The present application also provides a schematic diagram of a multi-version verification device for a SoC chip. Figure 4 A schematic diagram of the structure of a SoC chip multi-version verification device provided in an embodiment of the present application is shown as follows: Figure 4 As shown, the SoC chip multi-version verification device may include: stimulus model 1 401 and stimulus model 2 402. Stimulus model 1 sends stimuli that comply with the interface protocol of the first verification version interface 201; stimulus model 2 sends stimuli that comply with the interface protocol of the second verification version interface 202. Both stimulus models can execute the method described in any of the above embodiments. Specifically, stimulus model 1 401 is connected to the first verification version interface 201, and stimulus model 2 402 is connected to the second verification version interface 202.

[0072] For other details about how the processor in the above-mentioned SoC chip multi-version verification device implements the above-mentioned technical solution, please refer to the description of the SoC chip multi-version verification method provided in the above-mentioned invention embodiment, which will not be repeated here.

[0073] In the embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the various parts is only a logical function division. In actual implementation, there may be other division methods, such as multiple components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interface, device or module, which can be electrical, mechanical or other forms.

[0074] The various components of the apparatus described as separate components may or may not be physically separate. For example, the components of the register model may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these modules may be selected to implement the solution of this embodiment according to actual needs.

[0075] In addition, in the various embodiments of the present application, the various parts of the device can be integrated into a processing unit, can exist separately physically, or can be two or more integrated into a single unit. The thus formed unit can be implemented in the form of hardware or in the form of hardware plus software functional units. The above-mentioned integrated modules implemented in the form of software functional modules can be stored in a computer-readable storage medium. The above-mentioned software functional modules are stored in a storage medium and include a number of instructions for causing a computer device (which can be a personal computer, server, or network device, etc.) or a processor to perform some steps of the method described in the various embodiments of the present application.

[0076] The above is a detailed introduction to a SoC chip multi-version verification method, device and equipment disclosed in an embodiment of the present invention. Although the preferred embodiment of the present invention has been described, it is only used as an example, and the present invention is not limited to the specific implementation methods described above. Once those skilled in the art know the basic creative concepts, they can make additional changes and modifications to these embodiments. Therefore, for those skilled in the art, based on the ideas of the present invention, equivalent modifications or substitutions made to the invention are also within the scope of the present invention, and equal transformations, modifications, improvements, etc. made without departing from the spirit and principle of the present invention should all be covered within the scope of the present invention. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A multi-version verification method for a SoC chip, characterized in that: The following steps are involved: S1 sets a random variable; before step S1 also includes establishing a register model, the register model includes a verification code corresponding to the design to be tested, the verification code contains all the information of the design register to be tested; S2 constrains the random variable and selects the design register to be tested according to the value of the random variable; S3. Passing the value of the random variable to the verification top layer, connecting different interfaces of the design under test according to the value of the random variable and the constraint conditions; wherein step S3 further includes: driving the SoC chip pin to select the corresponding verification version according to the value of the random variable; driving the verification environment to select the corresponding interface component and connect it to the chip pin according to the value of the random variable; S4. According to the value of the random variable, the stimulus is transmitted to the register of the design to be tested through the corresponding interface.

2. A SoC chip multi-version verification method according to claim 1, characterized in that: Step S4 further includes: Selecting a corresponding interface component according to the value of the random variable, the interface component sends the stimulus to the corresponding SoC chip pin in the timing format of the corresponding interface of the SoC chip; Send stimulus from the corresponding SoC chip pin to the corresponding interface inside the SoC chip; The stimulus is sent to the corresponding register of the design to be tested from the corresponding interface inside the SoC chip, and the write and read operations of the register of the design to be tested are performed.

3. A SoC chip multi-version verification method according to claim 2, characterized in that: Use fun_sel to represent the random variable. When fun_sel=0, the first verification version interface is selected to access the design register to be tested, the register model is connected to the first interface component corresponding to the first verification version interface, and the first interface component is connected to the first verification version interface; when fun_sel=1, the second verification version interface is selected to access the design register to be tested, the register model is connected to the second interface component corresponding to the second verification version interface, and the second interface component is connected to the second verification version interface.

4. A SoC chip multi-version verification method according to claim 3, characterized in that: The first verification version interface and the second verification version interface are JTAG interfaces, SW interfaces, I2C interfaces, AXI interfaces, or AHB interfaces.

5. A SoC chip multi-version verification method according to claim 4, characterized in that: The first verification version interface and the second verification version interface are of different interface types.

6. A SoC chip multi-version verification device for executing the SoC chip multi-version verification method according to any one of claims 1 to 5, characterized in that: include: Setting module, used to set random variables; A constraint module, configured to constrain the random variable and select a design register to be tested according to the value of the random variable; A connection module, used to pass the value of the random variable to the verification top layer and connect different interfaces of the design to be tested according to the value of the random variable and the constraint conditions; The sending module is used to transmit the stimulus to the register of the design to be tested through the corresponding interface according to the value of the random variable.

7. A SoC chip multi-version verification device, characterized in that: The SoC chip multi-version verification device includes: at least two stimulus models, each stimulus model corresponds to an interface; the at least two stimulus models send stimulus according to the corresponding interface protocol, so that the SoC chip multi-version verification device executes the SoC chip multi-version verification method as described in any one of claims 1-5.

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