Quarter match parallel compensation in memory systems

Abstract

The present disclosure relates to quarter match parallel compensation in memory systems. An example device can perform parallel threshold voltage compensation in a memory array having distributed row redundancy. The example device can include a row decoder configured to, in response to determining that an original row address matches a defective original row address, initiate, in parallel, threshold voltage compensation operations for both an original row corresponding to the original row address in a respective plurality of original rows of memory cells of a first row section of a plurality of row sections and a respective redundant row of the second row section of the plurality of row sections. The row decoder can be further configured to prevent an access operation associated with the original row from proceeding based on a comparison of a subset of match signals from the first or second plurality of row sections.

Description

Technical Field

[0001] This disclosure relates to quarter-matching parallel compensation in memory systems. Background Technology

[0002] High data reliability, high memory access speed, and reduced chip size are desirable characteristics for semiconductor memories. In recent years, efforts have been made to further increase memory clock speeds without sacrificing reliability, which effectively reduces the absolute time cycles available for performing memory operations for a fixed number of clock cycles. One aspect that may hinder faster clock speeds is the time spent charging and discharging access lines during memory access operations. As clock speeds increase, charging and discharging access lines may consume an increasing share of the allocated time used to perform some memory access operations. The time cycle of a memory access operation that helps limit the total latency within the memory to provide data from the memory cell at the output is the minimum row address (RAS) to column address (CAS) delay, or tRCD. tRCD is the minimum number of clock cycles required to activate a row of memory and access the memory cell coupled to a column of memory cells in the activated row. Reducing tRCD provides more headroom for memory devices. Summary of the Invention

[0003] One aspect of this disclosure relates to an apparatus comprising: a first plurality of defective row address comparison circuits, each defective row address comparison circuit being associated with and configured to store a corresponding defective original row address in a first plurality of row segments of a memory array, wherein each of the first plurality of defective row address comparison circuits is configured to compare a received original row address with the stored corresponding defective original row address to provide a corresponding match signal; a second plurality of defective row address comparison circuits, each defective row address comparison circuit being associated with and configured to compare the received original row address with the corresponding defective original row address to provide a corresponding match signal; and a logic tree configured to compare corresponding hit signals from the first plurality of row address comparison circuits to provide a first fast hit signal, and to compare corresponding hit signals from the second plurality of row address comparison circuits to provide a second fast hit signal, wherein the logic tree is further configured to compare the first and second fast hit signals. A signal is provided to provide a hit signal; a line decoder includes a first predecoder associated with the first plurality of line segments and a second predecoder associated with the second plurality of line segments, wherein during an access operation: the first predecoder is configured to initiate a first threshold voltage compensation operation on a corresponding redundant line of the first line segment of the first plurality of line segments associated with the corresponding hit signal in response to a corresponding hit signal provided by one of the first plurality of defective line address comparison circuits indicating that the original line address matches the corresponding defective original line address; and the second predecoder is configured to initiate a second threshold voltage compensation operation on the original line of the second line segment of the second plurality of line segments in parallel with the first threshold voltage compensation operation when the original line of the second line segment of the second plurality of line segments corresponds to the original line address, wherein the second predecoder is further configured to prevent the access operation associated with the original line from continuing in response to the first fast hit signal.

[0004] Another aspect of this disclosure relates to an apparatus comprising: a first plurality of fuse latches and comparator circuits, each fuse latch and comparator circuit associated with and configured to store a corresponding defective row address in a first plurality of row segments, wherein individual fuse latches and comparator circuits in the first plurality of fuse latches and comparator circuits are each configured to provide a corresponding match signal in response to determining that a received original row address matches the corresponding defective row address; and a second plurality of fuse latches and comparator circuits, each fuse latch and comparator circuit associated with and configured to store a corresponding defective row address in a second plurality of row segments, wherein the second plurality of fuse latches and comparator circuits are configured to store a corresponding defective row address in response to determining that a received original row address matches the corresponding defective row address; ... wherein the second plurality of fuse latches and comparator circuits are configured to store a corresponding defective row address in response to determining that a received original row address matches the corresponding defective row address; wherein the second plurality of fuse latches and comparator circuits are configured to store a corresponding defective row address in response to determining that a received original row address matches the corresponding defective row address; wherein the second plurality of fuse latches and comparator circuits are configured to store a corresponding defective row address in response to determining that a received original row address matches the corresponding defective row address; wherein the second plurality of fuse latches and comparator circuits are configured to store a corresponding defective row address in response Individual fuse latches and comparator circuits in the fuse latch and comparator circuitry are each configured to provide a corresponding match signal in response to determining that the received original row address matches the corresponding defective row address; a logic tree configured to compare the corresponding match signals from a first plurality of fuse latches and comparator circuits to provide a first fast hit signal, and to compare the corresponding hit signals from a second plurality of fuse latches and comparator circuits to provide a second fast hit signal, wherein the logic tree is further configured to compare the first and second fast hit signals to provide a hit signal; a first pre-decoder coupled to the first plurality of fuse latches and comparator circuits to receive the corresponding match signal and connect to... The system receives the original row address, wherein a first threshold voltage compensation is initiated on a first redundant row associated with the first plurality of fuse latches and comparator circuits in response to one of the corresponding match signals; wherein a second threshold voltage compensation operation is initiated on the first original row in response to determining that the decoded original row address is targeted at the first original row of the first plurality of row segments; wherein the first pre-decoder is configured to prevent access operations associated with the first original row from continuing in response to the first or second fast hit signal being set; and a second pre-decoder, coupled to the second plurality of fuse latches and comparator circuits, and configured to receive the second match signal and... The original row address is received, wherein a third threshold voltage compensation is initiated on a second redundant row associated with the second fuse latch and comparator circuit in response to the first matching signal, wherein a fourth threshold voltage compensation operation is initiated on the second original row in response to determining that the decoded original row address is targeted as a second original row of a second plurality of row segments, wherein at least one of the first or third threshold voltage compensation operations is at least partially parallel to at least one of the second or fourth threshold voltage compensation operations, wherein the second predecoder is configured to prevent access operations associated with the second original row from continuing in response to the first or second fast hit signal being set.

[0005] Another aspect of this disclosure relates to a method comprising: receiving, at a first plurality of fuse latch comparator circuits, a second plurality of fuse latch comparator circuits, a first pre-decoder, and a second pre-decoder, an original row address associated with an access operation, wherein each of the first plurality of fuse latches and comparator circuits is associated with a specific row segment of a first plurality of row segments, and each of the second plurality of fuse latches and comparator circuits is associated with a specific row segment of a second plurality of row segments; providing a corresponding first corresponding match signal via the first plurality of fuse latch comparator circuits in response to determining that the original row address matches a corresponding defective row address; providing a corresponding second match signal via the second plurality of fuse latch comparator circuits in response to determining that the original row address matches a corresponding defective row address; and comparing the original row address received from the first plurality of fuse latch comparator circuits. The corresponding matching signal provided by the path is used to provide a first fast hit signal; the corresponding matching signal provided from the second plurality of fuse latch comparator circuits is compared to provide a second fast hit signal; the first and second fast hit signals are compared to provide a hit signal; and in parallel, in response to one of the corresponding matching signals provided from the first plurality of fuse latch comparator circuits, a first threshold voltage compensation is initiated on a first redundant row associated with one of the first plurality of fuse latch comparator circuits via the first predecoder; and in response to determining that the original row address is targeted as a first original row of the second plurality of row segments, a second threshold voltage compensation operation is initiated on the first original row via the second predecoder; and in response to the first or second fast hit signal, access operations associated with the first original row are prevented from continuing. Attached Figure Description

[0006] Figure 1 This is a schematic block diagram of a semiconductor device memory system according to embodiments of the present disclosure.

[0007] Figure 2 This is a block diagram of a semiconductor device according to an embodiment of the present disclosure.

[0008] Figure 3 This is a block diagram of a fuse latch circuit and a matching comparator between the fuse address and the row address according to an embodiment of the present disclosure.

[0009] Figure 4 This is a block diagram of a pre-decoder circuit according to an embodiment of the present disclosure.

[0010] Figure 5 This is a block diagram of an RXNOM tree according to an embodiment of the present disclosure.

[0011] Figure 6 This is a block diagram of a pre-decoder circuit according to an embodiment of the present disclosure.

[0012] Figure 7 This is a schematic block diagram of a main word line driver circuit according to an embodiment of the present disclosure.

[0013] Figure 8 This is a schematic block diagram of an FX driver circuit according to an embodiment of the present disclosure.

[0014] Figure 9 This is an illustration of an exemplary timing diagram depicting a hit-case parallel compensation operation according to embodiments of the present disclosure. Detailed Implementation

[0015] This disclosure describes examples of systems for performing quarter-match parallel compensation in a memory system with distributed row redundancy. In a semiconductor memory, a memory array may be divided into memory banks, wherein each memory bank is further divided into row segments, each having a common number of rows. Some semiconductor device memories may contain redundant or repaired rows of memory cells within the memory array, which can repair defective memory along the rows. The repair can be achieved by remapping the memory address of an initial memory location in a memory block to a redundant memory cell, thereby repairing the defective initial memory location. In some instances, redundant rows may be distributed across the array such that some or all row segments have at least one repaired row. In some instances, the repaired row or multiple repaired rows in each segment can be used to replace a defective row in any row segment within the memory bank.

[0016] When a memory access command (e.g., read or write) is received, the memory can initiate a memory access operation in response to the command. For a read operation, the memory access operation may include an event chain (e.g., a row address (RAS) chain) to prepare the memory to retrieve the requested data from the origin or destination location within the memory array and to provide the requested data to the data endpoint for transmission via the data bus. A time cycle that helps limit the total latency within the memory to provide data from the memory cell at the output of the memory access operation is the minimum RAS to column address (CAS) delay, or tRCD. tRCD is the minimum number of clock cycles required to activate a row of memory and access the memory cell coupled to a column of memory cells in the activated row.

[0017] In some instances, a portion of the RAS chain may perform threshold voltage compensation in the sense amplifier used to sense data stored in the sense memory cell. A sense amplifier containing a threshold voltage compensation circuitry system can compensate for threshold voltage differences between components of the sense amplifier. Compensation for threshold voltage differences between circuit components within the sense amplifier can improve reliability. However, the process used to compensate for threshold voltage differences may increase tRCD because adding a compensation stage to the sensing operation can increase the total time to complete the sensing operation.

[0018] Upon receiving an ACT command (e.g., initiating a read operation), the memory can decode the corresponding original or target row address received with the ACT command and determine whether the original row has been replaced with a redundant row. If so, the memory can redirect the ACT command access to the row address associated with the redundant row (e.g., the redundant row address). To determine whether the original row has been replaced with a redundant row, the memory may include a repair row logic tree (e.g., RXNOM) containing logic circuitry configured to compare repair row addresses stored in fuse latches for each row segment. The process of determining row redundancy may delay the ACT access operation.

[0019] To mitigate row redundancy latency, the memory can initiate access operations for the original row, including VtC compensation operations, simultaneously with determining row redundancy. Additionally, in response to the initial detection of the redundant row address (e.g., a hit or match with the original row address) but before the RXNOM tree has fully determined the redundancy comparison, the memory can also initiate access operations for the redundant row in parallel with the VtC compensation for the original row, including VtC compensation operations. If a hit is detected, the output of the RXNOM logic tree can pause the sensing operation at the original row to support the redundant row.

[0020] However, the delay of signals traveling through the RXNOM logic tree can still add to the latency before sensing operations can continue. Therefore, to further reduce tRCD, a quarter-matched RXNOM (e.g., RXNOMFast) signal can be used to pause the original row sensing operation (e.g., reset the row factor signal) before the full RXNOM signal. This allows word line activation to begin before waiting for the full RXNOM signal to complete.

[0021] If no hit is detected, no redundant access operation is initiated, and the original row sensing operation continues. By initiating VtC compensation in parallel in both the original row and the redundant row used for replacement before redundancy is fully resolved, and pausing the original row upon detection of a hit, the memory can reduce the tRCD of access operations compared to waiting until redundancy determination is complete before activating the word line. Furthermore, skipping parallel VtC compensation when no redundant row is detected reduces power consumption compared to always performing parallel VtC compensation.

[0022] Figure 1This is a schematic block diagram of a semiconductor device 100 according to an embodiment of the present disclosure. For example, the semiconductor device 100 may include a chip 135. Chip 135 may include a clock input circuit 105, an internal clock generator 107, an address command input circuit 115, an address decoder 120, a command decoder 125, control circuitry 121, multiple row decoders 130, a memory cell array 145 including a sense amplifier 150 and a transmission gate 195, multiple column decoders 140, multiple memory bank control circuits 128, multiple read / write amplifiers 165, input / output (I / O) circuitry 170, and a voltage generator 190. The semiconductor device 100 may include multiple external terminals, including address and command terminals coupled to a command / address bus 110, clock terminals CK and / or CK, data terminals DQ, DQS, and DM, and power terminals VDD, VSS, VDDQ, and VSSQ. Chip 135 may be mounted on a substrate, such as a memory module substrate, motherboard, or the like.

[0023] The memory cell array 145 includes multiple memory banks 0-N, each memory bank 0-N comprising multiple word lines WL, multiple bit lines BL, and multiple memory cells MC arranged at the intersections of the multiple word lines WL and the multiple bit lines BL. The multiple memory banks 0-N may contain 2, 4, 8, 16, or any other number of memory banks. Each of the memory banks 0-N may be divided into two or more memory planes (e.g., column planes), which may be selected by a column selection CS signal from the column decoder 140. In some instances, each of the memory banks 0-N may contain 2, 4, 8, 16, 32, etc., column planes. The selection of the word lines WL for each memory bank is performed by the corresponding row decoder 130, and the selection of the bit lines BL is performed by the corresponding column decoder 140. Multiple sense amplifiers 150 are positioned for their corresponding bit lines BL and coupled to at least one corresponding local I / O line, which is further coupled to one of at least two main I / O line pairs via a transmission gate TG 195 acting as a switch. In some instances, the multiple sense amplifiers 150 may include a threshold voltage compensation circuitry to compensate for threshold voltage differences between components of the sense amplifiers.

[0024] Address / command input circuit 115 can receive address signals and memory address signals from external sources at the command / address end via command / address bus 110, and can transmit the address signals and memory address signals to address decoder 120. Address decoder 120 can decode the address signals received from address / command input circuit 115, and provide row address signal XADD to row decoder 130, and column address signal YADD to column decoder 140. Address decoder 120 can also receive memory address signals and provide memory address signal BADD to row decoder 130 and column decoder 140.

[0025] Address / command input circuitry 115 can receive command signals from an external source, such as memory controller 105 at the command / address terminal, via command / address bus 110, and provide the command signals to command decoder 125. Command decoder 125 can decode the command signals and generate various internal command signals to provide to row decoder 130, column decoder 140, and memory bank control circuitry 128. Memory bank control circuitry 128 can provide row control signals and column control signals to row decoder 130 and column decoder 140, respectively, to control the timing of RAS chain operations. Signals from memory bank control circuitry 128 may include row command signals for selecting word lines and column command signals for selecting bit lines, such as read commands or write commands, etc.

[0026] Typically, when a read command is issued and ACT and R / W commands are supplied to the row and column addresses as appropriate, read data is read from the memory cells specified by the row and column addresses in the memory cell array 145. The read / write amplifier 165 receives the read data DQ and provides it to the I / O circuit 170. The I / O circuit 170 provides the read data DQ, along with a data strobe signal at DQS and / or a data mask signal at DM, to the external location via the data terminal DQ. Similarly, when a write command is issued and ACT and R / W commands are supplied to the row and column addresses as appropriate, the input / output circuit 170 receives the write data at the data terminal DQ, along with the data strobe signal at DQS and / or the data mask signal at DM, and provides the write data to the memory cell array 145 via the read / write amplifier 165. Therefore, write data can be written to the memory cells specified by the row and column addresses.

[0027] In some instances, the memory bank 0-N of the memory cell array 145 may be divided into row segments, where each row segment has a common number of initial rows. Additionally, the memory cell array 145 may further include redundant or repair rows of memory cells distributed across each row segment of the memory cell array 145, which can be used to repair defective initial rows. The repair is achieved by remapping the memory addresses of the initial rows to redundant memory cells. In some instances, redundant rows may be distributed across the memory cell array 145 such that some or all row segments have at least one repair row. In some instances, redundant rows or multiple redundant rows in each row segment can be used to replace defective rows in another row segment.

[0028] Therefore, as explained above, when a memory access (e.g., read or write) command is received, the semiconductor device can initiate a memory access operation in response to the command. For a read operation, the memory access operation may include an event chain (e.g., a row address (RAS) chain) to prepare the semiconductor device 100 to retrieve requested data from an origin or destination location within the memory cell array 145 and to provide the requested data to the data terminal DQ for transmission via the data bus. A time cycle that helps limit the total latency within memory to provide data from the memory cell at the output of the memory access operation is the minimum RAS to column address (CAS) delay, or tRCD. tRCD is the minimum number of clock cycles required to activate a row of memory and access a memory cell coupled to a column of memory cells in the activated row.

[0029] Upon receiving a read command, command decoder 125 may provide the ACT command to row decoder 130, column decoder 140, and memory bank control circuitry 128. In response, memory bank control circuitry 128 may provide row control signals and column control signals to row decoder 130 and column decoder, respectively. Row decoder 130 may include multiple pre-decoder circuits configured to decode the received raw row address XADD to determine which word line to activate. Each of the multiple pre-decoders may be associated with a subset of row segments of memory bank 0-N.

[0030] Additionally, the line decoder 130 may include fuse latches configured to store the addresses of defective rows received from the fuse array 129. In some instances, the fuse array 129 may provide fuse array data containing the addresses of defective rows to the fuse latches of the line decoder 130 as part of a power-on or reboot / reset sequence. A set of fuse latches may be assigned to each replacement row. The line decoder 130 may include a line redundancy comparison logic tree (e.g., an RXNOM tree) configured to compare the received corresponding original row or target row address with a read command to determine whether the original row has been replaced with a redundant row. If so, the RXNOM tree may cause the appropriate predecoder among multiple predecoders to redirect the read command access to the row address associated with the redundant row (e.g., the redundant row address). The process of determining row redundancy may delay read access operations.

[0031] Therefore, to mitigate row redundancy latency, while determining row redundancy, the corresponding original row predecoder among multiple predecoders can initiate access operations for the original row, including VtC compensation operations. Additionally, in response to the initial detection of the redundant row address (e.g., a hit or match with the original row address) but before the RXNOM tree has fully determined the redundancy comparison, the corresponding original row predecoder among multiple predecoders can also initiate access operations for the redundant row in parallel with the access operations for the original row, including VtC compensation operations. If a hit is detected, the output of the RXNOM logic tree can pause the access operations performed by the original row predecoder to support the redundant row predecoder. In some instances, the sensing operation can be paused before activating the word line used for the original row word line.

[0032] However, the delay of signals traveling through the RXNOM logic tree can still add to the latency before sensing operations can continue. Therefore, to further reduce tRCD, a quarter-matched RXNOM (e.g., RXNOMFast) signal can be used to pause the original row sensing operation (e.g., reset the row factor signal) before the full RXNOM signal. This allows word line activation to begin before waiting for the full RXNOM signal to complete.

[0033] If no hit is detected, activation operations are not initiated for redundant rows, and the original row pre-decoder access operations can continue. By initiating VtC compensation in parallel for both the original row and the redundant row used for replacement before redundancy is fully resolved, and pausing the original row upon a hit detection, the memory can reduce the tRCD of access operations compared to waiting until redundancy determination is complete before activating word lines. Furthermore, skipping parallel VtC compensation when no redundant row is detected reduces power consumption compared to always performing parallel VtC compensation.

[0034] Instead, the external terminals included in semiconductor device 100, clock terminals CK and / CK, can receive an external clock signal and a complementary external clock signal, respectively. The external clock signal (including the complementary external clock signal) can be supplied to clock input circuit 105. Clock input circuit 105 receives the external clock signal and generates an internal clock signal ICLK. Clock input circuit 105 can provide the internal clock signal ICLK to internal clock generator 107. Internal clock generator 107 can generate a phase-controlled internal clock signal LCLK based on the received internal clock signal ICLK and the clock enable signal CKE from address / command input circuit 115. Although not limited to this, a DLL circuit can be used as internal clock generator 107. Internal clock generator 107 can provide the phase-controlled internal clock signal LCLK to IO circuit 170. IO circuit 170 can use the phase-controlled internal clock signal LCLK as a timing signal to determine the output timing for reading data.

[0035] The power supply terminal can receive power supply voltages VDD and VSS. These power supply voltages VDD and VSS can be supplied to voltage generator circuit 190. Voltage generator circuit 190 can generate various internal voltages VPP, VOD, VARY, VPERI, etc., based on the power supply voltages VDD and VSS. The internal voltage VPP is mainly used in the line decoder 130, the internal voltages VOD and VARY are mainly used in the sense amplifier 150 included in the memory cell array 145, and the internal voltage VPERI is used in many other circuit blocks. The power supply terminal can also receive power supply voltages VDDQ and VSSQ. I / O circuit 170 can receive power supply voltages VDDQ and VSSQ. For example, power supply voltages VDDQ and VSSQ can be the same voltages as power supply voltages VDD and VSS, respectively. However, dedicated power supply voltages VDDQ and VSSQ can be used in I / O circuit 170.

[0036] Figure 2 This is a block diagram of a semiconductor device 200 according to an embodiment of the present disclosure. The semiconductor device 200 may include a memory array pad 210 having row segments 0 to 52 divided into pre-decoder row segment groups 212(0)-(4) and a row decoder (e.g., including fuse latches and comparators 214(0)-(52), an RXNOM tree 220, pre-decoders 230(0)-(3), and an x-decoder 250). The row decoder may be coupled to a main word line driver 260 and an FX driver 270. In some instances, Figure 1 The line decoder 130 can be implemented Figure 2 The line decoder.

[0037] The memory array pad 210 may contain 53 row segments of memory cells, wherein each row segment contains multiple original rows of memory cells. Additionally, some or all of the 53 row segments may contain at least one redundant row of memory cells for repairing defective rows of memory cells in any of the 53 row segments. Each of the corresponding one or more redundant rows of the 53 row segments may be associated with a corresponding one of fuse latches and comparators 214(0)-(52). The fuse latches and comparators 214(0)-(52) may be configured to store the corresponding defective row address when a redundant row in the segment has been allocated to replace the defective row of the memory cell associated with the defective row address, and to compare the received row address RA to determine whether the target row or the original row matches the defective row. When a match is detected by a corresponding one of the fuse latches and comparators 214(0)-(52), an S0-S52 match signal may be provided. For clarity, Figure 2 Only the S0 and S52 matched signals are depicted, but it should be understood that each fuse latch and comparator 214(0)-(52) can provide one of the corresponding S0-S52 matched signals.

[0038] A subset of each of the 53 row segments can be grouped together in predecoder row segment groups 212(0)-(4). For example, each predecoder row segment group 212(0)-(4) may contain a corresponding 13 or 14 rows of memory array pad 210. Each predecoder row segment group 212(0)-(4) may be coupled to one of the predecoders 230(0)-(3) to provide S0-S52 matched signals. For example, predecoder row segment group 212(0) may be coupled to predecoder 230(0), predecoder row segment group 212(1) may be coupled to predecoder 230(1), etc. Although Figure 2 The diagram depicts four predecoder row segment groups 212(0)-(3) and four predecoders 230(0)-(3), but it should be understood that there may be more or fewer than four predecoder row segment groups and predecoders in the memory array pad 210 and the row decoders.

[0039] Additionally, each predecoder line segment group 212(0)-(4) may be coupled to an RXNOM tree 220 to provide S0-S52 match signals. The RXNOM tree 220 may contain logic for comparing all S0-S52 match signals to provide RXNOM signals to predecoders 230(0)-(3). RXNOM signals may indicate whether there is a hit or miss for a replacement line with respect to line address RA. Furthermore, the RXNOM tree 220 may be configured to provide corresponding quarter-match signals RXNOMFast0-3 to predecoders 230(0)-(3). Each RXNOMFast0-3 signal represents a partial comparison of the S0-S52 match signals. For example, the RXNOMFast0 signal can represent a comparison of signals S0-S12, the RXNOMFast1 signal can represent a comparison of signals S13-S25, the RXNOMFast2 signal can represent a comparison of signals S26-S38, and the RXNOMFast3 signal can represent a comparison of signals S39-S52.

[0040] Each of the pre-decoders 230(0)-(3) may receive the row address RA indicating the original or target row of the access operation, one of the corresponding RXNOMFast0-3 signals, the RXNOM signal, a corresponding subset of the S0-S52 match signals, and the segment enable signal SecEn (e.g., from, for example...). Figure 1(Received by the memory control circuit 128, etc.). The predecoders 230(0)-(3) can be configured to decode the received signals to set the row factor signal. For example, in response to the SecEn signal, when one of the predecoders 230(0)-(3) (e.g., the original row predecoder) detects that the original row address RA is targeted at a row memory cell in the assigned predecoder row segment group 212(0)-(3), the original row predecoder can set the corresponding row factor RF0-3 signal to start an access operation on the original row of the memory cell, the access operation starting with a VtC compensation operation. Additionally, in response to the SecEn signal, when one of the predecoders 230(0)-(3) (e.g., the redundant row predecoder) receives one of the corresponding S0-S52 matching signals indicating a hit (e.g., the original row is defective and has been replaced by a redundant row in the row segment corresponding to the S0-S52 matching signal), the assigned redundant row predecoder may set the corresponding row factor RF0-3 signal to initiate an access operation to the redundant row of the memory cell, the access operation starting with a VtC compensation operation. If none of the S0-S52 matching signals indicates a hit, the predecoders 230(0)-(3) may not initiate a redundant row access operation. When any of the S0-S52 signals indicates a hit, a hit signal may flow through the RXNOM tree 220 to provide a hit indication on the corresponding one of the RXNOMFast0-3 signals and on the RXNOM signal. In response to a hit indication in one of the RXNOMFast0-3 signals, the corresponding pre-decoder 230(0)-(3) can stop the original row access operation to support access operations associated with redundant rows. Additionally, when the RXNOM signal indicates a hit, the original row pre-decoder can further stop the original row access operation to support access operations associated with redundant rows.

[0041] The x decoder 250 can receive the line factor signal and can provide the line factor signal and other control signals to the main word line driver 260 and the FX driver 270. In response to the activation signal R1AC (e.g., from, for example...), Figure 1 The memory control circuit 128 (and other memory control circuits) receives signals from the memory control circuit. The main word line driver 260 can be configured to activate the main word line associated with the original row and / or redundant row. The FX driver 270 can be configured to provide control signals to the array segment associated with the original row and / or redundant row.

[0042] In operation, each of the fuse latches and comparators 214(0)-(52) can be assigned to a redundant row of memory cells, which can be used to replace the original row of a defective memory cell. During an initialization sequence (e.g., as part of a power-on or reset operation), the fuse array can provide fuse data to the corresponding one or more fuse latches and comparators 214(0)-(52) to indicate the assigned replacement of the corresponding defective memory row. In response, one or more fuse latches and comparators 214(0)-(52) can latch the received address of the defective original row.

[0043] When an ACT command is received targeting the original row of memory array pad 210, the row address RA is provided to the fuse latch and comparators 214(0)-(52) and the pre-decoder 230(0)-(3). The pre-decoder circuits 230(0)-(3) can decode the original row address RA, and in response to the SecEn signal, the corresponding one of the pre-decoder circuits 230(0)-(3) associated with the original row address RA (the original row pre-decoder) sets the corresponding RF0-3 signal to initiate an access operation, including VtC compensation.

[0044] In parallel with the decoding of the original row address RA by the predecoders 230(0)-(3), the fuse latches and comparators 214(0)-(52) can compare the original row address RA with the latched defective row address. When a match or hit is detected, the corresponding one of the fuse latches and comparators 214(0)-(52) can provide the associated predecoder (redundant row predecoder) in the RXNOM tree 220 and the predecoders 230(0)-(3) with the corresponding S0-S52 match signal indicating a hit. In response to the corresponding S0-S52 match signal indicating a hit, the redundant row predecoder can set the corresponding RF0-3 signal to initiate an access operation for the redundant row, including VtC compensation.

[0045] Similarly, in response to the corresponding S0-S52 match signal indicating a hit, the RXNOM tree 220 can set one of the RXNOMFast0-3 signals and the RXNOM signal to indicate a hit. Since RXNOM contains a logic tree, the hit indication on one of the S0-S52 match signals can reach the redundant line pre-decoder 230(0)-(3) before the corresponding RXNOMFast0-3 signal indicating a hit and the RXNOM signal indicating a hit are received at the pre-decoder 230(0)-(3).

[0046] When a hit indication RXNOMFast0-3 signal is received at the original row predecoder, the original row predecoder can reset some of the RF0-3 signals to stop access to the original row, thus supporting access associated with redundant rows. Additionally, when a hit indication RXNOM signal is received at the original row predecoder, the original row predecoder can reset other RF0-3 signals to stop access to the original row, thus supporting access associated with redundant rows. However, since a hit indication on the RXNOM signal has already been received at predecoder 230(0)-(3), using the RXNOMFast0-3 signal to stop access to the original row reduces tRCD compared to relying on the RXNOM signal.

[0047] If the fuse latch and comparator 214(0)-(52) do not detect a hit, the predecoder 230(0)-(3) may not start the redundant line access operation, and RXNOM will indicate a miss to allow the access operation associated with the original line to continue.

[0048] The x decoder 250 can receive RF0-3 signals and can provide control signals to a corresponding one of the main word line drivers 260 and a corresponding one of the FX drivers 270. In response to the control signals and the RIAC signal, the corresponding one of the main word line drivers 260 and the corresponding one of the FX drivers 270 can perform an access operation. Since parallel access operations occur in the event of a hit, the RIAC signal can be delayed until the RXNOM tree 220 fully rules the S0-S52 signals to detect a hit, thus avoiding activation of both word lines. By initiating VtC compensation in parallel in the original line and the redundant line while redundancy is being determined, the semiconductor device 200 can reduce the tRCD of the access operation compared to waiting until redundancy determination is complete before initiating the sensing operation. Furthermore, skipping parallel VtC compensation when no redundant line is detected reduces power consumption compared to always performing parallel VtC compensation.

[0049] Figure 3 This is a block diagram of a fuse latch circuit and a matching comparator 300 between a fuse address and a row address according to an embodiment of the present disclosure. The fuse latch circuit and matching comparator 300 between the fuse address and the row address includes fuse latches 1-m and 310(0)-(m), each coupled to a corresponding comparator 320(0)-(m). In some instances, Figure 1 Line decoder 130 and / or Figure 2 The fuse latch and comparator 214(0)-(52) can implement the fuse latch circuit and the matching comparator 300 between the fuse address and the row address.

[0050] Each of the fuse latches 1-m 310(0)-(m) can be configured to store the corresponding defective row address when a redundant row in the corresponding row segment has been allocated to replace the defective row of the memory cell associated with the defective row address. During the initialization sequence (e.g., as part of a power-on or reset operation), the defective row address can be provided from the fuse array via the fuse array data 1-m signal. During access operations, each of the fuse comparators 1-m 320(0)-(m) can compare the original row address RA with the latched row address from the corresponding fuse latch in the fuse latches 310(0)-(m).

[0051] The fuse comparator 1-m 320(0)-(m) can provide a corresponding S0-Sm match signal based on a comparison. For example, the fuse comparator 1-m 320(0)-(m) can provide a corresponding S0-Sm match signal with a first value when a match is detected (e.g., a hit), and can provide a corresponding S0-Sm match signal with a second value when no match is detected (e.g., a miss). In some instances, the S0-Sm match signal can be reset to indicate a miss between access operations. In some instances, the fuse comparator 1-m 320(0)-(m) can include a bit-by-bit XOR logic tree to perform the comparison. The S0-Sm match signal can be provided to the RXNOM tree and the corresponding pre-decoder.

[0052] Figure 4 This is a block diagram of a portion of a pre-decoder circuit 400 according to an embodiment of the present disclosure. The portion of the pre-decoder circuit 400 may include an RF345 decoder circuit 410, an RF678 decoder circuit 420, an RF910 decoder circuit 430, an RF1415 decoder circuit 440, and an RF16 decoder circuit 450. The portion of the pre-decoder circuit 400 may be configured to provide a subset of the line factor (RF) signal. In some instances, Figure 1 The line decoder 130 and / or the pre-decoder 230(0)-(3) may each implement a portion of the pre-decoder circuit 400.

[0053] The RF1415 decoder circuit 440 may include decoding logic 442 configured to receive the RXNOM signal, row address RA<15:14> bits, and other control signals. In response to the RXNOM signal, row address RA<15:14> bits, and other control signals, the decoding logic 442 may provide a row factor block enable signal RF1415BLKEN to indicate the target memory pad. In some instances, the decoding logic 442 may disable the RF1415BLKEN signal when a hit is indicated on the RXNOM signal (e.g., a logic low value). The RF1415 decoder circuit 440 may further include a timing NAND gate 444 configured to control the release of the RF1415BLKEN signal to the output of the RF1415 decoder circuit 440 in response to the SecEn signal. The RF1415BLKEN signal may be used by the RF345 decoder circuit 410, the RF678 decoder circuit 420, the RF910 decoder circuit 430, and the RF16 decoder circuit 450.

[0054] RF345 decoder circuitry 410 may include decoding logic 412 configured to receive the RXNOM signal, the row address RA<5:3> bits, and the RF1415BLKEN signal. In response to the RXNOM signal, the row address RA<5:3> bits, and the RF1415BLKEN signal, decoding logic 412 may provide a row factor 345 signal RF345 to control the main word line driver (e.g., ...). Figure 2 (Main word line driver 260). In some instances, decoding logic 412 may disable the RF345 signal when a hit is indicated on the RXNOM signal (e.g., a logic low value). The RF345 decoder circuit 410 may further include a NAND gate 414 configured to control the release of the RF345 signal to the output of the RF345 decoder circuit 410 in response to the SecEn signal.

[0055] The RF678 decoder circuit 420 may include decoding logic 422 configured to receive the output of NAND gate 404, the row address RA<8:6> bits, and the RF1415BLKEN signal. NAND gate 404 may receive the inverted RXNOM and RXNOMFast signals and may be applied with NAND logic to provide an output. In response to the output of NAND gate 404, the row address RA<8:6> bits, and the RF1415BLKEN signal, decoding logic 422 may provide the row factor 678 signal RF678 to control the master word line driver (e.g., ...). Figure 2(Master word line driver 260). In some instances, decoding logic 422 may disable the RF678 signal when a hit is indicated on the RXNOM signal (e.g., a logic low value). The RF678 decoder circuit 420 may further include a NAND gate 424 configured to control the release of the RF678 signal to the output of the RF678 decoder circuit 420 in response to the SecEn signal.

[0056] The RF910 decoder circuit 430 may include decoding logic 432 configured to receive the output of NAND gate 406, the row address RA<10:9> bits, and the RF1415BLKEN signal. NAND gate 406 may receive the inverted RXNOM and RXNOMFast signals and may be applied with NAND logic to provide an output. In response to the output of NAND gate 406, the row address RA<10:9> bits, and the RF1415BLKEN signal, decoding logic 432 may provide the row factor 910 signal RF910 to control the master word line driver (e.g., ...). Figure 2 (Main word line driver 260). The RF910 decoder circuit 430 may further include a NAND gate 434 configured to control the release of RF910 signals to the output of the RF910 decoder circuit 430 in response to the SecEn signal.

[0057] RF16 decoder circuit 450 may include components configured to receive the output of NAND gate 408 and row address RA. <16> The decoding logic 452 includes the bit, RF1415BLKEN signal, and other control signals. The NAND gate 408 can receive the inverted RXNOM and RXNOMFast signals and can be used with NAND logic to provide an output. In response to the output of the NAND gate 408, the row address RA... <16> The decoding logic 442 provides row factor 16<1:0> signals RF16<1:0> to control the main word line driver (e.g., bit, RF1415BLKEN signal, and other control signals). Figure 2 (Master word line driver 260). In some instances, decoding logic 452 may disable the RF16<1:0> signals when a hit is indicated on the RXNOM (e.g., logic low) or RXNOMFast (e.g., logic high) signals. RF16 decoder circuitry 450 may further include NAND gate 454 and inverter 456 configured to control the release of the RF16<1:0> signals to the output of RF16 decoder circuitry 450 in response to the SecEn signal.

[0058] Figure 5This is a block diagram of an RXNOM tree 500 according to an embodiment of the present disclosure. The RXNOM tree 500 may include an RXNOM comparator tree 510, an inverter 512, a latch 520, and a multiplexer 530. The RXNOM tree 500 may be configured to provide RXNOM signals. In some instances, Figure 1 The line decoder 130 and / or RXNOM tree 220 can implement RXNOM tree 500.

[0059] The RXNOM comparison tree 510 is configured to compare the fuse latches and match the signals S0-Sm (e.g., Figure 2 The S0-52 matched signal and / or Figure 3 The S0-Sm matched signals are used to provide the RXNOM comparison signal. The RXNOM comparison signal can indicate whether either of the S0-Sm matched signals indicates a hit of the replacement for the defective original row address. In some instances, the RXNOM comparison tree 510 may contain a bit-by-bit XOR logic tree to perform the comparison. The inverted RXNOM comparison signal can be provided to each of latch 520 and multiplexer 530 (e.g., via inverter 512). Latch 520 can be configured to respond to the RXNOM clock signal (e.g., by, for example...) Figure 1 The memory control circuit 128 and other memory control logic provide the latch for the RXNOM comparison signal. The latch 520 can be configured to reset the output in response to the SecEn signal. The output of the latch 520 can be provided to the multiplexer 530.

[0060] Multiplexer 530 can be configured to provide either the output of inverter 512 or the output of latch 520 as the RXNOM signal based on a parallel compensation enable signal. For example, when parallel compensation is disabled, multiplexer 530 can provide the output of inverter 512 as the RXNOM signal. When parallel compensation is enabled, multiplexer 530 can provide the output of latch 520 as the RXNOM signal. Since the output of latch 520 is reset when a new access operation begins via the SecEn signal, the remaining output of the RXNOM compare tree 510 from the previous access operation can be masked to avoid interrupting the next access operation when parallel compensation is enabled.

[0061] Figure 6 This is a block diagram of a portion of a pre-decoder circuit 600 according to an embodiment of the present disclosure. The portion of the pre-decoder circuit 600 may include a raw segment decoder circuit 610 coupled to a raw or redundant segment multiplexer circuit 620. The portion of the pre-decoder circuit 600 may be configured to provide a line factor 313 signal RP313. In some instances, Figure 1 The line decoder 130 and / or pre-decoder 230(0)-(3) may each implement a portion of the pre-decoder circuit 600.

[0062] The raw segment decoder circuit 610 can be configured to receive the row address bits RA<13:3> and provide the initial RP313 signal RF313P. The RP313P signal indicates that the raw row is contained in a subset of the rows managed by the pre-decoder circuit 600.

[0063] The original or redundant section multiplexer circuit 620 can be configured to receive the RP313P signal, along with the RF1415BLKEN signal (e.g., from...). Figure 4 The RF1415 decoder circuit 440), Sx matched signal (e.g., from Figure 2 The S0-S53 matched signals, and / or Figure 3 and 5 The original or redundant section multiplexer circuit 620 may include NAND gates 622, 624, 626, and 628. NAND gate 622 may be configured to apply NAND logic to the RP313P, R1415BLKE, and RXNOM signals to provide an output signal to NAND gate 626. Therefore, when no defective row hit is detected (e.g., RXNOM has a logic high indicating a miss), the output of NAND gate 622 is controlled by the RP313P and RF1415BLKEN signals. When the RXNOM signal indicates a hit (e.g., has a logic low value), the RP313P and RF1415BLKEN signals are overridden. NAND gate 624 may be configured to apply NAND logic to the Sx matching signal and a high supply voltage signal to provide an output signal to NAND gate 626.

[0064] NAND gate 626 can be configured to apply NAND logic to the outputs of NAND gates 622 and 624 to provide the output to NAND gate 628. Therefore, when the output of either or both of NAND gate 622 (e.g., the original row where a defective row was not detected) and NAND gate 624 (e.g., a defective row was detected) is low, the output of NAND gate 626 can be forced high. Otherwise, the output of NAND gate 626 can be set low. That is, the output of NAND gate 626 can indicate whether the pre-decoder circuit 600 should begin access operations on the original row and / or redundant rows.

[0065] The combination of NAND gate 628 and inverter 629 applies AND logic to the output of NAND gate 626 and the SecEn signal to provide the RP313 signal. Therefore, in response to the SecEn signal being set, the RP313 signal provided from NAND gate 628 and inverter 629 reflects the output of NAND gate 626 (e.g., whether the pre-decoder circuit 600 should begin accessing the original row and / or redundant rows).

[0066] Figure 7 This is a schematic block diagram of a main word line driver circuit 700 according to an embodiment of the present disclosure. The main word line driver circuit 700 may include initial activation stages (e.g., NAND gate 710, delay and inverter circuit 712, delay / driver circuit 714, and delay / driver circuit 716) coupled to a redundant main word line driver 720 and the original main word line driver 730. In some instances, Figure 1 Line decoder 130 and / or Figure 2 The main word line driver 260 can implement the main word line driver circuit 700.

[0067] NAND gate 710 can be configured to apply NAND logic to RP313 signals (e.g., from...). Figure 6 The original or redundant section multiplexer circuit 620 provides) and the R1AC activation signal (e.g., from the original or redundant section multiplexer circuit 620 ... Figure 1 The memory control circuit 128 provides an enable signal to the delay and inverter circuit 712. The delay and inverter circuit 712 delays and inverts the output of the NAND gate 710 to provide the output signal to the delay / driver circuit 714, which provides the redundant main word line enable signal RMWLEN, and to the delay / driver circuit 716, which provides the main word line enable signal MMWLEN (via the delay and inverter circuit 712 and the delay / driver circuit 714).

[0068] The redundant main word line driver 720 can be based on the RMWLEN signal, RF345 signal (e.g., from...). Figure 1 The RF345 decoder circuit 410), RF678 signal (e.g., from Figure 4 The RF678 decoder circuit 420) and the RF910 signal (e.g., from the RF910 signal) Figure 4 The RF910 decoder circuit 430 provides redundant ARM MWL signals RARMWLRF. The original main word line driver 730 can be based on the RMWLEN signal, RF345 signal (e.g., from...). Figure 1 The RF345 decoder circuit 410), RF678 signal (e.g., from Figure 4 The RF678 decoder circuit 420), RF910 signal (e.g., from Figure 4The RF910 decoder circuit 430 provides the raw armMWL signal ARMWLRF. The redundant main word line driver 720 and the original main word line driver 730 may contain the same circuitry. Therefore, for clarity and simplicity, only the detailed circuitry of the original main word line driver 730 is depicted and described. It should be understood that the circuitry of the redundant main word line driver 720 may be the same as that depicted in the original main word line driver 730 and will operate in the same manner.

[0069] The original main word line driver 730 may include an inverter 732 configured to receive a MWINN signal, wherein pull-down is controlled by transistors 733a, 733b, and 733c. Transistors 733a, 733b, and 733c may be controlled by signals RF345, RF678, and RF910, respectively. Therefore, for the original segment, when a defective row is detected, signals RF313, RF678, and RF910 prevent the output of inverter 732 from being pulled down. The original main word line driver 730 may further include an inverter formed by transistors 735 and 736 to receive the output of inverter 732 and provide an ARMWLP signal. The original main word line driver 730 may further include a transistor 734 having a gate coupled to the output of the inverter formed by transistors 735 and 736, a drain coupled to the input of the inverter formed by transistors 735 and 736, and a source coupled to a high voltage. When the output of the inverter formed by transistors 735 and 736 goes low, transistor 734 can bring the output of the inverter formed by transistors 735 and 736 back high. Inverter 738 can be configured to invert the output of the inverter formed by transistors 735 and 736 to provide an ARMWLRF signal.

[0070] Figure 8 This is a schematic block diagram of an FX driver circuit 800 according to an embodiment of the present disclosure. The FX driver circuit 800 may include an initial activation stage (e.g., NAND gate 810, NAND gate 812, and inverter / delay circuit 814), an FX driver first stage 820, and an FX driver second stage 860. The FX driver circuit 800 may be configured to control sub-word line drivers and other circuitry to facilitate access operations. In some instances, Figure 1 Line decoder 130 and / or Figure 2 The FX driver 270 can implement the FX driver circuit 800.

[0071] NAND gate 810 can be configured to apply NAND logic to the active-low FX select 0 and 1 signals FXSEL0F and FXSEL1F to provide the FXSet signal. NAND gate 812 can be configured to provide the output to the inverter / delay circuit 814 to the FXSet signal and the R1AC activation signal. Inverter / delay circuit 814 can be configured to delay and invert the output of NAND gate 812 to provide the R1CP signal to the first stage 820 of the FX driver.

[0072] The first stage 820 of the FX driver may include a first segment 840 and a second segment 850. The circuitry of the first segment 840 and the second segment 850 may be identical, differing only in that they are based on RF16. <0> The signal further controls the first segment 840, and is based on RF16. <1> The signal further controls the second segment 850. The RF16<1:0> signal can be controlled by the pre-decoder line factor circuitry system (e.g., Figure 4 The RF16 decoder circuit 450 is provided.

[0073] The first segment 840 may include an inverter 842 configured to receive an R1ACP signal, wherein the pull-down is controlled by a transistor 843. The transistor 843 may be controlled by RF16. <0> Signal control. Therefore, for the original section, when a defective row is detected, RF16 <0> The signal prevents the output of inverter 842 from being pulled down. The first section 840 may further include an inverter formed by transistors 845 and 846 coupled in series with inverter 848. The inverter formed by transistors 845 and 846 coupled in series with inverter 848 can be used to receive the output of inverter 842 and provide RF 16PF. <0> Signal. The first segment 840 may further include a transistor 844 having a gate coupled to the output of an inverter formed by transistors 845 and 846, a drain coupled to the input of the inverter formed by transistors 845 and 846, and a source coupled to a high voltage. When the output of the inverter formed by transistors 845 and 846 goes low, transistor 844 can bring the output of the inverter formed by transistors 845 and 846 back high.

[0074] The second segment 850 may include an inverter 852 configured to receive an R1ACP signal, wherein the pull-down is controlled by a transistor 853. The transistor 853 may be controlled by RF16. <1> Signal control. Therefore, for the original section, when a defective row is detected, RF16 <1> The signal prevents the output of inverter 852 from being pulled down. The second section 850 may further include an inverter formed by transistors 855 and 856 coupled in series with inverter 858. The inverter formed by transistors 855 and 856 coupled in series with inverter 858 can be used to receive the output of inverter 852 and provide RF 16PF. <1> Signal. The second segment 850 may further include a transistor 854 having a gate coupled to the output of an inverter formed by transistors 855 and 856, a drain coupled to the input of the inverter formed by transistors 855 and 856, and a source coupled to a high voltage. When the output of the inverter formed by transistors 855 and 856 goes low, transistor 854 can bring the output of the inverter formed by transistors 855 and 856 back high.

[0075] In response to the RF16PF<1:0> signal, the second stage 860 of the FX driver can drive control signals to facilitate access operations in the memory array.

[0076] Figure 9 This is an illustration of an exemplary timing diagram 900 depicting a hit-case parallel compensation operation according to embodiments of the present disclosure. Timing diagram 900 primarily illustrates a memory logic control circuitry system (e.g., Figure 1 (128) and line decoder circuitry (e.g., Figure 1 Line decoder 130 Figure 2 Semiconductor devices 200 Figure 3 The fuse latch circuit and the matching comparator 300 between the fuse address and the row address Figure 4 The pre-decoder circuit 400 Figure 5 RXNOM tree 500, Figure 6 The operation of the pre-decoder circuit 600 (or any combination thereof). The Sx matching signal can correspond to Figure 2 Any of the S0-S52 matched signals Figure 3 either of the S0-Sm matched signals or Figure 6 The Sx matched signal. The RXNOMFast signal can correspond to Figure 2 RXNOMFast signal or Figure 4 Either of the RXNOMFast signals. The RXNOM signal can correspond to... Figure 2 , 4 The RXNOM signal in any of the figures 5 and 6. The redundant and original RP313 signals can correspond to... Figure 6Or the RP313 signal in any of the figures in 7. The RF signal may correspond to Figure 2 RF0-3 signal, Figure 4 Or the RF345 and / or RF678 signals in any of the figures in 7, Figure 4 and 6 RF1415BLKEN signal, Figure 4 Or RF16<1:0> in any of the diagrams in Figure 8, or any combination thereof. The R1AC signal may correspond to Figure 4 , 7 Or the R1AC signal in any of the figures in 8.

[0077] Before time T0, an access command can be received. At time T0, in response to the access command, the activation command signal ACT can go high to begin the access operation. In response to the access command, the fuse latch (e.g., Figure 2 fuse latches and comparators 214(0)-(52) and / or Figure 3 The fuse latch circuit and the match comparator 300 between the fuse address and the row address can begin to compare the original row address with the faulty row address stored in the fuse latch.

[0078] At time T1, the Sx match signal can go high, indicating a match between the defect address and the original row address. Just before time T2, the SecEn signal can go high. In response, at time T2, compensation operations for the original row can begin, including setting the original segment row factor signal RF between times T3 and T4.

[0079] Additionally, at time T2, in response to the hit indication on the SecEn signal and the Sx match signal, a compensation operation can be initiated on the redundant row. Additionally, at time T3, the RXNOMFast signal can change from a miss indication to a hit indication based on the Sx match signal. To respond to the change in the RXNOMFast signal indicating a hit, some RF signals can be changed to reflect the hit indication, and some original row RF signals can be reset to prevent issues when the redundant row is in a different row segment (e.g., ...). Figure 2 The original line word line is activated when the other line segment (0-53) is active. If the original line and the redundant line are in the same line segment, then both the original line and the redundant line will have only one RP313 signal, and it will remain high.

[0080] At time T4, the R1AC signal can be changed based on the RF signal to initiate word line activation. At time T5, RNFOM can be changed from a miss indication to a hit indication based on the Sx match signal and the RXNOMFast signal. In response, when the original segment is different from the redundant segment, the original segment RP313 signal can be changed low.

[0081] Timing diagram 900 is exemplary and serves to illustrate the operation of various described embodiments. While timing diagram 900 depicts a specific arrangement of signal transformations of the included signals, those skilled in the art will understand that additional or different transformations may be included in different contexts without departing from the scope of this disclosure. Furthermore, the description of the magnitudes of the signals represented in timing diagram 900 is not intended to be drawn to scale, and the representative timing is an illustrative example of timing characteristics.

[0082] While the detailed description has depicted certain preferred embodiments and examples, those skilled in the art will understand that the scope of this disclosure extends from the specifically disclosed embodiments to other alternative embodiments and / or the use of the described embodiments and their obvious modifications and equivalents. Furthermore, other modifications within the scope of this disclosure will be apparent to those skilled in the art. Various combinations or sub-combinations of the specific features and aspects of the embodiments are also contemplated and remain within the scope of this disclosure. Therefore, it should be understood that various features and aspects of the disclosed embodiments can be combined with or substituted for each other to form variations of the disclosed embodiments. Therefore, it is intended that the scope of at least some aspects of this disclosure should not be limited to the specific disclosed embodiments described above.

Claims

1. A semiconductor device comprising: First plurality of defective row address comparison circuits, each associated with and configured to store a corresponding row segment in a first plurality of row segments of a memory array, wherein each of the first plurality of defective row address comparison circuits is configured to compare the received original row address with the stored corresponding defective original row address to provide a corresponding matching signal. The second plurality of defective row address comparison circuits are each associated with a corresponding row segment in the second plurality of row segments of the memory array and configured to compare the received original row address with the corresponding defective original row address to provide a corresponding matching signal; A logic tree configured to compare corresponding hit signals from a first plurality of row address comparison circuits to provide a first fast hit signal, and to compare corresponding hit signals from a second plurality of row address comparison circuits to provide a second fast hit signal, wherein the logic tree is further configured to compare the first and second fast hit signals to provide a hit signal; The line decoder includes a first predecoder associated with the first plurality of line segments and a second predecoder associated with the second plurality of line segments, wherein during access operations: The first pre-decoder is configured to, in response to a corresponding hit signal provided by one of the first plurality of defective row address comparison circuits indicating that the original row address matches the corresponding defective original row address, initiate a first threshold voltage compensation operation on a corresponding redundant row of a first row segment of the first plurality of row segments associated with the corresponding hit signal; and The second predecoder is configured to, in parallel with the first threshold voltage compensation operation, initiate a second threshold voltage compensation operation on the original row of the second row segment in the second plurality of row segments when the original row of the second row segment in the second plurality of row segments corresponds to the original row address, wherein the second predecoder is further configured to prevent access operations associated with the original row from continuing in response to the first fast hit signal.

2. The semiconductor device of claim 1, further comprising first and second plurality of defective row address latch circuits, each of the first and second plurality of defective row address latch circuits being associated with and configured to latch the corresponding defective original row address of a corresponding row segment in the first and second plurality of row segments.

3. The semiconductor device of claim 1, wherein the second pre-decoder is configured to stop the access operation associated with the original row in response to the hit signal.

4. The semiconductor device of claim 3, wherein the logic tree causes the first fast hit signal to indicate a hit prior to the hit signal.

5. The semiconductor device of claim 1, wherein the second pre-decoder is configured to prevent activation of word lines coupled to the original row in response to the first fast hit signal.

6. The semiconductor device of claim 1, further comprising a main word line driver configured to receive a signal from the second pre-decoder to control the activation of a main word line coupled to the word line.

7. The semiconductor device of claim 1, further comprising a sub-word line driver circuit configured to receive a signal from the second pre-decoder to control the activation of the word line.

8. The semiconductor device of claim 1, wherein the second pre-decoder is configured to, in response to a corresponding hit signal provided by one of the second plurality of defective row address comparison circuits indicating that the original row address matches the corresponding defective original row address, initiate the first threshold voltage compensation operation on a corresponding redundant row of a third row segment of the second plurality of row segments associated with the corresponding hit signal.

9. The semiconductor device of claim 1, wherein during the access operation, the first pre-decoder is configured to prevent the first threshold voltage compensation operation from being initiated on any corresponding redundant row of any of the first plurality of row segments in response to a corresponding hit signal indicating a miss in each of the first plurality of defective row address comparison circuits.

10. The semiconductor device of claim 1, wherein during the access operation, the first predecoder is configured to initiate a second threshold voltage compensation operation on the original row of the third row segment of the first plurality of row segments when the original row of the third row segment in the first plurality of row segments corresponds to the original row address.

11. A semiconductor device comprising: The first plurality of fuse latches and comparator circuits are each associated with and configured to store a corresponding defective row address in a first plurality of row segments, wherein each of the individual fuse latches and comparator circuits is configured to provide a corresponding match signal in response to determining that the received original row address matches the corresponding defective row address; The second plurality of fuse latches and comparator circuits are each associated with a specific row segment in the second plurality of row segments and configured to store a corresponding defective row address, wherein each individual fuse latch and comparator circuit in the second plurality of fuse latches and comparator circuits is configured to provide a corresponding match signal in response to determining that the received original row address matches the corresponding defective row address; A logic tree configured to compare corresponding matching signals from the first plurality of fuse latches and comparator circuits to provide a first fast hit signal, and to compare corresponding hit signals from the second plurality of fuse latches and comparator circuits to provide a second fast hit signal, wherein the logic tree is further configured to compare the first and second fast hit signals to provide a hit signal; A first pre-decoder, coupled to the first plurality of fuse latches and comparator circuits to receive the corresponding match signal and the original row address, wherein in response to one of the corresponding match signals, a first threshold voltage compensation is initiated on a first redundant row associated with the first plurality of fuse latches and comparator circuits, wherein in response to determining that the decoded original row address is targeted at a first original row of the first plurality of row segments, a second threshold voltage compensation operation is initiated on the first original row, wherein in response to the first or second fast hit signal being set, the first pre-decoder is configured to prevent access operations associated with the first original row from continuing; as well as A second pre-decoder, coupled to the second plurality of fuse latches and comparator circuits, and configured to receive a second match signal and the original row address, wherein in response to the first match signal, a third threshold voltage compensation is initiated on a second redundant row associated with the second fuse latches and comparator circuits, wherein in response to determining that the decoded original row address is targeted at a second original row of the second plurality of row segments, a fourth threshold voltage compensation operation is initiated on the second original row, wherein at least one of the first or third threshold voltage compensation operations is at least partially parallel to at least one of the second or fourth threshold voltage compensation operations, wherein in response to the first or second fast hit signal being set, the second pre-decoder is configured to prevent access operations associated with the second original row from continuing.

12. The semiconductor device of claim 11, further comprising a memory array pad, the memory array pad including the first and second plurality of row segments.

13. The semiconductor device of claim 11, wherein in response to the hit signal, the first predecoder is configured to stop the second parallel threshold voltage compensation operation on the first original row, wherein in response to the hit signal, the second predecoder is configured to stop the second parallel threshold voltage compensation operation on the second original row.

14. The semiconductor device of claim 11, wherein the hit signal provided by the logic tree is delayed relative to the first and second fast hit signals.

15. The semiconductor device of claim 11, wherein each of the first plurality of fuse latches and comparator circuits includes a respective fuse latch configured to store a respective detection raw address received from the fuse array.

16. The semiconductor device of claim 15, wherein the first pre-decoder is configured to skip the initiation of a first threshold voltage compensation operation when a first matching signal provided from the first plurality of fuse latches and comparator circuits indicates that the original row address is different from the corresponding defective row address.

17. A method for memory operations, comprising: The original row address associated with the access operation is received at a first plurality of fuse latch comparator circuits, a second plurality of fuse latch comparator circuits, a first predecoder and a second predecoder, wherein each of the first plurality of fuse latches and comparator circuits is associated with a specific row segment in a first plurality of row segments, and each of the second plurality of fuse latches and comparator circuits is associated with a specific row segment in a second plurality of row segments; In response to determining that the original row address matches the corresponding defective row address, a corresponding first matching signal is provided via the first plurality of fuse latch comparator circuits; In response to determining that the original row address matches the corresponding defective row address, a corresponding second matching signal is provided via the second plurality of fuse latch comparator circuits; Compare the corresponding matching signals provided from the first plurality of fuse latch comparator circuits to provide a first fast hit signal; Compare the corresponding matching signals provided from the second plurality of fuse latch comparator circuits to provide a second fast hit signal; The first and second fast hit signals are compared to provide a hit signal; and In parallel: In response to one of the corresponding matching signals provided from the first plurality of fuse latch comparator circuits, a first threshold voltage compensation is initiated via the first pre-decoder on a first redundant row associated with one of the first plurality of fuse latch comparator circuits. as well as In response to determining that the original row address is targeted at the first original row of the second plurality of row segments, a second threshold voltage compensation operation is initiated on the first original row via the second predecoder; as well as In response to the first or second fast hit signal, prevent access operations associated with the first original row from proceeding.

18. The method of claim 17, further comprising, in response to the hit signal, stopping the second parallel threshold voltage compensation operation on the first original row.

19. The method of claim 18, wherein the hit signal is delayed relative to the first and second fast hit signals.

20. The method of claim 17, further comprising using an XOR gate to compare the corresponding matching signals provided from the first plurality of fuse latch comparator circuits to provide the first fast hit signal.

21. The method of claim 17, further comprising: In response to one of the corresponding matching signals provided from the second plurality of fuse latch comparator circuits, a third threshold voltage compensation is initiated via the second pre-decoder on a second redundant row associated with one of the second plurality of fuse latch comparator circuits; and In response to determining that the original row address is targeted as a second original row of the first plurality of row segments, a fourth threshold voltage compensation operation is initiated on the second original row via the first predecoder.

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