Infrared LED epitaxial structure and manufacturing method thereof

Abstract

The present application discloses an infrared LED epitaxial structure and a manufacturing method thereof. The infrared LED epitaxial structure comprises, stacked from bottom to top, a substrate, a first semiconductor layer, a first space layer, a multi-quantum well layer, a second space layer, and a second semiconductor layer. The first semiconductor layer and the second semiconductor layer have opposite doping types. The first space layer and the second space layer are superlattice structures. The highest Al composition in each layer of the first space layer is lower than the highest Al composition in each layer of the second space layer, so that the first space layer and the second space layer form an asymmetric structure. The asymmetric space layer in the present application can increase the height of the effective barrier, suppress the overflow of carriers, and enhance the quantum confinement effect on carriers. Moreover, due to the tunneling characteristics of the superlattice, the mobility of carriers is improved. In addition, the asymmetric design can effectively reduce the overflow of carriers from the multi-quantum well, improve the light field distribution, and enhance the photoelectric efficiency and reliability of the infrared light-emitting diode.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and more specifically, to an infrared LED epitaxial structure and a manufacturing method thereof. Background Art

[0002] Infrared LEDs (IR Light Emitting Diodes) are light-emitting devices that convert electrical energy into near-infrared light. Their low power consumption and long lifespan make them widely used in various fields, including optocoupler switches, security monitoring, and night vision surveillance. To enhance the brightness of existing IR LED epitaxial structures, wide-bandgap quantum well barrier layers or carrier confinement layers are commonly used to enhance the quantum confinement effect and increase the probability of carrier recombination. However, this approach increases the operating voltage of the IR LED, potentially reducing its photoelectric efficiency. Furthermore, the increased operating voltage and reduced photoelectric efficiency can increase the junction temperature of the IR LED, reducing its reliability.

[0003] Therefore, it is necessary to provide an infrared LED epitaxial structure and a preparation method thereof to improve the photoelectric efficiency and reliability of infrared light-emitting diodes. Summary of the Invention

[0004] In view of the above problems, the purpose of the present disclosure is to provide an infrared LED epitaxial structure and a preparation method thereof, so as to achieve the purpose of taking into account the carrier recombination probability, photoelectric efficiency and reliability of the infrared light-emitting diode.

[0005] According to one aspect of an embodiment of the present disclosure, an infrared LED epitaxial structure is provided, comprising: a substrate, a first semiconductor layer, a first space layer, a multi-quantum well layer, a second space layer, and a second semiconductor layer stacked in sequence from bottom to top, wherein the first semiconductor layer and the second semiconductor layer have opposite doping types.

[0006] The first space layer and the second space layer are superlattice structures, and the highest Al composition in each layer of the first space layer is smaller than the highest Al composition in each layer of the second space layer so that the first space layer and the second space layer form an asymmetric structure.

[0007] Optionally, the single-period thickness of the superlattice layer in the first space layer is not greater than the single-period thickness of the superlattice layer in the second space layer, and the thickness of the first space layer is not greater than the thickness of the second space layer.

[0008] Optionally, the first spatial layer includes:

[0009] a first waveguide layer located on the first semiconductor layer; and

[0010] The first superlattice layer is located between the first waveguide layer and the multi-quantum well layer.

[0011] Optionally, the first waveguide layer is Al a Ga 1-a As layer, the first superlattice layer is Al b Ga 1-b As / Al c Ga 1- c As stack,

[0012] Among them, b>a and b>c, the value range of a includes 0.1 to 0.2, the value range of b includes 0.2 to 0.3, and the value range of c includes 0.1 to 0.2.

[0013] Optionally, the number of periods of the first superlattice layer is 2 to 6, the thickness of a single period ranges from 4 nm to 20 nm, and the thickness of the first waveguide layer ranges from 100 nm to 600 nm.

[0014] Optionally, the second spatial layer includes:

[0015] a second superlattice layer located on the multi-quantum well layer; and

[0016] The second waveguide layer is located between the second superlattice layer and the second semiconductor layer.

[0017] Optionally, the second waveguide layer is Al d Ga 1-d As layer, the second superlattice layer is Al e Ga 1-e As / Al f Ga 1- f As stack,

[0018] Among them, f>d and f>e, the value range of d includes 0.1 to 0.25, the value range of e includes 0.1 to 0.25, and the value range of f includes 0.25 to 0.4.

[0019] Optionally, the number of periods of the second superlattice layer is 2 to 6, the thickness of a single period ranges from 4 nm to 20 nm, and the thickness of the second waveguide layer ranges from 100 nm to 600 nm.

[0020] Optionally, the first semiconductor layer includes a first ohmic contact layer, a first current spreading layer and a first confinement layer arranged in sequence from bottom to top.

[0021] Optionally, the second semiconductor layer includes a second confinement layer, a second current spreading layer, a transition layer and a second ohmic contact layer arranged in sequence from bottom to top.

[0022] According to another aspect of the present disclosure, a method for manufacturing an infrared LED epitaxial structure is provided, comprising sequentially forming a first semiconductor layer, a first space layer, a multi-quantum well layer, a second space layer, and a second semiconductor layer on a substrate from bottom to top, wherein the first semiconductor layer and the second semiconductor layer have opposite doping types.

[0023] The first space layer and the second space layer are superlattice structures, and the highest Al composition in each layer of the first space layer is smaller than the highest Al composition in each layer of the second space layer so that the first space layer and the second space layer form an asymmetric structure.

[0024] Optionally, the single-period thickness of the superlattice layer in the first space layer is not greater than the single-period thickness of the superlattice layer in the second space layer, and the thickness of the first space layer is not greater than the thickness of the second space layer.

[0025] Optionally, forming the first space layer includes:

[0026] forming a first waveguide layer on the first semiconductor layer; and

[0027] A first superlattice layer is formed on the first waveguide layer, wherein the first superlattice layer is located between the first waveguide layer and the multi-quantum well layer.

[0028] Optionally, the first waveguide layer is Al a Ga 1-a As layer, the first superlattice layer is Al b Ga 1-b As / Al c Ga 1- c As stack,

[0029] Among them, b>a and b>c, the value range of a includes 0.1 to 0.2, the value range of b includes 0.2 to 0.3, and the value range of c includes 0.1 to 0.2.

[0030] Optionally, the number of periods of the first superlattice layer is 2 to 6, the thickness of a single period ranges from 4 nm to 20 nm, and the thickness of the first waveguide layer ranges from 100 nm to 600 nm.

[0031] Optionally, forming the second space layer includes:

[0032] forming a second superlattice layer on the multi-quantum well layer; and

[0033] A second waveguide layer is formed on the second superlattice layer, the second waveguide layer being located between the second superlattice layer and the second semiconductor layer.

[0034] Optionally, the second waveguide layer is Al d Ga 1-d As layer, the second superlattice layer is Al e Ga 1-e As / Al f Ga 1- f As stack,

[0035] Among them, f>d and f>e, the value range of d includes 0.1 to 0.25, the value range of e includes 0.1 to 0.25, and the value range of f includes 0.25 to 0.4.

[0036] Optionally, the number of periods of the second superlattice layer is 2 to 6, the thickness of a single period ranges from 4 nm to 20 nm, and the thickness of the second waveguide layer ranges from 100 nm to 600 nm.

[0037] Optionally, forming the first semiconductor layer includes sequentially forming a first ohmic contact layer, a first current spreading layer, and a first confinement layer on the substrate from bottom to top.

[0038] Optionally, forming the second semiconductor layer includes sequentially forming a second confinement layer, a second current spreading layer, a transition layer, and a second ohmic contact layer on the second space layer from bottom to top.

[0039] According to the infrared LED epitaxial structure and preparation method provided by the embodiments of the present disclosure, by respectively arranging the first spatial layer and the second spatial layer of the superlattice structure on both sides (n-side and p-side) of the multi-quantum well layer, the first spatial layer and the second spatial layer are set to an asymmetric structure, wherein the highest Al component in the second spatial layer located on the p-side is greater than the highest Al component in the first spatial layer located on the n-side, so that the potential barrier of the second spatial layer located on the p-side is higher, thereby effectively enhancing the quantum confinement effect, suppressing the overflow of electrons, and thereby enhancing the recombination probability of carriers, thereby improving the photoelectric efficiency and reliability of the infrared light-emitting diode.

[0040] If the potential barrier is increased simply by increasing the Al composition, the operating voltage will increase. Therefore, the first space layer and the second space layer disclosed in the present invention are both formed by a superlattice structure that is conducive to reducing the operating voltage. The high Al composition layers and the low Al composition layers are stacked alternately to ensure the original quantum confinement effect. The Al composition of the first space layer located on the n-side is lower, so the potential barrier of the first space layer is lower, thereby reducing the operating voltage.

[0041] Furthermore, in the superlattice structure, due to the thin thickness of each layer, a tunnel effect is generated, which improves the carrier mobility and reduces the resistivity and operating voltage.

[0042] Furthermore, since carriers will diffuse toward the multi-quantum well layer due to concentration differences, and the diffusion lengths of P-type doping and N-type doping are different, in order to prevent carriers from diffusing into the multi-quantum well layer, the first space layer and the second space layer are set to appropriate thicknesses, preferably, the thickness of the first space layer is not greater than the thickness of the second space layer, so as to allow electrons and holes to recombine and emit light in the multi-quantum well layer as much as possible, thereby effectively controlling the light field distribution. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present application, and are not limitations to the present application.

[0044] Figure 1 A schematic structural diagram of an infrared LED epitaxial structure according to an embodiment of the present disclosure is shown.

[0045] Figure 2 Shown Figure 1 Schematic diagram of the structure of the first space layer and the second space layer. DETAILED DESCRIPTION

[0046] The infrared LED epitaxial structure and its fabrication method proposed in this disclosure are further described in detail below, with reference to the accompanying drawings and specific embodiments. The advantages and features of this disclosure will become more apparent from the following description. It should be noted that the accompanying drawings are highly simplified and not to exact scale, and are intended solely to facilitate and clearly illustrate the embodiments of this disclosure.

[0047] Before describing the embodiments of the present disclosure, the following is described in advance. First, in this specification, when simply labeled "GaInP," it represents an arbitrary compound in which the chemical composition ratio of a Group III element (the sum of In and Ga) to P is 1:1, and the ratio of the Group III element In to Ga is not fixed.

[0048] Figure 1 A schematic structural diagram of an infrared LED epitaxial structure according to an embodiment of the present disclosure is shown. Figure 2 Shown Figure 1 Schematic diagram of the structure of the first space layer and the second space layer.

[0049] like Figure 1 and Figure 2As shown, the infrared LED epitaxial structure of the embodiment of the present disclosure includes, from bottom to top, a substrate 101, a buffer layer 102, an etching stop layer 103, a first semiconductor layer, a first space layer 107, a multi-quantum well layer 108, a second space layer 109 and a second semiconductor layer, wherein the doping types of the first semiconductor layer and the second semiconductor layer are opposite. In this embodiment, the doping type of the first semiconductor layer is N-type, the doping type of the second semiconductor layer is P-type, and the first space layer 107 and the second space layer 109 are both unintentionally doped layers.

[0050] The first and second space layers 107 and 109 form a superlattice structure, with the highest Al composition in each layer of the first space layer 107 being lower than the highest Al composition in each layer of the second space layer 109. By providing the first and second space layers 107 and 109 of the superlattice structure on the n-side and p-side of the multi-quantum well layer 108, respectively, the asymmetric space layers can increase the height of the effective potential barrier, suppress carrier overflow, and enhance the quantum confinement effect on carriers. Furthermore, due to the tunneling characteristics of the superlattice, carrier mobility is also improved. Furthermore, the asymmetric design effectively reduces carrier overflow from the multi-quantum wells, improves the light field distribution, and enhances the photoelectric efficiency and reliability of the infrared light-emitting diode.

[0051] In this embodiment, the buffer layer 102 is adjacent to the substrate 101 , which can reduce defects and dislocations in the epitaxial structure caused by surface defects of the substrate 101 and provide a high-quality growth surface for the structural layer above the buffer layer 102 .

[0052] In some preferred embodiments, the substrate 101 is a GaAs substrate, and the doping type of the substrate 101 is N-type, but not limited thereto. The thickness of the buffer layer 102 ranges from 300 nm to 800 nm, and the material of the buffer layer 102 is, for example, GaAs, and the doping type of the buffer layer 102 is, for example, N-type. For example, the doping impurity in the buffer layer 102 is Si, and the doping concentration ranges from 1.0×10 18 cm -3 ~4.0×10 18 cm -3 In some specific embodiments, the thickness of the buffer layer 102 is 500 nm, and the doping concentration of the buffer layer 102 is 2.0×10 18 cm -3 .

[0053] In this embodiment, the etching stop layer 103 is used to remove the substrate 101 and the buffer layer 102 in conjunction with the reverse polarity infrared light emitting diode process, thereby preparing a reverse polarity infrared light emitting diode with N-side light output, which has higher photoelectric efficiency than the positive polarity infrared light emitting diode with P-side light output.

[0054] In some preferred embodiments, the thickness of the corrosion stop layer 103 ranges from 100 nm to 500 nm, the material of the corrosion stop layer 103 is, for example, GaInP, and the doping type of the corrosion stop layer 103 is, for example, N-type. For example, the doping impurity in the corrosion stop layer 103 is Si, and the doping concentration ranges from 4.0×10 18 cm -3 ~8.0×10 18 cm -3 In some specific embodiments, the thickness of the corrosion stop layer 103 is 200 nm, and the doping concentration of the corrosion stop layer 103 is 7.0×10 18 cm -3 .

[0055] In this embodiment, the first semiconductor layer includes, from bottom to top, a first ohmic contact layer 104, a first current spreading layer 105, and a first confinement layer 106. The first ohmic contact layer 104 is located on the etching stop layer 103. The first ohmic contact layer 104 provides ohmic contact between the N-electrode and the first semiconductor layer, thereby producing a reverse-polarity infrared light-emitting diode (IRLED) with N-side emission. The first current spreading layer 105 is used to coordinate with the roughening process of the reverse-polarity IRLED to enhance product brightness. The first confinement layer 106 provides electrons and confines the light field distribution.

[0056] In some preferred embodiments, the thickness of the first ohmic contact layer 104 ranges from 50 nm to 200 nm. The material of the first ohmic contact layer 104 is, for example, GaAs. The doping type of the first ohmic contact layer 104 is, for example, N-type. For example, the doping impurity in the first ohmic contact layer 104 is Si, and the doping concentration ranges from 5.0×10 18 cm -3 ~2.0×10 19 cm -3 In some specific embodiments, the thickness of the first ohmic contact layer 104 is 100 nm, and the doping concentration of the first ohmic contact layer 104 is 1.0×10 19 cm -3 .

[0057] In some preferred embodiments, the thickness of the first current spreading layer 105 ranges from 3 μm to 10 μm, and the material of the first current spreading layer 105 is, for example, Al g Ga 1-g As,g ranges from 0.1 to 0.4, and the doping type of the first current spreading layer 105 is, for example, N-type. For example, the doping impurity in the first current spreading layer 105 is Si, and the doping concentration range includes 1.0×10 18 cm -3 ~4.0×10 18 cm -3In some specific embodiments, the first current spreading layer 105 is an Al layer with a thickness of 8 μm. 0.15 Ga 0.85 As layer, its doping concentration is 2.0×10 18 cm -3 .

[0058] In some preferred embodiments, the thickness of the first confinement layer 106 ranges from 200 to 600 nm. The material of the first confinement layer 106 is, for example, Al. h Ga 1-h As,h ranges from 0.1 to 0.4, and the doping type of the first confinement layer 106 is, for example, N-type. For example, the doping impurity in the first confinement layer 106 is Si, and the doping concentration range includes 1.0×10 18 cm -3 ~4.0×10 18 cm -3 In some specific embodiments, the first confinement layer 106 is an Al2O3 layer having a thickness of 500 nm. 0.2 Ga 0.8 As layer, its doping concentration is 2.0×10 18 cm -3 .

[0059] In this embodiment, the first spatial layer 107 is an unintentionally doped layer, meaning that no impurity elements are doped into the first spatial layer 107. The first spatial layer 107 includes a first waveguide layer 201 and a first superlattice layer 202. The first waveguide layer 201 is located on the first confinement layer 106, and the first superlattice layer 202 is located on the first waveguide layer 201. The first waveguide layer 201 and the second waveguide layer 204, described later, are used to control the light field distribution. Specifically, carriers recombine and emit light in the multi-quantum well layer 108. Due to the different effective masses and velocities of electrons and holes, the location of recombination in the multi-quantum well layer 108 depends on the thickness of the first spatial layer 107 and the second spatial layer 109. The first waveguide layer 201 and the second waveguide layer 204 are used to control the light field distribution, ensuring that carriers recombine within the multi-quantum well layer 108 rather than forming non-radiative recombination outside the multi-quantum well layer 108.

[0060] In some preferred embodiments, the first waveguide layer 201 is Al a Ga 1-a As layer, the first superlattice layer 202 is Al b Ga 1-b As / Al c Ga 1-c As stack. The thickness of the first waveguide layer 201 ranges from 100nm to 600nm, and Al b Ga 1-b As / Alc Ga 1-c The number of periods N1 of the As stack is 2 to 6, the thickness range of a single period includes 4 nm to 20 nm, b>a and b>c, optionally, the value ranges of a and c both include 0.1 to 0.2, and the value range of b includes 0.2 to 0.3.

[0061] In some specific embodiments, the first waveguide layer 201 is an Al2O3 layer having a thickness of 400 nm. 0.1 Ga 0.9 As layer. The first superlattice layer 202 is Al with a period number of 4. 0.25 Ga 0.75 As / Al 0.1 Ga 0.9 As stack, in which Al 0.25 Ga 0.75 The thickness of the As layer is 4 nm, and the Al 0.1 Ga 0.9 The thickness of the As layer is 10 nm, and the total thickness of the first space layer 107 is 456 nm.

[0062] In this embodiment, the multi-quantum well layer 108 adopts a multi-quantum well structure in which well layers and barrier layers are alternately grown with a period number N3.

[0063] In some preferred embodiments, the period number N3 of the multi-quantum well layer 108 ranges from 3 to 15. x Ga 1-x As layer, and the range of x includes 0 to 0.5, and the single layer thickness of the well layer ranges from 4 to 15 nm. The barrier layer is Al y Ga 1- y As z P 1-z layer, and the range of y includes 0 to 0.4, the range of z includes 0.5 to 1, and the single layer thickness of the barrier layer ranges from 5 to 50 nm. In an optional embodiment, the barrier layer is GaAs z P 1-z layer, i.e. y=0.

[0064] In some specific embodiments, the period number of the multi-quantum well layer 108 is 6, and the well layer is 10 nm thick In 0.1 Ga 0.9 As layer, barrier layer is 25nm thick GaAs 0.95 P 0.05 layer.

[0065] In this embodiment, the second spatial layer 109 is an unintentionally doped layer, that is, no impurity elements are doped in the second spatial layer 109. The second spatial layer 109 includes a second waveguide layer 204 and a second superlattice layer 203. The second superlattice layer 203 is located on the multiple quantum well layer 108, and the second waveguide layer 204 is located on the second superlattice layer 203.

[0066] In some preferred embodiments, the second waveguide layer 204 is an Al d Ga 1-d As layer, and the second superlattice layer 203 is an Al e Ga 1-e As / Al f Ga 1-f As stack. The thickness range of the second waveguide layer 204 includes 100 nm to 600 nm. The number of periods N2 of the Al e Ga 1-e As / Al f Ga 1-f As stack is 2 to 6, and the single-period thickness range includes 4 nm to 20 nm. f > d and f > e. Optionally, the ranges of both d and e include 0.1 to 0.25, and the value range of f includes 0.25 to 0.4. Among them, the highest Al component in each layer of the first spatial layer 107 is less than the highest Al component in each layer of the second spatial layer 109, that is, b < f. Preferably, the single-period thickness in the first superlattice layer 202 is not greater than the single-period thickness in the second superlattice layer 203, and the total thickness of the first spatial layer 107 is not greater than the total thickness of the second spatial layer 109.

[0067] In some specific embodiments, the second waveguide layer 204 is an Al 0.2 Ga 0.8 As layer with a thickness of 500 nm. The second superlattice layer 203 is an Al 0.2 Ga 0.8 As / Al 0.35 Ga 0.65 As stack with 4 periods. Among them, the thickness of Al 0.2 Ga 0.8 As is 15 nm, and the thickness of Al 0.35 Ga 0.65 As is 6 nm. The total thickness of the second spatial layer 109 is 584 nm.

[0068] The first space layer 107 and the second space layer 109 are set to a structure with an asymmetric Al composition, wherein the highest Al composition in the second space layer 109 located on the p-side is greater than the highest Al composition in the first space layer 107 located on the n-side, so that the potential barrier of the second space layer 109 located on the p-side is higher, thereby effectively enhancing the quantum confinement effect, suppressing the overflow of electrons, and further enhancing the recombination probability of carriers, thereby improving the photoelectric efficiency and reliability of the infrared light-emitting diode.

[0069] If the potential barrier is increased simply by increasing the Al composition, the operating voltage will increase. Therefore, the first space layer 107 and the second space layer 109 disclosed in the present invention are both formed by a superlattice structure that is conducive to reducing the operating voltage. The high Al composition layers and the low Al composition layers are stacked alternately to ensure the original quantum confinement effect. The Al composition of the first space layer 107 located on the n-side is lower, so the potential barrier of the first space layer 107 is lower, thereby reducing the operating voltage.

[0070] Since the first space layer 107 and the second space layer 109 are both superlattice structures, in the superlattice structure, since the thickness of each layer is relatively thin, a tunnel effect is generated, which improves the carrier mobility and reduces the resistivity and the operating voltage.

[0071] Furthermore, since carriers will diffuse toward the multi-quantum well layer 108 due to concentration differences, and the diffusion lengths of P-type doping and N-type doping are different, in order to prevent carriers from diffusing into the multi-quantum well layer, the first space layer 107 and the second space layer 109 are respectively set to appropriate thicknesses. Preferably, the thickness of the first space layer 107 is not greater than the thickness of the second space layer 109, so as to allow electrons and holes to recombine and emit light in the multi-quantum well layer as much as possible, thereby effectively controlling the light field distribution.

[0072] In this embodiment, the second semiconductor layer includes, from bottom to top, a second confinement layer 110, a second current spreading layer 111, a transition layer 112, and a second ohmic contact layer 113. The second confinement layer 110 is located on the second space layer 109. The second confinement layer 110 is used to provide holes and limit the light field distribution. The second current spreading layer 111 is used to spread the current laterally, reducing the operating voltage of the infrared light-emitting diode. The second ohmic contact layer 113 is used to provide ohmic contact between the P-electrode and the second semiconductor layer.

[0073] In this embodiment, the first confinement layer 106 and the second confinement layer 110 serve as confinement layers for two main functions: on the one hand, they restrict minority carriers from overflowing the multi-quantum well layer 108, thereby improving the composite luminescence efficiency; on the other hand, they serve as an important window, allowing photons emitted by the multi-quantum well layer 108 to easily pass through the confinement layers, thereby improving the luminescence efficiency of the infrared light-emitting diode.

[0074] In some preferred embodiments, the thickness of the second confinement layer 110 ranges from 200 to 600 nm. The material of the second confinement layer 110 is, for example, Al. j Ga 1-j As, and j ranges from 0.1 to 0.4, and the doping type of the second confinement layer 110 is, for example, P type. For example, the doping impurity in the second confinement layer 110 is C, and the doping concentration range includes 1.0×10 18 cm -3 ~4.0×10 18 cm -3 In some specific embodiments, the second confinement layer 110 is an Al2O3 layer having a thickness of 300 nm. 0.2 Ga 0.8 As layer, its doping concentration is 2.0×10 18 cm -3 .

[0075] In some preferred embodiments, the thickness of the second current spreading layer 111 ranges from 200 to 1500 nm, and the material of the second current spreading layer 111 is, for example, Al k Ga 1-k As,k range includes 0.1 to 0.4, and the doping type of the second current spreading layer 111 is, for example, P type. For example, the doping impurity in the second current spreading layer 111 is C, and the doping concentration range includes 1.0×10 18 cm -3 ~4.0×10 18 cm -3 In some specific embodiments, the second current spreading layer 111 is an Al2O3 layer having a thickness of 500 nm. 0.15 Ga 0.85 As layer, its doping concentration is 2.0×10 18 cm -3 .

[0076] In some preferred embodiments, the thickness of the transition layer 112 ranges from 10 to 60 nm, and the material of the transition layer 112 is a composition-gradient Ga n In 1-n The range of P and n includes 0.4 to 0.9, and the value of n increases as the distance from the second ohmic contact layer 113 decreases. The doping type of the transition layer 112 is, for example, P type, and the doping impurity is, for example, Mg, and the doping concentration range includes 4.0×10 18 cm -3 ~2.0×10 19 cm -3 In some specific embodiments, the transition layer 112 has a thickness of 50 nm and is composed of Ga 0.5 In 0.5 P gradually changes to Ga0.85 In 0.15 P, with a doping concentration of 4.0×10 18 ~8.0×10 18 cm -3 .

[0077] In some preferred embodiments, the thickness of the second ohmic contact layer 113 ranges from 20 to 150 nm, the material of the second ohmic contact layer 113 is GaP, and the doping type of the second ohmic contact layer 113 is, for example, P-type. For example, the doping impurity in the second ohmic contact layer 113 is C, and the doping concentration is greater than 2.0×10 19 cm -3 In some specific embodiments, the thickness of the second ohmic contact layer 113 is 100 nm, and the doping concentration of the second ohmic contact layer 113 is 5.0×10 19 cm -3 .

[0078] The embodiment of the present disclosure also provides a method for preparing an infrared LED epitaxial structure, comprising: sequentially forming a buffer layer 102, an etching stop layer 103, a first semiconductor layer, a first space layer 107, a multi-quantum well layer 108, a second space layer 109, and a second semiconductor layer on a substrate 101, wherein the doping types of the first semiconductor layer and the second semiconductor layer are opposite. In this embodiment, the doping type of the first semiconductor layer is N-type, the doping type of the second semiconductor layer is P-type, and both the first space layer 107 and the second space layer 109 are unintentionally doped layers.

[0079] The first and second space layers 107 and 109 form a superlattice structure, with the highest Al composition in each layer of the first space layer 107 being lower than the highest Al composition in each layer of the second space layer 109. By providing the first and second space layers 107 and 109 of the superlattice structure on the n-side and p-side of the multi-quantum well layer 108, respectively, the asymmetric space layers can increase the height of the effective potential barrier, suppress carrier overflow, and enhance the quantum confinement effect on carriers. Furthermore, due to the tunneling characteristics of the superlattice, carrier mobility is also improved. Furthermore, the asymmetric design effectively reduces carrier overflow from the multi-quantum wells, improves the light field distribution, and enhances the photoelectric efficiency and reliability of the infrared light-emitting diode.

[0080] The preparation process of the infrared LED epitaxial structure disclosed in the present invention is any one of MOCVD process, molecular beam epitaxy process, HVPE process, plasma-assisted chemical vapor deposition and sputtering, preferably MOCVD process. The following specific embodiments use MOCVD process as an example for description.

[0081] In this embodiment, the buffer layer 102 is adjacent to the substrate 101 , which can reduce defects and dislocations in the epitaxial structure caused by surface defects of the substrate 101 and provide a high-quality growth surface for the structural layer above the buffer layer 102 .

[0082] In some preferred embodiments, the substrate 101 is a GaAs substrate, and the doping type of the substrate 101 is N-type, but not limited thereto. The growth temperature range of the buffer layer 102 includes 600°C to 700°C, the thickness range of the buffer layer 102 includes 300nm to 800nm, the material of the buffer layer 102 is, for example, GaAs, and the doping type of the buffer layer 102 is, for example, N-type. For example, the doping impurity in the buffer layer 102 is Si, and the doping concentration range includes 1.0×10 18 cm -3 ~4.0×10 18 cm -3 In some specific embodiments, the growth temperature of the buffer layer 102 is 650° C., the thickness of the buffer layer 102 is 500 nm, and the doping concentration of the buffer layer 102 is 2.0×10 18 cm -3 .

[0083] In this embodiment, the etching stop layer 103 is used to remove the substrate 101 and the buffer layer 102 in conjunction with the reverse polarity infrared light emitting diode process, thereby preparing a reverse polarity infrared light emitting diode with N-side light output, which has higher photoelectric efficiency than the positive polarity infrared light emitting diode with P-side light output.

[0084] In some preferred embodiments, the growth temperature of the etch stop layer 103 ranges from 650° C. to 750° C., the thickness of the etch stop layer 103 ranges from 100 nm to 500 nm, the material of the etch stop layer 103 is, for example, GaInP, and the doping type of the etch stop layer 103 is, for example, N-type. For example, the doping impurity in the etch stop layer 103 is Si, and the doping concentration ranges from 4.0×10 18 cm -3 ~8.0×10 18 cm -3 In some specific embodiments, the growth temperature of the corrosion stop layer 103 is 680° C., the thickness of the corrosion stop layer 103 is 200 nm, and the doping concentration of the corrosion stop layer 103 is 7.0×10 18 cm -3 .

[0085] In this embodiment, forming the first semiconductor layer includes forming, from bottom to top, a first ohmic contact layer 104, a first current spreading layer 105, and a first confinement layer 106. The first ohmic contact layer 104 is located on the etching stop layer 103. The first ohmic contact layer 104 provides ohmic contact between the N-electrode and the first semiconductor layer, thereby producing a reverse-polarity infrared light-emitting diode (IRLED) with N-side emission. The first current spreading layer 105 is used to coordinate with the roughening process of the reverse-polarity infrared light-emitting diode to enhance product brightness. The first confinement layer 106 provides electrons and confines the light field distribution.

[0086] In some preferred embodiments, the growth temperature of the first ohmic contact layer 104 ranges from 600° C. to 700° C., the thickness of the first ohmic contact layer 104 ranges from 50 nm to 200 nm, the material of the first ohmic contact layer 104 is, for example, GaAs, and the doping type of the first ohmic contact layer 104 is, for example, N-type. For example, the doping impurity in the first ohmic contact layer 104 is Si, and the doping concentration ranges from 5.0×10 18 cm -3 ~2.0×10 19 cm -3 In some specific embodiments, the growth temperature of the first ohmic contact layer 104 is 650° C., the thickness of the first ohmic contact layer 104 is 100 nm, and the doping concentration of the first ohmic contact layer 104 is 1.0×10 19 cm -3 .

[0087] In some preferred embodiments, the growth temperature range of the first current spreading layer 105 includes 650° C. to 750° C., the thickness range of the first current spreading layer 105 includes 3 to 10 μm, and the material of the first current spreading layer 105 is, for example, Al g Ga 1- g As,g ranges from 0.1 to 0.4, and the doping type of the first current spreading layer 105 is, for example, N-type. For example, the doping impurity in the first current spreading layer 105 is Si, and the doping concentration range includes 1.0×10 18 cm -3 ~4.0×10 18 cm -3 In some specific embodiments, the growth temperature of the first current spreading layer 105 is 700° C., and the first current spreading layer 105 is Al with a thickness of 8 μm. 0.15 Ga 0.85 As layer, its doping concentration is 2.0×10 18 cm -3 .

[0088] In some preferred embodiments, the growth temperature of the first confinement layer 106 ranges from 650° C. to 750° C., the thickness of the first confinement layer 106 ranges from 200 nm to 600 nm, and the material of the first confinement layer 106 is, for example, Al h Ga 1-h As,h ranges from 0.1 to 0.4, and the doping type of the first confinement layer 106 is, for example, N-type. For example, the doping impurity in the first confinement layer 106 is Si, and the doping concentration range includes 1.0×10 18 cm -3 ~4.0×10 18 cm -3 In some specific embodiments, the growth temperature of the first confinement layer 106 is 700° C., and the first confinement layer 106 is Al with a thickness of 500 nm. 0.2 Ga 0.8 As layer, its doping concentration is 2.0×10 18 cm -3 .

[0089] In this embodiment, the first spatial layer 107 is an unintentionally doped layer, meaning that no impurity elements are doped into the first spatial layer 107. The first spatial layer 107 includes a first waveguide layer 201 and a first superlattice layer 202. The first waveguide layer 201 is located on the first confinement layer 106, and the first superlattice layer 202 is located on the first waveguide layer 201. The first waveguide layer 201 and the second waveguide layer 204, described later, are used to control the light field distribution. Specifically, carriers recombine and emit light in the multi-quantum well layer 108. Due to the different effective masses and velocities of electrons and holes, the location of recombination in the multi-quantum well layer 108 depends on the thickness of the first spatial layer 107 and the second spatial layer 109. The first waveguide layer 201 and the second waveguide layer 204 are used to control the light field distribution, ensuring that carriers recombine within the multi-quantum well layer 108 rather than forming non-radiative recombination outside the multi-quantum well layer 108.

[0090] In some preferred embodiments, the growth temperature of the first space layer 107 is in the range of 650°C to 750°C, and the first waveguide layer 201 is Al a Ga 1-a As layer, the first superlattice layer 202 is Al b Ga 1-b As / Al c Ga 1-c As stack. The thickness of the first waveguide layer 201 ranges from 100nm to 600nm, and Al b Ga 1-b As / Al c Ga 1-cThe number of periods N1 of the As stack is 2 to 6, the thickness range of a single period includes 4 nm to 20 nm, b>a and b>c, optionally, the value ranges of a and c both include 0.1 to 0.2, and the value range of b includes 0.2 to 0.3.

[0091] In some specific embodiments, the growth temperature of the first waveguide layer 201 is 700° C., and the first waveguide layer 201 is Al with a thickness of 400 nm. 0.1 Ga 0.9 The growth temperature of the first superlattice layer 202 is 700°C. The first superlattice layer 202 is an Al layer with a period number of 4. 0.25 Ga 0.75 As / Al 0.1 Ga 0.9 As stack, in which Al 0.25 Ga 0.75 The thickness of the As layer is 4 nm, and the Al 0.1 Ga 0.9 The thickness of the As layer is 10 nm, and the total thickness of the first space layer 107 is 456 nm.

[0092] In this embodiment, the multi-quantum well layer 108 adopts a multi-quantum well structure in which well layers and barrier layers are alternately grown with a period number N3.

[0093] In some preferred embodiments, the growth temperature of the multi-quantum well layer 108 ranges from 550° C. to 650° C., and the period number N3 of the multi-quantum well layer 108 ranges from 3 to 15. x Ga 1-x As layer, and the range of x includes 0 to 0.5, and the single layer thickness of the well layer ranges from 4 to 15 nm. The barrier layer is Al y Ga 1-y As z P 1-z layer, and the range of y includes 0 to 0.4, the range of z includes 0.5 to 1, and the single layer thickness of the barrier layer ranges from 5 to 50 nm. In an optional embodiment, the barrier layer is GaAs z P 1-z layer, i.e. y=0.

[0094] In some specific embodiments, the growth temperature of the multi-quantum well layer 108 is 600° C., the period number of the multi-quantum well layer 108 is 6, and the well layer is 10 nm thick In 0.1 Ga 0.9 As layer, barrier layer is 25nm thick GaAs 0.95 P 0.05 layer.

[0095] In this embodiment, the second spatial layer 109 is an unintentionally doped layer, that is, no impurity elements are doped in the second spatial layer 109. The second spatial layer 109 includes a second waveguide layer 204 and a second superlattice layer 203. The second superlattice layer 203 is located on the multiple quantum well layer 108, and the second waveguide layer 204 is located on the second superlattice layer 203.

[0096] In some preferred embodiments, the growth temperature range of the second spatial layer 109 includes 650 °C to 750 °C. The second waveguide layer 204 is an Al d Ga 1-d As layer, and the second superlattice layer 203 is an Al e Ga 1-e As / Al f Ga 1-f As stack. The thickness range of the second waveguide layer 204 includes 100 nm to 600 nm. The period number N2 of the Al e Ga 1-e As / Al f Ga 1-f As stack is 2 to 6. The single-period thickness range includes 4 nm to 20 nm. f > d and f > e. Optionally, the ranges of both d and e include 0.1 to 0.25, and the value range of f includes 0.25 to 0.4. Among them, the highest Al component in each layer of the first spatial layer 107 is less than the highest Al component in each layer of the second spatial layer 109, that is, b < f. Preferably, the single-period thickness in the first superlattice layer 202 is not greater than the single-period thickness in the second superlattice layer 203, and the total thickness of the first spatial layer 107 is not greater than the total thickness of the second spatial layer 109.

[0097] In some specific embodiments, the growth temperature of the second waveguide layer 204 is 700 °C, and the second waveguide layer 204 is an Al 0.2 Ga 0.8 As layer with a thickness of 500 nm. The growth temperature of the second superlattice layer 203 is 700 °C, and the second superlattice layer 20:3 is an Al 0.2 Ga 0.8 As / Al 0.35 Ga 0.65 As stack with a period number of 4. Among them, the thickness of Al 0.2 Ga 0.8 As is 15 nm, and the thickness of Al 0.35 Ga 0.65 As is 6 nm. The total thickness of the second spatial layer 109 is 584 nm.

[0098] The first space layer 107 and the second space layer 109 are set to a structure with an asymmetric Al composition, wherein the highest Al composition in the second space layer 109 located on the p-side is greater than the highest Al composition in the first space layer 107 located on the n-side, so that the potential barrier of the second space layer 109 located on the p-side is higher, thereby effectively enhancing the quantum confinement effect, suppressing the overflow of electrons, and further enhancing the recombination probability of carriers, thereby improving the photoelectric efficiency and reliability of the infrared light-emitting diode.

[0099] If the potential barrier is increased simply by increasing the Al composition, the operating voltage will increase. Therefore, the first space layer 107 and the second space layer 109 disclosed in the present invention are both formed by a superlattice structure that is conducive to reducing the operating voltage. The high Al composition layers and the low Al composition layers are stacked alternately to ensure the original quantum confinement effect. The Al composition of the first space layer 107 located on the n-side is lower, so the potential barrier of the first space layer 107 is lower, thereby reducing the operating voltage.

[0100] Since the first space layer 107 and the second space layer 109 are both superlattice structures, in the superlattice structure, since the thickness of each layer is relatively thin, a tunnel effect is generated, which improves the carrier mobility and reduces the resistivity and the operating voltage.

[0101] Furthermore, since carriers will diffuse toward the multi-quantum well layer 108 due to concentration differences, and the diffusion lengths of P-type doping and N-type doping are different, in order to prevent carriers from diffusing into the multi-quantum well layer, the first space layer 107 and the second space layer 109 are respectively set to appropriate thicknesses. Preferably, the thickness of the first space layer 107 is not greater than the thickness of the second space layer 109, so as to allow electrons and holes to recombine and emit light in the multi-quantum well layer as much as possible, thereby effectively controlling the light field distribution.

[0102] In this embodiment, forming the second semiconductor layer includes sequentially forming, from bottom to top, a second confinement layer 110, a second current spreading layer 111, a transition layer 112, and a second ohmic contact layer 113. The second confinement layer 110 is located on the second space layer 109. The second confinement layer 110 is used to provide holes and limit the light field distribution. The second current spreading layer 111 is used to spread the current laterally, reducing the operating voltage of the infrared light-emitting diode. The second ohmic contact layer 113 is used to provide ohmic contact between the P-electrode and the second semiconductor layer.

[0103] In this embodiment, the first confinement layer 106 and the second confinement layer 110 serve as confinement layers for two main functions: on the one hand, they restrict minority carriers from overflowing the multi-quantum well layer 108, thereby improving the composite luminescence efficiency; on the other hand, they serve as an important window, allowing photons emitted by the multi-quantum well layer 108 to easily pass through the confinement layers, thereby improving the luminescence efficiency of the infrared light-emitting diode.

[0104] In some preferred embodiments, the growth temperature range of the second confinement layer 110 includes 650° C. to 750° C., the thickness range of the second confinement layer 110 includes 200 to 600 nm, and the material of the second confinement layer 110 is, for example, Al j Ga 1-j As, and j ranges from 0.1 to 0.4, and the doping type of the second confinement layer 110 is, for example, P type. For example, the doping impurity in the second confinement layer 110 is C, and the doping concentration range includes 1.0×10 18 cm -3 ~4.0×10 18 cm -3 In some specific embodiments, the growth temperature of the second confinement layer 110 is 700° C., and the second confinement layer 110 is Al with a thickness of 300 nm. 0.2 Ga 0.8 As layer, its doping concentration is 2.0×10 18 cm -3 .

[0105] In some preferred embodiments, the growth temperature range of the second current spreading layer 111 includes 650° C. to 750° C., the thickness range of the second current spreading layer 111 includes 200 to 1500 nm, and the material of the second current spreading layer 111 is, for example, Al k Ga 1-k As,k range includes 0.1 to 0.4, and the doping type of the second current spreading layer 111 is, for example, P type. For example, the doping impurity in the second current spreading layer 111 is C, and the doping concentration range includes 1.0×10 18 cm -3 ~4.0×10 18 cm -3 In some specific embodiments, the growth temperature of the second current spreading layer 111 is 700° C., and the second current spreading layer 111 is Al with a thickness of 500 nm. 0.15 Ga 0.85 As layer, its doping concentration is 2.0×10 18 cm -3 .

[0106] In some preferred embodiments, the growth temperature range of the transition layer 112 includes 550° C. to 650° C., the thickness range of the transition layer 112 includes 10 to 60 nm, and the material of the transition layer 112 is a composition-graded Ga n In 1-n The range of P and n includes 0.4 to 0.9, and the value of n increases as the distance from the second ohmic contact layer 113 decreases. The doping type of the transition layer 112 is, for example, P type, and the doping impurity is, for example, Mg, and the doping concentration range includes 4.0×1018 cm -3 ~2.0×10 19 cm -3 In some specific embodiments, the growth temperature range of the transition layer 112 is 620° C., the thickness of the transition layer 112 is 50 nm, and the transition layer 112 is GaN-containing. 0.5 In 0.5 P gradually changes to Ga 0.85 In 0.15 P, with a doping concentration of 4.0×10 18 ~8.0×10 18 cm -3 .

[0107] In some preferred embodiments, the growth temperature of the second ohmic contact layer 113 ranges from 500° C. to 600° C., the thickness of the second ohmic contact layer 113 ranges from 20 nm to 150 nm, the material of the second ohmic contact layer 113 is GaP, and the doping type of the second ohmic contact layer 113 is, for example, P-type. For example, the doping impurity in the second ohmic contact layer 113 is C, and the doping concentration is greater than 2.0×10 19 cm -3 In some specific embodiments, the growth temperature range of the second ohmic contact layer 113 includes 550° C., the thickness of the second ohmic contact layer 113 is 100 nm, and the doping concentration of the second ohmic contact layer 113 is 5.0×10 19 cm -3 .

[0108] Compared with the traditional infrared LED epitaxial structure, the voltage of the infrared light-emitting diode prepared by using the infrared LED epitaxial structure with the asymmetric space layer in this embodiment is reduced by about 0.03V on average, and the brightness is increased by 5% to 8%.

[0109] According to the infrared LED epitaxial structure and preparation method provided by the embodiments of the present disclosure, by respectively arranging the first spatial layer and the second spatial layer of the superlattice structure on both sides (n-side and p-side) of the multi-quantum well layer, the first spatial layer and the second spatial layer are set to an asymmetric structure, wherein the highest Al component in the second spatial layer located on the p-side is greater than the highest Al component in the first spatial layer located on the n-side, so that the potential barrier of the second spatial layer located on the p-side is higher, thereby effectively enhancing the quantum confinement effect, suppressing the overflow of electrons, and thereby enhancing the recombination probability of carriers, thereby improving the photoelectric efficiency and reliability of the infrared light-emitting diode.

[0110] If the potential barrier is increased simply by increasing the Al composition, the operating voltage will increase. Therefore, the first space layer and the second space layer disclosed in the present invention are both formed by a superlattice structure that is conducive to reducing the operating voltage. The high Al composition layers and the low Al composition layers are stacked alternately to ensure the original quantum confinement effect. The Al composition of the first space layer located on the n-side is lower, so the potential barrier of the first space layer is lower, thereby reducing the operating voltage.

[0111] Furthermore, in the superlattice structure, due to the thin thickness of each layer, a tunnel effect is generated, which improves the carrier mobility and reduces the resistivity and operating voltage.

[0112] Furthermore, since carriers will diffuse toward the multi-quantum well layer due to concentration differences, and the diffusion lengths of P-type doping and N-type doping are different, in order to prevent carriers from diffusing into the multi-quantum well layer, the first space layer and the second space layer are set to appropriate thicknesses, preferably, the thickness of the first space layer is not greater than the thickness of the second space layer, so as to allow electrons and holes to recombine and emit light in the multi-quantum well layer as much as possible, thereby effectively controlling the light field distribution.

[0113] In addition, it is understood that although the present disclosure has been disclosed above with preferred embodiments, the above embodiments are not intended to limit the present disclosure. For any person skilled in the art, without departing from the scope of the technical solution of the present disclosure, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present disclosure, or to modify it into an equivalent embodiment with equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present disclosure without departing from the content of the technical solution of the present disclosure still falls within the scope of protection of the technical solution of the present disclosure.

[0114] It should also be understood that the present disclosure is not limited to the specific methods, compounds, materials, manufacturing techniques, uses, and applications described herein, which may vary. It should also be understood that the terms described herein are used only to describe specific embodiments and are not intended to limit the scope of the present disclosure. It should be noted that the singular forms "a," "an," and "the" used herein and in the appended claims include plural references unless the context clearly indicates otherwise. Thus, for example, a reference to "a step" means a reference to one or more steps, and may include secondary steps. All conjunctions used should be understood in their broadest sense. Thus, the word "or" should be understood to have the definition of a logical "or" rather than a logical "exclusive or" unless the context clearly indicates otherwise. Structures described herein will be understood to also refer to functional equivalents of the structures. Language that can be interpreted as approximating should be understood as such unless the context clearly indicates otherwise.

Claims

1. An infrared LED epitaxial structure, comprising: a substrate, a first semiconductor layer, a first space layer, a multi-quantum well layer, a second space layer, and a second semiconductor layer stacked in sequence from bottom to top, wherein the first semiconductor layer and the second semiconductor layer have opposite doping types. in, The first space layer and the second space layer are both superlattice structures, and the highest Al composition in each layer of the first space layer is smaller than the highest Al composition in each layer of the second space layer so that the first space layer and the second space layer form an asymmetric structure. The single-period thickness of the superlattice layer in the first space layer is not greater than the single-period thickness of the superlattice layer in the second space layer.

2. The infrared LED epitaxial structure according to claim 1, wherein: The thickness of the first space layer is not greater than the thickness of the second space layer.

3. The infrared LED epitaxial structure according to claim 1, wherein: The first spatial layer includes: a first waveguide layer located on the first semiconductor layer; and The first superlattice layer is located between the first waveguide layer and the multi-quantum well layer.

4. The infrared LED epitaxial structure according to claim 3, wherein: The first waveguide layer is Al a Ga 1-a As layer, the first superlattice layer is Al b Ga 1-b As / Al c Ga 1-c As stack, Among them, b>a and b>c, the value range of a includes 0.1~0.2, the value range of b includes 0.2~0.3, and the value range of c includes 0.1~0.

2.

5. The infrared LED epitaxial structure according to claim 3, wherein: The number of periods of the first superlattice layer is 2-6, the thickness of a single period ranges from 4 nm to 20 nm, and the thickness of the first waveguide layer ranges from 100 nm to 600 nm.

6. The infrared LED epitaxial structure according to claim 1, wherein: The second spatial layer includes: a second superlattice layer located on the multi-quantum well layer; and The second waveguide layer is located between the second superlattice layer and the second semiconductor layer.

7. The infrared LED epitaxial structure according to claim 6, wherein: The second waveguide layer is Al d Ga 1-d As layer, the second superlattice layer is Al e Ga 1-e As / Al f Ga 1-f As stack, Among them, f>d and f>e, the value range of d includes 0.1~0.25, the value range of e includes 0.1~0.25, and the value range of f includes 0.25~0.

4.

8. The infrared LED epitaxial structure according to claim 6, wherein: The number of periods of the second superlattice layer is 2-6, the thickness of a single period ranges from 4 nm to 20 nm, and the thickness of the second waveguide layer ranges from 100 nm to 600 nm. 9 . The infrared LED epitaxial structure according to claim 1 , wherein the first semiconductor layer comprises a first ohmic contact layer, a first current spreading layer, and a first confinement layer, which are sequentially arranged from bottom to top.

10. The infrared LED epitaxial structure according to any one of claims 1 to 8, wherein: The second semiconductor layer includes a second confinement layer, a second current spreading layer, a transition layer and a second ohmic contact layer which are sequentially arranged from bottom to top.

11. A method for manufacturing an infrared LED epitaxial structure, comprising forming a first semiconductor layer, a first space layer, a multi-quantum well layer, a second space layer, and a second semiconductor layer in sequence from bottom to top on a substrate, wherein the first semiconductor layer and the second semiconductor layer have opposite doping types. in, The first space layer and the second space layer are both superlattice structures, and the highest Al composition in each layer of the first space layer is smaller than the highest Al composition in each layer of the second space layer so that the first space layer and the second space layer form an asymmetric structure. The single-period thickness of the superlattice layer in the first space layer is not greater than the single-period thickness of the superlattice layer in the second space layer.

12. The manufacturing method according to claim 11, wherein: The thickness of the first space layer is not greater than the thickness of the second space layer.

13. The manufacturing method according to claim 11, wherein: Forming the first space layer includes: forming a first waveguide layer on the first semiconductor layer; and A first superlattice layer is formed on the first waveguide layer, wherein the first superlattice layer is located between the first waveguide layer and the multi-quantum well layer.

14. The manufacturing method according to claim 13, wherein: The first waveguide layer is Al a Ga 1-a As layer, the first superlattice layer is Al b Ga 1-b As / Al c Ga 1-c As stack, Among them, b>a and b>c, the value range of a includes 0.1~0.2, the value range of b includes 0.2~0.3, and the value range of c includes 0.1~0.

2.

15. The manufacturing method according to claim 13, wherein: The number of periods of the first superlattice layer is 2-6, the thickness of a single period ranges from 4 nm to 20 nm, and the thickness of the first waveguide layer ranges from 100 nm to 600 nm.

16. The manufacturing method according to claim 11, wherein: Forming the second space layer includes: forming a second superlattice layer on the multi-quantum well layer; and A second waveguide layer is formed on the second superlattice layer, the second waveguide layer being located between the second superlattice layer and the second semiconductor layer.

17. The manufacturing method according to claim 16, wherein: The second waveguide layer is Al d Ga 1-d As layer, the second superlattice layer is Al e Ga 1-e As / Al f Ga 1-f As stack, Among them, f>d and f>e, the value range of d includes 0.1~0.25, the value range of e includes 0.1~0.25, and the value range of f includes 0.25~0.

4.

18. The manufacturing method according to claim 16, wherein: The number of periods of the second superlattice layer is 2-6, the thickness of a single period ranges from 4 nm to 20 nm, and the thickness of the second waveguide layer ranges from 100 nm to 600 nm.

19. The manufacturing method according to any one of claims 11 to 18, wherein: Forming the first semiconductor layer includes sequentially forming a first ohmic contact layer, a first current spreading layer, and a first confinement layer on the substrate from bottom to top.

20. The manufacturing method according to any one of claims 11 to 18, wherein: Forming the second semiconductor layer includes sequentially forming a second confinement layer, a second current spreading layer, a transition layer, and a second ohmic contact layer on the second space layer from bottom to top.

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