A driving circuit, a chip and an electronic device

Abstract

The application provides a driving circuit, a chip and an electronic device. A control port of a logic device in the driving circuit is connected with a first end of a first switch unit and a first end of a second switch unit respectively. A second end of the first switch unit is connected with a driving power supply, and a second end of the second switch unit is grounded. An anti-backflow unit is connected with a third end of the first switch unit and a third end of the second switch unit respectively. A wiring terminal is led out between the anti-backflow unit and the second switch unit, and is used as an output end of the driving circuit. A control signal input end of the anti-backflow unit and a control signal input end of the first switch unit are used for switching the driving circuit to a target driving mode when corresponding control signals are acquired. The target driving mode includes a drain open circuit driving mode and a push-pull output driving mode. The anti-backflow unit is arranged, so that current backflow and a large leakage current are avoided, and the logic device can output correct driving high level.

Description

Technical Field

[0001] This application relates to the field of chips, and more specifically, to a driving circuit, a chip, and an electronic device. Background Technology

[0002] Many commonly used chips require logic output drivers, necessitating the deployment of driver circuitry within the chip. Different adaptation protocols have different driver requirements, resulting in different compatible drivers. These drivers may be push-pull output drivers or open-drain drivers. To reduce chip development and design costs, a chip needs to be designed to support multiple protocol drivers. For example, to support different digital communication protocols, the output driver needs to support both push-pull and open-drain outputs.

[0003] When supporting open-drain drive output, an external power supply is required via a pull-up resistor. If the voltage of the external power supply is higher than the chip's drive power supply voltage, reverse current flow may occur. Therefore, designing a drive circuit that is compatible with both push-pull and open-drain drive outputs, while ensuring that reverse current flow does not occur in different voltage domains, has become a challenging problem of concern to those skilled in the art. Summary of the Invention

[0004] The purpose of this application is to provide a driving circuit, chip, and electronic device to at least partially improve the above-mentioned problems.

[0005] To achieve the above objectives, the technical solutions adopted in the embodiments of this application are as follows:

[0006] In a first aspect, embodiments of this application provide a driving circuit, the driving circuit including logic devices, a first switching unit, a second switching unit, and an anti-backflow unit;

[0007] The control port of the logic device is connected to the first end of the first switching unit and the first end of the second switching unit, respectively.

[0008] The second terminal of the first switching unit is connected to the driving power supply, the second terminal of the second switching unit is grounded, and the anti-backflow unit is connected to the third terminal of the first switching unit and the third terminal of the second switching unit, respectively.

[0009] A wiring terminal is led out between the anti-backflow unit and the second switch unit to serve as the output terminal of the drive circuit;

[0010] The control signal input terminal of the anti-backflow unit and the control signal input terminal of the first switching unit are used to switch the driving circuit to the target driving mode when the corresponding control signal is obtained. The target driving mode includes open-drain driving mode and push-pull output driving mode.

[0011] Optionally, the anti-backflow unit includes a first subunit and a second subunit;

[0012] The first end of the first sub-unit is connected to the third end of the first switching unit, the second end of the first sub-unit is connected to the third end of the second switching unit, the third end of the first sub-unit is connected to the second end of the second sub-unit, and the first end of the second sub-unit is connected to the driving power supply.

[0013] When the control signal corresponding to the push-pull output drive mode is received at the control signal input terminal of the anti-backflow unit and the control signal input terminal of the first switch unit, the second sub-unit switches to the normally on state to pull up the third terminal of the first sub-unit to the drive power supply so that the first sub-unit switches to the normally on state. The on / off state of the first switch unit is controlled by the trigger signal issued by the control port of the logic device to switch the drive circuit to the push-pull output drive mode.

[0014] When the control signal corresponding to the open-drain drive mode is received at the control signal input terminal of the anti-backflow unit and the control signal input terminal of the first switch unit, the second sub-unit switches to the normally off state, and the third terminal of the first sub-unit is connected to the output terminal of the drive circuit, so that the first sub-unit switches to the normally off state, the first switch unit switches to the normally off state, and the drive circuit is switched to the open-drain drive mode.

[0015] Optionally, the first sub-unit includes a second PMOS transistor, a third PMOS transistor, and a fourth PMOS transistor;

[0016] The first terminal of the fourth PMOS transistor is connected to the third terminal of the first sub-unit as the first terminal of the first switching unit.

[0017] The second terminal of the fourth PMOS transistor is connected to the third terminal of the second switching unit as the second terminal of the first sub-unit.

[0018] The substrate of the fourth PMOS transistor is connected to the first terminal of the third PMOS transistor, and the substrate of the third PMOS transistor is connected to the first terminal of the third PMOS transistor. A terminal is led out between the substrate of the fourth PMOS transistor and the first terminal of the third PMOS transistor, which serves as the third terminal of the first sub-unit and is connected to the second terminal of the second sub-unit. The second terminal of the third PMOS transistor is connected to the output terminal of the driving circuit.

[0019] The first terminal of the second PMOS transistor is connected to the output terminal of the driving circuit, the substrate of the second PMOS transistor is connected to the first terminal of the second PMOS transistor, and the second terminal of the second PMOS transistor is connected to the gate of the fourth PMOS transistor.

[0020] Optionally, the first sub-unit further includes a second NMOS transistor; the source of the second NMOS transistor is grounded, and the drain of the second NMOS transistor is connected to the gate of the fourth PMOS transistor; the gate of the second NMOS transistor, the gate of the second PMOS transistor, and the gate of the third PMOS transistor serve as control signal input terminals of the first sub-unit.

[0021] Optionally, the second sub-unit includes a fifth PMOS transistor, a sixth PMOS transistor, and a seventh PMOS transistor;

[0022] The source of the sixth PMOS transistor is connected to the driving power supply as the first terminal of the second sub-unit;

[0023] The first terminal of the fifth PMOS transistor is connected to the third terminal of the first sub-unit as the second terminal of the second sub-unit. The substrate of the fifth PMOS transistor is connected to the first terminal of the fifth PMOS transistor. The drain of the sixth PMOS transistor is connected to the second terminal of the fifth PMOS transistor.

[0024] The first terminal of the seventh PMOS transistor is connected between the first terminal of the fifth PMOS transistor and the third terminal of the first sub-unit. The substrate of the seventh PMOS transistor is connected to the first terminal of the seventh PMOS transistor, and the second terminal of the seventh PMOS transistor is connected to the gate of the fifth PMOS transistor.

[0025] Optionally, the second sub-unit further includes a third NMOS transistor; the source of the third NMOS transistor is grounded, and the drain of the third NMOS transistor is connected to the gate of the fifth PMOS transistor;

[0026] The gates of the third NMOS transistor, the seventh PMOS transistor, and the sixth PMOS transistor serve as the control signal input terminals of the second sub-unit.

[0027] Optionally, the first switching unit includes a first PMOS transistor and a NAND gate;

[0028] The source of the first PMOS transistor is connected to the driving power supply as the second terminal of the first switching unit, and the drain of the first PMOS transistor is connected to the anti-backflow unit as the third terminal of the first switching unit.

[0029] The first input terminal of the NAND gate is connected to the control port of the logic device as the first terminal of the first switching unit, the second input terminal of the NAND gate is connected to the control signal input terminal of the first switching unit, and the output terminal of the NAND gate is connected to the gate of the first PMOS transistor.

[0030] Optionally, the driving circuit further includes a state switching unit, the output terminal of which is connected to the control signal input terminal of the first switching unit and the control signal input terminal of the anti-backflow unit, respectively.

[0031] The input terminal of the state switching unit is used to receive the drive mode signal and output a corresponding control signal based on the drive mode signal to switch the state of the first switching unit and the anti-backflow unit so that the drive circuit switches to the target drive mode.

[0032] Optionally, the state switching unit includes a first inverter and a second inverter, wherein the output terminal of the first inverter is connected to the input terminal of the second inverter;

[0033] The input terminal of the first inverter serves as the input terminal of the state switching unit;

[0034] The output of the second inverter serves as the first output of the state switching unit;

[0035] A terminal is led out between the output terminal of the first inverter and the input terminal of the second inverter to serve as the second output terminal of the state switching unit;

[0036] The control signal input terminal of the first switching unit and the control signal input terminal of the anti-backflow unit are connected to the first output terminal and / or the second output terminal of the state switching unit.

[0037] Optionally, when the driving circuit is in open-drain driving mode, the output terminal of the driving circuit is also used to be connected in sequence to a pull-up resistor and an external power supply.

[0038] Secondly, embodiments of this application provide a chip, the chip including the driving circuit described in the first aspect.

[0039] Thirdly, embodiments of this application provide an electronic device, which includes the chip described in the second aspect.

[0040] Compared to existing technologies, the present application provides a driving circuit, chip, and electronic device, including a logic device, a first switching unit, a second switching unit, and an anti-backflow unit. The control port of the logic device is connected to the first terminals of the first and second switching units, respectively. The second terminal of the first switching unit is connected to a driving power supply, and the second terminal of the second switching unit is grounded. The anti-backflow unit is connected to the third terminals of both the first and second switching units. A terminal block is led out between the anti-backflow unit and the second switching unit as the output terminal of the driving circuit. The control signal input terminal of the anti-backflow unit and the control signal input terminal of the first switching unit are used to switch the driving circuit to a target driving mode when a corresponding control signal is received. The target driving mode includes an open-drain driving mode and a push-pull output driving mode. By setting the anti-backflow unit, current backflow and the generation of large leakage current are avoided, ensuring that the logic device outputs a correct high-level drive.

[0041] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0042] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0043] Figure 1 This is a connection diagram of a push-pull output driver provided in an embodiment of this application;

[0044] Figure 2 This is a connection diagram of an open-drain driver provided in an embodiment of this application;

[0045] Figure 3 A schematic diagram of a push-pull output and open-drain drive multiplexing circuit provided in an embodiment of this application;

[0046] Figure 4 This is a connection diagram of the driving circuit provided in an embodiment of this application;

[0047] Figure 5 This is a connection diagram of the anti-backflow unit provided in the embodiments of this application;

[0048] Figure 6 Another connection diagram of the driving circuit provided in the embodiments of this application;

[0049] Figure 7This is a connection diagram of the state switching unit provided in an embodiment of this application.

[0050] In the diagram: 10 - First switching unit; 20 - Second switching unit; 30 - Logic device; 40 - Anti-backflow unit; 401 - First sub-unit; 402 - Second sub-unit; 50 - State switching unit. Detailed Implementation

[0051] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0052] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0053] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this application, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0054] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0055] In the description of this application, it should be noted that the terms "upper", "lower", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship that the product of this application is usually placed in. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0056] In the description of this application, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set" and "connection" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0057] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0058] Please refer to Figure 1 and Figure 2 , Figure 1 This is a connection diagram of the push-pull output driver provided in an embodiment of this application. Figure 2 This is a connection diagram of an open-drain driver provided in an embodiment of this application. It should be understood that... Figure 1 The push-pull output driver shown features low power consumption and high speed; Figure 2 The open-drain driver shown often has an external pull-up resistor to enable wired-AND functionality.

[0059] When designing a chip that supports multiple protocol drivers, for example, to support different digital communication protocols, the output port VOUT needs to support both push-pull and open-drain drive outputs. For details, please refer to... Figure 3 , Figure 3 This is a schematic diagram of a push-pull output and open-drain drive multiplexing circuit provided in an embodiment of this application. It should be understood that in push-pull output mode, an external pull-up resistor is not required at the output port VOUT, while in open-drain drive mode, an external pull-up resistor can be provided at the output port VOUT.

[0060] Specifically, such as Figure 3 As shown, when MODE_CTRL = 0, the chip implements open-drain drive; when MODE_CTRL = 1, the chip implements push-pull output drive. The chip can support circuit designs with both drive outputs. However... Figure 3The method shown has a significant limitation. When MODE_CTRL = 0, in open-drain applications, the external power supply voltage connected to the pull-up resistor must be strictly limited to not exceeding the internal I / O power supply voltage of the chip. Otherwise, the PMOS may experience reverse current flow, resulting in a large backflow current and preventing the logic output from driving a high level correctly.

[0061] To overcome the above problems, embodiments of this application provide a driving circuit that can be deployed within a chip. Please refer to... Figure 4 , Figure 4 This is a connection diagram of the driving circuit provided in an embodiment of this application. Figure 4 As shown, the driving circuit includes a logic device 30, a first switching unit 10, a second switching unit 20, and an anti-backflow unit 40.

[0062] The control port of the logic device 30 is connected to the first terminal (a1) of the first switching unit 10 and the first terminal (b1) of the second switching unit 20, respectively.

[0063] The logic device 30 is used to issue a trigger signal, which is used to control the on / off state of the first switching unit 10 and the second switching unit 20, thereby controlling the output of the drive circuit.

[0064] The second terminal (a2) of the first switching unit 10 is connected to the driving power supply, the second terminal (b2) of the second switching unit 20 is grounded, and the anti-backflow unit 40 is connected to the third terminal (a3) ​​of the first switching unit 10 and the third terminal (b3) of the second switching unit 20 respectively.

[0065] A wiring terminal is led out between the anti-backflow unit 40 and the second switch unit 20 as the output terminal (VOUT) of the drive circuit.

[0066] The anti-backflow unit 40 is used to prevent the external high-voltage power supply connected to the terminal block from backflowing into the drive power supply.

[0067] The control signal input terminal of the anti-backflow unit 40 and the control signal input terminal (a4) of the first switching unit 10 are used to switch the drive circuit to the target drive mode when the corresponding control signal is obtained. The target drive mode includes the open drain drive mode and the push-pull output drive mode.

[0068] Optionally, when in open-drain drive mode, the anti-backflow unit 40 is in a normally off state, the first switching unit 10 is in a normally off state, the on / off state of the first switching unit 10 is not controlled by the trigger signal of the logic device 30, and the on / off state of the second switching unit 20 changes with the trigger signal of the logic device 30. For example, when the trigger signal is high, the second switching unit 20 is turned on, and when the trigger signal is low, the second switching unit 20 is turned off.

[0069] Because the anti-backflow unit 40 is in a normally off state, the external power supply will not backflow into the first switching unit 10 and the drive power supply, thereby avoiding the above-mentioned situation of current backflow and generating a large leakage current, and ensuring that the logic device 30 outputs the correct drive high level.

[0070] When in push-pull output drive mode, the anti-backflow unit 40 is in a normally on state, turning on the first switch unit 10 and the second switch unit 20. The on / off state of the first switch unit 10 and the second switch unit 20 changes with the trigger signal of the logic device 30.

[0071] In summary, this application provides a driving circuit including a logic device, a first switching unit, a second switching unit, and an anti-backflow unit. The control port of the logic device is connected to the first terminal of the first switching unit and the first terminal of the second switching unit, respectively. The second terminal of the first switching unit is connected to the driving power supply, and the second terminal of the second switching unit is grounded. The anti-backflow unit is connected to the third terminal of the first switching unit and the third terminal of the second switching unit, respectively. A terminal block is led out between the anti-backflow unit and the second switching unit as the output terminal of the driving circuit. The control signal input terminal of the anti-backflow unit and the control signal input terminal of the first switching unit are used to switch the driving circuit to the target driving mode when the corresponding control signal is obtained. The target driving mode includes an open-drain driving mode and a push-pull output driving mode. By setting the anti-backflow unit, the situation of current backflow and large leakage current is avoided, ensuring that the logic device outputs a correct high-level drive.

[0072] Please continue to refer to this. Figure 4 Regarding the specific structure of the first switching unit 10, this application embodiment also provides a possible implementation method. For example... Figure 4 As shown, the first switching unit 10 includes a first PMOS transistor PM1 and a NAND gate U1.

[0073] The source of the first PMOS transistor PM1 is connected to the driving power supply as the second terminal of the first switching unit 10, and the drain of the first PMOS transistor PM1 is connected to the anti-backflow unit 40 as the third terminal of the first switching unit 10.

[0074] The first input terminal of the NAND gate U1 is connected to the control port of the logic device 30 as the first terminal (a1) of the first switching unit 10, the second input terminal of the NAND gate U1 is connected to the control signal input terminal (a4) of the first switching unit 10, and the output terminal of the NAND gate U1 is connected to the gate of the first PMOS transistor PM1.

[0075] For example, when MCP is 1, i.e., the push-pull output mode is selected, the on / off state of the first switching unit 10 changes according to the trigger signal of the logic device 30. For instance, when the output of the logic device 30 is high (1), the NAND gate U1 outputs a low level, and the first switching unit 10 is turned on. When the output of the logic device 30 is low (0), the NAND gate U1 outputs a high level, and the first switching unit 10 is turned off. When MCP is 0, i.e., the open-drain drive mode is selected, regardless of whether the output of the logic device 30 is high or low, the NAND gate output is always high (1), and the first switching unit 10 is in the off state.

[0076] Please continue to refer to this. Figure 4 Regarding the specific structure of the second switching unit 20, this application embodiment also provides a possible implementation method. For example... Figure 4 As shown, the second switching unit 20 uses a first NMOS transistor PM1. The source of the first NMOS transistor PM1 is grounded, the gate of the first NMOS transistor PM1 is connected to the logic device 30, and the drain of the first NMOS transistor PM1 is connected to the anti-backflow unit 40.

[0077] exist Figure 4 Based on this, regarding the specific structure of the anti-backflow unit 40, this application embodiment also provides a possible implementation method, please refer to... Figure 5 , Figure 5 This is a connection diagram of the anti-backflow unit provided in an embodiment of this application.

[0078] like Figure 5 As shown, the backflow prevention unit 40 includes a first subunit 401 and a second subunit 402.

[0079] Optionally, the control signal input terminal of the anti-backflow unit 40 includes the control signal input terminal of the first subunit 401 and the control signal input terminal of the second subunit 402.

[0080] The first end (d1) of the first subunit 401 is connected to the third end (a3) ​​of the first switching unit 10, the second end (d2) of the first subunit 401 is connected to the third end (b3) of the second switching unit 20, the third end (d3) of the first subunit 401 is connected to the second end (e2) of the second subunit 402, and the first end (e2) of the second subunit 402 is connected to the driving power supply.

[0081] When the control signal corresponding to the push-pull output drive mode is received at the control signal input terminal of the anti-backflow unit 40 and the control signal input terminal of the first switch unit 10, the second sub-unit 402 switches to the normally on state to pull up the third terminal of the first sub-unit 401 to the drive power supply, so that the first sub-unit 401 switches to the normally on state and switches the drive circuit to the push-pull output drive mode.

[0082] When the control signal corresponding to the open-drain drive mode is received at the control signal input terminal of the anti-backflow unit 40 and the control signal input terminal of the first switching unit 10, the second sub-unit 402 switches to the normally open state, and the third terminal of the first sub-unit 401 is connected to the output terminal (VOUT) of the drive circuit, so that the first sub-unit 401 switches to the normally open state, the first switching unit 10 switches to the normally open state, and the drive circuit is switched to the open-drain drive mode.

[0083] Please continue to refer to this. Figure 5 Regarding the specific structure of the first subunit 401 and the second subunit 402, this application embodiment also provides a possible implementation method.

[0084] like Figure 5 As shown, the first sub-unit 401 includes a second NMOS transistor NM2, a second PMOS transistor PM2, a third PMOS transistor PM3, and a fourth PMOS transistor PM4.

[0085] The first terminal of the fourth PMOS transistor PM4 is connected to the third terminal of the first sub-unit 401 as the first terminal of the first switching unit 10.

[0086] The second terminal of the fourth PMOS transistor PM4 is connected to the third terminal of the second switching unit 20 as the second terminal of the first sub-unit 401.

[0087] The substrate (also known as the body) of the fourth PMOS transistor PM4 is connected to the first terminal of the third PMOS transistor PM3. The substrate of the third PMOS transistor PM3 is connected to the first terminal of the third PMOS transistor PM3. A terminal is led out between the substrate of the fourth PMOS transistor PM4 and the first terminal of the third PMOS transistor PM3, which serves as the third terminal of the first sub-unit 401 and is connected to the second terminal of the second sub-unit 402. The second terminal of the third PMOS transistor PM3 is connected to the output terminal of the drive circuit.

[0088] The first terminal of the second PMOS transistor PM2 is connected to the output terminal of the driving circuit, the substrate of the second PMOS transistor PM2 is connected to the first terminal of the second PMOS transistor PM2, and the second terminal of the second PMOS transistor PM2 is connected to the gate of the fourth PMOS transistor.

[0089] The source of the second NMOS transistor NM2 is grounded, and the drain of the second NMOS transistor NM2 is connected to the gate of the fourth PMOS transistor.

[0090] The gates of the second NMOS transistor NM2, the second PMOS transistor PM2, and the third PMOS transistor PM3 serve as the control signal input terminals of the first sub-unit 401.

[0091] It should be noted that the control signals received by the gates of the second NMOS transistor NM2, the second PMOS transistor PM2, and the third PMOS transistor PM3 may be of the same type, for example, all of them may be... Figure 5 The MCP shown can, of course, be different, and is not limited here.

[0092] Please continue to refer to this. Figure 5 The second sub-unit 402 includes a third NMOS transistor NM3, a fifth PMOS transistor PM5, a sixth PMOS transistor PM6, and a seventh PMOS transistor PM7.

[0093] The source of the sixth PMOS transistor PM6 is connected to the drive power supply as the first terminal of the second sub-unit 402.

[0094] The first terminal of the fifth PMOS transistor PM5 is connected to the third terminal of the first sub-unit 401 as the second terminal of the second sub-unit 402. The substrate of the fifth PMOS transistor PM5 is connected to the first terminal of the fifth PMOS transistor PM5. The drain of the sixth PMOS transistor PM6 is connected to the second terminal of the fifth PMOS transistor PM5.

[0095] The first terminal of the seventh PMOS transistor PM7 is connected between the first terminal of the fifth PMOS transistor and the third terminal of the first sub-unit 401. The substrate of the seventh PMOS transistor PM7 is connected to the first terminal of the seventh PMOS transistor PM7, and the second terminal of the seventh PMOS transistor PM7 is connected to the gate of the fifth PMOS transistor.

[0096] The source of the third NMOS transistor NM3 is grounded, and the drain of the third NMOS transistor NM3 is connected to the gate of the fifth PMOS transistor.

[0097] The gates of the third NMOS transistor NM3, the seventh PMOS transistor PM7, and the sixth PMOS transistor PM6 serve as the control signal input terminals of the second sub-unit 402.

[0098] It should be noted that the control signals corresponding to the gates of the third NMOS transistor NM3, the seventh PMOS transistor PM7, and the sixth PMOS transistor PM6 can be different, such as... Figure 5 As shown, the control signals corresponding to the gates of the third NMOS transistor NM3 and the seventh PMOS transistor PM7 are MCP, while the control signal corresponding to the gate of the sixth PMOS transistor PM6 is MCN, which is the opposite of MCP.

[0099] It should be understood that the switching of output modes in this application needs to be completed based on control signals. Regarding how to generate control signals, embodiments of this application also provide a possible implementation method, please refer to... Figure 6 , Figure 6This is another connection diagram of the driving circuit provided in an embodiment of this application.

[0100] like Figure 6 As shown, the driving circuit also includes a state switching unit 50, the output terminal of which is connected to the control signal input terminal of the first switching unit 10 and the control signal input terminal of the anti-backflow unit 40, respectively.

[0101] The input terminal of the state switching unit 50 is used to receive the drive mode signal and output the corresponding control signal based on the drive mode signal to switch the state of the first switching unit 10 and the anti-backflow unit 40 so that the drive circuit switches to the target drive mode.

[0102] Regarding the specific structure of the state switching unit 50, this application embodiment also provides a possible implementation method, please refer to... Figure 7 , Figure 7 This is a connection diagram of the state switching unit provided in an embodiment of this application.

[0103] like Figure 7 As shown, the state switching unit 50 includes a first inverter T1 and a second inverter T2, with the output terminal of the first inverter T1 connected to the input terminal of the second inverter T2.

[0104] The input terminal of the first inverter T1 serves as the input terminal of the state switching unit 50, and is connected to the drive mode signal (MODE_CTRL).

[0105] The output of the second inverter T2 serves as the first output of the state switching unit 50, outputting the MCP signal.

[0106] A terminal is led out between the output of the first inverter T1 and the input of the second inverter T2 to serve as the second output of the state switching unit 50, which outputs the MCN signal.

[0107] The control signal input terminal of the first switching unit 10 and the control signal input terminal of the second switching unit 20 are connected to the first output terminal and / or the second output terminal of the state switching unit 50.

[0108] Specifically, the connection relationship is as follows: Figure 5 As shown, the control signals received by the gates of the second NMOS transistor NM2, the second PMOS transistor PM2, and the third PMOS transistor PM3 may be of the same type, namely MCP. The control signals corresponding to the gates of the third NMOS transistor NM3 and the seventh PMOS transistor PM7 are MCP, while the control signal corresponding to the gate of the sixth PMOS transistor PM6 is MCN, which is the opposite of MCP. The NAND gate U1 receives the control signal MCP.

[0109] exist Figure 7and Figure 5 Based on the above, this application also provides a possible implementation method for how to achieve driver mode switching, please refer to the following.

[0110] When MODE_CTRL=1, the third PMOS transistor PM3 is in the off state, the gate of the fifth PMOS transistor PM5 is pulled to ground by the third NMOS transistor NM3 and is in the normally on state, the sixth PMOS transistor PM6 is in the normally on state, the substrate of the fourth PMOS transistor PM4 is pulled up to the drive power supply VDD, the gate voltage of the fourth PMOS transistor PM4 is pulled down to ground by the second NMOS transistor NM2, and the fourth PMOS transistor PM4 is in the normally on state. The chip realizes push-pull output.

[0111] When MODE_CTRL = 0, the chip implements open-drain drive. Specifically, the second PMOS transistor PM2 is in the on state, and its body is connected to VOUT, pulling the gate voltage of the fourth PMOS transistor PM4 to VOUT. The body of the fourth PMOS transistor PM4 is pulled up to VOUT by the third PMOS transistor PM3. The fourth PMOS transistor PM4 is turned off and is not limited by VOUT, thereby preventing the current flowing into VOUT from flowing back through the fourth PMOS transistor PM4.

[0112] Furthermore, the sixth PMOS transistor PM6 is turned off, and the seventh PMOS transistor PM7 is turned on. The gate voltage of the fifth PMOS transistor PM5 is pulled to the body of PM4 by the seventh PMOS transistor PM7. The substrate of the fifth PMOS transistor PM5 is also connected to the body of PM4. Therefore, the fifth PMOS transistor PM5 is turned off, thus preventing the current flowing into VOUT from flowing back through the third PMOS transistor PM3 and then through the fifth PMOS transistor PM5. The body of the fourth PMOS transistor PM4 changes with the change of VOUT, so even if the external power supply voltage is higher than the chip's VDD voltage, there will be no reverse current flow.

[0113] In one possible implementation, when the drive circuit is in open-drain drive mode, the output of the drive circuit is also used to connect in sequence with a pull-up resistor and an external power supply.

[0114] Optionally, a third switching unit can be set at the output terminal and pull-up resistor of the drive circuit. When in open-drain drive mode, the third switching unit is turned on, and when in push-pull output drive mode, the third switching unit is turned off.

[0115] This application provides a reverse-current protection drive circuit. The digital output driver supports different drive types, including push-pull output and open-drain output. Only one control bit is needed to switch the output mode, and only one circuit is needed to prevent reverse current from occurring when the external voltage is higher than the chip power supply voltage when the drain is open.

[0116] This application also provides a chip, which includes the driving circuit described above.

[0117] This application also provides an electronic device, which includes the chip described above.

[0118] Alternatively, the electronic device can be a mobile phone, computer, portable terminal device, wearable device, or other computing device.

[0119] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

[0120] It will be apparent to those skilled in the art that this application is not limited to the details of the exemplary embodiments described above, and that this application can be implemented in other specific forms without departing from the spirit or essential characteristics of this application. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this application is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this application. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A driving circuit, characterized in that, The driving circuit includes logic devices, a first switching unit, a second switching unit, and an anti-backflow unit; The control port of the logic device is connected to the first end of the first switching unit and the first end of the second switching unit, respectively. The second terminal of the first switching unit is connected to the driving power supply, the second terminal of the second switching unit is grounded, and the anti-backflow unit is connected to the third terminal of the first switching unit and the third terminal of the second switching unit, respectively. A wiring terminal is led out between the anti-backflow unit and the second switch unit to serve as the output terminal of the drive circuit; The control signal input terminal of the anti-backflow unit and the control signal input terminal of the first switching unit are used to switch the driving circuit to the target driving mode when the corresponding control signal is obtained. The target driving mode includes open drain driving mode and push-pull output driving mode. The backflow prevention unit includes a first subunit and a second subunit. The first subunit includes a second PMOS transistor, a third PMOS transistor, and a fourth PMOS transistor. The first terminal of the fourth PMOS transistor is connected to the third terminal of the first switching unit as the first terminal of the first sub-unit. The second terminal of the fourth PMOS transistor is connected to the third terminal of the second switching unit as the second terminal of the first sub-unit. The substrate of the fourth PMOS transistor is connected to the first terminal of the third PMOS transistor. A terminal is led out between the substrate of the fourth PMOS transistor and the first terminal of the third PMOS transistor, which is connected to the second terminal of the second sub-unit as the third terminal of the first sub-unit. The first terminal of the second sub-unit is connected to the driving power supply. The second terminal of the third PMOS transistor is connected to the output terminal of the driving circuit. The first terminal of the second PMOS transistor is connected to the output terminal of the driving circuit, the substrate of the second PMOS transistor is connected to the first terminal of the second PMOS transistor, the second terminal of the second PMOS transistor is connected to the gate of the fourth PMOS transistor, and the gate of the second PMOS transistor and the gate of the third PMOS transistor serve as the control signal input terminal of the first sub-unit. When the control signal corresponding to the push-pull output drive mode is received at the control signal input terminal of the anti-backflow unit and the control signal input terminal of the first switch unit, the second sub-unit switches to the normally on state to pull up the third terminal of the first sub-unit to the drive power supply, so that the first sub-unit switches to the normally on state and the drive circuit switches to the push-pull output drive mode. When the control signal corresponding to the open-drain drive mode is received at the control signal input terminal of the anti-backflow unit and the control signal input terminal of the first switch unit, the second sub-unit switches to the normally off state, and the third terminal of the first sub-unit is connected to the output terminal of the drive circuit, so that the first sub-unit switches to the normally off state, the first switch unit switches to the normally off state, and the drive circuit is switched to the open-drain drive mode.

2. The driving circuit as described in claim 1, characterized in that, The first sub-unit also includes a second NMOS transistor; The source of the second NMOS transistor is grounded, and the drain of the second NMOS transistor is connected to the gate of the fourth PMOS transistor. The gate of the second NMOS transistor also serves as the control signal input terminal of the first sub-unit.

3. The driving circuit as described in claim 1, characterized in that, The second sub-unit includes a fifth PMOS transistor, a sixth PMOS transistor, and a seventh PMOS transistor; The source of the sixth PMOS transistor is connected to the driving power supply as the first terminal of the second sub-unit; The first terminal of the fifth PMOS transistor is connected to the third terminal of the first sub-unit as the second terminal of the second sub-unit. The substrate of the fifth PMOS transistor is connected to the first terminal of the fifth PMOS transistor. The drain of the sixth PMOS transistor is connected to the second terminal of the fifth PMOS transistor. The first terminal of the seventh PMOS transistor is connected between the first terminal of the fifth PMOS transistor and the third terminal of the first sub-unit. The substrate of the seventh PMOS transistor is connected to the first terminal of the seventh PMOS transistor, and the second terminal of the seventh PMOS transistor is connected to the gate of the fifth PMOS transistor.

4. The driving circuit as described in claim 3, characterized in that, The second sub-unit also includes a third NMOS transistor; The source of the third NMOS transistor is grounded, and the drain of the third NMOS transistor is connected to the gate of the fifth PMOS transistor. The gates of the third NMOS transistor, the seventh PMOS transistor, and the sixth PMOS transistor serve as the control signal input terminals of the second sub-unit.

5. The driving circuit as described in claim 1, characterized in that, The first switching unit includes a first PMOS transistor and a NAND gate; The source of the first PMOS transistor is connected to the driving power supply as the second terminal of the first switching unit, and the drain of the first PMOS transistor is connected to the anti-backflow unit as the third terminal of the first switching unit. The first input terminal of the NAND gate is connected to the control port of the logic device as the first terminal of the first switching unit, the second input terminal of the NAND gate is connected to the control signal input terminal of the first switching unit, and the output terminal of the NAND gate is connected to the gate of the first PMOS transistor.

6. The driving circuit as described in claim 1, characterized in that, The driving circuit further includes a state switching unit, the output terminal of which is connected to the control signal input terminal of the first switching unit and the control signal input terminal of the anti-backflow unit, respectively. The input terminal of the state switching unit is used to receive the drive mode signal and output a corresponding control signal based on the drive mode signal to switch the state of the first switching unit and the anti-backflow unit so that the drive circuit switches to the target drive mode.

7. The driving circuit as described in claim 6, characterized in that, The state switching unit includes a first inverter and a second inverter, and the output terminal of the first inverter is connected to the input terminal of the second inverter. The input terminal of the first inverter serves as the input terminal of the state switching unit; The output of the second inverter serves as the first output of the state switching unit; A terminal is led out between the output terminal of the first inverter and the input terminal of the second inverter to serve as the second output terminal of the state switching unit; The control signal input terminal of the first switching unit and the control signal input terminal of the anti-backflow unit are connected to the first output terminal and / or the second output terminal of the state switching unit.

8. The driving circuit as described in claim 1, characterized in that, When the driving circuit is in open-drain driving mode, the output terminal of the driving circuit is also used to connect to the pull-up resistor and the external power supply in sequence.

9. A chip, characterized in that, The chip includes the driving circuit described in any one of claims 1-8.

10. An electronic device, characterized in that, The electronic device includes the chip of claim 9.

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