A synchronous data acquisition card

Abstract

This application provides a synchronous data acquisition card, which includes a conversion unit, a signal acquisition module, and a control chip. The control chip generates training instructions, and the conversion unit switches the data channel to the synchronous signal training channel according to the training instructions. Next, the control chip generates a first synchronous training signal and a second synchronous training signal with the same phase frequency. Then, the signal acquisition module samples the first synchronous training signal and the second synchronous training signal respectively through the synchronous signal training channel to obtain a first training sampled signal and a second training sampled signal. Finally, the control chip calibrates the signal acquisition module based on the first training sampled signal and the second training sampled signal, and synchronously samples through the sampling channel. The above scheme ensures that the data acquired simultaneously from different channels are synchronous data, reduces the lag relationship between data from different channels, and obtains the best state of data synchronization across different channels.

Description

Technical Field

[0001] This application relates to the field of data acquisition technology, specifically to a synchronous data acquisition card. Background Technology

[0002] A data acquisition card is a computer expansion card that enables data acquisition. Data acquisition cards are commonly used in the electronic measurement industry to acquire data from the object under test, send it to a host computer for analysis and processing, and then display the waveform details of the object under test using an oscilloscope.

[0003] With the development of integrated multi-object-under-test (DUT) technology in the electronic measurement industry, the synchronous acquisition results of multi-channel data directly affect the accurate representation of waveform details of the DUT. Therefore, the ability to accurately and synchronously acquire different types of DUT signals across multiple channels is crucial. Currently, when acquiring different types of DUT signals across multiple channels, commonly used data acquisition cards often directly acquire data from multiple channels simultaneously. However, the acquired data from different channels typically exhibit a lag, leading to asynchrony and consequently affecting the accurate representation of waveform details of the DUT.

[0004] Therefore, due to the lack of existing technical means, there is an urgent need for a synchronous data acquisition card to reduce the lag between data from different channels and ensure that the data acquired simultaneously from different channels are synchronous. Summary of the Invention

[0005] This application provides a synchronous data acquisition card that ensures that data acquired simultaneously from different channels is synchronous.

[0006] The acquisition card provided in this application includes: a conversion unit, a signal acquisition module, and a control chip;

[0007] The conversion unit, the signal acquisition module, and the control chip are interconnected through a data channel.

[0008] The control chip is used to generate training instructions and send the training instructions to the conversion unit to control the conversion unit to switch the data channel to the synchronization signal training channel;

[0009] The control chip is also used to generate a first synchronous training signal and a second synchronous training signal; the first synchronous training signal and the second synchronous training signal have the same phase frequency;

[0010] The conversion unit is used to control the data channel to switch between the synchronization signal training channel and the sampling channel;

[0011] The signal acquisition module is used to sample the first synchronous training signal and the second synchronous training signal through the synchronous signal training channel to obtain the first training sampling signal and the second training sampling signal.

[0012] The control chip is also used to correct the signal acquisition module according to the first training sampling signal and the second training sampling signal, so that the signal acquisition module can synchronously sample through the sampling channel.

[0013] In one possible implementation, the conversion unit includes a first conversion unit and a second conversion unit; the signal acquisition module includes a first signal acquisition chip and a second signal acquisition chip;

[0014] The first conversion unit, the first signal acquisition chip, and the control chip are interconnected through a first synchronization signal training channel; the second conversion unit, the second signal acquisition chip, and the control chip are interconnected through a second synchronization signal training channel.

[0015] The control chip is used to simultaneously acquire the same first training instruction and second training instruction, and send the first training instruction to the first conversion unit and the second training instruction to the second conversion unit;

[0016] The first conversion unit is used to switch the first data channel to the first synchronization signal training channel according to the first training instruction;

[0017] The second conversion unit is used to switch the second data channel to the second synchronization signal training channel according to the second training instruction;

[0018] The first signal acquisition chip is used to sample the first synchronization training signal through the first synchronization signal training channel to obtain the first training sampling signal;

[0019] The second signal acquisition chip is used to sample the second synchronization training signal through the second synchronization signal training channel to obtain the second training sampling signal.

[0020] In one possible implementation, the acquisition card further includes a clock buffer unit;

[0021] The clock buffer unit is used to acquire the target waveform data signal and, based on the target waveform data signal, acquire the first synchronization training signal and the second synchronization training signal.

[0022] In one possible implementation, the control chip includes a synchronization signal generation module;

[0023] The two ends of the clock buffer unit are respectively connected to the synchronization signal generation module and the conversion unit;

[0024] The synchronization signal generation module is used to generate target waveform data signals according to the training instructions.

[0025] In one possible implementation, the control chip further includes a delay module;

[0026] The delay module is connected to the signal acquisition chip;

[0027] The delay module is used to perform multiple delay operations on at least one of the first training sampling signal and the second training sampling signal acquired by the signal acquisition chip based on the received delay data, so that the control chip can correct the signal acquisition chip based on the comparison result between the first training sampling signal and the second training sampling signal after the delay operation.

[0028] In one possible implementation, the delay module includes at least one memory; the memory is used to store either a first training sample signal or a second training sample signal.

[0029] The memory contains 18 addresses, each of which can be filled with 192 bits of data.

[0030] In one possible implementation, the delay module is further configured to parse the delay data to obtain the number of shifts and the shift address, and to read the data in the memory based on the number of shifts and the shift address.

[0031] In one possible implementation, the delay module is further configured to determine the target address based on the number of shifts, and read the first data in the target address and the second data of the address preceding the target address from the memory;

[0032] The delay module is also used to construct the target data by using the first data as the high-order 192 bits and the second data as the low-order 192 bits.

[0033] The delay module is also used to shift the target data according to the number of shifts, so that the lower 192 bits of the shifted target data are used as the result of the delay operation.

[0034] In one possible implementation, the control chip further includes a control module;

[0035] One end of the control module is connected to the synchronization signal generation module;

[0036] The control module is used to generate the same first training instruction and second training instruction according to the training instruction, and to control the synchronization signal generation module to generate the target waveform data signal.

[0037] The control module is configured to control the first conversion unit to switch the first synchronization signal training channel to the first synchronization signal training channel according to the first training instruction, and to control the second conversion unit to switch the second synchronization signal training channel to the second synchronization signal training channel according to the second training instruction.

[0038] In one possible implementation, the control module is configured to generate an acquisition command after the signal acquisition chip completes calibration, and control the first conversion unit to switch the first synchronization signal training channel to the first synchronization signal acquisition channel based on the acquisition command, and control the second conversion unit to switch the second synchronization signal training channel to the second synchronization signal acquisition channel.

[0039] The technical solution provided in this application may include the following beneficial effects:

[0040] The synchronous data acquisition card includes a conversion unit, a signal acquisition module, and a control chip. The control chip first generates training instructions and sends them to the conversion unit to control the conversion unit to switch the data channel to the synchronous signal training channel. Then, it generates a first synchronous training signal and a second synchronous training signal with the same phase frequency. The signal acquisition module samples the first and second synchronous training signals through the synchronous signal training channel to obtain a first training sampled signal and a second training sampled signal. Finally, the control chip calibrates the signal acquisition module based on the first and second training sampled signals to ensure that the signal acquisition module samples synchronously through the sampling channel. After calibration, the signal acquisition module can sample synchronously, thereby reducing the lag between data from different channels and obtaining the best state of data synchronization across different channels, ensuring that the data acquired simultaneously from different channels are synchronous. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0042] Figure 1 This is a schematic diagram of the structure of a synchronous data acquisition card according to an exemplary embodiment.

[0043] Figure 2 This is a schematic diagram of the structure of a synchronous data acquisition card according to an exemplary embodiment.

[0044] Figure 3 This is a schematic diagram of the structure of a synchronous data acquisition card according to an exemplary embodiment.

[0045] Figure 4 This is a schematic diagram of the structure of a synchronous data acquisition card according to an exemplary embodiment.

[0046] Figure 5 This is a schematic diagram of a delay module according to an exemplary embodiment. Detailed Implementation

[0047] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0048] It should be understood that the term "instruction" mentioned in the embodiments of this application can be a direct instruction, an indirect instruction, or an indication of a relationship. For example, A instructing B can mean that A directly instructs B, such as B being able to obtain information through A; it can also mean that A indirectly instructs B, such as A instructing C, so B can obtain information through C; or it can mean that there is a relationship between A and B.

[0049] In the description of the embodiments of this application, the term "correspondence" may indicate that there is a direct or indirect correspondence between two things, or that there is an association between two things, or that there is a relationship of instruction and being instructed, configuration and being configured, etc.

[0050] In the embodiments of this application, "predefined" can be achieved by pre-storing corresponding codes, tables or other means that can be used to indicate relevant information in the device (e.g., including terminal devices and network devices). This application does not limit the specific implementation method.

[0051] Figure 1 This is a schematic diagram illustrating the structure of a synchronous data acquisition card according to an exemplary embodiment. For example... Figure 1 The present invention relates to a synchronous data acquisition card, which includes: a conversion unit, a signal acquisition module, and a control chip;

[0052] The conversion unit, the signal acquisition module, and the control chip are interconnected through a data channel.

[0053] The control chip is used to generate training instructions and send the training instructions to the conversion unit to control the conversion unit to switch the data channel to the synchronization signal training channel;

[0054] The control chip is also used to generate a first synchronous training signal and a second synchronous training signal; the first synchronous training signal and the second synchronous training signal have the same phase frequency;

[0055] The conversion unit is used to control the data channel to switch between the synchronization signal training channel and the sampling channel;

[0056] The signal acquisition module is used to sample the first synchronous training signal and the second synchronous training signal through the synchronous signal training channel to obtain the first training sampling signal and the second training sampling signal.

[0057] The control chip is also used to correct the signal acquisition module according to the first training sampling signal and the second training sampling signal, so that the signal acquisition module can synchronously sample through the sampling channel.

[0058] Furthermore, to ensure that the data signals acquired by the signal acquisition module are synchronized, the module needs to be trained and calibrated using training signals. This ensures that the data acquired by the module from different channels are synchronized. Therefore, the signal acquisition module needs to be trained and calibrated before data acquisition.

[0059] In specific application scenarios, the user first sends an external input command to the control chip according to the actual situation. This external input command can be a request for the synchronous data acquisition card to perform data training or data acquisition. When the external input command is to perform data training, the control chip receives the external input command and generates a training command based on it. After generating the training command, the control chip sends the training command to the conversion unit, which then controls the conversion unit to switch the data channel to the synchronous signal training channel (when the control chip generates an acquisition command, the conversion unit switches the data channel to the sampling channel) to perform synchronous training.

[0060] When the control chip controls the conversion unit to switch the data channel to the synchronization signal training channel, the control chip also generates a first synchronization training signal and a second synchronization training signal with the same phase frequency according to the training instruction, and sends the first synchronization training signal and the second synchronization training signal to the signal acquisition module through the synchronization signal training channel.

[0061] The signal acquisition module samples the first and second synchronous training signals generated by the control chip through the synchronous signal training channel to obtain the first and second training sampling signals, respectively. After the signal acquisition module acquires the first and second training sampling signals, the control chip analyzes them to correct the signal acquisition module. The corrected signal acquisition module can then perform synchronous sampling through the sampling channel.

[0062] In one possible implementation, such as Figure 2 The synchronous data acquisition card shown includes a conversion unit comprising a first conversion unit (i.e., Figure 2 The conversion unit 1) and the second conversion unit (i.e. Figure 2 The conversion unit 2); the signal acquisition module includes a first signal acquisition chip (i.e., Figure 2 Signal acquisition chip 1) and second signal acquisition chip (i.e. Figure 2 2) Signal acquisition chip;

[0063] The first conversion unit, the first signal acquisition chip, and the control chip are interconnected through a first synchronization signal training channel; the second conversion unit, the second signal acquisition chip, and the control chip are interconnected through a second synchronization signal training channel.

[0064] The control chip is used to simultaneously acquire the same first training instruction and second training instruction, and send the first training instruction to the first conversion unit and the second training instruction to the second conversion unit;

[0065] The first conversion unit is used to switch the first data channel to the first synchronization signal training channel according to the first training instruction;

[0066] The second conversion unit is used to switch the second data channel to the second synchronization signal training channel according to the second training instruction;

[0067] The first signal acquisition chip is used to sample the first synchronization training signal through the first synchronization signal training channel to obtain the first training sampling signal;

[0068] The second signal acquisition chip is used to sample the second synchronization training signal through the second synchronization signal training channel to obtain the second training sampling signal.

[0069] Optional, such as Figure 3The synchronous data acquisition card shown here requires a conversion unit to have a multiple-choice function in order to switch the data channel. For example, the conversion unit can be an RF switch or a DIP switch.

[0070] Optionally, the signal acquisition module needs to have the function of acquiring data from analog signals. For example, the signal acquisition module is an ADC module (analog-to-digital converter), which can convert analog signals generated in the real world (such as temperature, pressure, sound, fingerprints, or images) into a digital form that is easier to process.

[0071] Optionally, the control chip can be an FPGA (Field Programmable Gate Array). An FPGA is a further development based on programmable devices such as PAL (Programmable Array Logic) and GAL (General Purpose Array Logic). This FPGA can generate a fixed square wave signal (i.e., Figure 3 The signal generated by the FPGA in the signal acquisition module provides a synchronous training signal with the same phase frequency for synchronous training.

[0072] Furthermore, when the control chip acquires the first training instruction and the second training instruction (i.e. Figure 3 The two control signals in the process, when the synchronous data acquisition card needs to acquire data, these two control signals are the first acquisition command and the second acquisition command, and they control the data acquisition process. Figure 3 When the two sampled signals are acquired, the first conversion unit controls the first data channel to switch to the first synchronization signal training channel according to the first training instruction. Then, the first signal acquisition chip samples the first synchronization training signal generated by the control chip through the first synchronization signal training channel to obtain the first training sample signal. At the same time, the second conversion unit controls the second data channel to switch to the second synchronization signal training channel according to the second training instruction. Then, the second signal acquisition chip samples the second synchronization training signal generated by the control chip through the second synchronization signal training channel to obtain the second training sample signal.

[0073] Optionally, the first synchronous training signal and the second synchronous training signal are the same square wave signal. Therefore, when sampling the first synchronous training signal and the second synchronous training signal respectively, instantaneous sampling can be performed at each rising edge of the first synchronous training signal and the second synchronous training signal.

[0074] For example, taking an FPGA (control chip) operating at a frequency of 187.5MHz and an ADC sampling rate of 3GHz as an example, when the FPGA receives one rising edge, ADC1 (the first signal acquisition chip) and ADC2 (the second signal acquisition chip) output 16 sampling points (that is, when the FPGA receives one rising edge, ADC1 and ADC2 perform one acquisition, each sampling 16 sampling points). Since the bit width of ADC1 and ADC2 is 12 bits, the data sampled each time can be combined to form a data with a bit width of 192 bits.

[0075] In one possible implementation, such as Figure 4 The diagram shows a synchronous data acquisition card, which further includes a clock buffer unit;

[0076] The clock buffer unit is used to acquire the target waveform data signal and, based on the target waveform data signal, acquire the first synchronization training signal and the second synchronization training signal.

[0077] Optionally, the clock buffer unit can be a clock buffer that can copy the target waveform data signal to form two identical synchronous training signals.

[0078] Furthermore, when the control chip controls the conversion unit to switch the data channel to the synchronization signal training channel, the synchronization signal generation module in the control chip generates a target waveform data signal (the target waveform data signal is a fixed square wave waveform signal) based on the training instruction. The clock buffer unit acquires the target waveform data signal and divides the target waveform data signal into two identical waveforms, namely the first synchronization training signal and the second synchronization training signal.

[0079] In one possible implementation, such as Figure 4 As shown, the control chip includes a synchronization signal generation module;

[0080] The two ends of the clock buffer unit are respectively connected to the synchronization signal generation module and the conversion unit;

[0081] The synchronization signal generation module is used to generate a target waveform data signal (i.e., ...) according to the training instructions. Figure 4 (synchronization signal in the middle).

[0082] In one possible implementation, the control chip further includes a delay module;

[0083] The delay module is connected to the signal acquisition chip;

[0084] The delay module is used to perform multiple delay operations on at least one of the first training sampling signal and the second training sampling signal acquired by the signal acquisition chip based on the received delay data, so that the control chip can correct the signal acquisition chip based on the comparison result between the first training sampling signal and the second training sampling signal after the delay operation.

[0085] Furthermore, after the first signal acquisition chip acquires the first training sampling signal and the second signal acquisition chip acquires the second training sampling signal, the delay module performs multiple delay operations on at least one of the first and second training sampling signals based on the received delay data. The control chip analyzes and compares the delayed first and second training sampling signals, and corrects the first and second signal acquisition chips based on the comparison results. The corrected first and second signal acquisition chips can achieve synchronous sampling through the sampling channel.

[0086] In one possible implementation, such as Figure 5 The diagram shows a block diagram of a delay module, which includes at least one memory; the memory is used to store either a first training sample signal or a second training sample signal.

[0087] The memory contains 18 addresses, each of which can be filled with 192 bits of data.

[0088] Optionally, the delay module includes a first delay module (i.e. Figure 4 The delay module 1 and the second delay module (i.e. Figure 4 The delay module 2 in the second signal acquisition chip is used to perform delay operation on the first training sampling signal. The first delay module is used to perform delay operation on the second signal acquisition chip. The first delay module includes a first memory for storing the first training sampling signal and a second memory for storing the first training sampling signal.

[0089] Optionally, when storing the training sampling signal into the memory (storing the first training sampling signal into the first memory, and storing the first training sampling signal into the second memory), since there are 18 addresses in the memory, the first input data (the training sampling signal acquired by the signal acquisition module for the first time) is filled into the space at address 17, the next data (the training sampling signal acquired by the signal acquisition module for the second time) will be filled into the space at address 0, and the subsequent data will be filled in according to the address incremented by one. When the address is incremented to 17, it will be cleared to zero, and then the filling will start again. The delay process will be performed according to the input delay data (which consists of the number of bits to be moved and the address to be moved).

[0090] In one possible implementation, the delay module is further configured to parse the delay data to obtain the number of shifts and the shift address, and to read the data in the memory based on the number of shifts and the shift address.

[0091] Furthermore, the delayed data is split into the number of bits to be shifted and the shift address. There is an initial base address of 0. With each rising edge of the clock, the base address is incremented by one. When it reaches 17, it is reset to zero and restarted. The shift address plus the base address is used as the memory read address, and the data at that address is read from memory. When the read address reaches 17, it is reset to zero and read from 0. The data read from the current address and the data read from the previous address are combined to form a 384-bit data set. The data from the previous address is placed in the low-order bits, and the data read from the current address is placed in the high-order bits. Since the input data is 192 bits, composed of 16 groups of 12 bits, the shift number obtained from the delayed data actually represents how many 12-bit data sets will be shifted. Therefore, during the actual shift, the calculated shift number is multiplied by 12 to obtain the actual shift number. The data is then right-shifted accordingly, and the lower 192 bits of the shifted data are extracted and transmitted to the synchronization judgment module for processing.

[0092] In one possible implementation, the delay module is further configured to determine the target address based on the number of shifts, and read the first data in the target address and the second data of the address preceding the target address from the memory;

[0093] The delay module is also used to construct the target data by using the first data as the high-order 192 bits and the second data as the low-order 192 bits.

[0094] The delay module is also used to shift the target data according to the number of shifts, so that the lower 192 bits of the shifted target data are used as the result of the delay operation.

[0095] Furthermore, based on this delay data, the number of bits to be moved and the address to be moved are obtained. In addition, there is a base address with an initial value of 0. With each rising edge of the clock, the value of the base address is incremented by one. When it reaches 17, it is cleared to zero and then restarted (corresponding to the storage process of the memory). Then, the base address is added to the address to be moved as the read address of the memory, and the data (training sampling signal) stored at the read address in the memory is read out. When the read address is incremented by 17, it is cleared to zero and read from 0.

[0096] Furthermore, the data read from the current address (first data) and the data read from the previous address (second data) will be combined to form a 384-bit data (target data). The data from the previous address will be placed in the low-order bits, and the data read from the current address will be placed in the high-order bits. (Alternatively...) Figure 5 As shown, the data read from the current address and the data read from the next address are combined to form a 384-bit data (the data from the current address is placed in the low-order bits, and the data read from the next address is placed in the high-order bits). Since the input data (training sampling signal) to this delay module is 192 bits, which is composed of 16 12-bit data, the shift bits obtained from the delay data actually mean how many 12-bit data will be shifted. Therefore, when shifting, the calculated shift bits are multiplied by 12 to get the actual shift bits. The data is shifted right according to this, and the lower 192 bits of the shifted data are taken out and transmitted to the processing module for processing.

[0097] Furthermore, the arithmetic module is located in the control chip and connected to the delay module. The arithmetic module is used to process the data output from the delay module, calculate the delay difference between the first training sample signal and the second training sample signal after each delay operation of the delay module, and find the minimum value of the delay difference so that the control chip can correct the signal acquisition chip based on the minimum value.

[0098] In one possible implementation, the control chip further includes a control module;

[0099] One end of the control module is connected to the synchronization signal generation module;

[0100] The control module is used to generate the same first training instruction and second training instruction according to the training instruction, and to control the synchronization signal generation module to generate the target waveform data signal.

[0101] The control module is configured to control the first conversion unit to switch the first synchronization signal training channel to the first synchronization signal training channel according to the first training instruction, and to control the second conversion unit to switch the second synchronization signal training channel to the second synchronization signal training channel according to the second training instruction.

[0102] In one possible implementation, the control module is configured to generate an acquisition command after the signal acquisition chip completes calibration, and control the first conversion unit to switch the first synchronization signal training channel to the first synchronization signal acquisition channel based on the acquisition command, and control the second conversion unit to switch the second synchronization signal training channel to the second synchronization signal acquisition channel.

[0103] In summary, the synchronous data acquisition card includes a conversion unit, a signal acquisition module, and a control chip. The control chip first generates training instructions and sends them to the conversion unit to control the conversion unit to switch the data channel to the synchronous signal training channel. Then, it generates a first synchronous training signal and a second synchronous training signal with the same phase frequency. The signal acquisition module samples the first and second synchronous training signals through the synchronous signal training channel to obtain the first and second training sampled signals. Finally, the control chip calibrates the signal acquisition module based on the first and second training sampled signals to ensure synchronous sampling through the sampling channel. After calibration, the signal acquisition module can sample synchronously, thereby reducing the lag between data from different channels and achieving the best synchronization state across different channels, ensuring that the data acquired simultaneously from different channels are synchronous.

[0104] The present application has been described in detail above with reference to specific embodiments and exemplary examples; however, these descriptions should not be construed as limiting the present application. Those skilled in the art will understand that various equivalent substitutions, modifications, or improvements can be made to the technical solutions and implementation methods of the present application without departing from the spirit and scope of the present application, and all such modifications and improvements fall within the scope of the present application. The scope of protection of the present application is determined by the appended claims.

Claims

1. A synchronous data acquisition card, characterized by, The acquisition card comprises a conversion unit, a signal acquisition module and a control chip; The conversion unit, the signal acquisition module and the control chip are connected to each other through a data channel; The control chip is configured to generate a training instruction and send the training instruction to the conversion unit to control the conversion unit to switch the data channel to a synchronization signal training channel; The control chip is further configured to generate a first synchronization training signal and a second synchronization training signal; the first synchronization training signal and the second synchronization training signal have the same phase frequency; The conversion unit is configured to control the data channel to switch between the synchronization signal training channel and a sampling channel; The signal acquisition module is configured to sample the first synchronization training signal and the second synchronization training signal through the synchronization signal training channel to obtain a first training sampling signal and a second training sampling signal; The control chip is further configured to correct the signal acquisition module according to the first training sampling signal and the second training sampling signal, so that the signal acquisition module synchronously samples through the sampling channel; The conversion unit comprises a first conversion unit and a second conversion unit; the signal acquisition module comprises a first signal acquisition chip and a second signal acquisition chip; and the signal acquisition module is an ADC module; The first conversion unit, the first signal acquisition chip and the control chip are connected to each other through a first synchronization signal training channel; the second conversion unit, the second signal acquisition chip and the control chip are connected to each other through a second synchronization signal training channel; The control chip is configured to simultaneously obtain the same first training instruction and second training instruction, and send the first training instruction to the first conversion unit and the second training instruction to the second conversion unit; The first conversion unit is configured to switch a first data channel to a first synchronization signal training channel according to the first training instruction; The second conversion unit is configured to switch a second data channel to a second synchronization signal training channel according to the second training instruction; The first signal acquisition chip is configured to sample the first synchronization training signal through the first synchronization signal training channel to obtain the first training sampling signal; The second signal acquisition chip is configured to sample the second synchronization training signal through the second synchronization signal training channel to obtain the second training sampling signal; The control chip further comprises a delay module; The delay module is connected to the signal acquisition chip; The delay module is configured to perform multiple delay operations on at least one of the first training sampling signal and the second training sampling signal obtained by the signal acquisition chip according to received delay data, so that the control chip corrects the signal acquisition chip according to a comparison result between the first training sampling signal and the second training sampling signal after the delay operation. The control chip is further configured to calculate a delay difference between the first training sampling signal and the second training sampling signal after each execution of the delay module, and find a minimum value in the delay difference, so as to correct the signal acquisition chip based on the minimum value.

2. The synchronous data acquisition card of claim 1, wherein, The acquisition card further comprises a clock buffer unit; The clock buffer unit is configured to obtain a target waveform data signal, and obtain the first synchronization training signal and the second synchronization training signal based on the target waveform data signal.

3. The synchronous data acquisition card of claim 2, wherein, The control chip comprises a synchronization signal generation module; Two ends of the clock buffer unit are connected with the synchronization signal generation module and the conversion unit respectively; The synchronization signal generation module is configured to generate a target waveform data signal according to the training instruction.

4. The synchronous data acquisition card of claim 3, wherein, The delay module comprises at least one memory, and the memory is configured to store any one of the first training sampling signal and the second training sampling signal. There are 18 addresses in the memory, and each address can be filled with 192 bits of data.

5. The synchronous data acquisition card of claim 4, wherein, The delay module is further configured to parse delay data, obtain a moving bit number and a moving address, and read data in the memory based on the moving bit number and the moving address.

6. A synchronous data acquisition card according to claim 5, wherein, The delay module is further configured to determine a target address according to the moving bit number, read first data in the target address and second data in a previous address of the target address in the memory. The delay module is further configured to construct target data by taking the first data as 192 bits of high bits and taking the second data as 192 bits of low bits. The delay module is further configured to shift the target data according to the moving bit number, so that 192 bits of low bits in the shifted target data are taken as a delay operation result.

7. A synchronous data acquisition card according to claim 6, wherein, The control chip further comprises a control module; One end of the control module is connected with the synchronization signal generation module. The control module is configured to generate the same first training instruction and second training instruction according to the training instruction, and control the synchronization signal generation module to generate a target waveform data signal. The control module is configured to control the first conversion unit to switch the first synchronization signal training channel to a first synchronization signal acquisition channel according to the first training instruction, and control the second conversion unit to switch the second synchronization signal training channel to a second synchronization signal acquisition channel according to the second training instruction.

8. The synchronous data acquisition card of claim 7, wherein, The control module is configured to generate an acquisition instruction after the signal acquisition chip is corrected, and control the first conversion unit to switch the first synchronization signal training channel to a first synchronization signal acquisition channel and control the second conversion unit to switch the second synchronization signal training channel to a second synchronization signal acquisition channel based on the acquisition instruction.

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