Display panel and display device

Abstract

A display panel has a display area and a fan-out area. The display panel includes: a substrate; a plurality of sub-pixels and a plurality of signal transmission lines located in the display area; a scanning drive circuit; a power supply voltage bus and a plurality of connection lines located in the fan-out area. The plurality of sub-pixels are arranged into a plurality of rows along a first direction and into a plurality of columns along a second direction; a signal transmission line is electrically connected to at least one column of sub-pixels. The scanning drive circuit includes a multi-stage shift register and a plurality of clock signal lines located in the display area. The plurality of connection lines extend along the second direction and are located on a side of the power supply voltage bus away from the plurality of sub-pixels. The plurality of connection lines include: a plurality of first sub-connection lines, a plurality of second sub-connection lines, and a plurality of third sub-connection lines. A first sub-connection line is electrically connected to the signal transmission line, a second sub-connection line is electrically connected to the power supply voltage bus, and a third sub-connection line is electrically connected to a clock signal line.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] The scan drive circuit is an important component of the display device. The scan drive circuit may include a multi-stage cascaded shift register, and each stage of the shift register may be electrically connected to a line in the display device. The scan drive circuit may input scan signals line by line to multiple lines (such as gate lines or enable signal lines, etc.) in the display device so that the display device can display a picture.

[0003] Providing a scan driving circuit in a display device can effectively reduce costs and improve yield. Summary of the invention

[0004] In one aspect, a display panel is provided. The display panel has a display area and a fan-out area located on one side of the display area. The display panel includes: a substrate; a plurality of sub-pixels and a plurality of signal transmission lines located in the display area; a scan drive circuit; a power supply voltage bus located in the fan-out area; and a plurality of connection lines located in the fan-out area. The plurality of sub-pixels are arranged in a plurality of rows along a first direction and in a plurality of columns along a second direction. A signal transmission line is electrically connected to at least one column of sub-pixels. The scan drive circuit includes a multi-stage shift register and a plurality of clock signal lines located in the display area. The power supply voltage bus extends along the first direction. The plurality of connection lines are located on the same side of the substrate as the plurality of sub-pixels, the plurality of signal transmission lines, the scan drive circuit, and the power supply voltage bus. The plurality of connection lines extend along the second direction and are located on a side of the power supply voltage bus away from the plurality of sub-pixels. Wherein, the plurality of connection lines include: a plurality of first sub-connection lines, a plurality of second sub-connection lines, and a plurality of third sub-connection lines. A first sub-connection line is electrically connected to the signal transmission line, a second sub-connection line is electrically connected to the power supply voltage bus, and a third sub-connection line is electrically connected to a clock signal line.

[0005] In some embodiments, the display panel includes: a first light-transmitting layer, a first metal layer, a second metal layer and a second light-transmitting layer stacked in sequence. The first light-transmitting layer includes: a first end of a storage capacitor in the plurality of sub-pixels. The first metal layer includes: a control electrode of a transistor in the plurality of sub-pixels, the power supply voltage bus, a control electrode of a transistor in the multi-stage shift register and at least one of the first sub-connection lines. The second metal layer includes: a first electrode and a second electrode of a transistor in the plurality of sub-pixels, the plurality of signal transmission lines, a first electrode and a second electrode of a transistor in the multi-stage shift register and at least one of the first sub-connection lines. The second light-transmitting layer includes: an anode or a cathode of a light-emitting device in the plurality of sub-pixels.

[0006] In some embodiments, along a direction parallel to the substrate, at least a portion of the third sub-connection line is located in a gap between two adjacent first sub-connection lines.

[0007] In some embodiments, when the display panel further includes a first light-transmitting layer, the first light-transmitting layer further includes: at least one third sub-connecting line.

[0008] In some embodiments, when a portion of the third sub-connection line is located in the gap between the two adjacent first sub-connection lines, the orthographic projection of the third sub-connection line on the substrate partially overlaps with the orthographic projection of at least one of the two adjacent first sub-connection lines on the substrate.

[0009] In some embodiments, a size in the first direction of an overlapping portion of an orthographic projection of the third sub-connection line on the substrate and an orthographic projection of one of the two adjacent first sub-connection lines on the substrate is less than or equal to 1 / 5 of a size in the first direction of an orthographic projection of the first sub-connection line on the substrate.

[0010] In some embodiments, when the display panel further includes a second metal layer, the second metal layer further includes: at least one third sub-connection line. The orthographic projection of the third sub-connection line on the substrate and the orthographic projections of the two adjacent first sub-connection lines on the substrate do not overlap and have a spacing.

[0011] In some embodiments, when the two adjacent first sub-connection lines are respectively located in the first metal layer and the second metal layer, the distance between the orthographic projection of the third sub-connection line on the substrate and the orthographic projection of a first sub-connection line located in the second metal layer on the substrate is greater than the distance between the orthographic projection of the third sub-connection line on the substrate and the orthographic projection of a first sub-connection line located in the first metal layer on the substrate.

[0012] In some embodiments, the spacing between the orthographic projection of the third sub-connection line on the substrate and the orthographic projection of a first sub-connection line located in the second metal layer on the substrate is greater than or equal to 4 μm. The spacing between the orthographic projection of the third sub-connection line on the substrate and the orthographic projection of a first sub-connection line located in the first metal layer on the substrate is greater than or equal to 1 μm.

[0013] In some embodiments, a size of the second sub-connection line in the first direction is 1.5 to 2.5 times a size of the first sub-connection line in the first direction.

[0014] In some embodiments, the second light-transmitting layer further comprises: at least one third sub-connecting line. Along a direction perpendicular to the substrate, a distance between the first light-transmitting layer and the second metal layer is smaller than a distance between the second metal layer and the second light-transmitting layer.

[0015] In some embodiments, the display panel further includes: a buffer layer and a gate insulating layer disposed between the first light-transmitting layer and the second metal layer and stacked in sequence; and a passivation layer and a planarization layer disposed between the second metal layer and the second light-transmitting layer. The sum of the thicknesses of the buffer layer and the gate insulating layer is less than the sum of the thicknesses of the passivation layer and the planarization layer.

[0016] In some embodiments, the sum of the thicknesses of the passivation layer and the planarization layer is greater than or equal to twice the sum of the thicknesses of the buffer layer and the gate insulation layer.

[0017] In some embodiments, a size of the second sub-connection line in the first direction is 3 to 5 times a size of the first sub-connection line in the first direction.

[0018] In some embodiments, when the display panel further includes a first metal layer and a second metal layer, along the first direction, each first sub-connection line located in the first metal layer and each first sub-connection line located in the second metal layer are alternately arranged in sequence.

[0019] In some embodiments, the orthographic projections of any two adjacent first sub-connection lines on the substrate do not overlap.

[0020] In some embodiments, the second metal layer further includes: at least one second sub-connection line. The orthographic projection of the second sub-connection line on the substrate does not overlap with the orthographic projections of the plurality of first sub-connection lines on the substrate, and there is a spacing between the orthographic projection of the second sub-connection line on the substrate and the orthographic projection of the adjacent first sub-connection line on the substrate.

[0021] In some embodiments, at least one of the third sub-connection lines is not located in the second metal layer. The orthographic projection of the third sub-connection line on the substrate partially overlaps with the orthographic projection of the second sub-connection line on the substrate.

[0022] In some embodiments, the plurality of signal transmission lines include a plurality of data lines and a plurality of sensing lines, and the plurality of first sub-connection lines include a plurality of data connection lines and a plurality of sensing connection lines. A data connection line is electrically connected to a data line, and a sensing connection line is electrically connected to a sensing line. At least two data connection lines are arranged between any two adjacent sensing connection lines.

[0023] In some embodiments, a first-stage shift register is electrically connected to at least one row of sub-pixels. The shift register includes a plurality of device groups, one device group is located in a region between two adjacent sub-pixels in the at least one row of sub-pixels; the device group includes at least one transistor and / or at least one capacitor. A clock signal line is electrically connected to at least one first-stage shift register; the clock signal line is located between two adjacent columns of sub-pixels.

[0024] In another aspect, a display device is provided, comprising: a display panel as described in any one of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the products involved in the embodiments of the present disclosure.

[0026] Figure 1 is a structural diagram of a display panel according to an implementation manner;

[0027] Figure 2 is a structural diagram of a display device according to some embodiments of the present disclosure;

[0028] Figure 3 is a structural diagram of a display panel according to some embodiments of the present disclosure;

[0029] Figure 4 is a structural diagram of a sub-pixel according to some embodiments of the present disclosure;

[0030] Figure 5 is a circuit diagram of a shift register according to some embodiments of the present disclosure;

[0031] Figure 6 is a circuit diagram of another shift register according to some embodiments of the present disclosure;

[0032] Figure 7 is a circuit diagram of yet another shift register according to some embodiments of the present disclosure;

[0033] Figure 8 is a circuit diagram of yet another shift register according to some embodiments of the present disclosure;

[0034] Fig. 9 is a structural diagram of a gate driving circuit according to some embodiments of the present disclosure;

[0035] Fig.10 According to some embodiments of the present disclosure, Figure 6 The timing control diagram of the shift register shown;

[0036] Fig.11 is a partial structural diagram of a sub-pixel and a gate driving circuit according to some embodiments of the present disclosure;

[0037] Fig.12 is a partial enlarged view of a sub-pixel according to some embodiments of the present disclosure;

[0038] Fig.13 for Fig.12 A cross-sectional view of the structure shown along the MM' direction;

[0039] Fig.14 is a structural diagram of a connection line according to an implementation manner;

[0040] Fig.15 For the corresponding Fig.14 A timing diagram of the connecting lines shown;

[0041] Fig.16 is a structural diagram of a connecting line according to some embodiments of the present disclosure;

[0042] Fig.17 for Fig.16 A cross-sectional view of the structure shown along the NN' direction;

[0043] Fig.18 To correspond to Fig.16 A timing diagram of the connecting lines shown;

[0044] Fig.19 is a structural diagram of another connecting line in some embodiments of the present disclosure;

[0045] Fig. 20 for Fig.19 A cross-sectional view of the structure shown along the OO' direction;

[0046] Fig.21 is a structural diagram of another connecting line in some embodiments of the present disclosure;

[0047] Fig. 22 for Fig.21 A cross-sectional view of the structure shown along the PP' direction;

[0048] Fig.23 To correspond to Fig.21 A timing diagram of the connecting lines shown. DETAILED DESCRIPTION

[0049] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0050] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and other forms thereof, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open, inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0051] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0052] When describing some embodiments, the term "connected" and its derivative expressions may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0053] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0054] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0055] As used herein, the term "if" is optionally interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined that" or "if [a stated condition or event] is detected" are optionally interpreted to mean "upon determining that" or "in response to determining that" or "upon detecting [a stated condition or event]" or "in response to detecting [a stated condition or event]," depending on the context.

[0056] The use of "adapted to" or "configured to" herein is meant to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0057] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0058] As used herein, "about" or "approximately" includes the stated value and the average value that is within an acceptable range of deviation from the particular value, where the acceptable range of deviation is determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0059] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0060] The transistors used in the circuits provided in the embodiments of the present disclosure may be thin film transistors, field effect transistors (such as oxide thin film transistors) or other switching devices with the same characteristics. The embodiments of the present disclosure are described using thin film transistors as examples.

[0061] In some embodiments, the control electrode of each transistor used in the shift register is the gate of the transistor, the first electrode is one of the source and drain of the transistor, and the second electrode is the other of the source and drain of the transistor. Since the source and drain of the transistor can be symmetrical in structure, the source and drain thereof can be indistinguishable in structure, that is, the first electrode and the second electrode of the transistor in the embodiments of the present disclosure can be indistinguishable in structure. Exemplarily, in the case where the transistor is a P-type transistor, the first electrode of the transistor is the source and the second electrode is the drain; Exemplarily, in the case where the transistor is an N-type transistor, the first electrode of the transistor is the drain and the second electrode is the source.

[0062] In the circuit provided by the embodiments of the present disclosure, nodes such as pull-up nodes and pull-down nodes do not represent actual existing components, but represent the junction points of related electrical connections in the circuit diagram, that is, these nodes are nodes formed by the equivalent junction points of related electrical connections in the circuit diagram.

[0063] In the embodiments of the present disclosure, the term "pull-up" means charging a node or an electrode of a transistor so that the absolute value of the level of the node or the electrode is increased, thereby realizing the operation of the corresponding transistor (e.g., turn-on). The term "pull-down" means discharging a node or an electrode of a transistor so that the absolute value of the level of the node or the electrode is reduced, thereby realizing the operation of the corresponding transistor (e.g., turn-off).

[0064] In the following, in the circuits provided in the embodiments of the present disclosure, N-type transistors are used as examples for description.

[0065] Some embodiments of the present disclosure provide a display panel 100 and a display device 1000 . The display panel 100 and the display device 1000 are respectively introduced below.

[0066] Some embodiments of the present disclosure provide a display device 1000, such as Figure 2 As shown. The display device 1000 can be any device that displays an image, whether in motion (e.g., video) or fixed (e.g., still image), and whether text or. More specifically, it is contemplated that the embodiments described may be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controls and / or displays, displays of camera views (e.g., displays of rear-view cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of a piece of jewelry), etc.

[0067] In some examples, the display device 1000 includes a frame, a display panel 100 disposed in the frame, a circuit board, a display driver IC (Integrated Circuit), and other electronic components.

[0068] The above-mentioned display panel 100 can be, for example: an organic light emitting diode (OLED) display panel, a quantum dot light emitting diode (QLED) display panel, a micro light emitting diode (Micro LED) display panel or a mini light emitting diode (Mini LED) display panel, etc., and the present disclosure does not make any specific limitations on this.

[0069] In the following, some embodiments of the present disclosure are schematically described by taking the display panel 100 as an OLED display panel as an example.

[0070] In some examples, such as Figure 3 As shown, the display panel 100 has a display area A. Of course, the display panel 100 may also have a frame area B. The frame area B may be located beside the display area A.

[0071] Exemplarily, the side refers to one side, two sides, three sides or the periphery of the display area A. That is, the frame area B may be located on one side, two sides or three sides of the display area A, or may be located on the periphery of the display area A, surrounding the display area A.

[0072] In some examples, such as Figure 3 As shown, the display panel 100 may include: a substrate 1 , a plurality of sub-pixels 2 , a plurality of transmission signal lines 3 and a scan driving circuit 4 .

[0073] There are many types of the substrate 1, which can be selected according to actual needs.

[0074] Exemplarily, the substrate 1 may be a rigid substrate, such as a glass substrate or a PMMA (Polymethyl methacrylate) substrate.

[0075] Exemplarily, the substrate 1 may be a flexible substrate. The flexible substrate may be, for example, a PET (Polyethyleneterephthalate) substrate, a PEN (Polyethylene naphthalate twoformic acid glycol ester) substrate, or a PI (Polyimide) substrate. In this case, the display panel 100 may be a flexible display panel.

[0076] In some examples, such as Figure 3 As shown, the above-mentioned multiple sub-pixels 2 are arranged on one side of the substrate 1 and are located in the display area A. The multiple sub-pixels 2 can be arranged into multiple rows along the first direction X, and arranged into multiple columns along the second direction Y. Each row of sub-pixels 2 may include multiple sub-pixels 2, and each column of sub-pixels 2 may include multiple sub-pixels 2. Among them, the number of sub-pixels 2 included in different rows of sub-pixels 2 may be the same or different; the number of sub-pixels 2 included in different columns of sub-pixels 2 may be the same or different. The number of sub-pixels 2 included in different rows of sub-pixels 2 and the number of sub-pixels 2 included in different columns of sub-pixels 2 can be selected and set according to actual needs (such as the shape of the display panel 100).

[0077] Here, the first direction X and the second direction Y intersect each other. The angle between the first direction X and the second direction Y can be set according to actual needs. For example, the angle between the first direction X and the second direction Y can be 85°, 89°, 90°, 92° or 95°, etc.

[0078] There are many arrangements of the plurality of sub-pixels 2, which can be selected and set according to actual needs.

[0079] For example, Figure 3 As shown, the plurality of sub-pixels 2 are relatively evenly arranged on one side of the substrate 1. The intervals between any two adjacent sub-pixels 2 are equal or substantially equal.

[0080] For another example, at least two sub-pixels 2 form a group of sub-pixels, and the multiple groups of sub-pixels are arranged in multiple rows along the first direction X and in multiple columns along the second direction Y. Fig.11 As shown, four sub-pixels 2 constitute a group of sub-pixels, and the four sub-pixels 2 include, for example, a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel.

[0081] For example, Figure 4 and Fig.11 As shown, among the above-mentioned multiple sub-pixels 2, each sub-pixel 2 may include a pixel driving circuit 21 and a light-emitting device 22 electrically connected to the pixel driving circuit 21. In a direction perpendicular to the substrate 1, the light-emitting device 22 may be located, for example, on a side of the pixel driving circuit 21 away from the substrate 1. In a direction parallel to the substrate 1, the orthographic projections of the light-emitting device 22 and the pixel driving circuit 21 on the substrate 1 may, for example, have no overlap or partially overlap.

[0082] The structure of the above-mentioned light-emitting device 22 includes various structures, which can be selected and set according to actual needs. For example, the light-emitting device 22 may include an anode, a light-emitting layer and a cathode stacked in sequence. In addition, the light-emitting device 22 may also include a hole injection layer and / or a hole transport layer arranged between the anode and the light-emitting layer, and may also include an electron transport layer and / or an electron injection layer arranged between the light-emitting layer and the cathode. Among them, the pixel driving circuit 21 is electrically connected to the anode of the light-emitting device 22, for example.

[0083] Exemplarily, at least one of the anode and the cathode may be made of a conductive material with high light transmittance, such as indium tin oxide (ITO).

[0084] When the anode is a light-transmitting layer, the light emitted by the light-emitting device 22 can be emitted in the direction pointing to the substrate 1. In this case, the display panel 100 can be a bottom-emitting display panel. When the cathode is a light-transmitting layer, the light emitted by the light-emitting device 22 can be emitted in the direction away from the substrate 1. In this case, the display panel 100 can be a top-emitting display panel. When both the anode and the cathode are light-transmitting layers, the display panel 100 can emit light from both sides.

[0085] The structure of the above-mentioned pixel driving circuit 21 includes multiple types, which can be selected and set according to actual needs. For example, the structure of the pixel driving circuit 21 may include a structure such as "2T1C", "3T1C", "6T1C", "7T1C", "6T2C" or "7T2C". Here, "T" represents a thin film transistor, and the number in front of "T" represents the number of thin film transistors, and "C" represents a storage capacitor, and the number in front of "C" represents the number of storage capacitors. Among them, the pixel driving circuit 21 may include, for example, a switching transistor and a driving transistor.

[0086] In some examples, such as Figure 3 As shown, the display panel 100 may further include: a plurality of gate lines GL disposed on one side of the substrate 1 and extending along the first direction X, a plurality of data lines DL extending along the second direction Y, and a plurality of power supply voltage signal lines EL extending along the second direction Y.

[0087] Exemplarily, the plurality of data lines DL may be located on a side of the plurality of gate lines GL away from the substrate 1 and insulated from each other. The plurality of power supply voltage signal lines EL may be located on a side of the plurality of gate lines GL away from the substrate 1 and insulated from each other. The plurality of data lines DL and the plurality of power supply voltage signal lines EL may be arranged in the same layer and insulated from each other.

[0088] It should be noted that the "same layer" mentioned in this article refers to a layer structure formed by using the same film-forming process to form a film layer for forming a specific pattern, and then using the same mask template through a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses. In this way, the above-mentioned multiple data lines DL and multiple power supply voltage signal lines EL can be prepared and formed simultaneously in a single patterning process, which is conducive to simplifying the preparation process of the display panel 100.

[0089] Of course, the plurality of data lines DL and the plurality of power supply voltage signal lines EL may be located in different layers and insulated from each other. For example, the plurality of power supply voltage signal lines EL may be located on a side of the plurality of data lines DL away from the substrate 1 .

[0090] By arranging the data line DL and the power voltage signal line EL in different layers, it is beneficial to increase the wiring space and reduce the wiring difficulty.

[0091] For example, Figure 3 and Fig.11As shown, one gate line GL can be electrically connected to multiple pixel driving circuits 21 in at least one row of sub-pixels 2, one data line DL can be electrically connected to multiple pixel driving circuits 21 in at least one column of sub-pixels 2, and one power supply voltage signal line EL can be electrically connected to multiple pixel driving circuits 21 in at least one column of sub-pixels 2. The number of gate lines GL electrically connected to multiple pixel driving circuits 21 in the same row of sub-pixels 2 can be set according to the structure of the pixel driving circuit 21.

[0092] For example, Fig.11 As shown, one data line DL can be electrically connected to a plurality of pixel driving circuits 21 in one column of sub-pixels 2 , and one power supply voltage signal line EL can be electrically connected to a plurality of pixel driving circuits 21 in four columns of sub-pixels 2 .

[0093] Of course, illustratively, the display panel 100 may further include: a plurality of enable signal lines disposed on one side of the substrate 1 and extending along the first direction X. illustratively, the plurality of enable signal lines may be disposed in the same layer as the plurality of gate lines GL; or, the plurality of enable signal lines may be located in a different layer from the plurality of gate lines GL and be insulated from the plurality of gate lines GL.

[0094] Exemplarily, one enable signal line may be electrically connected to a plurality of pixel driving circuits 21 in the same row of sub-pixels 2. The configuration of the enable signal line may be determined according to the structure of the pixel driving circuit.

[0095] During the display process of the display panel 100, the pixel driving circuit 21 can receive the scanning signal from the corresponding gate line GL, the data signal from the corresponding data line DL, and the power supply voltage signal from the power supply voltage signal line EL to form a driving current, and transmit the driving current to the light-emitting device 22 to drive the light-emitting device 22 to emit light. Alternatively, the pixel driving circuit 21 can receive the scanning signal from the corresponding gate line GL, the data signal from the corresponding data line DL, the power supply voltage signal from the power supply voltage signal line EL, and the enable signal from the corresponding enable signal line to form a driving current, and transmit the driving current to the light-emitting device 22 to drive the light-emitting device 22 to emit light. The light-emitting devices 22 of multiple sub-pixels cooperate with each other, so that the display panel 100 can display images.

[0096] The scan driving circuit 3 may have various structures, which may be selected and configured according to actual needs.

[0097] Exemplarily, the scanning driving circuit 3 may be a light emitting control circuit. When the pixel driving circuit 21 is also electrically connected to the enable signal line, the light emitting control circuit may be electrically connected to the above-mentioned multiple enable signal lines to provide the enable signal to the corresponding pixel driving circuit 21 through the multiple enable signal lines.

[0098] Exemplarily, the scan driving circuit 3 may also be a gate driving circuit. The gate driving circuit may be electrically connected to the plurality of gate lines GL to provide a scan signal to the corresponding pixel driving circuit 21 through the plurality of gate lines GL.

[0099] Here, during the use of the display panel 100, the stability of the transistors and the light-emitting devices 22 in the pixel driving circuit 21 may decrease (for example, the threshold voltage of the driving transistor drifts), affecting the display effect of the display panel 100, so that the sub-pixel 2 needs to be compensated.

[0100] There are many ways to compensate the sub-pixel 2, which can be selected according to actual needs. For example, a pixel compensation circuit can be set in the sub-pixel 2 to use the pixel compensation circuit to perform internal compensation on the sub-pixel 2. For another example, the driving transistor or the light-emitting device 22 can be sensed by the transistor inside the sub-pixel 2, and the sensed data can be transmitted to the external sensing circuit, so that the driving voltage value to be compensated can be calculated by the external sensing circuit and fed back, thereby realizing external compensation for the sub-pixel 2.

[0101] The present disclosure takes the scanning driving circuit 3 as the gate driving circuit, adopts external compensation (sensing the driving transistor) to compensate the sub-pixel 2, and the pixel driving circuit 21 adopts the 3T1C structure as an example to schematically illustrate the structure and working process of the sub-pixel 2.

[0102] For example, Figure 4 As shown, the pixel driving circuit 21 may include: a switching transistor T1, a driving transistor T2, a sensing transistor T3 and a storage capacitor Cst.

[0103] For example, Figure 4 As shown, the control electrode of the switch transistor T1 is electrically connected to the first scan signal terminal G1, the first electrode of the switch transistor T1 is electrically connected to the data signal terminal Data, and the second electrode of the switch transistor T1 is electrically connected to the first node G. The switch transistor T1 is configured to transmit the data signal received at the data signal terminal Data to the first node G in response to the first scan signal received at the first scan signal terminal G1.

[0104] Here, the data signal includes, for example, a detection data signal and a display data signal.

[0105] For example, Figure 4As shown, the control electrode of the driving transistor T2 is electrically connected to the first node G, the first electrode of the driving transistor T2 is electrically connected to the power supply voltage signal terminal ELVDD, and the second electrode of the driving transistor T2 is electrically connected to the second node S. The driving transistor T2 is configured to transmit the power supply voltage signal received at the power supply voltage signal terminal ELVDD to the second node S under the control of the voltage of the node G.

[0106] For example, Figure 4 As shown, a first end of the storage capacitor Cst is electrically connected to the first node G, and a second end of the storage capacitor Cst is electrically connected to the second node S. In the process of charging the first node G, the switch transistor T1 simultaneously charges the storage capacitor Cst.

[0107] For example, Figure 4 As shown, the anode of the light emitting device 22 is electrically connected to the second node S, and the cathode of the light emitting device 22 is electrically connected to the first voltage signal terminal ELVSS. The light emitting device 22 is configured to emit light under the cooperation of the power supply voltage signal from the second node S and the first voltage signal transmitted by the first voltage signal terminal ELVSS.

[0108] For example, Figure 4 As shown, the control electrode of the sensing transistor T3 is electrically connected to the second scanning signal terminal G2, the first electrode of the sensing transistor T3 is electrically connected to the second node S, and the second electrode of the sensing transistor T3 is electrically connected to the sensing signal terminal Sense. The sensing transistor T3 is configured to detect the electrical characteristics of the driving transistor T2 in response to the second scanning signal received at the second scanning signal terminal G2 to achieve external compensation. The electrical characteristics include, for example, the threshold voltage and / or carrier mobility of the driving transistor T2.

[0109] Here, the sensing signal terminal Sense can transmit a reset signal or obtain a sensing signal, wherein the reset signal is used to reset the second node S, and the sensing signal is used to obtain the threshold voltage of the driving transistor T2.

[0110] In this example, the display phase of one frame may include, for example, a display period and a blanking period performed sequentially.

[0111] During the display period in a frame display stage, the working process of the sub-pixel 2 may include, for example: a reset stage, a data writing stage and a light emitting stage.

[0112] In the reset stage, the level of the second scan signal transmitted by the second scan signal terminal G2 is high, and the level of the reset signal transmitted by the sensing signal terminal Sense is low. The sensing transistor T3 is turned on under the control of the second scan signal, receives the reset signal, and transmits the reset signal to the second node S to reset the second node S.

[0113] In the data writing stage, the level of the first scanning signal transmitted by the first scanning signal terminal G1 is high, and the level of the display data signal transmitted by the data signal terminal Data is high. The switching transistor T1 is turned on under the control of the first scanning signal, receives the display data signal, and transmits the display data signal to the first node G, while charging the storage capacitor Cst.

[0114] In the light-emitting stage, the level of the first scanning signal transmitted by the first scanning signal terminal G1 is low, the level of the second scanning signal transmitted by the second scanning signal terminal G2 is low, and the level of the power supply voltage signal transmitted by the power supply voltage signal terminal ELVDD is high. The switching transistor T1 is turned off under the control of the first scanning signal, and the sensing transistor T3 is turned off under the control of the second scanning signal. The storage capacitor Cst begins to discharge, so that the voltage of the first node G remains at a high level. The driving transistor T2 is turned on under the control of the voltage of the first node G, receives the power supply voltage signal, and transmits the power supply voltage signal to the second node S, so that the light-emitting device 22 emits light under the mutual cooperation of the power supply voltage signal and the first voltage signal transmitted by the first voltage signal terminal ELVSS.

[0115] During the blanking period in a frame display stage, the working process of the sub-pixel 2 may include, for example, a first stage and a second stage.

[0116] In the first stage, the level of the first scanning signal transmitted by the first scanning signal terminal G1 and the level of the second scanning signal transmitted by the second scanning signal terminal G2 are both high levels, and the level of the detection data signal transmitted by the data signal terminal Data is high. The switching transistor T1 is turned on under the control of the first scanning signal, receives the detection data signal, and transmits the detection data signal to the first node G to charge the first node G. The sensing transistor T3 is turned on under the control of the second scanning signal, receives the reset signal provided by the sensing signal terminal Sense, and transmits the reset signal to the second node S.

[0117] In the second stage, the sensing signal terminal Sense is in a suspended state. The driving transistor T2 is turned on under the control of the voltage of the first node G, receives the power supply voltage signal transmitted by the power supply voltage signal terminal ELVDD, and transmits the power supply voltage signal to the second node S, charging the second node S, so that the voltage of the second node S increases until the driving transistor T2 is turned off. At this time, the voltage difference Vgs between the first node G and the second node S is equal to the threshold voltage Vth of the driving transistor T2.

[0118] Since the sensing transistor T3 is in the on state and the sensing signal terminal Sense is in the suspended state, the sensing signal terminal Sense is also charged while the driving transistor T2 is charging the second node S. By sampling the voltage of the sensing signal terminal Sense (i.e., obtaining the sensing signal), the threshold voltage Vth of the driving transistor T2 can be calculated based on the relationship between the voltage of the sensing signal terminal Sense and the level of the detection data signal.

[0119] After the threshold voltage Vth of the driving transistor T2 is calculated, the threshold voltage Vth can be compensated into the display data signal of the display period in the next frame display stage, thereby completing the external compensation of the sub-pixel 2.

[0120] Based on the structure of the pixel driving circuit 21, the plurality of pixel driving circuits 21 in the same row of sub-pixels 2 can be electrically connected to two gate lines GL (i.e., the first gate line and the second gate line). For example, each first scanning signal terminal G1 can be electrically connected to the corresponding first gate line and receive the first scanning signal transmitted by the first gate line; each second scanning signal terminal G2 can be electrically connected to the corresponding second gate line and receive the second scanning signal transmitted by the second gate line. Moreover, each data signal terminal Data can be electrically connected to the corresponding data line DL and receive the data signal transmitted by the data line DL; each power supply voltage signal terminal ELVDD can be electrically connected to the corresponding power supply voltage signal line EL and receive the power supply voltage signal transmitted by the power supply voltage signal line EL.

[0121] In addition, for example, Figure 3 and Fig.11 As shown, the display panel 100 may further include: a plurality of sensing lines SL disposed on one side of the substrate 1 and extending along the second direction Y. The plurality of sensing lines SL may be located on a side of the plurality of gate lines GL away from the substrate 1 and insulated from each other. The plurality of sensing lines SL may, for example, be disposed on the same layer as at least one of the plurality of power supply voltage signal lines EL and the plurality of data lines DL.

[0122] Among the plurality of sensing lines SL, one sensing line SL may be electrically connected to a plurality of pixel driving circuits 21 in at least one column of sub-pixels 2. Fig.11 As shown, one sensing line SL can be electrically connected to multiple pixel driving circuits 21 in four columns of sub-pixels 2. When one data line DL is electrically connected to multiple pixel driving circuits 21 in one column of sub-pixels 2, four data lines DL can be arranged between every two adjacent sensing lines SL.

[0123] like Figure 2 and Figure 4As shown, each of the sensing signal terminals Sense may be electrically connected to a corresponding sensing line SL, and receive a reset signal transmitted by the sensing line SL or transmit a sensing signal to the sensing line SL.

[0124] It should be noted here that since the data lines DL and the sensing lines SL both extend along the second direction Y, and one data line DL is electrically connected to at least one column of sub-pixels 2, and one sensing line SL is electrically connected to at least one column of sub-pixels 2, some embodiments of the present disclosure collectively refer to the above-mentioned multiple data lines DL and multiple sensing lines SL as multiple signal transmission lines 3, so as to more clearly and concisely describe the structure of the display panel 100.

[0125] In some examples, such as Figure 3 As shown, the scanning driving circuit 4 can be located on the same side of the substrate 1 as the plurality of sub-pixels 2 and the plurality of signal transmission lines 3. The scanning driving circuit 4 can include a multi-stage shift register 41, and the multi-stage shift register 41 is cascaded. A stage shift register 41 can be electrically connected to a plurality of pixel driving circuits 21 in at least one row of sub-pixels 2.

[0126] It should be noted that, in the display stage of one frame, the first scanning signal transmitted by the first scanning signal terminal G1 and the second scanning signal transmitted by the second scanning signal terminal G2 are both provided by the scanning driving circuit 4. That is, each stage of the shift register 41 in the scanning driving circuit 4 can be electrically connected to the first scanning signal terminal G1 through the first gate line, transmit the first scanning signal to the first scanning signal terminal G1 through the first gate line, and be electrically connected to the second scanning signal terminal G2 through the second gate line, and transmit the second scanning signal to the second scanning signal terminal G2 through the second gate line.

[0127] The shift register 31 has a variety of structures, which can be selected and set according to actual needs. The following schematically illustrates the structures of the shift register 31 with four structures, but the shift register 31 in the present disclosure is not limited to the four structures.

[0128] In some examples, the first-stage shift register 41 may be electrically connected to a plurality of pixel driving circuits 21 in a row of sub-pixels 2 .

[0129] like Figure 5 As shown, the shift register 41 may include, for example: a first input circuit 4101, an anti-leakage circuit 4102, an output circuit 4103, a control circuit 4104, a first reset circuit 4105, a second reset circuit 4106, a third reset circuit 4107, a fourth reset circuit 4108, a fifth reset circuit 4109, a blanking circuit 4110, and a sixth reset circuit 4111. Of course, the shift register 41 may include only some of the multiple circuits, as long as the sub-pixel 2 can realize the above working process.

[0130] For example, Figure 5 As shown, the first input circuit 4101 is connected to the input signal terminal Input (abbreviated as Iput in the figure and below), the pull-up node Q <n>And leakage protection node OFF <n>The first input circuit 4101 is configured to transmit the input signal to the pull-up node Q in response to the input signal received at the input signal terminal Iput during the display period of a frame display stage. <n>. Wherein, N is a positive integer, which represents the number of rows of sub-pixels.

[0131] For example, during a display period in a frame display stage, when the level of the input signal is high, the first input circuit 4101 can be turned on by the input signal and transmit the input signal to the pull-up node Q <n>, pull up node Q <n>Charging is performed so that the pull-up node Q <n>The voltage increases.

[0132] Optional, such as Figure 5 As shown, the first input circuit 4101 may include: a first transistor M1 and a second transistor M2.

[0133] For example, Figure 5 As shown, the control electrode of the first transistor M1 is electrically connected to the input signal terminal Iput, the first electrode of the first transistor M1 is electrically connected to the input signal terminal Iput, and the second electrode of the first transistor M1 is electrically connected to the first electrode of the second transistor M2 and the first anti-leakage node OFF1. The control electrode of the second transistor M2 is electrically connected to the input signal terminal Iput, and the second electrode of the second transistor M2 is electrically connected to the first pull-up node Q <n>Electrical connection.

[0134] Here, during a display period in a frame display stage, when the level of the input signal transmitted by the input signal terminal Iput is high, the first transistor M1 and the second transistor M2 can be turned on at the same time under the action of the input signal. The first transistor M1 can receive the input signal transmitted by the input signal terminal Iput, and transmit the received input signal to the first electrode and the anti-leakage node OFF of the second transistor M2. <n>The second transistor M2 can transmit the input signal from the first transistor M1 to the pull-up node Q <n>, pull up node Q <n>Charging is performed so that the pull-up node Q <n>The voltage increases.

[0135] For example, Figure 5 As shown, the leakage protection circuit 4102 and the pull-up node Q <n>, the second voltage signal terminal VDD and the leakage prevention node OFF <n>The leakage protection circuit 4102 is configured to pull up the node Q <n>Under the control of the voltage of the second voltage signal terminal VDD, the second voltage signal received at the second voltage signal terminal VDD is transmitted to the leakage prevention node OFF <n>to prevent the pull-up of node Q <n>The second voltage signal is, for example, a constant high voltage signal.

[0136] For example, at the pull-up node Q <n>When the voltage of is high, the leakage protection circuit 4102 can pull up the node Q <n>The second voltage signal is received and transmitted to the anti-leakage node OFF. <n>, making the leakage protection node OFF <n>The voltage increases.

[0137] Optional, such as Figure 5 As shown, the leakage protection circuit 4102 may include: a third transistor M3.

[0138] For example, Figure 5 As shown, the control electrode of the third transistor M3 is connected to the pull-up node Q <n>The first electrode of the third transistor M3 is electrically connected to the second voltage signal terminal VDD, and the second electrode of the third transistor M3 is electrically connected to the anti-leakage node OFF <n>Electrical connection.

[0139] Here, at the pull-up node Q <n>When the voltage of is high, the third transistor M3 can pull up the node Q <n>The second voltage signal is received and transmitted to the anti-leakage node OFF. <n>, making the leakage protection node OFF <n>The voltage of the second transistor M2 is increased, and the voltage difference between the control electrode and the first electrode of the second transistor M2 is less than zero, ensuring that the second transistor M2 is completely or relatively completely turned off. This can avoid pulling up the node Q <n>Leakage occurs through the first input circuit 4101, causing the pull-up node Q <n>Able to maintain a higher and more stable voltage.

[0140] For example, Figure 5 As shown, the output circuit 4103 and the pull-up node Q <n>, the first clock signal terminal CLKD_1, the shift signal terminal CR <n>, the second clock signal terminal CLKE_1 and the first output signal terminal Output1 <n>(The attached figure and the following text are abbreviated as Oput1 <n>) is electrically connected. The output circuit 4103 is configured to pull up the node Q during the display period of a frame display stage. <n>Under the control of the voltage of <n>, the second clock signal received at the second clock signal terminal CLKE_1 is transmitted to the first output signal terminal Oput1 <n>And, during the blanking period in a frame display phase, the pull-up node Q <n>Under the control of the voltage of <n>.

[0141] For example, during the display period of a frame display stage, at the pull-up node Q <n>When the voltage of the output circuit 4103 increases, the output circuit 4103 can pull up the node Q <n>The first clock signal received at the first clock signal terminal CLKD_1 is turned on under the control of the voltage of the first clock signal terminal CLKD_1, and the first clock signal received at the first clock signal terminal CLKD_1 is used as the shift signal, and the first clock signal received at the first clock signal terminal CLKD_1 is turned on under the control of the voltage of the first clock signal terminal CLKD_1, and the first clock signal received at the first clock signal terminal CLKD_1 is used as the shift <n>Output; the second clock signal received at the second clock signal terminal CLKE_1 is used as the first output signal (ie, the first scanning signal received by the pixel driving circuit 21), from the first output signal terminal Oput1 <n>Output. During the blanking period in a frame display phase, the pull-up node Q <n>When the voltage of the output circuit 4103 increases, the output circuit 4103 can pull up the node Q <n>The second clock signal received at the second clock signal terminal CLKE_1 is turned on under the control of the voltage of the pixel driving circuit 21, and the second clock signal received at the second clock signal terminal CLKE_1 is used as the first output signal (that is, the second scanning signal received by the pixel driving circuit 21), and the first output signal terminal Oput1 is output. <n>Output.

[0142] In this example, for example, the first output signal terminal Oput1 of the shift register 31 <n>It can be electrically connected to both the first gate line and the second gate line, so that during a display period in a frame display stage, the first output signal terminal Oput1 of the shift register 31 <n>The first output signal can be used as a first scanning signal, and is sequentially transmitted to the corresponding pixel driving circuit 21 through the first gate line and the first scanning signal terminal G1, and during the blanking period in a frame display stage, the first output signal terminal Oput1 of the shift register 31 is <n>The first output signal can be used as a second scanning signal, and is sequentially transmitted to the corresponding pixel driving circuit 21 via the second gate line and the second scanning signal terminal G2. <n>The first output signal terminal Oput1 of the shift register 31 can be electrically connected to the first scanning signal terminal G1 and the second scanning signal terminal G2 through a gate line, so that during a display period of a frame display stage, the first output signal terminal Oput1 of the shift register 31 <n>The first scanning signal can be transmitted to the pixel driving circuit 21 via the gate line and the first scanning signal terminal G1 in sequence, and during the blanking period in a frame display stage, the first output signal terminal Oput1 of the shift register 31 <n>The second scanning signal may be transmitted to the pixel driving circuit 21 via the gate line and the second scanning signal terminal G2 in sequence.

[0143] Optional, such as Figure 5 As shown, the output circuit 4103 may include: a fourth transistor M4, a fifth transistor M5 and a first capacitor C1.

[0144] For example, Figure 5 As shown, the control electrode of the fourth transistor M4 is connected to the pull-up node Q <n>The first electrode of the fourth transistor M4 is electrically connected to the first clock signal terminal CLKD_1, and the second electrode of the fourth transistor M4 is electrically connected to the shift signal terminal CR <n>Electrical connection.

[0145] During the display period of a frame display stage, the first input circuit 4101 is turned on, so that the pull-up node Q <n>When the voltage of the node Q increases, the fourth transistor M4 can pull up the node Q <n>The first clock signal is received and transmitted to the shift signal terminal CR under the control of the high voltage of <n>and uses the first clock signal as a shift signal from the shift signal terminal CR <n>Output.

[0146] For example, Figure 5 As shown, the control electrode of the fifth transistor M5 is connected to the pull-up node Q <n>The first electrode of the fifth transistor M5 is electrically connected to the second clock signal terminal CLKE_1, and the second electrode of the fifth transistor M5 is electrically connected to the first output signal terminal Oput1 <n>The first end of the first capacitor C1 is electrically connected to the pull-up node Q <n>The second end of the first capacitor C1 is electrically connected to the first output signal end Oput1 <n>Electrical connection.

[0147] During the display period of a frame display stage, when the first input circuit 4101 is turned on, the pull-up node Q <n>When the voltage of the first input circuit 4101 is turned off, the first capacitor C1 can be discharged, so that the pull-up node Q <n>Maintaining a high level, the fifth transistor M5 can remain in a conducting state, receiving and transmitting the second clock signal to the first output signal terminal Oput1 <n>and uses the second clock signal as the first output signal (that is, the first scanning signal received by the pixel driving circuit 21) from the first output signal terminal Oput1 <n>Output.

[0148] During the blanking period of a frame display stage, the pull-up node Q <n>When the voltage of the first capacitor C1 increases, the first capacitor C1 will be charged. In the corresponding stage, the first capacitor C1 can be discharged, so that the pull-up node Q <n>The fifth transistor M5 is kept at a high level, so that the second clock signal is transmitted to the first output signal terminal Oput1. <n>and uses the second clock signal as the first output signal (that is, the second scanning signal received by the pixel driving circuit 21) from the first output signal terminal Oput1 <n>Output.

[0149] Here, after the multiple-stage shift registers 41 are cascaded to form the scan driving circuit 4, the shift signal terminal CR in the N-th stage shift register 41 is <n>For example, it can be electrically connected to the input signal terminal Iput in the N+1th stage shift register 41, thereby connecting the shift signal terminal CR of the Nth stage shift register 41 to the input signal terminal Iput of the N+1th stage shift register 41. <n>The output shift signal is used as an input signal in the (N+1)th stage shift register 41. Of course, the cascade connection of the multiple stages of shift registers 41 is not limited to this.

[0150] In addition, the input signal terminal Iput of the partial shift register 41 can be electrically connected to the start signal terminal STU, so as to receive the start signal transmitted by the start signal terminal STU as an input signal. The partial shift register 41 can be, for example, the first-stage shift register 41 in the scan drive circuit 4, or can be, for example, the first-stage shift register 41 and the second-stage shift register 41, etc.

[0151] Here, the number of the shift registers 41 electrically connected to the start signal terminal STU is not limited and can be selected and set according to actual needs.

[0152] For example, Figure 5 As shown, the control circuit 4104 and the pull-up node Q <n>, the third voltage signal terminal VDD_A, the pull-down node QB_A <n>The control circuit 4104 is configured to pull up the node Q <n>The pull-down node QB_A is controlled by the voltage of the third voltage signal terminal VDD_A and the third voltage signal transmitted by the third voltage signal terminal VDD_A. <n>The voltage of the third voltage signal can be controlled. The level of the third voltage signal can be unchanged in the display stage of one frame. The fourth voltage signal terminal VGL1 can be configured to transmit a DC low-level signal (for example, lower than or equal to the low-level part of the clock signal). The fourth voltage signal terminal VGL1 can be grounded, for example.

[0153] For example, in the display phase of a frame, the level of the third voltage signal is high. <n>When the voltage of the fourth voltage signal terminal VGL1 increases, the control circuit 4104 may transmit the fourth voltage signal transmitted by the fourth voltage signal terminal VGL1 to the pull-down node QB_A <n>, pull down node QB_A <n>The voltage of the pull-up node Q <n>When the voltage of the third voltage signal terminal VDD_A is at a low level, the control circuit 4104 can transmit the third voltage signal transmitted by the third voltage signal terminal VDD_A to the pull-down node QB_A. <n>, pull down node QB_A <n>The voltage is pulled up to a high level.

[0154] Optional, such as Figure 5 As shown, the control circuit 4104 may include: a seventh transistor M7, an eighth transistor M8, a ninth transistor M9 and a tenth transistor M10.

[0155] For example, Figure 5 As shown, the control electrode of the seventh transistor M7 is electrically connected to the third voltage signal terminal VDD_A, the first electrode of the seventh transistor M7 is electrically connected to the third voltage signal terminal VDD_A, the second electrode of the seventh transistor M7 is electrically connected to the control electrode of the eighth transistor M8 and the first electrode of the ninth transistor M9. The first electrode of the eighth transistor M8 is electrically connected to the third voltage signal terminal VDD_A, the second electrode of the eighth transistor M8 is electrically connected to the pull-down node QB_A <n>The control electrode of the ninth transistor M9 is electrically connected to the pull-up node Q <n>The control electrode of the tenth transistor M10 is electrically connected to the pull-up node Q. <n>The second electrode of the tenth transistor M10 is electrically connected to the fourth voltage signal terminal VGL1.

[0156] When the level of the third voltage signal transmitted by the third voltage signal terminal VDD_A is high, the seventh transistor M7 can be turned on under the action of the third voltage signal, and receive and transmit the third voltage signal to the control electrode of the eighth transistor M8 and the first electrode of the ninth transistor M9. The eighth transistor M8 can be turned on under the action of the third voltage signal, and receive and transmit the third voltage signal to the pull-down node QB_A. <n>and a first electrode of the tenth transistor M10.

[0157] At the pull-up node Q <n>When the voltage of Q is high, the ninth transistor M9 and the tenth transistor M10 can pull up the node Q <n>The ninth transistor M9 can transmit the fourth voltage signal transmitted by the fourth voltage signal terminal VGL1 to the control electrode of the eighth transistor M8, so that the eighth transistor M8 is turned off, and the tenth transistor M10 can transmit the fourth voltage signal to the pull-down node QB_A <n>, pull down node QB_A <n>The voltage is pulled down to a low level.

[0158] At the pull-up node Q <n>When the voltage of Q is low, the ninth transistor M9 and the tenth transistor M10 can pull up the node Q <n>The eighth transistor M8 can transmit the received third voltage signal to the pull-down node QB_A. <n>, pull down node QB_A <n>The voltage is pulled up to a high level.

[0159] For example, Figure 5 As shown, the first reset circuit 4105 and the pull-down node QB_A <n>, pull up node Q <n>, the fourth voltage signal terminal VGL1 and the leakage protection node OFF <n>The first reset circuit 4105 is configured to pull down the node QB_A. <n>Under the control of the voltage on the pull-up node Q <n>Perform a reset.

[0160] For example, in the drop-down node QB_A <n>When the voltage of QB_A is high, the first reset circuit 4105 can pull down the node QB_A <n>The fourth voltage signal transmitted by the fourth voltage signal terminal VGL1 is transmitted to the pull-up node Q <n>, pull up node Q <n>Pull-down reset.

[0161] Optional, such as Figure 5 As shown, the first reset circuit 4105 may include: an eleventh transistor M11 and a twelfth transistor M12.

[0162] For example, Figure 5 As shown, the control electrode of the eleventh transistor M11 is connected to the pull-down node QB_A. <n>The first electrode of the eleventh transistor M11 is electrically connected to the pull-up node Q <n>The second electrode of the eleventh transistor M11 is electrically connected to the first electrode of the twelfth transistor M12 and the leakage prevention node OFF. <n>The control electrode of the twelfth transistor M12 is electrically connected to the pull-down node QB_A. <n>The second electrode of the twelfth transistor M12 is electrically connected to the fourth voltage signal terminal VGL1.

[0163] In the drop-down node QB_A <n>When the voltage of QB_A is high, the eleventh transistor M11 and the twelfth transistor M12 can pull down the node QB_A. <n>The twelfth transistor M12 can transmit the fourth voltage signal transmitted by the fourth voltage signal terminal VGL1 to the anti-leakage node OFF. <n>, the eleventh transistor M11 can turn off the leakage protection node <n>The fourth voltage signal is transmitted to the pull-up node Q <n>, pull up node Q <n>Perform a reset.

[0164] Here, at the pull-up node Q <n>When the potential of the first reset circuit 4105 is high and the first reset circuit 4105 is not in operation, the third transistor M3 can pull up the node Q <n>The second voltage signal is transmitted to the anti-leakage node OFF. <n>, making the leakage protection node OFF <n>The voltage of the eleventh transistor M11 is increased, so that the voltage difference between the control electrode and the second electrode of the eleventh transistor M11 is less than zero, ensuring that the eleventh transistor M11 is completely or relatively completely turned off. <n>Leakage occurs through the first reset circuit 4105, causing the node Q to be pulled up. <n>Able to maintain a higher and more stable voltage.

[0165] For example, Figure 5 As shown, the second reset circuit 4106 is connected to the display reset signal terminal STD and the pull-up node Q <n>, the fourth voltage signal terminal VGL1 and the leakage protection node OFF <n>The second reset circuit 4106 is configured to, under the control of the display reset signal transmitted by the display reset signal terminal STD, pull up the node Q <n>Perform a reset.

[0166] For example, when the level of the display reset signal is high, the second reset circuit 4106 can be turned on under the action of the display reset signal to transmit the fourth voltage signal transmitted by the fourth voltage signal terminal VGL1 to the pull-up node Q <n>, pull up node Q <n>Pull-down reset.

[0167] Optional, such as Figure 5 As shown, the second reset circuit 4106 may include: a thirteenth transistor M13 and a fourteenth transistor M14.

[0168] For example, Figure 5 As shown, the control electrode of the thirteenth transistor M13 is electrically connected to the display reset signal terminal STD, and the first electrode of the thirteenth transistor M13 is electrically connected to the pull-up node Q <n>The second electrode of the thirteenth transistor M13 is electrically connected to the first electrode of the fourteenth transistor M14 and the anti-leakage node OFF <n>The control electrode of the fourteenth transistor M14 is electrically connected to the display reset signal terminal STD, and the second electrode of the fourteenth transistor M14 is electrically connected to the fourth voltage signal terminal VGL1.

[0169] When the voltage of the display reset signal is at a high level, the thirteenth transistor M13 and the fourteenth transistor M14 can be turned on at the same time under the action of the display reset signal, and the fourteenth transistor M14 can transmit the fourth voltage signal transmitted by the fourth voltage signal terminal VGL1 to the anti-leakage node OFF <n>, the thirteenth transistor M13 can turn off the leakage protection node <n>The fourth voltage signal is transmitted to the pull-up node Q <n>, pull up node Q <n>Perform a reset.

[0170] Here, at the pull-up node Q <n>When the potential of the node Q is high and the second reset circuit 4106 is not in operation, the third transistor M3 can pull up the node Q <n>The second voltage signal is transmitted to the anti-leakage node OFF. <n>, making the leakage protection node OFF <n>The voltage of the thirteenth transistor M13 is increased, so that the voltage difference between the control electrode and the second electrode of the thirteenth transistor M13 is less than zero, ensuring that the thirteenth transistor M13 is completely or relatively completely turned off. <n>Leakage occurs through the second reset circuit 4106, causing the pull-up node Q <n>Able to maintain a higher and more stable voltage.

[0171] Here, after the multiple shift registers 41 are cascaded to form the scan driving circuit 4, the display reset signal terminal STD of the Nth stage shift register 41 can be connected to the shift signal terminal CR of the N+1th stage shift register 41. <n>The shift signal terminal CR of the N+1th stage shift register 41 is electrically connected to <n>The output shift signal serves as a display reset signal of the Nth stage shift register 41 .

[0172] Of course, the relationship of the cascade connection of the multiple shift registers 41 is not limited to this. For example, the display reset signal terminal STD of the Nth stage shift register 41 can be connected to the shift signal terminal CR of the N+4th stage shift register 41. <n>The shift signal terminal CR of the N+4th stage shift register 41 is electrically connected to <n>The output shift signal serves as a display reset signal of the Nth stage shift register 41 .

[0173] For example, Figure 5 As shown, the third reset circuit 4107 is connected to the global reset signal terminal TRST and the pull-up node Q <n>, the fourth voltage signal terminal VGL1 and the leakage protection node OFF <n>The third reset circuit 4107 is configured to, under the control of the global reset signal transmitted by the global reset signal terminal TRST, pull up the node Q <n>Perform a reset.

[0174] For example, when the level of the global reset signal is high, the third reset circuit 4107 can be turned on under the action of the global reset signal to transmit the fourth voltage signal transmitted by the fourth voltage signal terminal VGL1 to the pull-up node Q <n>, pull up node Q <n>Pull-down reset.

[0175] Optional, such as Figure 5 As shown, the third reset circuit 4107 may include: a fifteenth transistor M15 and a sixteenth transistor M16.

[0176] For example, Figure 5 As shown, the control electrode of the fifteenth transistor M15 is electrically connected to the global reset signal terminal TRST, and the first electrode of the fifteenth transistor M15 is electrically connected to the pull-up node Q <n>The second electrode of the fifteenth transistor M15 is electrically connected to the first electrode of the sixteenth transistor M16 and the anti-leakage node OFF. <n>The control electrode of the sixteenth transistor M16 is electrically connected to the global reset signal terminal TRST, and the second electrode of the sixteenth transistor M16 is electrically connected to the fourth voltage signal terminal VGL1.

[0177] When the voltage of the global reset signal is at a high level, the fifteenth transistor M15 and the sixteenth transistor M16 can be turned on at the same time under the action of the global reset signal, and the sixteenth transistor M16 can transmit the fourth voltage signal transmitted by the fourth voltage signal terminal VGL1 to the anti-leakage node OFF. <n>, the fifteenth transistor M15 can turn off the leakage protection node <n>The fourth voltage signal is transmitted to the pull-up node Q <n>, pull up node Q <n>Perform a reset.

[0178] Here, at the pull-up node Q <n>When the potential of the node Q is high and the third reset circuit 4107 is not in operation, the third transistor M3 can pull up the node Q <n>The second voltage signal is transmitted to the anti-leakage node OFF. <n>, making the leakage protection node OFF <n>The voltage of the node Q is increased, thereby making the voltage difference between the control electrode and the second electrode of the fifteenth transistor M15 less than zero, ensuring that the fifteenth transistor M15 is completely or relatively completely turned off. <n>Leakage occurs through the third reset circuit 4107, causing the node Q to be pulled up. <n>Able to maintain a higher and more stable voltage.

[0179] For example, Figure 5 As shown, the fourth reset circuit 4108 and the pull-down node QB_A <n>, shift signal terminal CR <n>, the first output signal terminal Oput1 <n>, the fourth voltage signal terminal VGL1 and the fifth voltage signal terminal VGL2 are electrically connected. The fourth reset circuit 4108 is configured to pull down the node QB_A <n>Under the control of the voltage, the shift signal terminal CR <n>and the first output signal terminal Oput1 <n>Reset. The fifth voltage signal terminal VGL2 is configured to transmit a DC low-level signal (for example, lower than or equal to the low-level portion of the clock signal). The fifth voltage signal terminal VGL2 can be grounded, for example. The low-level signals transmitted by the fourth voltage signal terminal VGL1 and the fifth voltage signal terminal VGL2 can be equal or unequal.

[0180] For example, in the drop-down node QB_A <n>When the voltage of QB_A is high, the fourth reset circuit 4108 can pull down the node QB_A <n>The fourth voltage signal transmitted by the fourth voltage signal terminal VGL1 is transmitted to the shift signal terminal CR <n>, for the shift signal terminal CR <n>Pull-down reset is performed, and the fifth voltage signal transmitted by the fifth voltage signal terminal VGL2 is transmitted to the first output signal terminal Oput1 <n>, for the first output signal terminal Oput1 <n>Pull-down reset.

[0181] Optional, such as Figure 5 As shown, the fourth reset circuit 4108 may include: a seventeenth transistor M17 and an eighteenth transistor M18.

[0182] For example, Figure 5 As shown, the control electrode of the seventeenth transistor M17 is connected to the pull-down node QB_A. <n>The first electrode of the seventeenth transistor M17 is electrically connected to the shift signal terminal CR <n>The second electrode of the seventeenth transistor M17 is electrically connected to the fourth voltage signal terminal VGL1.

[0183] In the drop-down node QB_A <n>When the voltage of is high, the seventeenth transistor M17 can pull down the node QB_A <n>The fourth voltage signal transmitted by the fourth voltage signal terminal VGL1 is transmitted to the shift signal terminal CR <n>, for the shift signal terminal CR <n>Pull-down reset.

[0184] For example, Figure 5 As shown, the control electrode of the eighteenth transistor M18 is connected to the pull-down node QB_A. <n>The first electrode of the eighteenth transistor M18 is electrically connected to the first output signal terminal Oput1 <n>The second electrode of the eighteenth transistor M18 is electrically connected to the fifth voltage signal terminal VGL2.

[0185] In the drop-down node QB_A <n>When the voltage of QB_A is high, the eighteenth transistor M18 can pull down the node QB_A <n>The fifth voltage signal transmitted by the fifth voltage signal terminal VGL2 is transmitted to the first output signal terminal Oput1 <n>, for the first output signal terminal Oput1 <n>Pull-down reset.

[0186] For example, Figure 5 As shown, the fifth reset circuit 4109 is connected to the input signal terminal Iput and the pull-down node QB_A <n>The fifth reset circuit 4109 is configured to, under the control of the input signal transmitted by the input signal terminal Iput, pull down the node QB_A. <n>Perform a reset.

[0187] For example, when the level of the input signal is high, the fifth reset circuit 4109 can be turned on under the action of the input signal to transmit the fourth voltage signal transmitted by the fourth voltage signal terminal VGL1 to the pull-down node QB_A. <n>, for the drop-down node QB_A <n>Pull-down reset.

[0188] Optional, such as Figure 5 As shown, the fifth reset circuit 4109 may include: a twentieth transistor M20.

[0189] For example, Figure 5 As shown, the control electrode of the twentieth transistor M20 is electrically connected to the input signal terminal Iput, and the first electrode of the twentieth transistor M20 is electrically connected to the pull-down node QB_A. <n>The second electrode of the twentieth transistor M20 is electrically connected to the fourth voltage signal terminal VGL1.

[0190] When the level of the input signal is high, the twentieth transistor M20 can be turned on under the action of the input signal to transmit the fourth voltage signal transmitted by the fourth voltage signal terminal VGL1 to the pull-down node QB_A. <n>, for the drop-down node QB_A <n>Pull-down reset.

[0191] It should be noted that the blanking input circuit 32 is configured to control the corresponding shift register 31 to input a blanking control signal (ie, a second scanning signal) to the pixel driving circuit 21 of the corresponding row during the blanking period of a frame display stage, so that the pixel driving circuit 21 obtains a sensing signal.

[0192] The structure of the blanking circuit 4110 can be selected and set according to actual needs. For example, Figure 5 As shown, the blanking circuit 4110 may include: a selection control circuit 41101 , a second input circuit 41102 and a transmission circuit 41103 .

[0193] For example, Figure 5 As shown, the selection control circuit 41101 is connected to the selection control signal terminal OE and the shift signal terminal CR <n>, the second voltage signal terminal VDD and the first blanking node H are electrically connected. The selection control circuit 41101 is configured to, under the control of the selection control signal transmitted by the selection control signal terminal OE, shift the signal terminal CR to the shift signal terminal CR. <n>The shift signal received at is transmitted to the first blanking node H.

[0194] For example, when the level of the selection control signal is high, the selection control circuit 41101 can be turned on under the control of the selection control signal, and transmit the received shift signal to the first blanking node H, charge the first blanking node H, so that the voltage of the first blanking node H increases.

[0195] During the blanking period of a frame display stage, when it is necessary to obtain a sensing signal, the waveform timing of the selection control signal can be made the same as the waveform timing of the input signal, thereby turning on the selection control circuit 41101.

[0196] Optional, such as Figure 5 As shown, the selection control circuit 41101 may include: a twenty-first transistor M21, a twenty-second transistor M22 and a third capacitor C3.

[0197] For example, Figure 5 As shown, the control electrode of the twenty-first transistor M21 is electrically connected to the selection control signal terminal OE, and the first electrode of the twenty-first transistor M21 is electrically connected to the shift signal terminal CR <n>The second electrode of the 21st transistor M21 is electrically connected to the first electrode of the 22nd transistor M22. The control electrode of the 22nd transistor M22 is electrically connected to the selection control signal terminal OE, and the second electrode of the 22nd transistor M22 is electrically connected to the first blanking node H.

[0198] When the level of the selection control signal transmitted by the selection control signal terminal OE is high, the twenty-first transistor M21 and the twenty-second transistor M22 can be turned on at the same time under the action of the selection control signal, and the twenty-first transistor M21 can shift the shift signal terminal CR <n>The transmitted shift signal is transmitted to the first electrode of the twenty-second transistor M22 . The twenty-second transistor M22 can receive and transmit the shift signal to the first blanking node H to charge the first blanking node H.

[0199] For example, Figure 5 As shown, a first end of the third capacitor C3 is electrically connected to the first blanking node H, and a second end of the third capacitor C3 is electrically connected to the second voltage signal terminal VDD.

[0200] The third capacitor C3 is also charged when the selection control circuit 41101 charges the first blanking node H. In this way, when the selection control circuit 41101 is turned off, the third capacitor C3 is used to discharge, so that the first blanking node H maintains a high level.

[0201] In addition, if Figure 5 As shown, the selection control circuit 41101 may further include, for example: a twenty-third transistor M23. The control electrode of the twenty-third transistor M23 is electrically connected to the first blanking node H, the first electrode of the twenty-third transistor M23 is electrically connected to the second voltage signal terminal VDD, and the second electrode of the twenty-third transistor M23 is electrically connected to the first electrode of the twenty-second transistor M22.

[0202] When the voltage of the first blanking node H is at a high level and the 21st transistor M21 and the 22nd transistor M22 are not working, the 23rd transistor M23 can be turned on under the control of the voltage of the first blanking node H, and the second voltage signal transmitted by the second voltage signal terminal VDD is transmitted to the first electrode of the 22nd transistor M22, so that the voltage of the first electrode of the 22nd transistor M22 is increased, and then the voltage difference between the control electrode and the first electrode of the 22nd transistor M22 is less than zero, ensuring that the 22nd transistor M22 is completely or relatively completely turned off. In this way, the first blanking node H can be prevented from leaking through the 22nd transistor M22, so that the first blanking node H can maintain a higher and more stable voltage.

[0203] For example, Figure 5 As shown, the second input circuit 41102 is electrically connected to the first blanking node H, the second blanking node N and the second voltage signal terminal VDD. The second input circuit 41102 is configured to transmit the second voltage signal received at the second voltage signal terminal VDD to the second blanking node N under the control of the voltage of the first blanking node H.

[0204] For example, when the selection control circuit 41101 is turned on and the voltage of the first blanking node H increases, the second input circuit 41102 can be turned on under the control of the voltage of the first blanking node H, receive the second voltage signal transmitted by the second voltage signal terminal VDD, and transmit the second voltage signal to the second blanking node N.

[0205] Optional, such as Figure 5 As shown, the second input circuit 41102 may include: a twenty-fourth transistor M24.

[0206] For example, Figure 5 As shown, the control electrode of the twenty-fourth transistor M24 is electrically connected to the first blanking node H, the first electrode of the twenty-fourth transistor M24 is electrically connected to the second voltage signal terminal VDD, and the second electrode of the twenty-fourth transistor M24 is electrically connected to the second blanking node N.

[0207] When the voltage of the first blanking node H is at a high level, the twenty-fourth transistor M24 may be turned on under the control of the voltage of the first blanking node H, and transmit the second voltage signal received at the second voltage signal terminal VDD to the second blanking node N.

[0208] For example, Figure 5 As shown, the transmission circuit 41103 is connected to the second blanking node N, the third clock signal terminal CLKA and the pull-up node Q <n>The transmission circuit 41102 is configured to transmit the second voltage signal received at the second blanking node N to the pull-up node Q under the control of the third clock signal transmitted by the third clock signal terminal CLKA. <n>.

[0209] For example, when the level of the third clock signal transmitted by the third clock signal terminal CLKA is high, the transmission circuit 41102 can be turned on under the control of the third clock signal, and receive the second voltage signal from the second blanking node N, and transmit the received second voltage signal to the pull-up node Q <n>, so that the pull-up node Q <n>The voltage of the output circuit 4103 is increased, so that the output circuit 4103 is turned on, so that the first output signal terminal Oput1 of the output circuit 4103 <n>A second output signal is output.

[0210] Optional, such as Figure 5 As shown, the transmission circuit 41103 may include: a twenty-fifth transistor M25.

[0211] For example, Figure 5 As shown, the control electrode of the twenty-fifth transistor M25 is electrically connected to the third clock signal terminal CLKA, the first electrode of the twenty-fifth transistor M25 is electrically connected to the second blanking node N, and the second electrode of the twenty-fifth transistor M25 is electrically connected to the pull-up node Q <n>Electrical connection.

[0212] When the level of the third clock signal transmitted by the third clock signal terminal CLKA is high, the twenty-fifth transistor M25 can be turned on under the action of the third clock signal, and the twenty-fifth transistor M25 can transmit the second voltage signal from the second blanking node N to the pull-up node Q <n>, pull up node Q <n>The fifth transistor M5 in the output circuit 4103 can pull up the node Q <n>The second clock signal is turned on under the control of the voltage of the first output signal terminal Oput1, and the second clock signal is used as the first output signal. <n>Output.

[0213] In addition, if Figure 5 As shown, the transmission circuit 41103 may further include: a twenty-sixth transistor M26.

[0214] For example, Figure 5 As shown, the control electrode of the twenty-sixth transistor M26 is electrically connected to the third clock signal terminal CLKA, the first electrode of the twenty-sixth transistor M26 is electrically connected to the second electrode of the twenty-fifth transistor M25, and the second electrode of the twenty-sixth transistor M26 is electrically connected to the pull-up node Q <n>That is, the twenty-fifth transistor M25 is electrically connected to the pull-up node Q through the twenty-sixth transistor M26. <n>Electrical connection.

[0215] When the level of the third clock signal transmitted by the third clock signal terminal CLKA is high, the twenty-fifth transistor M25 and the second sixteenth transistor M26 can be turned on at the same time under the action of the third clock signal, and the twenty-fifth transistor M25 can transmit the second voltage signal from the second blanking node N to the first electrode of the twenty-sixth transistor M26, and the twenty-sixth transistor M26 can receive and transmit the second voltage signal to the pull-up node Q <n>, pull up node Q <n>to charge.

[0216] The transmission circuit 41103 also has an anti-leakage node OFF <n>In case of electrical connection, Figure 5 As shown, the first electrode of the twenty-sixth transistor M26 can be connected to the anti-leakage node OFF <n>Electrical connection.

[0217] Here, at the pull-up node Q <n>When the potential of the node Q is high and the transmission circuit 41103 is not in operation, the third transistor M3 can pull up the node Q <n>The second voltage signal is transmitted to the anti-leakage node OFF. <n>, making the leakage protection node OFF <n>The voltage of the 26th transistor M26 is increased, so that the voltage difference between the control electrode and the first electrode of the 26th transistor M26 is less than zero, ensuring that the 26th transistor M26 is completely or relatively completely turned off. <n>Leakage occurs through the transmission circuit 41103, causing the pull-up node Q <n>Able to maintain a higher and more stable voltage.

[0218] For example, Figure 5 As shown, the sixth reset circuit 4111 is connected to the third clock signal terminal CLKA, the first blanking node H, and the pull-down node QB_A <n>The sixth reset circuit 4111 is configured to, during a blanking period of a display frame, under the common control of the third clock signal transmitted by the third clock signal terminal CLKA and the voltage of the first blanking node H, pull down the node QB_A. <n>Perform a reset.

[0219] For example, in the blanking period of a frame display stage, when the level of the third clock signal is high and the voltage of the first blanking node H is high, the sixth reset circuit 4111 can be turned on under the common control of the third clock signal and the voltage of the first blanking node H, and the fourth voltage signal transmitted by the fourth voltage signal terminal VGL1 is transmitted to the pull-down node QB_A. <n>, for the drop-down node QB_A <n>Pull-down reset.

[0220] Optional, such as Figure 5 As shown, the sixth reset circuit 4111 may include: a twenty-seventh transistor M27 and a twenty-eighth transistor M28.

[0221] For example, Figure 5 As shown, the control electrode of the twenty-seventh transistor M27 is electrically connected to the first blanking node H, and the first electrode of the twenty-seventh transistor M27 is electrically connected to the pull-down node QB_A. <n>The second electrode of the twenty-seventh transistor M27 is electrically connected to the first electrode of the twenty-eighth transistor M28. The control electrode of the twenty-eighth transistor M28 is electrically connected to the third clock signal terminal CLKA, and the second electrode of the twenty-eighth transistor M28 is electrically connected to the fourth voltage signal terminal VGL1.

[0222] When the level of the third clock signal is high and the voltage of the first blanking node H is high, the twenty-eighth transistor M28 can be turned on under the control of the third clock signal, and the fourth voltage signal is transmitted to the first electrode of the twenty-eighth transistor M28. The twenty-seventh transistor M27 can be turned on under the control of the voltage of the first blanking node H, and the fourth voltage signal is transmitted from the first electrode of the twenty-eighth transistor M28 to the pull-down node QB_A. <n>, for the drop-down node QB_A <n>Pull-down reset.

[0223] In other examples, such as Figure 6 As shown, at least two stages of shift registers 41 can share the same blanking circuit 4110. At this time, at least two stages of shift registers 41 sharing the same blanking circuit 4110 can be collectively referred to as a shift register 41, and the circuit part other than the blanking circuit 4110 is referred to as a scanning unit.

[0224] like Figure 6 As shown, it is taken that two adjacent shift registers 41 share a blanking circuit 4110 to form a shift register 41 as an example. The shift register 41 may include a first scanning unit 41a and a second scanning unit 41b. The first scanning unit 41a may be electrically connected to a plurality of pixel driving circuits 21 in a row of sub-pixels 2, for example, and the second scanning unit 41b may be electrically connected to a plurality of pixel driving circuits 21 in another row of sub-pixels 2, for example.

[0225] For example, Figure 6 As shown, the first scanning unit 41a and the second scanning unit 41b may include: a first input circuit 4101, an anti-leakage circuit 4102, an output circuit 4103, a control circuit 4104, a first reset circuit 4105, a second reset circuit 4106, a third reset circuit 4107, a fourth reset circuit 4108, a fifth reset circuit 4109 and a sixth reset circuit 4111.

[0226] Among them, the first input circuit 4101 in the first scanning unit 41a and the second scanning unit 41b can have the same structure and function as the first input circuit 4101 in some of the above examples, the anti-leakage circuit 4102 in the first scanning unit 41a and the second scanning unit 41b can have the same structure and function as the anti-leakage circuit 4102 in some of the above examples, the output circuit 4103 in the first scanning unit 41a can have the same structure and function as the output circuit 4103 in some of the above examples, the control circuit 4104 in the first scanning unit 41a can have the same structure and function as the control circuit 4104 in some of the above examples, the first reset circuit 4105 in the first scanning unit 41a and the second scanning unit 41b can have the same structure and function as the first reset circuit 4105 in some of the above examples, and the first scanning unit 41 The second reset circuit 4106 in the first scanning unit 41a and the second scanning unit 41b may have the same structure and function as the second reset circuit 4106 in some of the above examples, the third reset circuit 4107 in the first scanning unit 41a and the second scanning unit 41b may have the same structure and function as the third reset circuit 4107 in some of the above examples, the fourth reset circuit 4108 in the first scanning unit 41a may have the same structure and function as the fourth reset circuit 4108 in some of the above examples, the fifth reset circuit 4109 in the first scanning unit 41a and the second scanning unit 41b may have the same structure and function as the fifth reset circuit 4109 in some of the above examples, and the sixth reset circuit 4111 in the first scanning unit 41a and the second scanning unit 41b may have the same structure and function as the sixth reset circuit 4111 in some of the above examples. The structures and functions of the same circuits will not be described in detail here.

[0227] For example, Figure 6 As shown, compared with the output circuit 4103 in the first scanning unit 41a, the output circuit 4103 in the second scanning unit 41b may not be provided with the fourth transistor M4 and is not connected to the shift signal terminal CR <n>Electrically connected to the first clock signal terminal CLKD_1.

[0228] For example, Figure 6 As shown, the control circuit 4104 in the second scanning unit 41b can be electrically connected to the sixth voltage signal terminal VDD_B, and the sixth voltage signal terminal VDD_B is used to replace the third voltage signal terminal VDD_A. In the display stage of one frame, the third voltage signal transmitted by the third voltage signal terminal VDD_A and the sixth voltage signal transmitted by the sixth voltage signal terminal VDD_B are mutually inverted signals.

[0229] For example, Figure 6 As shown, the fourth reset circuit 4108 in the second scanning unit 41b may not be provided with the seventeenth transistor M17 compared with the fourth reset circuit 4108 in the first scanning unit 41a.

[0230] Based on this, in order to more clearly describe the structure of the shift register 41, the pull-up node Q in the first scanning unit 41a can be <n>It is called the first pull-up node Q <n>, pull up the node Q in the second scanning unit 41b <n>The second pull-up node Q<N+1> ; The pull-down node QB_A in the first scanning unit 41a can be <n>It is called the first pull-down node QB_A <n>, pull down node QB_A in the second scanning unit 41b <n>It is called the second pull-down node QB_B <n>; The leakage prevention node in the first scanning unit 41a can be OFF <n>It is called the first leakage protection node OFF <n>, turn off the leakage protection node in the second scanning unit 41b <n>It is called the second leakage protection node OFF<N+1> The second clock signal CLKE_1 in the second scanning unit 41b can be called the fourth clock signal CLKE_2; the first output signal terminal Oput1 in the first scanning unit 41a can be called <n>It is called the first sub-output signal terminal Oput1 <n>, the first output signal terminal Oput1 in the second scanning unit 41b <n>It is called the second sub-output signal terminal Oput1<N+1> .

[0231] For example, Figure 6 As shown, the first pull-down node QB_A in the first scanning unit 41a <n>It can be electrically connected to the second scanning unit 41b, and the second pull-down node QB_B of the second scanning unit 41b <n>Can be electrically connected to the first scanning unit 41a.

[0232] Based on this, for example, Figure 6 As shown, the first reset circuit 4105 in the first scanning unit 41a can also be connected to the second pull-down node QB_B <n>The first reset circuit 4105 is further configured to, at the second pull-down node QB_B <n>Under the control of the voltage of the first pull-up node Q <n>Perform a reset.

[0233] For example, at the second pull-down node QB_B <n>When the voltage of QB_B is high, the first reset circuit 4105 can reset the second pull-down node QB_B <n>The fourth voltage signal transmitted by the fourth voltage signal terminal VGL1 is transmitted to the first pull-up node Q <n>, for the first pull-up node Q <n>Pull-down reset.

[0234] Optional, such as Figure 6 As shown, the first reset circuit 4105 in the first scanning unit 41a may further include: a twenty-ninth transistor M29 and a thirtieth transistor M30.

[0235] For example, Figure 6 As shown, in the first scanning unit 41a, the control electrode of the twenty-ninth transistor M29 is connected to the second pull-down node QB_B <n>The first electrode of the twenty-ninth transistor M29 is electrically connected to the first pull-up node Q <n>The second electrode of the 29th transistor M29 is electrically connected to the first electrode of the 30th transistor M30 and the first leakage prevention node OFF. <n>The control electrode of the 30th transistor M30 is electrically connected to the second pull-down node QB_B <n>The second electrode of the thirtieth transistor M30 is electrically connected to the fourth voltage signal terminal VGL1.

[0236] At the second pull-down node QB_B <n>When the voltage of QB_B is at a high level, the 29th transistor M29 and the 30th transistor M30 can be pulled down at the second pull-down node QB_B <n>The thirtieth transistor M30 can transmit the fourth voltage signal transmitted by the fourth voltage signal terminal VGL1 to the first anti-leakage node OFF. <n>The twenty-ninth transistor M29 can turn off the first leakage protection node <n>The fourth voltage signal is transmitted to the first pull-up node Q <n>, for the first pull-up node Q <n>Perform a reset.

[0237] For example, Figure 6 As shown, the first reset circuit 4105 in the second scanning unit 41b can also be connected to the first pull-down node QB_A <n>The first reset circuit 4105 is further configured to, at the first pull-down node QB_A <n>Under the control of the voltage of the second pull-up node Q<N+1> Perform a reset.

[0238] For example, at the first drop-down node QB_A <n>When the voltage of QB_A is high, the first reset circuit 4105 can reset the first pull-down node QB_A <n>The fourth voltage signal transmitted by the fourth voltage signal terminal VGL1 is transmitted to the second pull-up node Q<N+1> , for the second pull-up node Q<N+1> Pull-down reset.

[0239] Optional, such as Figure 6 As shown, the first reset circuit 4105 in the second scanning unit 41b may further include: a twenty-ninth transistor M29 and a thirtieth transistor M30.

[0240] For example, Figure 6 As shown, in the second scanning unit 41b, the control electrode of the twenty-ninth transistor M29 is connected to the first pull-down node QB_A <n>The first electrode of the twenty-ninth transistor M29 is electrically connected to the second pull-up node Q<N+1> The second electrode of the 29th transistor M29 is electrically connected to the first electrode of the 30th transistor M30 and the second anti-leakage node OFF.<N+1> The control electrode of the 30th transistor M30 is electrically connected to the first pull-down node QB_A <n>The second electrode of the thirtieth transistor M30 is electrically connected to the fourth voltage signal terminal VGL1.

[0241] At the first drop-down node QB_A <n>When the voltage of QB_A is high, the 29th transistor M29 and the 30th transistor M30 can be pulled down at the first pull-down node QB_A <n>The thirtieth transistor M30 can transmit the fourth voltage signal transmitted by the fourth voltage signal terminal VGL1 to the second anti-leakage node OFF.<N+1> The twenty-ninth transistor M29 can turn off the power from the second leakage prevention node<N+1> The fourth voltage signal is transmitted to the second pull-up node Q<N+1> , for the second pull-up node Q<N+1> Perform a reset.

[0242] For example, Figure 6 As shown, the fourth reset circuit 4108 in the first scanning unit 41a can also be connected to the second pull-down node QB_B <n>The fourth reset circuit 4108 is further configured to, at the second pull-down node QB_B <n>Under the control of the voltage, the shift signal terminal CR <n>and the first sub-output signal terminal Oput1 <n>Perform a reset.

[0243] For example, at the second pull-down node QB_B <n>When the voltage of the second pull-down node QB_B is at a high level, the fourth reset circuit 4108 can <n>The fourth voltage signal transmitted by the fourth voltage signal terminal VGL1 is transmitted to the shift signal terminal CR <n>, for the shift signal terminal CR <n>Pull-down reset is performed, and the fifth voltage signal transmitted by the fifth voltage signal terminal VGL2 is transmitted to the first sub-output signal terminal Oput1 <n>, for the first sub-output signal terminal Oput1 <n>Pull-down reset.

[0244] Optional, such as Figure 6 As shown, the fourth reset circuit 4108 in the first scanning unit 41a may further include: a thirty-first transistor M31 and a thirty-second transistor M32.

[0245] For example, Figure 6 As shown, the control electrode of the thirty-first transistor M31 is connected to the second pull-down node QB_B <n>The first electrode of the thirty-first transistor M31 is electrically connected to the shift signal terminal CR <n>The second electrode of the thirty-first transistor M31 is electrically connected to the fourth voltage signal terminal VGL1.

[0246] At the second pull-down node QB_B <n>When the voltage of QB_B is at a high level, the thirty-first transistor M31 can <n>The fourth voltage signal transmitted by the fourth voltage signal terminal VGL1 is transmitted to the shift signal terminal CR <n>, for the shift signal terminal CR <n>Pull-down reset.

[0247] For example, Figure 6 As shown, the control electrode of the thirty-second transistor M32 is connected to the second pull-down node QB_B <n>The first electrode of the thirty-second transistor M32 is electrically connected to the first sub-output signal terminal Oput1 <n>The second electrode of the thirty-second transistor M32 is electrically connected to the fifth voltage signal terminal VGL2.

[0248] At the second pull-down node QB_B <n>When the voltage of QB_B is at a high level, the thirty-second transistor M32 can be <n>The fifth voltage signal transmitted by the fifth voltage signal terminal VGL2 is transmitted to the first sub-output signal terminal Oput1 <n>, for the first sub-output signal terminal Oput1 <n>Pull-down reset.

[0249] For example, Figure 6 As shown, the fourth reset circuit 4108 in the second scanning unit 41b can also be connected to the first pull-down node QB_A <n>The fourth reset circuit 4108 is further configured to, at the first pull-down node QB_A <n>Under the control of the voltage, the second sub-output signal terminal Oput1<N+1> Perform a reset.

[0250] For example, at the first drop-down node QB_A <n>When the voltage of QB_A is high, the fourth reset circuit 4108 can reset the first pull-down node QB_A <n>The fifth voltage signal transmitted by the fifth voltage signal terminal VGL2 is transmitted to the second sub-output signal terminal Oput1<N+1> , for the second sub-output signal terminal Oput1<N+1> Pull-down reset.

[0251] Optional, such as Figure 6 As shown, the fourth reset circuit 4108 in the second scanning unit 41b may further include: a thirty-second transistor M32.

[0252] For example, Figure 6 As shown, the control electrode of the thirty-second transistor M32 is connected to the first pull-down node QB_A. <n>The first electrode of the thirty-second transistor M32 is electrically connected to the second sub-output signal terminal Oput1<N+1> The second electrode of the thirty-second transistor M32 is electrically connected to the fifth voltage signal terminal VGL2.

[0253] At the first drop-down node QB_A <n>When the voltage of QB_A is high, the thirty-second transistor M32 can be connected to the first pull-down node QB_A <n>The fifth voltage signal transmitted by the fifth voltage signal terminal VGL2 is transmitted to the second sub-output signal terminal Oput1<N+1> , for the second sub-output signal terminal Oput1<N+1> Pull-down reset.

[0254] In this example, the shift signal terminal CR in the Nth stage shift register 41 is <n>For example, it can be electrically connected to the input signal terminal Iput of the first scanning unit 41a and the second scanning unit 41b in the N+1th stage shift register 41, thereby connecting the shift signal terminal CR <n>The output shift signal is used as an input signal of the first scanning unit 41a and the second scanning unit 41b in the N+1 stage shift register 41. The display reset signal terminal STD of the first scanning unit 41a and the second scanning unit 41b in the N stage shift register 41 can be connected to the shift signal terminal CR of the N+1 stage shift register 41.<N+1> The shift signal terminal CR of the N+1th stage shift register 41 is electrically connected to<N+1> The output shift signal is used as a display reset signal of the first scanning unit 41a and the second scanning unit 41b in the N-th stage shift register 41. Of course, the cascade relationship of the multiple stages of shift registers 41 is not limited to this.

[0255] For example, the shift signal terminal CR in the first stage shift register 41 <1> The shift signal terminal CR in the fifth stage shift register 41 can be electrically connected to the input signal terminal Iput in the third stage and the fourth stage shift register 41. <5> It can be electrically connected to the display reset signal terminal STD in the first stage and the second stage shift register 41.

[0256] This helps to simplify the structure of the scan driving circuit 4 and reduce the space occupied by the scan driving circuit 4 in the display panel 100 .

[0257] In some other examples, the first-stage shift register 41 may be electrically connected to a plurality of pixel driving circuits 21 in a row of sub-pixels 2 .

[0258] like Figure 7 As shown, the shift register 41 may include, for example: a first input circuit 4101, an anti-leakage circuit 4102, an output circuit 4103, a control circuit 4104, a first reset circuit 4105, a second reset circuit 4106, a third reset circuit 4107, a fourth reset circuit 4108, a fifth reset circuit 4109, a blanking circuit 4110, and a sixth reset circuit 4111. Of course, the shift register 41 may include only some of the multiple circuits, as long as the sub-pixel 2 can realize the above working process.

[0259] Exemplarily, the structure and function of the first input circuit 4101 in this example can be the same as the first input circuit 4101 in the first example, the structure and function of the anti-leakage circuit 4102 in this example can be the same as the anti-leakage circuit 4102 in the first example, the structure and function of the control circuit 4104 in this example can be the same as the control circuit 4104 in the first example, the structure and function of the first reset circuit 4105 in this example can be the same as the first reset circuit 4105 in the first example, and the second reset circuit 4106 in this example can be the same as the first example. The structure and function of the second reset circuit 4106 in the example may be the same, the structure and function of the third reset circuit 4107 in this example may be the same as the structure and function of the third reset circuit 4107 in the first example, the structure and function of the fifth reset circuit 4109 in this example may be the same as the structure and function of the fifth reset circuit 4109 in the first example, the structure and function of the blanking circuit 4110 in this example may be the same as the structure and function of the blanking circuit 4110 in the first example, and the structure and function of the sixth reset circuit 4111 in this example may be the same as the structure and function of the sixth reset circuit 4111 in the first example. The structures and functions of the same circuits will not be described in detail here.

[0260] For example, Figure 7 As shown, the output circuit 4103 and the pull-up node Q <n>, the first clock signal terminal CLKD_1, the shift signal terminal CR <n>, the second clock signal terminal CLKE_1, the first output signal terminal Oput1 <n>, a fifth clock signal terminal CLKF_1 and a second output signal terminal Output2 <n>(The attached figure and the following text are abbreviated as Oput2 <n>) is electrically connected. The output circuit 4103 is configured to pull up the node Q during the display period of a frame display stage. <n>Under the control of the voltage of <n>, the second clock signal received at the second clock signal terminal CLKE_1 is transmitted to the first output signal terminal Oput1 <n>And, during the blanking period in a frame display phase, the pull-up node Q <n>Under the control of the voltage of , the fifth clock signal received at the fifth clock signal terminal CLKF_1 is transmitted to the second output signal terminal Oput2 <n>.

[0261] For example, during the display period of a frame display stage, at the pull-up node Q <n>When the voltage of the output circuit 4103 increases, the output circuit 4103 can pull up the node Q <n>The first clock signal received at the first clock signal terminal CLKD_1 is turned on under the control of the voltage of the first clock signal terminal CLKD_1, and the first clock signal received at the first clock signal terminal CLKD_1 is used as the shift signal, and the first clock signal received at the first clock signal terminal CLKD_1 is turned on under the control of the voltage of the first clock signal terminal CLKD_1, and the first clock signal received at the first clock signal terminal CLKD_1 is used as the shift <n>Output; the second clock signal received at the second clock signal terminal CLKE_1 is used as the first output signal (ie, the first scanning signal received by the pixel driving circuit 21), from the first output signal terminal Oput1 <n>Output. During the blanking period in a frame display phase, the pull-up node Q <n>When the voltage of the output circuit 4103 increases, the output circuit 4103 can pull up the node Q <n>The fifth clock signal received at the fifth clock signal terminal CLKF_1 is turned on under the control of the voltage of the pixel driving circuit 21, and the fifth clock signal received at the fifth clock signal terminal CLKF_1 is used as the second output signal (that is, the second scanning signal received by the pixel driving circuit 21), and the pixel driving circuit 21 outputs the fifth clock signal from the second output signal terminal Oput2 <n>Output.

[0262] In this example, the first output signal terminal Oput1 <n>Can be electrically connected to the first gate line, the first output signal terminal Oput1 <n>The first output signal can be used as a first scanning signal and is sequentially transmitted to the corresponding pixel driving circuit 21 via the first gate line and the first scanning signal terminal G1. <n>Can be electrically connected to the second gate line, the second output signal terminal Oput2 <n>The output second output signal can be used as a second scanning signal and transmitted to the corresponding pixel driving circuit 21 via the second gate line and the second scanning signal terminal G2 in sequence.

[0263] Optional, such as Figure 7 As shown, the output circuit 4103 may include: a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a first capacitor C1 and a second capacitor C2.

[0264] For example, Figure 7 As shown, the control electrode of the fourth transistor M4 is connected to the pull-up node Q <n>The first electrode of the fourth transistor M4 is electrically connected to the first clock signal terminal CLKD_1, and the second electrode of the fourth transistor M4 is electrically connected to the shift signal terminal CR <n>Electrical connection.

[0265] During the display period of a frame display stage, the first input circuit 4101 is turned on, so that the pull-up node Q <n>When the voltage of the node Q increases, the fourth transistor M4 can pull up the node Q <n>The first clock signal is received and transmitted to the shift signal terminal CR under the control of the high voltage of <n>and uses the first clock signal as a shift signal from the shift signal terminal CR <n>Output.

[0266] For example, Figure 7 As shown, the control electrode of the fifth transistor M5 is connected to the pull-up node Q <n>The first electrode of the fifth transistor M5 is electrically connected to the second clock signal terminal CLKE_1, and the second electrode of the fifth transistor M5 is electrically connected to the first output signal terminal Oput1 <n>The first end of the first capacitor C1 is electrically connected to the pull-up node Q <n>The second end of the first capacitor C1 is electrically connected to the first output signal end Oput1 <n>Electrical connection.

[0267] During the display period of a frame display stage, when the first input circuit 4101 is turned on, the pull-up node Q <n>When the voltage of the first input circuit 4101 is turned off, the first capacitor C1 can be discharged, so that the pull-up node Q <n>Maintaining a high level, the fifth transistor M5 can remain in a conducting state, receiving and transmitting the second clock signal to the first output signal terminal Oput1 <n>and uses the second clock signal as the first output signal (that is, the first scanning signal received by the pixel driving circuit 21) from the first output signal terminal Oput1 <n>Output.

[0268] For example, Figure 7 As shown, the control electrode of the sixth transistor M6 is connected to the pull-up node Q <n>The first electrode of the sixth transistor M6 is electrically connected to the fifth clock signal terminal CLKF_1, and the second electrode of the sixth transistor M6 is electrically connected to the second output signal terminal Oput2 <n>The first end of the second capacitor C2 is electrically connected to the pull-up node Q <n>The second end of the second capacitor C2 is electrically connected to the second output signal end Oput2 <n>Electrical connection.

[0269] During the blanking period of a frame display stage, the pull-up node Q <n>When the voltage of the pull-up node Q increases, the second capacitor C2 will be charged. In the corresponding stage, the second capacitor C2 can be discharged, so that the pull-up node Q <n>The sixth transistor M6 is kept at a high level, thereby maintaining a conductive state, and transmitting the fifth clock signal to the second output signal terminal Oput2. <n>and outputs the fifth clock signal as the second output signal from the second output signal terminal Oput2 <n>Output.

[0270] For example, Figure 7 As shown, the fourth reset circuit 4108 and the pull-down node QB_A <n>, shift signal terminal CR <n>, the first output signal terminal Oput1 <n>, the second output signal terminal Oput2 <n>, the fourth voltage signal terminal VGL1 and the fifth voltage signal terminal VGL2 are electrically connected. The fourth reset circuit 4108 is configured to pull down the node QB_A <n>Under the control of the voltage, the shift signal terminal CR <n>, the first output signal terminal Oput1 <n>Reset and second output signal terminal Oput2 <n>.

[0271] For example, in the drop-down node QB_A <n>When the voltage of QB_A is high, the fourth reset circuit 4108 can pull down the node QB_A <n>The fourth voltage signal transmitted by the fourth voltage signal terminal VGL1 is transmitted to the shift signal terminal CR <n>, for the shift signal terminal CR <n>Pull-down reset is performed to transmit the fifth voltage signal transmitted by the fifth voltage signal terminal VGL2 to the first output signal terminal Oput1 <n>, for the first output signal terminal Oput1 <n>Pull-down reset is performed, and the fifth voltage signal transmitted by the fifth voltage signal terminal VGL2 is transmitted to the second output signal terminal Oput2 <n>, for the second output signal terminal Oput2 <n>Pull-down reset.

[0272] Optional, such as Figure 7 As shown, the fourth reset circuit 4108 may include: a seventeenth transistor M17, an eighteenth transistor M18 and a nineteenth transistor M19.

[0273] For example, Figure 7 As shown, the control electrode of the seventeenth transistor M17 is connected to the pull-down node QB_A. <n>The first electrode of the seventeenth transistor M17 is electrically connected to the shift signal terminal CR <n>The second electrode of the seventeenth transistor M17 is electrically connected to the fourth voltage signal terminal VGL1.

[0274] In the drop-down node QB_A <n>When the voltage of is high, the seventeenth transistor M17 can pull down the node QB_A <n>The fourth voltage signal transmitted by the fourth voltage signal terminal VGL1 is transmitted to the shift signal terminal CR <n>, for the shift signal terminal CR <n>Pull-down reset.

[0275] For example, Figure 7 As shown, the control electrode of the eighteenth transistor M18 is connected to the pull-down node QB_A. <n>The first electrode of the eighteenth transistor M18 is electrically connected to the first output signal terminal Oput1 <n>The second electrode of the eighteenth transistor M18 is electrically connected to the fifth voltage signal terminal VGL2.

[0276] In the drop-down node QB_A <n>When the voltage of QB_A is high, the eighteenth transistor M18 can pull down the node QB_A <n>The fifth voltage signal transmitted by the fifth voltage signal terminal VGL2 is transmitted to the first output signal terminal Oput1 <n>, for the first output signal terminal Oput1 <n>Pull-down reset.

[0277] For example, Figure 7 As shown, the control electrode of the nineteenth transistor M19 is connected to the pull-down node QB_A. <n>The first electrode of the nineteenth transistor M19 is electrically connected to the second output signal terminal Oput2 <n>The second electrode of the nineteenth transistor M19 is electrically connected to the fifth voltage signal terminal VGL2.

[0278] In the drop-down node QB_A <n>When the voltage of is high, the nineteenth transistor M19 can pull down the node QB_A <n>The fifth voltage signal transmitted by the fifth voltage signal terminal VGL2 is transmitted to the second output signal terminal Oput2 <n>, for the second output signal terminal Oput2 <n>Pull-down reset.

[0279] In some other examples, such as Figure 8 As shown, at least two stages of shift registers 41 in the third example can share the same blanking circuit 4110. At this time, at least two stages of shift registers 41 sharing the same blanking circuit 4110 can be collectively referred to as a shift register 41, and the circuit part other than the blanking circuit 4110 is referred to as a scanning unit.

[0280] like Figure 8 As shown, it is taken that two adjacent shift registers 41 share a blanking circuit 4110 to form a shift register 41 as an example. The shift register 41 may include a first scanning unit 41a and a second scanning unit 41b. The first scanning unit 41a may be electrically connected to a plurality of pixel driving circuits 21 in a row of sub-pixels 2, for example, and the second scanning unit 41b may be electrically connected to a plurality of pixel driving circuits 21 in another row of sub-pixels 2, for example.

[0281] For example, Figure 8 As shown, the first scanning unit 41a and the second scanning unit 41b may include: a first input circuit 4101, an anti-leakage circuit 4102, an output circuit 4103, a control circuit 4104, a first reset circuit 4105, a second reset circuit 4106, a third reset circuit 4107, a fourth reset circuit 4108, a fifth reset circuit 4109 and a sixth reset circuit 4111.

[0282] Among them, the first input circuit 4101 in the first scanning unit 41a and the second scanning unit 41b can have the same structure and function as the first input circuit 4101 in some of the above examples, the anti-leakage circuit 4102 in the first scanning unit 41a and the second scanning unit 41b can have the same structure and function as the anti-leakage circuit 4102 in some of the above examples, the output circuit 4103 in the first scanning unit 41a can have the same structure and function as the output circuit 4103 in some of the above examples, the control circuit 4104 in the first scanning unit 41a can have the same structure and function as the control circuit 4104 in some of the above examples, the first reset circuit 4105 in the first scanning unit 41a and the second scanning unit 41b can have the same structure and function as the first reset circuit 4105 in some of the above examples, and the first scanning unit 41 The second reset circuit 4106 in the first scanning unit 41a and the second scanning unit 41b may have the same structure and function as the second reset circuit 4106 in some of the above examples, the third reset circuit 4107 in the first scanning unit 41a and the second scanning unit 41b may have the same structure and function as the third reset circuit 4107 in some of the above examples, the fourth reset circuit 4108 in the first scanning unit 41a may have the same structure and function as the fourth reset circuit 4108 in some of the above examples, the fifth reset circuit 4109 in the first scanning unit 41a and the second scanning unit 41b may have the same structure and function as the fifth reset circuit 4109 in some of the above examples, and the sixth reset circuit 4111 in the first scanning unit 41a and the second scanning unit 41b may have the same structure and function as the sixth reset circuit 4111 in some of the above examples. The structures and functions of the same circuits will not be described in detail here.

[0283] For example, Figure 8 As shown, compared with the output circuit 4103 in the first scanning unit 41a, the output circuit 4103 in the second scanning unit 41b may not be provided with the fourth transistor M4 and is not connected to the shift signal terminal CR <n>Electrically connected to the first clock signal terminal CLKD_1.

[0284] For example, Figure 8 As shown, the control circuit 4104 in the second scanning unit 41b can be electrically connected to the sixth voltage signal terminal VDD_B, and the sixth voltage signal terminal VDD_B is used to replace the third voltage signal terminal VDD_A. In the display stage of one frame, the third voltage signal transmitted by the third voltage signal terminal VDD_A and the sixth voltage signal transmitted by the sixth voltage signal terminal VDD_B are mutually inverted signals.

[0285] For example, Figure 8 As shown, the fourth reset circuit 4108 in the second scanning unit 41b may not be provided with the seventeenth transistor M17 compared with the fourth reset circuit 4108 in the first scanning unit 41a.

[0286] Based on this, in order to more clearly describe the structure of the shift register 41, the pull-up node Q in the first scanning unit 41a can be <n>It is called the first pull-up node Q <n>, pull up the node Q in the second scanning unit 41b <n>The second pull-up node Q<N+1> ; The pull-down node QB_A in the first scanning unit 41a can be <n>It is called the first pull-down node QB_A <n>, pull down node QB_A in the second scanning unit 41b <n>It is called the second pull-down node QB_B <n>; The leakage prevention node in the first scanning unit 41a can be OFF <n>It is called the first leakage protection node OFF <n>, turn off the leakage protection node in the second scanning unit 41b <n>It is called the second leakage protection node OFF<N+1> The second clock signal CLKE_1 in the second scanning unit 41b can be called the fourth clock signal CLKE_2; the fifth clock signal CLKF_1 in the second scanning unit 41b can be called the sixth clock signal CLKF_2; the first output signal terminal Oput1 in the first scanning unit 41a can be called <n>It is called the first sub-output signal terminal Oput1 <n>, the first output signal terminal Oput1 in the second scanning unit 41b <n>It is called the second sub-output signal terminal Oput1<N+1> The second output signal terminal Oput2 in the first scanning unit 41a can be <n>It is called the third sub-output signal terminal Oput2 <n>, the second output signal terminal Oput2 in the second scanning unit 41b <n>It is called the fourth sub-output signal terminal Oput2<N+1> .

[0287] For the description of the first reset circuit 4105 in the first scanning unit 41a and the second scanning unit 41b, reference may be made to the description of the first reset circuit 4105 in the first scanning unit 41a and the second scanning unit 41b in the second example above, which will not be repeated here.

[0288] For example, Figure 8 As shown, the fourth reset circuit 4108 in the first scanning unit 41a can also be connected to the second pull-down node QB_B <n>The fourth reset circuit 4108 is further configured to, at the second pull-down node QB_B <n>Under the control of the voltage, the shift signal terminal CR <n>, the first sub-output signal terminal Oput1 <n>And the third sub-output signal terminal Oput2 <n>.

[0289] For example, at the second pull-down node QB_B <n>When the voltage of the second pull-down node QB_B is at a high level, the fourth reset circuit 4108 can <n>The fourth voltage signal transmitted by the fourth voltage signal terminal VGL1 is transmitted to the shift signal terminal CR <n>, for the shift signal terminal CR <n>Pull-down reset is performed to transmit the fifth voltage signal transmitted by the fifth voltage signal terminal VGL2 to the first sub-output signal terminal Oput1 <n>, for the first sub-output signal terminal Oput1 <n>Pull-down reset is performed, and the fifth voltage signal transmitted by the fifth voltage signal terminal VGL2 is transmitted to the third sub-output signal terminal Oput2 <n>, for the third sub-output signal terminal Oput2 <n>Pull-down reset.

[0290] Optional, such as Figure 8 As shown, the fourth reset circuit 4108 in the first scanning unit 41a may further include: a thirty-first transistor M31, a thirty-second transistor M32 and a thirty-third transistor M33.

[0291] For example, Figure 8 As shown, the control electrode of the thirty-first transistor M31 is connected to the second pull-down node QB_B <n>The first electrode of the thirty-first transistor M31 is electrically connected to the shift signal terminal CR <n>The second electrode of the thirty-first transistor M31 is electrically connected to the fourth voltage signal terminal VGL1.

[0292] At the second pull-down node QB_B <n>When the voltage of QB_B is at a high level, the thirty-first transistor M31 can <n>The fourth voltage signal transmitted by the fourth voltage signal terminal VGL1 is transmitted to the shift signal terminal CR <n>, for the shift signal terminal CR <n>Pull-down reset.

[0293] For example, Figure 8 As shown, the control electrode of the thirty-second transistor M32 is connected to the second pull-down node QB_B <n>The first electrode of the thirty-second transistor M32 is electrically connected to the first sub-output signal terminal Oput1 <n>The second electrode of the thirty-second transistor M32 is electrically connected to the fifth voltage signal terminal VGL2.

[0294] At the second pull-down node QB_B <n>When the voltage of QB_B is at a high level, the thirty-second transistor M32 can be <n>The fifth voltage signal transmitted by the fifth voltage signal terminal VGL2 is transmitted to the first sub-output signal terminal Oput1 <n>, for the first sub-output signal terminal Oput1 <n>Pull-down reset.

[0295] For example, Figure 8 As shown, the control electrode of the thirty-third transistor M33 is connected to the second pull-down node QB_B <n>The first electrode of the thirty-second transistor M32 is electrically connected to the third sub-output signal terminal Oput2 <n>The second electrode of the thirty-second transistor M32 is electrically connected to the fifth voltage signal terminal VGL2.

[0296] At the second pull-down node QB_B <n>When the voltage of QB_B is at a high level, the thirty-third transistor M33 can be connected to the second pull-down node QB_B <n>The fifth voltage signal transmitted by the fifth voltage signal terminal VGL2 is transmitted to the third sub-output signal terminal Oput2 <n>, for the third sub-output signal terminal Oput2 <n>Pull-down reset.

[0297] For example, Figure 8 As shown, the fourth reset circuit 4108 in the second scanning unit 41b can also be connected to the first pull-down node QB_A <n>The fourth reset circuit 4108 is further configured to, at the first pull-down node QB_A <n>Under the control of the voltage, the second sub-output signal terminal Oput1<N+1> And the fourth sub-output signal terminal Oput2<N+1> Perform a reset.

[0298] For example, at the first drop-down node QB_A <n>When the voltage of QB_A is high, the fourth reset circuit 4108 can reset the first pull-down node QB_A <n>The fifth voltage signal transmitted by the fifth voltage signal terminal VGL2 is transmitted to the second sub-output signal terminal Oput1<N+1> , for the second sub-output signal terminal Oput1<N+1> Pull-down reset is performed, and the fifth voltage signal transmitted by the fifth voltage signal terminal VGL2 is transmitted to the fourth sub-output signal terminal Oput2<N+1> , for the fourth sub-output signal terminal Oput2<N+1> Pull-down reset.

[0299] Optional, such as Figure 8 As shown, the fourth reset circuit 4108 in the second scanning unit 41b may further include: a thirty-second transistor M32 and a thirty-third transistor M33.

[0300] For example, Figure 8 As shown, the control electrode of the thirty-second transistor M32 is connected to the first pull-down node QB_A. <n>The first electrode of the thirty-second transistor M32 is electrically connected to the second sub-output signal terminal Oput1<N+1> The second electrode of the thirty-second transistor M32 is electrically connected to the fifth voltage signal terminal VGL2.

[0301] At the first drop-down node QB_A <n>When the voltage of QB_A is high, the thirty-second transistor M32 can be connected to the first pull-down node QB_A <n>The fifth voltage signal transmitted by the fifth voltage signal terminal VGL2 is transmitted to the second sub-output signal terminal Oput1<N+1> , for the second sub-output signal terminal Oput1<N+1> Pull-down reset.

[0302] For example, Figure 8 As shown, the control electrode of the thirty-third transistor M33 is connected to the first pull-down node QB_A. <n>The first electrode of the thirty-second transistor M32 is electrically connected to the fourth sub-output signal terminal Oput2<N+1> The second electrode of the thirty-second transistor M32 is electrically connected to the fifth voltage signal terminal VGL2.

[0303] At the first drop-down node QB_A <n>When the voltage of QB_A is at a high level, the thirty-third transistor M33 can be connected to the first pull-down node QB_A <n>The fifth voltage signal transmitted by the fifth voltage signal terminal VGL2 is transmitted to the fourth sub-output signal terminal Oput2<N+1> , for the fourth sub-output signal terminal Oput2<N+1> Pull-down reset.

[0304] Next, the structure of the scan driving circuit 4 is further schematically described by taking the structure of the shift register 41 shown in the second example as an example.

[0305] In some examples, such as Fig. 9 As shown, the scan driving circuit 4 may further include: a plurality of clock signal lines 42 extending along the second direction Y. One clock signal line 42 may be electrically connected to at least one stage of shift register 41 , and one stage of shift register 41 may be electrically connected to at least one clock signal line 42 .

[0306] For example, Fig. 9 A1 and A2 shown in the figure respectively represent the first scanning unit 41a and the second scanning unit 41b in the first-stage shift register 41, and are respectively electrically connected to the pixel driving circuit 21 of the first row of sub-pixels 2 and the pixel driving circuit 21 of the second row of sub-pixels 2 in the display panel 100; A3 and A4 respectively represent the first scanning unit 41a and the second scanning unit 41b in the second-stage shift register 41, and are respectively electrically connected to the pixel driving circuit 21 of the third row of sub-pixels 2 and the pixel driving circuit 21 of the fourth row of sub-pixels 2 in the display panel 100; A5 and A6 respectively represent the first scanning unit 41a and the second scanning unit 41b in the third-stage shift register 31, and are respectively electrically connected to the pixel driving circuit 21 of the fifth row of sub-pixels 2 and the pixel driving circuit 21 of the sixth row of sub-pixels 2 in the display panel 100.

[0307] For example, Fig. 9 As shown, the plurality of clock signal lines 42 may include: a first sub-clock signal line CLK_1 , a second sub-clock signal line CLK_2 , and a third sub-clock signal line CLK_3 .

[0308] The first clock signal terminal CLKD_1 of the first scanning unit 41a in the 3N-2 stage shift register 41 is electrically connected to the first clock signal line CLK_1 to receive the first clock signal. The first clock signal terminal CLKD_1 of the first scanning unit 41a in the 3N-1 stage shift register 41 is electrically connected to the second clock signal line CLK_2 to receive the first clock signal. The first clock signal terminal CLKD_1 of the first scanning unit 41a in the 3N stage shift register 41 is electrically connected to the third clock signal line CLK_3 to receive the first clock signal.

[0309] For example, Fig. 9 As shown, the plurality of clock signal lines 42 may further include: a fourth sub-clock signal line CLK_4, a fifth sub-clock signal line CLK_5, a sixth sub-clock signal line CLK_6, a seventh sub-clock signal line CLK_7, an eighth sub-clock signal line CLK_8 and a ninth sub-clock signal line CLK_9.

[0310] The second clock signal terminal CLKE_1 of the first scanning unit 41a in the 3N-2 stage shift register 41 is electrically connected to the fourth sub-clock signal line CLK_4 to receive the second clock signal, and the fourth clock signal terminal CLKE_2 of the second scanning unit 41b is electrically connected to the fifth sub-clock signal line CLK_5 to receive the fourth clock signal.

[0311] The second clock signal terminal CLKE_1 of the first scanning unit 41a in the 3N-1th stage shift register 41 is electrically connected to the sixth sub-clock signal line CLK_6 to receive the second clock signal, and the fourth clock signal terminal CLKE_2 of the second scanning unit 41b is electrically connected to the seventh sub-clock signal line CLK_7 to receive the fourth clock signal.

[0312] The second clock signal terminal CLKE_1 of the first scanning unit 41a in the 3N-stage shift register 41 is electrically connected to the eighth sub-clock signal line CLK_8 to receive the second clock signal, and the fourth clock signal terminal CLKE_2 of the second scanning unit 41b is electrically connected to the ninth sub-clock signal line CLK_9 to receive the fourth clock signal.

[0313] For example, Fig. 9 As shown, the plurality of clock signal lines 42 may further include: a tenth sub-clock signal line CLK_10.

[0314] The global reset signal terminal TRST of the first scanning unit 41 a and the global reset signal terminal TRST of the second scanning unit 41 b in each stage of the shift register 41 may be electrically connected to the tenth sub-clock signal line CLK_10 to receive the global reset signal.

[0315] For example, Fig. 9 As shown, the plurality of clock signal lines 42 may further include: an eleventh sub-clock signal line CLK_11 and a twelfth sub-clock signal line CLK_12.

[0316] The selection control signal terminal OE of the blanking circuit 4110 in each stage of the shift register 41 may be electrically connected to the eleventh sub-clock signal line CLK_11 to receive the selection control signal.

[0317] The third clock signal terminal CLKA of the blanking circuit 4110 in each stage of the shift register 41 may be electrically connected to the twelfth sub-clock signal line CLK_12 to receive the third clock signal.

[0318] For example, Fig. 9 As shown, the plurality of clock signal lines 42 may further include: a thirteenth sub-clock signal line CLK_13 and a fourteenth sub-clock signal line CLK_14.

[0319] The third voltage signal terminal VDD_A of the first scanning unit 41a in each stage of the shift register 41 can be electrically connected to the thirteenth sub-clock signal line CLK_13 to receive the third voltage signal. The sixth voltage signal terminal VDD_B of the second scanning unit 41b in each stage of the shift register 41 is electrically connected to the fourteenth sub-clock signal line CLK_14 to receive the sixth voltage signal.

[0320] For example, Fig. 9 As shown, the plurality of clock signal lines 42 may further include: a fifteenth sub-clock signal line CLK_15.

[0321] The input signal terminal Iput of the first scanning unit 41a and the input signal terminal Iput of the second scanning unit 41b in the first-stage shift register 41 may be electrically connected to the fifteenth sub-clock signal line CLK_15 to receive the start signal as an input signal.

[0322] like Fig. 9 As shown, except for the first stage shift register 41, the input signal terminal Iput of the first scanning unit 41a and the second scanning unit 41b in the other stage shift register 41 and the shift signal terminal CR of the first scanning unit 41a in the previous stage shift register 41 <n>Except for the last two stages of shift registers 41, the display reset signal terminals STD of the first scanning unit 41a and the second scanning unit 41b in the other stages of shift registers 41 and the shift signal terminals CR of the first subunit 1 in the last two stages of shift registers 41 are connected. <n>Electrical connection.

[0323] It should be noted that Fig. 9 The cascading relationship shown in is only an example, and other cascading modes may be adopted according to actual conditions.

[0324] Fig.10 Shows Figure 6 The shift register 41 shown in FIG. Fig.10 Middle, Q <1> and Q <2> are respectively represented as the first pull-up node Q in the first stage shift register 41 <n>and the second pull-up node Q<N+1> , the number in the brackets indicates the number of rows of sub-pixels 2 in the display panel 100 corresponding to the node (the same below). <1> and Oput1 <1> are respectively represented as the first sub-output signal terminal Oput1 in the first stage shift register 41 <n>The first output signal and the second sub-output signal terminal Oput1<N+1> The second output signal of the output. <1> N represents the first blanking node H in the first stage shift register 41. <1> represents the second blanking node N in the first stage shift register 41. 1F represents one frame, Display represents the display period in one frame display stage, and Blank represents the blanking period in one frame display stage.

[0325] Combine the following Fig. 9 and Fig.10 ,right Figure 6 The driving method of the shift register 41 shown in the figure is schematically illustrated in the display stage of one frame.

[0326] At the beginning of the display stage of a frame, in the first stage 1, the level of the global reset signal provided by the tenth sub-clock signal line CLK_10 is high, and the fifteenth transistor M15 and the sixteenth transistor M16 of the third reset circuit 4107 in each stage of the shift register 41 are turned on, and the fourth voltage signal transmitted by the fourth voltage signal terminal VGL1 is transmitted to the first pull-up node Q1 and the second pull-up node Q2, and the first pull-up node Q1 and the second pull-up node Q2 in each stage of the shift register 41 are reset.

[0327] The level of the selection control signal provided by the eleventh sub-clock signal line CLK_11 is high, and the twenty-first transistor M21 and the twenty-second transistor M22 of the selection control circuit 41101 in each stage of the shift register 41 are turned on. Since the level of the shift signal output from each stage of the shift register 41 is low, the low-level shift signal can be transmitted to the first blanking node H, and the first blanking node H in each stage of the shift register 41 is reset, thereby completing the global reset.

[0328] The following describes the working process of the first-stage shift register 41 (ie, corresponding to the sub-pixels 2 in the first and second rows of the display panel 100 ) during the display period in a frame display stage.

[0329] In the second stage 2, the level of the start signal transmitted by the fifteenth sub-clock signal line CLK_15 is a high level. That is, the level of the signal transmitted to the input signal terminal Iput of the first-stage shift register 41 and the level of the input signal transmitted by the input signal terminal Iput are high. In the first-stage shift register 41, the first transistor M1 and the second transistor M2 of the first input circuit 4101 are turned on under the action of the input signal, and then the first pull-up node Q is pulled up by the high-level input signal. <1> charging, the first pull-up node Q <1> Pull up to high level and pull up the second node Q <2> To charge, pull the second node Q <2> Pull up to high level.

[0330] In the first scanning unit 41a of the first stage shift register 41, the fourth transistor M4 of the output circuit 4103 is at the first pull-up node Q <1> However, since the level of the first clock signal provided by the first sub-clock signal line CLK_1 is low, the shift signal terminal CR <1> The level of the output shift signal is low. The fifth transistor M5 of the output circuit 4130 is at the first pull-up node Q <1> However, since the level of the second clock signal provided by the fourth sub-clock signal line CLK_4 is low, the first sub-output signal terminal Oput1 in the first scanning unit 41a of the first-stage shift register 41 is turned on under the control of the voltage of <1> The first output signal Oput1 is output <1> The level is low.

[0331] In the second scanning unit 41b of the first stage shift register 41, the fifth transistor M5 of the output circuit 4103 is at the second pull-up node Q <2> However, since the level of the fourth clock signal provided by the fifth sub-clock signal line CLK_5 is low, the second sub-output signal terminal Oput1 in the second scanning unit 41b of the first-stage shift register 41 is turned on under the control of the voltage of <2> The second output signal Oput1 is output <2> is low level.

[0332] In the third phase 3, the level of the first clock signal provided by the first sub-clock signal line CLK_1 becomes high, and the level of the second clock signal provided by the fourth sub-clock signal line CLK_4 becomes high. <1> The voltage of the fourth transistor M4 and the fifth transistor M5 is further increased due to the bootstrap effect, so that the fourth transistor M4 and the fifth transistor M5 remain in the on state, thereby making the shift signal terminal CR in the first stage shift register 41 <1> The level of the output shift signal becomes high, so that the first sub-output signal terminal Oput1 <1> The first output signal Oput1 is output <1> However, since the fourth clock signal provided by the fifth sub-clock signal line CLK_5 is still at a low level, the second sub-output signal terminal Oput1 in the second scanning unit 41b is <2> The second output signal Oput1 is output <2> The level continues to remain low.

[0333] The selection control signal and the shift signal terminal CR provided by the eleventh sub-clock signal line CLK_11 <1> The output shift signal is the same, that is, the level of the selection control signal is high, the twenty-first transistor M21 and the twenty-second transistor M22 in the selection control circuit 41101 are turned on under the control of the selection control signal, and then the high-level shift signal is used to control the first blanking node H <1> Charge.

[0334] In the fourth stage 4, the level of the fourth clock signal provided by the fifth sub-clock signal line CLK_5 becomes high level, and in the second scanning unit 41b, the second pull-up node Q <2> The voltage of the fifth transistor M5 is further increased due to the bootstrap effect of the fifth transistor M5, so that the fifth transistor M5 remains in the on state, thereby making the second sub-output signal terminal Oput1 in the first-stage shift register 41 <2> The second output signal Oput1 is output <2> becomes a high level.

[0335] In the fifth stage 5, due to the holding effect of the first capacitor C1 in the first scanning unit 41a, the first pull-up node Q <1> Still maintains a high level, so that the fifth transistor M5 remains in the on state. However, since the level of the second clock signal provided by the fourth sub-clock signal line CLK_4 becomes a low level, the first sub-output signal terminal Oput1 in the first scanning unit 41a <1> The first output signal Oput1 is output <1> At the same time, due to the bootstrap effect of the fifth transistor M5, the first pull-up node Q <1> The voltage will also drop.

[0336] In the sixth stage 6, due to the holding effect of the first capacitor C1 in the second scanning unit 41b, the second pull-up node Q <2> Still maintains a high level, so that the fifth transistor M5 remains in the on state. However, since the fourth clock signal provided by the fifth sub-clock signal line CLK_5 becomes a low level, the second sub-output signal terminal Oput1 in the second scanning unit 41b <2> The second output signal Oput1 is output <2> At the same time, due to the bootstrap effect of the fifth transistor M5, the second pull-up node Q <2> The potential will also decrease.

[0337] In the second stage 2 to the sixth stage 6, due to the first pull-up node Q in the first scanning unit 41a <1> The voltage of the first anti-leakage node OFF is always kept at a high level, therefore, the third transistor M3 continuously transmits the second voltage signal to the first anti-leakage node OFF. <1> ; Due to the second pull-up node Q in the second scanning unit 41b <2> The voltage of the third transistor M3 is always kept at a high level, therefore, the third transistor M3 continuously transmits the second voltage signal to the second leakage prevention node OFF. <2> .

[0338] After the first shift register 41 drives the sub-pixels 2 of the first and second rows in the display panel 100 to complete display, the second, third, etc. shift registers 41 drive the sub-pixels 2 in the display panel 100 row by row to complete the display drive of one frame. At this point, the display period in one frame display stage ends.

[0339] During the blanking period in a frame display stage, the working process of the first-stage shift register 41 (ie, corresponding to the sub-pixels 2 in the first and second rows of the display panel 100 ) is described as follows.

[0340] Here, in the third stage 3, the first blanking node H <1> charging, so that the first blanking node H <1> After the voltage of the first blanking node H increases, the third capacitor C3 can be discharged so that the first blanking node H <1> The second input circuit 41102 can maintain a high potential at the first blanking node H during the display period of a frame display stage. <1> Under the action of the voltage, it remains in the turned-on state and inputs the second voltage signal to the second blanking node N <1> , so that the second blanking node N <1> The high potential is maintained during the display period in one frame display phase.

[0341] In the seventh stage 7, the level of the third clock signal provided by the twelfth sub-clock signal line CLK_12 is high. The twenty-fifth transistor M25 in the transmission circuit 41103 can be turned on under the control of the high-level third clock signal, and the second blanking node N <1> The second voltage signal is transmitted to the first pull-up node Q <1> and the second pull-up node Q <2> , respectively, for the first pull-up node Q <1> and the second pull-up node Q <2> The first pull-up node Q <1> and the second pull-up node Q <2> The voltage is pulled high.

[0342] In the eighth stage 8, the level of the second clock signal provided by the fourth sub-clock signal line CLK_4 changes to a high level, and the first pull-up node Q <1> The potential of the first sub-output signal terminal Oput1 of the first scanning unit 41a is further increased due to the bootstrap effect of the fifth transistor M5, so that the fifth transistor M5 remains in the on state, and the first sub-output signal terminal Oput1 of the first scanning unit 41a is <1> The first output signal Oput1 is output <1> The level of the second scanning signal (ie, the second scanning signal) becomes a high level.

[0343] Since the level of the fourth clock signal provided by the fifth sub-clock signal line CLK_5 is still at a low level, the second sub-output signal terminal Oput1 of the second scanning unit 41b is <2> The second output signal Oput1 is output <2> The level of the second scanning signal is low.

[0344] Here, the first output signal output in the eighth stage 8 may be used to drive the sensing transistor T3 in the sub-pixel 2 of the corresponding row in the display panel 100 to achieve external compensation.

[0345] In the ninth stage 9, due to the holding effect of the first capacitor C1, the first pull-up node Q <1> The level of the second clock signal provided by the fourth sub-clock signal line CLK_4 becomes low, so the first sub-output signal terminal Oput1 of the first scanning unit 41a is still maintained at a high level, so that the fifth transistor M5 remains in a conducting state. <1> The first output signal Oput1 is output <1> The level of the second scanning signal (ie, the second scanning signal) becomes a low level.

[0346] At the same time, due to the bootstrap effect of the fifth transistor M5, the first pull-up node Q <1> The potential will also decrease.

[0347] At this point, the blanking period in one frame display phase ends.

[0348] In the subsequent display phase of other frames, the driving process of the scan driving circuit 4 can refer to the above description, which will not be repeated here.

[0349] In one implementation, Figure 1 As shown, the display panel generally has a display area A and a frame area B surrounding the display area A. Subpixels P in the display panel are generally arranged in the display area A, and a scan driving circuit electrically connected to the subpixels P is generally arranged in the frame area B.

[0350] As the resolution of display panels becomes higher and higher, narrow borders or even borderless display panels have become the current development trend. In the display field, especially in large-size OLED displays, it is difficult to achieve narrow borders or even borderless display panels by setting the scan drive circuit in the border area B of the display panel. Moreover, the shape of the current display panel is mostly designed as a non-rectangular shape, which makes it more difficult to achieve narrow borders or even borderless display panels using the above-mentioned setting method to set the scan drive circuit.

[0351] Based on this, Figure 3 As shown, the multi-stage shift register 41 and the multiple clock signal lines 42 included in the scan driving circuit 4 can be located in the display area A. Each stage of the shift register 41 can include multiple device groups 411, and one period group 4111 can be located in the area between two adjacent sub-pixels 2 in the corresponding at least one row of sub-pixels 2.

[0352] For example, Figure 3 and Fig.11 As shown, one device group 411 may include at least one transistor and / or at least one capacitor. Figure 3 and Fig.11 The multiple device groups 411 shown in the figure are only a part of the transistors and a part of the capacitors in the corresponding one-stage shift register 41.

[0353] Here, the way of dividing the multiple transistors and capacitors included in the shift register 41 can be selected and set according to actual needs, so that the space occupied by the divided device group 411 is smaller and the complexity of the connection relationship between the device groups 411 is lower.

[0354] For example, Fig.11 As shown, one device group 411 may include a first transistor M1 and a second transistor M2 in a first input circuit 4101 .

[0355] For example, Fig.11 As shown, one device group 411 may include a third transistor M3 in the leakage protection circuit 4102 .

[0356] For example, Fig.11 As shown, one device group 411 may include a third capacitor C3 in the selection control circuit 41101 .

[0357] It should be noted that in actual products, some circuits include multiple transistors connected in parallel. Figures 5 to 8 and Fig.11 Only one of the shift registers 41 shown in the circuit diagram is shown.

[0358] For example, the first input circuit 4101 includes one first transistor M1 and one second transistor M2, respectively. In an actual product, the first input circuit 4101 may include a plurality of first transistors M1 and second transistors M2 connected in parallel. Each first transistor M1 and one second transistor M2 may constitute a device group 411, which is disposed in a region between two adjacent sub-pixels 2 in a corresponding row of sub-pixels 2.

[0359] For example, Fig.11 As shown, the arrangement of the device group 411 in the region between two adjacent sub-pixels 2 in the corresponding at least one row of sub-pixels 2 can be: when the device group 411 is arranged in the region between two adjacent sub-pixels 2 in the at least one row of sub-pixels 2, only one device group 411 is arranged in the region. That is, the regions where the multiple device groups 411 included in the shift register 41 are located are different, and at least one sub-pixel 2 is arranged between two adjacent device groups 411. Among them, "the corresponding at least one row of sub-pixels 2" refers to at least one row of sub-pixels 2 electrically connected to the first-level shift register 41, and the output signal output by the shift register 41 can be transmitted to the row of sub-pixels 2. "The region between two adjacent sub-pixels 2 in the corresponding at least one row of sub-pixels 2" refers to the region between two adjacent sub-pixels 2 arranged along the first direction X in the at least one row of sub-pixels 2.

[0360] By arranging the multiple device groups 411 included in the shift register 41 in the area between two adjacent sub-pixels 2 in at least one corresponding row of sub-pixels 2, the space occupied by the portion of the scanning drive circuit 4 located in the border area B can be effectively reduced, which is conducive to enabling the display panel 100 to achieve a narrow border design or even a borderless design.

[0361] For example, Figure 3 and Fig.11 As shown, the clock signal line 42 is located between two adjacent columns of sub-pixels 2 .

[0362] For example, Figure 3 and Fig.11 As shown, the area between two adjacent columns of sub-pixels 2 is called the first gap area. The clock signal line 42 may be arranged in the first gap area, for example: one clock signal line 42 may be arranged in one first gap area, and at least one column of sub-pixels 2 may be arranged between two adjacent clock signal lines 42.

[0363] Since the size of the clock signal line 42 in the first direction X is relatively large, by setting only one clock signal line 42 in a first gap area, it is possible to avoid increasing the size of the first gap area in the first direction X, thereby avoiding affecting the distribution uniformity of multiple sub-pixels 2 in the display panel 100 and avoiding reducing the PPI of the display panel 100.

[0364] Moreover, by arranging the clock signal line 42 in the first gap area, the space occupied by the scan driving circuit 4 in the border area B can be effectively reduced, thereby facilitating the display panel 100 to achieve a narrow border design or even a borderless design.

[0365] In some examples, such as Figure 3 As shown, the frame area B of the display panel 100 may include a fan-out area B1. The fan-out area B1 may be located at one side of the display area A. There may be a gap between the fan-out area B1 and the display area A, for example.

[0366] Of course, the arrangement between the fan-out area B1 and the display area A is not limited thereto.

[0367] Optional, such as Figure 3 As shown, the display area A and the fan-out area B1 are arranged in sequence along the second direction Y. For example, the center line of the display area A in the second direction Y coincides with the center line of the fan-out area B1 in the second direction Y, and the size of the fan-out area B1 in the first direction X is smaller than the size of the display area A in the first direction X.

[0368] In some examples, such as Figure 3 As shown, the display panel 100 may further include: a power supply voltage bus 5 disposed in the fan-out area B1. The power supply voltage bus 5 may extend along the first direction X.

[0369] For example, Figure 3 , Fig.16 , Fig.19 and Fig.21 As shown, the power supply voltage bus 5 can be electrically connected to at least a portion of the plurality of power supply voltage signal lines EL. Since each power supply voltage signal point EL extends along the second direction Y, one end of the power supply voltage signal point EL can, for example, extend into the fan-out area B1 and be electrically connected to the power supply voltage bus 5 through a corresponding via.

[0370] In this way, when the display panel 100 is displaying, the power voltage bus 5 can simultaneously transmit the power voltage signal to at least a portion of the multiple power voltage signal lines EL, and further simultaneously transmit the power voltage signal to the pixel driving circuits 21 in the multiple sub-pixels 2. This is conducive to improving the transmission efficiency of the power voltage signal and reducing the wiring difficulty of the display panel 100.

[0371] In some examples, such as Figure 3 As shown, the display panel 100 may further include: a plurality of connection lines 6. The plurality of connection lines 6 may be located on the same side of the substrate 1 as the plurality of sub-pixels 2, the plurality of signal transmission lines 3, the scan drive circuit 4 and the power supply voltage bus 5.

[0372] For example, Figure 3 As shown, the plurality of connection lines 6 may extend along the second direction Y and be located on a side of the power supply voltage bus 5 away from the plurality of sub-pixels 2. That is, the plurality of connection lines 6 are further away from the display area A than the power supply voltage bus 5. This facilitates the arrangement design of the plurality of connection lines 6.

[0373] The connection line 6 may be electrically connected to a signal line (e.g., a data line DL, a sensing line SL, or a clock signal line 42) located in the display area A. When the display panel 100 is applied to a display device 1000, the connection line 6 may also be electrically connected to a display driver IC or other electronic components in the display device 1000 to transmit a corresponding electrical signal to the signal line located in the display area A.

[0374] In some examples, such as Figure 3 As shown, the plurality of connection lines 6 may include: a plurality of first sub-connection lines 61 . One first sub-connection line 61 may be electrically connected to one signal transmission line 3 .

[0375] Here, if Figure 3 As shown, based on the fact that the plurality of signal transmission lines 3 include a plurality of data lines DL and a plurality of sensing lines SL, the plurality of first sub-connection lines 61 may include a plurality of data connection lines 611 and a plurality of sensing connection lines 612. Among them, one data connection line 611 may be electrically connected to one data line DL, for example, and one sensing connection line 612 may be electrically connected to one sensing line SL, for example.

[0376] The arrangement of the data connection lines 611 and the sensing connection lines 612 includes various arrangements, which can be arranged according to the arrangement of the data lines DL and the sensing lines SL in the display area A. For example, at least two data lines DL can be arranged between any two adjacent sensing lines SL, and at least two data connection lines 611 can be arranged between any two adjacent sensing connection lines 612.

[0377] For example, Figure 3 and Fig.11 As shown, four data lines DL may be arranged between any two adjacent sensing lines SL, that is, four columns of sub-pixels 2 share the same sensing line SL. Correspondingly, four data connection lines 611 may be arranged between any two adjacent sensing connection lines 612, and four data lines DL may be arranged between the four data connection lines 611 and the two adjacent sensing lines SL to be electrically connected to each other.

[0378] This can avoid crossing between traces extending in the same direction, thereby avoiding short circuits or capacitance between traces extending in the same direction.

[0379] Exemplarily, one end of the data line DL close to the fan-out area B1 can extend into the fan-out area B1 and be electrically connected to the corresponding data connection line 611. One end of the sensing line SL close to the fan-out area B1 can extend into the fan-out area B1 and be electrically connected to the corresponding sensing connection line 612.

[0380] In this way, during the display process of the display panel 100, the above-mentioned multiple data connection lines 611 can respectively transmit data signals to the corresponding data lines DL, and then transmit data signals to the pixel driving circuit 21 in the corresponding sub-pixel 2. The above-mentioned multiple sensing connection lines 612 can respectively transmit reset signals to the corresponding sensing lines SL, and then transmit reset signals to the pixel driving circuit 21 in the corresponding sub-pixel 2, or obtain sensing signals from the pixel driving circuit 21 in the corresponding sub-pixel 2 and the corresponding sensing line SL.

[0381] For example, Figure 3 , Fig.16 , Fig.19 and Fig.21 As shown, the orthographic projection shape of the data connection line 611 on the substrate 1 may be a rectangle or approximately a rectangle. The size of the data connection line 611 in the first direction X is larger than the size of the data line DL in the first direction X. The resistances of two adjacent data connection lines 611 may be equal or unequal.

[0382] It should be noted that if Figure 3 , Fig.16 , Fig.19 and Fig.21 As shown, since the size of the fan-out area B1 in the first direction X is smaller than the size of the display area A in the first direction X, after one end of each data line DL in the display area A extends into the fan-out area B1, the length of each data line DL will be different, and then the resistance of each data line DL will be different. Alternatively, since the shape of the display area A is an irregular rectangle, the length of each data line DL in the display area A will be different. After one end of each data line DL extends into the fan-out area B1, it is easy to make the length of each data line DL further different, and then the resistance of each data line DL will be different.

[0383] By electrically connecting each data line DL to the data connection line 611 and determining the resistance of the corresponding data connection line 611 according to the length or resistance of each data line DL, the overall resistance of each data line DL and the corresponding data connection line 611 can be adjusted so that the sum of the resistance of each data line DL and the corresponding data connection line 611 is equal or substantially equal. This helps to ensure the consistency of data signals transmitted to different positions in the display area A, so that the display panel 100 has a good display effect.

[0384] For example, the orthographic projection areas of two adjacent data connection lines 611 on the substrate 1 may be equal or unequal. Optionally, the sizes of two adjacent data connection lines 611 in the first direction X may be equal or unequal; the sizes of two adjacent data connection lines 611 in the second direction Y may be equal or unequal. The size of each data connection line 611 in the first direction X and the size in the second direction Y may be set according to actual needs.

[0385] For example, Figure 3 , Fig.16 , Fig.19 and Fig.21 As shown, the orthographic projection shape of the sensing connection line 612 on the substrate 1 may be a rectangle or approximately a rectangle. The dimension of the sensing connection line 612 in the first direction X is greater than the dimension of the sensing line SL in the first direction X. The resistances of two adjacent sensing connection lines 612 may be equal or unequal.

[0386] It should be noted that if Figure 3 , Fig.16 , Fig.19 and Fig.21 As shown, since the size of the fan-out area B1 in the first direction X is smaller than the size of the display area A in the first direction X, after one end of each sensing line SL in the display area A extends into the fan-out area B1, the length of each sensing line SL will be different, and then the resistance of each sensing line SL will be different. Alternatively, since the shape of the display area A is an irregular rectangle, the length of each sensing line SL in the display area A will be different. After one end of each sensing line SL extends into the fan-out area B1, it is easy to make the length of each sensing line SL further different, and then the resistance of each sensing line SL will be different.

[0387] By electrically connecting each sensing line SL to the sensing connection line 612 and determining the resistance of the corresponding sensing connection line 612 according to the length or resistance of each sensing line SL, the resistance of each sensing line SL and the corresponding sensing connection line 612 as a whole can be adjusted so that the sum of the resistance of each sensing line SL and the corresponding sensing connection line 612 is equal or substantially equal. This helps to ensure the consistency of the sensing signals transmitted to different positions in the display area A, so that the display panel 100 has a good display effect.

[0388] For example, the orthographic projection areas of two adjacent sensing connection lines 612 on the substrate 1 may be equal or unequal. Optionally, the sizes of two adjacent sensing connection lines 612 in the first direction X may be equal or unequal; the sizes of two adjacent sensing connection lines 612 in the second direction Y may be equal or unequal. The size of each sensing connection line 612 in the first direction X and the size in the second direction Y may be set according to actual needs.

[0389] In some examples, such as Figure 3 As shown, the plurality of connection lines 6 may further include: a plurality of second sub-connection lines 62 . One second sub-connection line 62 may be electrically connected to the power supply voltage bus 5 .

[0390] For example, Figure 3 As shown, the number of the power supply voltage bus 5 can be one. In this case, the power supply voltage bus 5 can be electrically connected to a plurality of second sub-connection lines 62 .

[0391] In this way, during the display process of the display panel 100, the above-mentioned multiple second sub-connection lines 62 can transmit power supply voltage signals to the power supply voltage bus 5, and then transmit the power supply voltage signals to the multiple power supply voltage signal lines EL in the display area A through the power supply voltage bus 5, and transmit the power supply voltage signals to the pixel driving circuit 21 in the corresponding sub-pixel 2.

[0392] For example, Figure 3 As shown, the number of the second sub-connection lines 62 is less than the number of the first sub-connection lines 61 , and the size of the second sub-connection lines 62 in the first direction X is greater than the size of the first sub-connection lines 61 in the first direction X.

[0393] Since the second sub-connection lines 62 are used to transmit power voltage signals and the number of the second sub-connection lines 62 is small, by setting the size of the second sub-connection lines 62 in the first direction X to a larger size, the second sub-connection lines 62 can be prevented from being damaged, thereby avoiding affecting the display effect of the display panel 100.

[0394] In some examples, such as Figure 3 As shown, the plurality of connection lines 6 may further include: a plurality of third sub-connection lines 63. One third sub-connection line 63 may be electrically connected to one clock signal line 42. The two may be electrically connected in a one-to-one correspondence, for example.

[0395] For example, the clock signal line 42 electrically connected to the third sub-connection line 63 can be: the first sub-clock signal line CLK_1, the second sub-clock signal line CLK_2, the third sub-clock signal line CLK_3, the fourth sub-clock signal line CLK_4, the fifth sub-clock signal line CLK_5, the sixth sub-clock signal line CLK_6 or the seventh sub-clock signal line CLK_7, etc.

[0396] In this way, during the display process of the display panel 100 , the plurality of third sub-connection lines 63 can transmit corresponding clock signals to the plurality of clock signal lines 42 in the display area A, and further transmit corresponding clock signals to the corresponding first-stage shift register 41 .

[0397] For example, Figure 3 As shown, the number of the third sub-connection lines 63 is less than the number of the first sub-connection lines 61 , and the size of the third sub-connection lines 63 in the first direction X is greater than the size of the first sub-connection lines 61 in the first direction X.

[0398] Here, among the plurality of connection lines 6 , there are various positional relationships among the first sub-connection line 61 , the second sub-connection line 62 and the third sub-connection line 63 , which can be selected and set according to actual needs.

[0399] The following is Figure 12-13 , Figure 16-17 and Figure 19 to Figure 22 The structure shown schematically describes the relationship between the film layers in the display panel 100, so as to more clearly and briefly describe the positional relationship between the first sub-connection line 61, the second sub-connection line 62 and the third sub-connection line 63. Of course, the relationship between the film layers in the display panel 100 is not limited to the relationship shown in the figure.

[0400] In some embodiments, Fig.13 As shown, the display panel 100 includes: a first light-transmitting layer F1, a first metal layer F2, a second metal layer F3 and a second light-transmitting layer F4 stacked in sequence. The first light-transmitting layer F1 is closer to the substrate 1 than the second light-transmitting layer F4.

[0401] Exemplarily, the material of the first light-transmitting layer F1 may include, for example, ITO, IZO (Indium Zinc Oxide) or IGZO (Indium Gallium Zinc Oxide). The material of the first metal layer F2 may include, for example, aluminum, copper, molybdenum, titanium or aluminum-neodymium alloy. The material of the second metal layer F3 may include, for example, aluminum, copper, molybdenum, titanium or aluminum-neodymium alloy. The material of the second light-transmitting layer F4 may include, for example, ITO, IZO or IGZO.

[0402] It should be noted that the first light-transmitting layer F1 includes a plurality of patterns (the plurality of patterns can be formed in one patterning process, for example), the first metal layer F2 includes a plurality of patterns (the plurality of patterns can be formed in one patterning process, for example), the second metal layer includes a plurality of patterns (the plurality of patterns can be formed in one patterning process, for example), and the second light-transmitting layer F4 includes a plurality of patterns (the plurality of patterns can be formed in one patterning process, for example). In the first light-transmitting layer F1, the first metal layer F2, the second metal layer F3 and the second light-transmitting layer F4, the patterns included in any two adjacent film layers are different. The patterns included in the plurality of film layers can, for example, constitute the pixel driving circuit 21, the signal transmission line 3, the scanning driving circuit 4, the power supply voltage bus 5 and the connecting line 6 in the sub-pixel 2.

[0403] In some examples, such as Fig.12 and Fig.13 As shown, the first light-transmitting layer F1 may include: the first end of the storage capacitor Cst in the plurality of sub-pixels 2 in the display panel 100. The second light-transmitting layer F4 may include: the anode or cathode of the light-emitting device 22 in the plurality of sub-pixels 2 mentioned above.

[0404] Here, if Fig.12 As shown, the storage capacitor Cst is the storage capacitor Cst in the pixel driving circuit 21 in each sub-pixel 2. The second end of the storage capacitor Cst can be arranged in the same layer as the active layer of each transistor in the pixel driving circuit 21, for example.

[0405] Exemplarily, the storage capacitor Cst has a larger orthographic projection area on the substrate 1, and the light-emitting device 22 has a larger orthographic projection area on the substrate 1. The orthographic projection of the storage capacitor Cst on the substrate 1 and the orthographic projection of the light-emitting device 22 on the substrate 1 can at least partially overlap to reduce the occupied area of ​​the sub-pixel 2 on the substrate 1 and achieve a higher PPI.

[0406] The first end of the storage capacitor Cst is located at the first light-transmitting layer F1, which means that the storage capacitor Cst can have a high light transmittance. In this way, when the light-emitting device 22 in the sub-pixel 2 emits light toward the substrate 1, the storage capacitor Cst can avoid blocking the light emitted by the light-emitting device 22.

[0407] In some examples, such as Figure 12-13 , Figure 16-17 and Figure 19 to Figure 22 As shown, the first metal layer F2 may include: control electrodes of transistors in the above-mentioned multiple sub-pixels 2, a power supply voltage bus 5, control electrodes of transistors in the multi-stage shift register 41 of the scan drive circuit 4, and at least one first sub-connection line 61. The second metal layer F3 may include: first electrodes and second electrodes of transistors in the above-mentioned multiple sub-pixels 2, the above-mentioned multiple signal transmission lines 3, first electrodes and second electrodes of transistors in the multi-stage shift register 41 of the scan drive circuit 4, and at least one first sub-connection line 61.

[0408] Exemplarily, the first metal layer F2 may further include: a plurality of gate lines GL electrically connected to the pixel driving circuit 21 of the sub-pixel 2 .

[0409] Since the gate lines GL and the power voltage bus lines 5 both extend along the first direction X, arranging the two on the same layer can simplify the manufacturing process of the display panel 100 and avoid increasing the thickness of the display panel 100 .

[0410] Exemplarily, “the control electrodes of transistors in the plurality of sub-pixels 2” may refer to the control electrodes of the switch transistor T1, the drive transistor T2, and the sense transistor T3 in the pixel drive circuit 21 of each sub-pixel 2. “The first and second electrodes of transistors in the plurality of sub-pixels 2” may refer to the first and second electrodes of the switch transistor T1, the first and second electrodes of the drive transistor T2, and the first and second electrodes of the sense transistor T3 in the pixel drive circuit 21 of each sub-pixel 2.

[0411] Exemplarily, “the control electrodes of transistors in the multi-stage shift register 41” may refer to the control electrodes of multiple transistors included in each stage of the shift register 41. For example, the control electrodes of the first transistor M1 and the second transistor M2 in the first input circuit 4101. “The first electrode and the second electrode of the transistor in the multi-stage shift register 41” may refer to the first electrode and the second electrode of multiple transistors included in each stage of the shift register 41. For example, the first electrode and the second electrode of the first transistor M1 and the first electrode and the second electrode of the second transistor M2 in the first input circuit 4101.

[0412] Here, among the plurality of first sub-connection lines 61 included in the display panel 100, at least one first sub-connection line 61 is located in the first metal layer F2, and at least one first sub-connection line 61 is located in the second metal layer F3. That is, in the case where the display panel 100 only includes the first metal layer F2 and the second metal layer F3, a portion of the plurality of first sub-connection lines 61 may be located in the first metal layer F2, and another portion may be located in the second metal layer F3. Of course, in the case where the display panel 100 also includes other metal layers, at least one of the plurality of first sub-connection lines 61 may also be located in other metal layers, which is not limited in this embodiment.

[0413] When two adjacent first sub-connection lines 61 are located in the same layer, a larger distance is required between the two adjacent first sub-connection lines 61 to avoid short circuit, but this will increase the area occupied by the first sub-connection lines 61 as a whole.

[0414] The present disclosure can reduce the distance between two adjacent first sub-connection lines 61 located in different layers by disposing the above-mentioned multiple first sub-connection lines 61 in different layers, which is beneficial to reducing the area occupied by the multiple first sub-connection lines 61 as a whole, and is beneficial to reducing the size of the fan-out area B1 in the first direction X.

[0415] In some examples, such as Figure 16-17 and Figure 19 to Figure 22 As shown, the display panel 100 includes a first metal layer F2 and a second metal layer F3. The arrangement of the plurality of first sub-connection lines 61 can be: along the first direction X, the first sub-connection lines 61 in the first metal layer F2 and the first sub-connection lines 61 in the second metal layer F3 are alternately arranged in sequence.

[0416] For example, the number of first sub-connection lines 61 in the first metal layer F2 is greater than the number of first sub-connection lines 61 in the second metal layer F3. At this time, in a portion of the first sub-connection lines 61, two adjacent first sub-connection lines 61 may be located in different layers; in another portion of the first sub-connection lines 61, two adjacent first sub-connection lines 61 are located in the same layer.

[0417] This is beneficial to reducing the area occupied by the plurality of first sub-connection lines 61 as a whole, and is beneficial to reducing the size of the fan-out area B1 in the first direction X.

[0418] For another example, the number of first sub-connection lines 61 in the first metal layer F2 is equal to or one less than the number of first sub-connection lines 61 in the second metal layer F3. Figure 16-17 and Figure 19 to Figure 22 As shown, any two adjacent first sub-connection lines 61 may be located in different layers.

[0419] This is beneficial to reducing the distance between any two adjacent first sub-connection lines 61 , and is beneficial to further reducing the area occupied by the plurality of first sub-connection lines 61 as a whole, and further reducing the size of the fan-out area B1 in the first direction X.

[0420] For example, Figure 16-17 and Figure 19 to Figure 22 As shown, the orthographic projections of any two adjacent first sub-connection lines 61 on the substrate 1 do not overlap. That is, the spacing between the orthographic projections of any two adjacent first sub-connection lines 61 on the substrate 1 can be 0, or greater than 0.

[0421] An insulating layer is provided between the first metal layer F2 and the second metal layer F3. When any two adjacent first sub-connection lines 61 are located in different layers, it is easy for the two adjacent first sub-connection lines 61 to form a storage capacitor structure, and thus signal crosstalk is easy to occur during the transmission of data signals or sensing signals.

[0422] The present disclosure sets the orthographic projections of any two adjacent first sub-connection lines 61 on the substrate 1 to have no overlap, which helps to avoid the two adjacent first sub-connection lines 61 from forming a storage capacitor structure, thereby helping to improve signal crosstalk and ensure the accuracy of the transmitted data signal or sensing signal.

[0423] Here, in the case where there is a spacing between the positive projections of any two adjacent first sub-connection lines 61 on the substrate 1, the spacing can be selected and set according to actual needs, so that the area occupied by the multiple first sub-connection lines 61 as a whole is small and any two adjacent first sub-connection lines 61 are avoided from forming a storage capacitor structure.

[0424] Optionally, the spacing between the orthographic projections of any two adjacent first sub-connection lines 61 on the substrate 1 may be greater than or equal to 1 μm. For example, the spacing between the orthographic projections of any two adjacent first sub-connection lines 61 on the substrate 1 may be 1 μm, 1.1 μm, 1.3 μm, 1.35 μm or 1.5 μm, etc.

[0425] There are many configuration positions and arrangement modes for the plurality of second sub-connection lines 62 , and they can be selected and configured according to actual needs.

[0426] In some examples, such as Figure 16-17 and Figure 19 to Figure 22 As shown, the second metal layer F3 further includes: at least one second sub-connection line 62. That is, at least a portion of the plurality of second sub-connection lines 62 included in the display panel 100 and a portion of the first sub-connection lines 62 are located in the same layer.

[0427] Exemplarily, the second metal layer F3 may include one second sub-connection line 62 , two second sub-connection lines 62 , or all second sub-connection lines 62 .

[0428] Since the number of second sub-connection lines 62 is less than the number of first sub-connection lines 61, a second sub-connection line 62 located in the second metal layer F3 may be adjacent to one or two first sub-connection lines 61. The first sub-connection line 61 adjacent to the second sub-connection line 62 may be located in the first metal layer F2 or in the second metal layer F3.

[0429] For example, Figure 16-17 and Figure 19 to Figure 22 As shown, the orthographic projection of the second sub-connection line 62 on the substrate 1 and the orthographic projection of the first sub-connection line 61 on the substrate 1 do not overlap, and there is a spacing between the orthographic projection of the second sub-connection line 62 on the substrate 1 and the orthographic projection of the adjacent first sub-connection line 61 on the substrate 1 .

[0430] This can avoid a short circuit between the second sub-connection line 62 and the adjacent first sub-connection line 61, or avoid the second sub-connection line 62 and the adjacent first sub-connection line 61 forming a storage capacitor structure, which is beneficial to improving signal crosstalk and ensuring the accuracy of the data signal or sensing signal transmitted by the first sub-connection line 61 and the accuracy of the power supply voltage signal transmitted by the second sub-connection line 62.

[0431] It can be understood that, along the direction parallel to the substrate 1, the spacing between the second sub-connection line 62 and the adjacent first sub-connection line 61 located in the second metal layer F3 (that is, the spacing between the orthographic projections of the two on the substrate 1) is greater than the spacing between the second sub-connection line 62 and the adjacent first sub-connection line 61 located in the first metal layer F2 (that is, the spacing between the orthographic projections of the two on the substrate 1).

[0432] Optionally, along the direction parallel to the substrate 1, the spacing between the second sub-connection line 62 and the adjacent first sub-connection line 61 located in the second metal layer F3 may be greater than or equal to 4 μm. For example, the spacing may be 4 μm, 4.15 μm, 4.25 μm, 4.5 μm or 5 μm.

[0433] Optionally, along the direction parallel to the substrate 1, the spacing between the second sub-connection line 62 and the adjacent first sub-connection line 61 located in the first metal layer F2 may be greater than or equal to 1 μm. For example, the spacing may be 1 μm, 1.15 μm, 1.25 μm, 1.5 μm or 2 μm.

[0434] In some other examples, the display panel 100 may further include other metal layers disposed between the second metal layer F3 and the second light-transmitting layer F5 , so as to expand the wiring space of the display panel 100 and reduce the difficulty of wiring.

[0435] At this time, at least a portion of the plurality of second sub-connection lines 62 included in the display panel 100 may also be located in other metal layers. The positional relationship between the second sub-connection lines 62 located in other metal layers and the first sub-connection lines 61 may refer to the description in the above example.

[0436] There are many configuration positions and arrangement modes of the plurality of third sub-connection lines 63 , which can be selected according to actual needs.

[0437] In some examples, such as Figure 16-17 and Figure 19-20 As shown, along the direction parallel to the substrate 1 , at least a portion of the third sub-connection line 63 is located in the gap between two adjacent first sub-connection lines 61 .

[0438] Exemplarily, the plurality of first sub-connection lines 61 included in the display panel 100 may include at least one first sub-connection line group, wherein each first sub-connection line group includes two adjacent first sub-connection lines 61, and there is a gap between the two adjacent first sub-connection lines 61, and the size of the gap in the first direction X is much larger than 1 μm.

[0439] For example, one first sub-connection line group may correspond to one third sub-connection line 63, and part or all of the third sub-connection line 63 is located in the gap in the first sub-connection line group along the direction parallel to the substrate 1. That is, the orthographic projection of the third sub-connection line 63 on the substrate 1 and the orthographic projection of the first sub-connection line group on the substrate 1 may not overlap or may partially overlap.

[0440] This can effectively reduce the facing area between the third sub-connection line 63 and the first sub-connection line group, and further effectively reduce the capacitance of the storage capacitor structure formed between the third sub-connection line 63 and the first sub-connection line group, or avoid the storage capacitor structure formed between the third sub-connection line 63 and the first sub-connection line group.

[0441] Here, the number of the first sub-connection line groups may be equal to the number of the clock signal lines 42 .

[0442] For example, Fig.16 As shown, the clock signal line 42 may include: a first sub-clock signal line CLK_1, a second sub-clock signal line CLK_2 and a third sub-clock signal line CLK_3. Accordingly, the number of the first sub-connection line group may be three.

[0443] For another example, the clock signal line 42 may also include: a fourth sub-clock signal line CLK_4, a fifth sub-clock signal line CLK_5, a sixth sub-clock signal line CLK_6, a seventh sub-clock signal line CLK_7, an eighth sub-clock signal line CLK_8 and a ninth sub-clock signal line CLK_9. Accordingly, the number of the first sub-connection line group may be nine.

[0444] The clock signal line 42 is taken as the first sub-clock signal line CLK_1 as an example, but it is not limited to the first sub-clock signal line CLK_1. Fig.15 As shown, in the data writing stage of the pixel driving circuit 21 in the sub-pixel 2, the level of the first scanning signal transmitted by the first scanning signal terminal G1 is high, and the level of the display data signal transmitted by the data signal terminal Data is high. The first scanning signal is the first output signal output by the corresponding shift register 41. Fig.10 It can be seen from the timing diagram shown that in the third stage 3 and the fourth stage 4, the level of the first clock signal (from the corresponding third sub-connection line 63) transmitted by the first sub-clock signal line CLK_1 and the level of the second clock signal (from the corresponding third sub-connection line 63) transmitted by the fourth sub-clock signal line CLK_4 are both high levels. In the process of data writing, the level of the first clock signal will change from a high level to a low level earlier than the level of the data signal.

[0445] like Fig.14 As shown, if the distance between the positive projections of any two adjacent first sub-connection lines 61 on the substrate 1 is small, the area directly opposite to the third sub-connection line 63 and the adjacent first sub-connection line 61 is large, so that the capacitance of the storage capacitor formed by the third sub-connection line 63 and the adjacent first sub-connection line 61 is large, then in the process of the level of the first clock signal changing from a high level to a low level, based on the bootstrap effect of the storage capacitor, the voltage value of the data signal transmitted from the first sub-connection line 61 to the corresponding data line DL, the data signal terminal Data and the first node G will be reduced. For example, Fig.15 As shown in FIG. 1 , when the level of the first clock signal drops to 10 V, the voltage value of the data signal written to the first node G changes from 3 V to 2.33 V. This may easily cause a poor display phenomenon of vertical dark spots.

[0446] Based on this, the present disclosure sets a first sub-connection line group corresponding to the third sub-connection line 63, and expands the spacing between two adjacent first sub-connection lines 61 in the first sub-connection line group, so that at least a portion of the third sub-connection line 63 is located in the gap between the two adjacent first sub-connection lines 61 in a direction parallel to the substrate 1, which can effectively reduce the area directly facing the third sub-connection line 63 and the two adjacent first sub-connection lines 61, and further effectively reduce the capacitance of the storage capacitor structure formed between the third sub-connection line 63 and the two adjacent first sub-connection lines 61, or avoid the storage capacitor structure formed between the third sub-connection line 63 and the two adjacent first sub-connection lines 61. In this way, the phenomenon that the voltage value of the data signal written to the first node G is reduced due to the decrease in the level of the first clock signal during the data writing stage of the pixel driving circuit 21 can be improved, or even eliminated, thereby improving or even eliminating the poor display phenomenon of vertical dark spots, and improving the display effect of the display panel 100.

[0447] Proven, such as Fig.18 As shown, in this example, in the data writing stage of the pixel driving circuit 21, when the level of the first clock signal drops to 10V, the voltage value of the data signal written to the first node G of the pixel driving circuit 21 is 2.95V. That is, the voltage value of the data signal can be written normally. At this time, the display defect phenomenon of vertical dark spots can be effectively improved or even eliminated.

[0448] In this example, the third sub-connection line 63 may be disposed at a variety of locations, which may be selected according to actual needs.

[0449] For example, Fig.16 and Fig.17 As shown, when the display panel 100 further includes a first light-transmitting layer F1, the first light-transmitting layer F1 may further include: at least one third sub-connecting line 63. That is, part or all of the third sub-connecting lines 63 may be located in the first light-transmitting layer F1.

[0450] Since the first light-transmitting layer F1 and the first metal layer F2 are insulated from each other, the first light-transmitting layer F1 and the second metal layer F3 are also insulated from each other. At this time, along the direction parallel to the substrate 1, the third sub-connection wires 63 may be entirely located in the gaps in the corresponding first sub-connection wire groups, or a portion of the third sub-connection wires 63 may be located in the gaps in the corresponding first sub-connection wire groups.

[0451] Here, when a portion of the third sub-connection line 63 is located in the gap between the corresponding first sub-connection line group (that is, two adjacent first sub-connection lines 61), the orthographic projection of the third sub-connection line 63 on the substrate 1 may partially overlap with the orthographic projection of at least one of the two adjacent first sub-connection lines 61 on the substrate 1.

[0452] For example, the orthographic projection of the third sub-connection line 63 on the substrate 1 may partially overlap with the orthographic projections of the two adjacent first sub-connection lines 61 on the substrate 1. In this case, the area directly facing each other between the third sub-connection line 63 and any one of the two adjacent first sub-connection lines 61 is small, and the capacitance of the storage capacitor structure formed is small, which can effectively improve the poor display phenomenon of the vertical dark spots.

[0453] For another example, the orthographic projection of the third sub-connection line 63 on the substrate 1 may partially overlap with the orthographic projection of one of the two adjacent first sub-connection lines 61 on the substrate 1, thereby reducing the facing area between the third sub-connection line 63 and the first sub-connection line 61, and further reducing the capacitance of the storage capacitor structure formed, which can effectively improve the poor display phenomenon of the above-mentioned vertical dark spots.

[0454] The orthographic projection of the third sub-connection line 63 on the substrate 1 does not overlap with the orthographic projection of the other first sub-connection line 61 of the two adjacent first sub-connection lines 61 on the substrate 1 and has a spacing therebetween. In this way, the third sub-connection line 63 and the other first sub-connection line 61 can be prevented from forming a storage capacitor structure, which can effectively improve the above-mentioned poor display phenomenon of vertical dark spots.

[0455] Optionally, the size of the overlapping portion of the orthographic projection of the third sub-connection line 63 on the substrate 1 and the orthographic projection of one of the two adjacent first sub-connection lines 61 on the substrate 1 in the first direction X is less than or equal to 1 / 5 of the size of the orthographic projection of the first sub-connection line 61 on the substrate 1 in the first direction X. That is, the size of the portion of the first sub-connection line 61 that is directly opposite to the portion of the third sub-connection line 63 in the first direction X is less than or equal to 1 / 5 of the size of the first sub-connection line 61 in the first direction X.

[0456] This can effectively reduce the capacitance of the storage capacitor formed by the third sub-connection line 63 and the adjacent first sub-connection line 61, effectively improve or even eliminate the above-mentioned poor display phenomenon of vertical dark spots, and avoid excessively increasing the distance between the two adjacent first sub-connection lines 61, so that the fan-out area B1 still has a smaller size.

[0457] For example, Fig.19 and Fig. 20 As shown, when the display panel 100 further includes a second metal layer F3, the second metal layer F3 may further include: at least one third sub-connection line 63. That is, part or all of the plurality of third sub-connection lines 63 may be located in the second metal layer F3. When part of the plurality of third sub-connection lines 63 is located in the second metal layer F3, as shown in FIG. Fig.19 and Fig. 20 As shown, the remaining portion of the third sub-connection line 63 may still be located in the first light-transmitting layer F1.

[0458] Since the resistance of the material of the second metal layer F3 is smaller than the resistance of the material of the first light-transmitting layer F1, the third sub-connection line 63 is disposed in the second metal layer F3, so that the size of the third sub-connection line 63 in the first direction X can be reduced. That is, the size of the third sub-connection line 63 located in the second metal layer F3 in the first direction X is smaller than the size of the third sub-connection line 63 located in the first light-transmitting layer F1 in the first direction X.

[0459] This is beneficial for further reducing the facing area between the third sub-connection line 63 and the adjacent first sub-connection line 61, reducing the capacitance of the storage capacitor structure formed by the two, or avoiding overlapping of the positive projections of the third sub-connection line 63 and the adjacent first sub-connection line 61 on the substrate 1, avoiding the two forming a storage capacitor structure, thereby further improving or even eliminating the above-mentioned poor display phenomenon of vertical dark spots, and improving the display effect of the display panel 100.

[0460] For example, Fig.19 and Fig. 20 As shown, the orthographic projection of the third sub-connection line 63 in the second metal layer F3 on the substrate 1 and the orthographic projection of the two adjacent first sub-connection lines 61 on the substrate 1 do not overlap and have a spacing therebetween.

[0461] In this way, the fringe field capacitance formed between the third sub-connection line 63 and the adjacent first sub-connection line 61 can be avoided, thereby further improving or even eliminating the above-mentioned poor display phenomenon of the vertical dark spot, and improving the display effect of the display panel 100 .

[0462] Moreover, since the second metal layer F3 includes the first sub-connection line 61, by setting the positional relationship between the third sub-connection line 63 and the adjacent first sub-connection line 61, the third sub-connection line 63 and the adjacent first sub-connection line 61 located in the second metal layer F3 can be prevented from being short-circuited.

[0463] Here, if Fig.19 and Fig. 20 As shown, in the case where two first sub-connection lines 61 adjacent to the third sub-connection line 63 are respectively located in the first metal layer F2 and the second metal layer F3, the spacing between the orthographic projection of the third sub-connection line 63 on the substrate 1 and the orthographic projection of a first sub-connection line 61 located in the second metal layer F3 on the substrate 1 can, for example, be greater than the spacing between the orthographic projection of the third sub-connection line 63 on the substrate 1 and the orthographic projection of a first sub-connection line 61 located in the first metal layer F2 on the substrate 1.

[0464] In this way, it can ensure that the third sub-connection line 63 and the first sub-connection line 61 located on the first metal layer F2 are staggered, so that the positive projections of the two on the substrate 1 have a certain distance, avoiding the two from forming a storage capacitor structure and having an adverse effect on the data signal transmitted by the first sub-connection line 61. It can also ensure that there is a large distance between the third sub-connection line 63 and the second metal layer F3, avoiding a short circuit between the two, and avoiding the formation of fringe field capacitance between the two, which affects the data signal transmitted by the first sub-connection line 61.

[0465] The spacing between the orthographic projection of the third sub-connection line 63 on the substrate 1 and the orthographic projection of a first sub-connection line 61 located in the second metal layer F3 on the substrate 1 can be set according to actual needs. The spacing between the orthographic projection of the third sub-connection line 63 on the substrate 1 and the orthographic projection of a first sub-connection line 61 located in the first metal layer F2 on the substrate 1 can be set according to actual needs.

[0466] Optionally, the distance between the orthographic projection of the third sub-connection line 63 on the substrate 1 and the orthographic projection of a first sub-connection line 61 located on the second metal layer F3 on the substrate 1 is greater than or equal to 4 μm. For example, the distance may be 4 μm, 4.11 μm, 4.24 μm, 4.78 μm or 5.1 μm, etc.

[0467] Optionally, the spacing between the orthographic projection of the third sub-connection line 63 on the substrate 1 and the orthographic projection of a first sub-connection line 61 located in the first metal layer F2 on the substrate 1 is greater than or equal to 1 μm. For example, the spacing may be 1 μm, 1.11 μm, 1.24 μm, 1.78 μm or 1.2 μm, etc.

[0468] In this example, the size of the second sub-connection line 62 in the first direction X is 1.5 to 2.5 times the size of the first sub-connection line 61 in the first direction X.

[0469] It should be noted that the size of each second sub-connection line 62 in the first direction X is generally designed to be 3 to 5 times the size of the first sub-connection line 61 in the first direction X to ensure a good transmission effect of the power supply voltage signal.

[0470] The present disclosure sets the size of at least one second sub-connection line 62 in the first direction X to 1.5 to 2.5 times the size of the first sub-connection line 61 in the first direction X, that is, by compressing the size of at least one second sub-connection line 62 in the first direction X, the area occupied by the plurality of second sub-connection lines 62 in the fan-out area B1 can be reduced, and the spacing between two adjacent first sub-connection lines 61 in at least one first sub-connection line group can be enlarged, and the area directly facing the third sub-connection line 63 and the two adjacent first sub-connection lines 61 can be reduced. In this way, it is possible to avoid increasing the size of the fan-out area B1 in the first direction X, and to avoid affecting the accuracy of data signal transmission by the two first sub-connection lines 61 adjacent to the third sub-connection line 63, thereby improving or eliminating the poor display phenomenon of vertical dark spots.

[0471] In other examples, such as Fig.21 and Fig. 22 As shown, the second light-transmitting layer F4 may further include: at least one third sub-connection line 63. That is, part or all of the plurality of third sub-connection lines 63 may be located in the second light-transmitting layer F4. In the case where part of the plurality of third sub-connection lines 63 are located in the second light-transmitting layer F4, the remaining third sub-connection lines 63 may still be located in the first light-transmitting layer F1.

[0472] For example, Fig. 22 As shown, along the direction perpendicular to the substrate 1 , the distance between the first light-transmitting layer F1 and the second metal layer F3 is smaller than the distance between the second metal layer F3 and the second light-transmitting layer F4 .

[0473] Here, along the direction perpendicular to the substrate 1, the pattern in the first metal layer F2 is disposed between a portion of the first light-transmitting layer F1 and the second metal layer F3, and the pattern in the first metal layer F2 is not disposed between the other portions. "The spacing between the first light-transmitting layer F1 and the second metal layer F3" may refer to the spacing between the first light-transmitting layer F1 and the other portions of the second metal layer F3.

[0474] By arranging the third sub-connection line 63 in the second light-transmitting layer F4, the distance between the third sub-connection line 63 and the second metal layer F3 can be increased, that is, the distance between the third sub-connection line 63 and the first sub-connection line 61 located in the second metal layer F3 can be increased. In this way, when the third sub-connection line 63 and the first sub-connection line 61 located in the second metal layer F3 form a storage capacitor structure, the capacitance of the storage capacitor structure can be effectively reduced.

[0475] In addition, it can be understood that the first metal layer F2 is located between the first light-transmitting layer F1 and the second metal layer F3, and the distance between the first light-transmitting layer F1 and the first metal layer F2 is smaller than the distance between the first metal layer F2 and the second light-transmitting layer F4. By arranging the third sub-connection line 63 in the second light-transmitting layer F4, the distance between the third sub-connection line 63 and the first metal layer F2 can be increased, that is, the distance between the third sub-connection line 63 and the first sub-connection line 61 located in the first metal layer F2 can be increased. In this way, when the third sub-connection line 63 and the first sub-connection line 61 located in the first metal layer F2 form a storage capacitor structure, the capacitance of the storage capacitor structure can be effectively reduced.

[0476] The present disclosure can effectively reduce the capacitance of the storage capacitor structure formed by the third sub-connection line 63 and the first sub-connection line 61 located in the first metal layer F2 by setting the third sub-connection line 63 in the second light-transmitting layer F4, and can effectively reduce the capacitance of the storage capacitor structure formed by the third sub-connection line 63 and the first sub-connection line 61 located in the second metal layer F3. In this way, during the data writing stage of the pixel driving circuit 21, the influence of the storage capacitor structure on the transmission of the data signal can be weakened, and the phenomenon that the voltage value of the data signal written to the first node G is reduced due to the decrease in the level of the first clock signal during the data writing stage of the pixel driving circuit 21 is improved or even eliminated, thereby improving or even eliminating the poor display phenomenon of vertical dark spots, and improving the display effect of the display panel 100.

[0477] Proven, such as Fig.23 As shown, in this example, in the data writing stage of the pixel driving circuit 21, when the level of the first clock signal drops to 10V, the voltage value of the data signal written to the first node G of the pixel driving circuit 21 is 2.85V. That is, the voltage value of the data signal can be written normally. At this time, the poor display phenomenon of vertical dark spots can be effectively improved or even eliminated.

[0478] An insulating material is disposed between the first light-transmitting layer F1 and the second metal layer F3, and an insulating material is disposed between the second metal layer F3 and the second light-transmitting layer F4. The spacing between the first light-transmitting layer F1 and the second metal layer F3 can be determined according to the insulating material therebetween, and the spacing between the second metal layer F3 and the second light-transmitting layer F4 can be determined according to the insulating material therebetween.

[0479] For example, Fig. 22 As shown, the display panel 100 further includes: a buffer layer F5 and a gate insulating layer F6 which are disposed between the first light-transmitting layer F1 and the second metal layer F4 and are sequentially stacked.

[0480] A plurality of patterns of the first metal layer F2 are disposed between a portion of the buffer layer F5 and a portion of the gate insulating layer F6, and another portion of the buffer layer F5 is in direct contact with another portion of the gate insulating layer F6. The spacing between the first light-transmitting layer F1 and the second metal layer F3 is, for example, the sum of the thicknesses of another portion of the buffer layer F5 and another portion of the gate insulating layer F6.

[0481] It should be noted that the material of the buffer layer F5 is an inorganic material, such as silicon dioxide and / or silicon nitride. The material of the gate insulating layer F6 is an inorganic material, such as silicon dioxide and / or silicon nitride. In the process of preparing the buffer layer F5 and the gate insulating layer F6, for example, PECVD (Plasma Enhanced Chemical Vapor Deposition) process can be used to form them. Based on this, the buffer layer F5 and the gate insulating layer F6 are both thin films with relatively uniform thickness, and the thickness of the two is relatively small.

[0482] For example, Fig. 22 As shown, the display panel 100 further includes a passivation layer F7 and a planarization layer F8 disposed between the second metal layer F3 and the second light-transmitting layer F4.

[0483] It should be noted that the material of the passivation layer F7 is an inorganic material, such as silicon nitride, etc. In the process of preparing and forming the passivation layer F7, for example, a PECVD process can be used to form it. Based on this, the passivation layer F7 is a thin film with a relatively uniform thickness and a small thickness.

[0484] The material of the flat layer F8 is an organic material, such as polyimide or an organic resin material. In the process of preparing and forming the flat layer F8, for example, a coating process (such as a spin coating process, a spray coating process or a spot coating process, etc.) can be used to form it. Based on this, the surface of the flat layer F8 on the side away from the substrate 1 is a relatively flat surface, and the flat layer F8 is a thin film with non-uniform thickness. Among them, the thickness of the flat layer F8 can refer to the average thickness of the flat layer F8, for example. Among them, the thickness of the flat layer F8 is relatively large, and the thickness of the flat layer F8 is greater than the thickness of any one of the buffer layer F5, the gate insulating layer F6 and the passivation layer F7.

[0485] For example, the sum of the thicknesses of the buffer layer F5 and the gate insulating layer F6 is less than the sum of the thicknesses of the passivation layer F7 and the planar layer F8. In other words, the spacing between the first light-transmitting layer F1 and the second metal layer F3 is less than the spacing between the second metal layer F3 and the second light-transmitting layer F4.

[0486] In this way, after the third sub-connection line 63 is set in the second light-transmitting layer F4, the passivation layer F7 and the flat layer F8 can be used to increase the distance between the third sub-connection line 63 and the second metal layer F3, and increase the distance between the third sub-connection line 63 and the first metal layer F2, which is beneficial to reduce the capacitance of the storage capacitor structure formed by the third sub-connection line 63 and the first sub-connection line 61 located in the second metal layer F3, and reduce the capacitance of the storage capacitor structure formed by the third sub-connection line 63 and the first sub-connection line 61 located in the first metal layer F2, which is beneficial to weaken the influence of the clock signal transmitted by the third sub-connection line 63 on the data signal transmitted by the first sub-connection line 61, and improve or even eliminate the poor display phenomenon of vertical dark spots.

[0487] Exemplarily, the sum of the thicknesses of the passivation layer F7 and the planarization layer F8 is greater than or equal to twice the sum of the thicknesses of the buffer layer F5 and the gate insulating layer F6 .

[0488] For example, when the third sub-connection line 63 is disposed in the first light-transmitting layer F1, the capacitance of the storage capacitor structure formed by the third sub-connection line 63 and the first sub-connection line 61 located in the second metal layer F3 is C 1 After the third sub-connection line 63 is disposed in the second light-transmitting layer F4, the capacitance of the storage capacitor structure formed by the third sub-connection line 63 and the first sub-connection line 61 located in the second metal layer F3 is C 2 .

[0489] in,

[0490] That is, after the third sub-connection line 63 is disposed in the second light-transmitting layer F4, the capacitance of the storage capacitor structure formed by the third sub-connection line 63 and the first sub-connection line 61 located in the second metal layer F3 can be reduced to at least 1 / 2 of the original capacitance.

[0491] Since the first metal layer F2 is located between the first light-transmitting layer F1 and the second metal layer F3, after the third sub-connection line 63 is set in the second light-transmitting layer F4, the capacitance of the storage capacitor structure formed by the third sub-connection line 63 and the first sub-connection line 61 located in the first metal layer F2 can be reduced further.

[0492] This effectively reduces the capacitance of the storage capacitor structure formed by the third sub-connection line 63 and the first sub-connection line 61, thereby effectively weakening the influence of the clock signal transmitted by the third sub-connection line 63 on the data signal transmitted by the first sub-connection line 61, thereby improving or even eliminating the poor display phenomenon of vertical dark spots.

[0493] Optionally, the thickness of the buffer layer F5 may range from For example, the thickness of the buffer layer F5 can be or wait.

[0494] Optionally, the thickness of the gate insulating layer F6 may range from For example, the thickness of the gate insulating layer F6 may be or wait.

[0495] Optionally, the thickness of the passivation layer F7 may range from For example, the thickness of the passivation layer F7 may be or wait.

[0496] Optionally, the thickness of the flat layer F8 is greater than or equal to For example, the thickness of the flat layer F8 may be or wait.

[0497] In this example, the size of the second sub-connection line 62 in the first direction X is 3 to 5 times the size of the first sub-connection line 61 in the first direction X.

[0498] After the size of each second sub-connection line 62 in the first direction X is set to 3 to 5 times the size of the first sub-connection line 61 in the first direction X, the spacing between two adjacent first sub-connection lines 61 may not be adjusted, so that the spacing between any two adjacent first sub-connection lines 61 is equal or substantially equal. This can not only avoid increasing the size of the fan-out area B1 in the first direction X, avoid increasing the difficulty of the wiring design of the display panel 100, but also ensure that the second sub-connection line 62 can transmit the power supply voltage signal well.

[0499] At this time, the third sub-connection line 63 may be disposed opposite to at least one first sub-connection line 61 , for example.

[0500] The present disclosure can effectively increase the distance between the third sub-connection line 63 and the first sub-connection line 61 by arranging the third sub-connection line 63 on the second transparent layer F4, effectively reduce the capacitance of the storage capacitor structure formed by the third sub-connection line 63 and the first sub-connection line 61, and weaken the influence of the third sub-connection line 63 on the transmission of data signals of the first sub-connection line 61. In this way, the display defect phenomenon of vertical dark spots can be improved or even eliminated on the basis of avoiding adjusting the first sub-connection line 61 and the second sub-connection line 62.

[0501] In some other examples, such as Figure 16-17 and Figure 19-20 As shown, at least one third sub-connection line 63 is not located in the second metal layer F3. The orthographic projection of the third sub-connection line 63 on the substrate 1 partially overlaps with the orthographic projection of the second sub-connection line 62 on the substrate 1.

[0502] For example, the third sub-connection line 63 may be located in the first light-transmitting layer F1 or the second light-transmitting layer F4. The size of the third sub-connection line 63 in the first direction X and the size of the second sub-connection line 62 in the first direction X may be equal or unequal.

[0503] Here, in the process of transmitting the clock signal, the third sub-connection line 63 has little influence on the transmission of the power supply voltage signal by the second sub-connection line 62 .

[0504] By setting the positional relationship between the third sub-connection line 63 and the second connection line 62 that are not located in the second metal layer F3, it is possible to avoid a short circuit between the third sub-connection line 63 and the second connection line 62, and to set the third sub-connection line 63 and the second connection line 62 in the gap of the same first sub-connection line group (including two adjacent first sub-connection lines 61 with a gap), thereby avoiding the third sub-connection line 63 and more first sub-connection lines 61 from forming a storage capacitor structure.

[0505] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be thought of by any person skilled in the art within the technical scope disclosed in the present disclosure should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.< / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A display panel, characterized in that: The display panel has a display area and a fan-out area located on one side of the display area; the display panel includes: substrate; A plurality of sub-pixels and a plurality of signal transmission lines are located in the display area; the plurality of sub-pixels are arranged into a plurality of rows along a first direction and into a plurality of columns along a second direction; a signal transmission line is electrically connected to at least one column of sub-pixels; A scanning driving circuit, comprising a multi-stage shift register and a plurality of clock signal lines located in the display area; A power supply voltage bus located in the fan-out region extends along the first direction; and The plurality of connection lines located in the fan-out region are located on the same side of the substrate as the plurality of sub-pixels, the plurality of signal transmission lines, the scan drive circuit and the power supply voltage bus; the plurality of connection lines extend along the second direction and are located on a side of the power supply voltage bus away from the plurality of sub-pixels; Wherein, the plurality of connection lines include: a plurality of first sub-connection lines, a plurality of second sub-connection lines and a plurality of third sub-connection lines; A first sub-connection line is electrically connected to the signal transmission line, a second sub-connection line is electrically connected to the power supply voltage bus, and a third sub-connection line is electrically connected to a clock signal line; Wherein, along a direction parallel to the substrate, at least a portion of the third sub-connection line is located in a gap between two adjacent first sub-connection lines; The orthographic projection of the third sub-connection line on the substrate partially overlaps or does not overlap with the orthographic projection of at least one of the two adjacent first sub-connection lines on the substrate.

2. The display panel according to claim 1, characterized in that: The display panel comprises: a first light-transmitting layer, a first metal layer, a second metal layer and a second light-transmitting layer which are stacked in sequence; The first light-transmitting layer includes: first terminals of storage capacitors in the plurality of sub-pixels; The first metal layer includes: control electrodes of transistors in the plurality of sub-pixels, the power supply voltage bus, control electrodes of transistors in the multi-stage shift register, and at least one of the first sub-connection lines; The second metal layer includes: the first and second electrodes of the transistors in the plurality of sub-pixels, the plurality of signal transmission lines, the first and second electrodes of the transistors in the multi-stage shift register, and at least one of the first sub-connection lines; The second light-transmitting layer includes: an anode or a cathode of the light-emitting device in the plurality of sub-pixels.

3. The display panel according to claim 2, characterized in that: The first light-transmitting layer further includes: at least one third sub-connecting line.

4. The display panel according to claim 1, characterized in that: The size in the first direction of the overlapping part of the orthographic projection of the third sub-connection line on the substrate and the orthographic projection of one of the two adjacent first sub-connection lines on the substrate is less than or equal to 1 / 5 of the size in the first direction of the orthographic projection of the first sub-connection line on the substrate.

5. The display panel according to claim 2, characterized in that: The second metal layer further includes: at least one third sub-connection line; The orthographic projection of the third sub-connection line on the substrate and the orthographic projections of the two adjacent first sub-connection lines on the substrate do not overlap and have a spacing therebetween.

6. The display panel according to claim 5, characterized in that: In the case where the two adjacent first sub-connection lines are located in the first metal layer and the second metal layer respectively, The distance between the orthographic projection of the third sub-connection line on the substrate and the orthographic projection of a first sub-connection line located in the second metal layer on the substrate is greater than the distance between the orthographic projection of the third sub-connection line on the substrate and the orthographic projection of a first sub-connection line located in the first metal layer on the substrate.

7. The display panel according to claim 6, characterized in that: A distance between an orthographic projection of the third sub-connection line on the substrate and an orthographic projection of a first sub-connection line located on the second metal layer on the substrate is greater than or equal to 4 μm; A distance between an orthographic projection of the third sub-connection line on the substrate and an orthographic projection of a first sub-connection line located in the first metal layer on the substrate is greater than or equal to 1 μm.

8. The display panel according to claim 1, characterized in that: A size of the second sub-connection line in the first direction is 1.5 to 2.5 times a size of the first sub-connection line in the first direction.

9. The display panel according to claim 2, characterized in that: The second light-transmitting layer further includes: at least one third sub-connecting line; Along a direction perpendicular to the substrate, a distance between the first light-transmitting layer and the second metal layer is smaller than a distance between the second metal layer and the second light-transmitting layer.

10. The display panel according to claim 9, characterized in that: The display panel further includes: a buffer layer and a gate insulating layer which are disposed between the first light-transmitting layer and the second metal layer and are stacked in sequence; and A passivation layer and a planarization layer disposed between the second metal layer and the second light-transmitting layer; The sum of the thicknesses of the buffer layer and the gate insulation layer is smaller than the sum of the thicknesses of the passivation layer and the planarization layer.

11. The display panel according to claim 10, characterized in that: The sum of the thicknesses of the passivation layer and the planarization layer is greater than or equal to twice the sum of the thicknesses of the buffer layer and the gate insulation layer.

12. The display panel according to claim 9, characterized in that: A size of the second sub-connection line in the first direction is 3 to 5 times a size of the first sub-connection line in the first direction.

13. The display panel according to any one of claims 2 to 12, characterized in that: In the case where the display panel further includes a first metal layer and a second metal layer, Along the first direction, the first sub-connection lines in the first metal layer and the first sub-connection lines in the second metal layer are alternately arranged in sequence.

14. The display panel according to claim 13, characterized in that: The orthographic projections of any two adjacent first sub-connection lines on the substrate do not overlap.

15. The display panel according to claim 13, characterized in that: The second metal layer further includes: at least one second sub-connection line; The orthographic projection of the second sub-connection line on the substrate has no overlap with the orthographic projections of the plurality of first sub-connection lines on the substrate, and there is a spacing between the orthographic projection of the second sub-connection line on the substrate and the orthographic projection of the adjacent first sub-connection line on the substrate.

16. The display panel according to claim 15, characterized in that: At least one of the third sub-connection lines is not located in the second metal layer; An orthographic projection of the third sub-connection line on the substrate partially overlaps with an orthographic projection of the second sub-connection line on the substrate.

17. The display panel according to any one of claims 1 to 12, characterized in that: The plurality of signal transmission lines include a plurality of data lines and a plurality of sensing lines, and the plurality of first sub-connection lines include a plurality of data connection lines and a plurality of sensing connection lines; A data connection line is electrically connected to a data line, and a sensing connection line is electrically connected to a sensing line; At least two data connection lines are arranged between any two adjacent sensing connection lines.

18. The display panel according to any one of claims 1 to 12, characterized in that: A first-level shift register is electrically connected to at least one row of sub-pixels; The shift register comprises a plurality of device groups, one device group being located in a region between two adjacent sub-pixels in the at least one row of sub-pixels; the device group comprises at least one transistor and / or at least one capacitor; A clock signal line is electrically connected to at least one stage of shift register; the clock signal line is located between two adjacent columns of sub-pixels.

19. A display device, characterized in that: The display device comprises: a display panel according to any one of claims 1 to 18.

Images