cache, data processing system, method, computer device and storage medium

Abstract

The application relates to a cache, a data processing system, a method, a computer device, a storage medium and a computer program product. The cache comprises a controller, an address memory and a data memory. The controller is used for parsing an access instruction, obtaining a target tag value, entry index information and data address information, reading a saved tag value from a register in the case that the target tag value meets a first preset condition, reading data from an address corresponding to the saved tag value in the data memory in the case that the target tag value is the same as the saved tag value, and feeding back the read data, reading a first tag value and a second tag value in sequence according to the entry index information in the case that the target tag value does not meet the first preset condition, reading data from an address corresponding to the data address information in the data memory, and feeding back the read data in the case that the same tag value as the target tag value exists in the first tag value and the second tag value. The system can reduce the performance loss of a processor.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a cache, data processing system, method, computer device, storage medium, and computer program product. Background Technology

[0002] With the development of computer technology, various types of processors have emerged, such as CPUs (Central Processing Units). Before the processor starts working, the necessary data is temporarily stored in the processor's cache, such as a cache. Then, when working, the corresponding data is read from the cache and processed.

[0003] In traditional technology, a cache consists of a TAG (Tag memory, storing addresses) and a DATA (Data memory, storing data). The TAG stores addresses, and the DATA stores data. When reading data, the processor typically first compares the access address in the read request with the address in the TAG. If the access address matches the address in the TAG, the corresponding data is then read from the DATA and returned to the processor. However, the need to check the processor's access address against the address in the TAG before each data read causes a delay in data reading, resulting in a performance penalty for the processor. Summary of the Invention

[0004] Therefore, it is necessary to provide a cache, data processing system, method, computer device, computer-readable storage medium, and computer program product that can reduce processor performance loss in response to the above-mentioned technical problems.

[0005] In a first aspect, this application provides a cache. The cache includes: a controller, an address memory, and a data memory, wherein the address memory includes registers and at least one way, and the way includes multiple entries, each entry storing tag values ​​for two consecutive cache lines;

[0006] The controller is configured to receive and parse access instructions to obtain target tag values, entry index information, and data address information. If the target tag value meets a first preset condition, it reads a stored tag value from the register. If the target tag value is the same as the stored tag value, it reads data from the address corresponding to the stored tag value in the data memory and feeds back the read data. If the target tag value does not meet the first preset condition, it reads consecutive first and second tag values ​​according to the entry index information and reads data from the address corresponding to the data address information in the data memory. If there is a tag value in the first and second tags that is the same as the target tag value, it feeds back the read data and stores the tag values ​​in the first and second tags that are different from the target tag value into the register.

[0007] In one embodiment, the controller is further configured to, when the target tag value is different from the stored tag value, read consecutive third and fourth tag values ​​according to the entry index information, and read data from the address corresponding to the data address information in the data memory; if there is a tag value in the third and fourth tag values ​​that is the same as the target tag value, feed back the read data, and store the tag values ​​in the third and fourth tag values ​​that are different from the target tag value into the register.

[0008] In one embodiment, the controller is further configured to read data from the address corresponding to the target tag value in the target memory and to feed back the read data if there is no tag value identical to the target tag value among the third tag value and the fourth tag value.

[0009] In one embodiment, the controller is further configured to read data from the address corresponding to the target tag value in the target memory and to report the read data if there is no tag value identical to the target tag value among the first tag value and the second tag value.

[0010] In one embodiment, each entry also stores a status identifier corresponding to the tag value; the status identifier is used to indicate whether the corresponding tag value is valid.

[0011] The controller is further configured to, when the target tag value does not meet the first preset condition, read the status identifier corresponding to the first tag value and the status identifier corresponding to the second tag value according to the entry index information, and determine that there is a tag value that is the same as the target tag value among the first tag value and the second tag value when both the status identifier corresponding to the first tag value and the status identifier corresponding to the second tag value are valid.

[0012] Secondly, this application provides a data processing system. The system includes: a processor and a cache as described in any embodiment of the first aspect;

[0013] The processor is used to send access instructions to the cache;

[0014] The processor is also configured to receive data returned by the cache based on the access instruction.

[0015] Thirdly, this application provides a data processing method. The method includes:

[0016] Receive and parse the access command to obtain the target tag value, entry index information, and data address information;

[0017] If the target tag value meets the first preset condition, the stored tag value is read from the register; if the target tag value is the same as the stored tag value, data is read from the address corresponding to the stored tag value in the data memory, and the read data is fed back.

[0018] If the target tag value does not meet the first preset condition, the first tag value and the second tag value are read consecutively according to the entry index information, and data is read from the address corresponding to the data address information in the data memory. If there is a tag value in the first tag value and the second tag value that is the same as the target tag value, the read data is fed back, and the tag values ​​in the first tag value and the second tag value that are different from the target tag value are stored in the register.

[0019] In one embodiment, after reading the stored tag value from the register when the target tag value meets a first preset condition, the method further includes:

[0020] If the target tag value is different from the saved tag value, the third and fourth consecutive tag values ​​are read according to the entry index information, and the data is read from the address corresponding to the data address information in the data storage.

[0021] If there is a tag value in the third tag value and the fourth tag value that is the same as the target tag value, the read data is fed back, and the tag values ​​in the third tag value and the fourth tag value that are different from the target tag value are stored in the register.

[0022] In one embodiment, after reading consecutive third and fourth tag values ​​according to the entry index information and reading data from the address corresponding to the data address information in the data memory, the method further includes:

[0023] If there is no tag value in the third tag value and the fourth tag value that is the same as the target tag value, data is read from the address corresponding to the target tag value in the target memory, and the read data is fed back.

[0024] In one embodiment, after reading consecutive first tag values ​​and second tag values ​​according to the entry index information, and reading data from the address corresponding to the data address information in the data memory, the method further includes:

[0025] If there is no tag value that is the same as the target tag value among the first tag value and the second tag value, data is read from the address corresponding to the target tag value in the target memory, and the read data is fed back.

[0026] In one embodiment, the method further includes:

[0027] If the target tag value does not meet the first preset condition, the status identifier corresponding to the first tag value and the status identifier corresponding to the second tag value are read according to the entry index information; the status identifier is used to indicate whether the corresponding tag value is valid.

[0028] If both the status identifier corresponding to the first tag value and the status identifier corresponding to the second tag value are valid, it is determined that there is a tag value among the first tag value and the second tag value that is the same as the target tag value.

[0029] Fourthly, this application also provides a computer device. The computer device includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program to perform the following steps:

[0030] Receive and parse the access command to obtain the target tag value, entry index information, and data address information;

[0031] If the target tag value meets the first preset condition, the stored tag value is read from the register; if the target tag value is the same as the stored tag value, data is read from the address corresponding to the stored tag value in the data memory, and the read data is fed back.

[0032] If the target tag value does not meet the first preset condition, the first tag value and the second tag value are read consecutively according to the entry index information, and data is read from the address corresponding to the data address information in the data memory. If there is a tag value in the first tag value and the second tag value that is the same as the target tag value, the read data is fed back, and the tag values ​​in the first tag value and the second tag value that are different from the target tag value are stored in the register.

[0033] Fifthly, this application also provides a computer-readable storage medium. The computer-readable storage medium stores a computer program thereon, which, when executed by a processor, performs the following steps:

[0034] Receive and parse the access command to obtain the target tag value, entry index information, and data address information;

[0035] If the target tag value meets the first preset condition, the stored tag value is read from the register; if the target tag value is the same as the stored tag value, data is read from the address corresponding to the stored tag value in the data memory, and the read data is fed back.

[0036] If the target tag value does not meet the first preset condition, the first tag value and the second tag value are read consecutively according to the entry index information, and data is read from the address corresponding to the data address information in the data memory. If there is a tag value in the first tag value and the second tag value that is the same as the target tag value, the read data is fed back, and the tag values ​​in the first tag value and the second tag value that are different from the target tag value are stored in the register.

[0037] Sixthly, this application also provides a computer program product. The computer program product includes a computer program that, when executed by a processor, performs the following steps:

[0038] Receive and parse the access command to obtain the target tag value, entry index information, and data address information;

[0039] If the target tag value meets the first preset condition, the stored tag value is read from the register; if the target tag value is the same as the stored tag value, data is read from the address corresponding to the stored tag value in the data memory, and the read data is fed back.

[0040] If the target tag value does not meet the first preset condition, the first tag value and the second tag value are read consecutively according to the entry index information, and data is read from the address corresponding to the data address information in the data memory. If there is a tag value in the first tag value and the second tag value that is the same as the target tag value, the read data is fed back, and the tag values ​​in the first tag value and the second tag value that are different from the target tag value are stored in the register.

[0041] The aforementioned cache, data processing system, method, computer device, storage medium, and computer program product, wherein the cache includes: a controller, an address memory, and a data memory; the address memory includes a register and at least one way; each way includes multiple entries, and each entry stores tag values ​​for two consecutive cache lines; the controller is configured to receive and parse access instructions to obtain a target tag value, entry index information, and data address information; if the target tag value meets a first preset condition, it reads the stored tag value from the register; if the target tag value is the same as the stored tag value, it reads data from the data memory at the data address corresponding to the stored tag value and feeds back the read data; if the target tag value does not meet the first preset condition, it reads consecutive first tag values ​​and second tag values ​​according to the entry index information, and reads data from the data memory at the address corresponding to the data address information; if there is a tag value in the first tag value and second tag value that is the same as the target tag value, it feeds back the read data; and stores the tag values ​​in the first tag value and second tag value that are different from the target tag value in the register. In this way, when the target tag value in the received access instruction does not meet the first preset condition, the controller in the cache reads consecutive first tag values ​​and second tag values ​​from the address memory according to the entry index information, and at the same time reads data from the address corresponding to the data address information in the data memory. This is beneficial because if there is a tag value in the first tag value and second tag value that is the same as the target tag value in the access instruction, the read data can be returned directly without causing data reading delay, avoiding processor performance loss, and thus improving processor performance. Furthermore, based on the entry index information, consecutive first tag values ​​and second tag values ​​are read from the address memory, and tag values ​​that are different from the target tag value are stored in a register. This allows the stored tag value to be read directly from the register when the target tag value meets the first preset condition, and to read data from the address corresponding to the stored tag value when the target tag value is the same as the stored tag value. The read data is then returned. This eliminates the need to read consecutive first tag values ​​and second tag values ​​from the address memory and read data from the address corresponding to the data address information simultaneously. This avoids the drawback of high power consumption during data access when it is unclear whether there is a tag value in the first and second tags that is the same as the target tag value. Thus, the goal of improving processor performance while reducing power consumption is achieved. Attached Figure Description

[0042] Figure 1 Here is a block diagram of the cache structure in one embodiment;

[0043] Figure 2 Here is a block diagram of the cache structure in another embodiment;

[0044] Figure 3 This is a flowchart illustrating a data processing method in one embodiment;

[0045] Figure 4 This is a flowchart illustrating the data return step in one embodiment;

[0046] Figure 5 This is a flowchart illustrating the data processing method in another embodiment;

[0047] Figure 6 This is a flowchart illustrating the data processing method in yet another embodiment;

[0048] Figure 7 This is a block diagram of the data processing system in one embodiment;

[0049] Figure 8 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0050] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0051] In one embodiment, such as Figure 1As shown, a cache is provided, comprising: a controller 101, an address memory 102, and a data memory 103. The address memory 102 includes a register and at least one way. Each way includes multiple entries, and each entry stores tag values ​​for two consecutive cache lines. The controller 101 is configured to receive and parse access instructions to obtain a target tag value, entry index information, and data address information. If the target tag value meets a first preset condition, the controller reads the stored tag value from the register. If the target tag value is the same as the stored tag value, the controller reads data from the address corresponding to the stored tag value in the data memory 103 and feeds back the read data. If the target tag value does not meet the first preset condition, the controller reads consecutive first and second tag values ​​according to the entry index information and reads data from the address corresponding to the data address information in the data memory 103. If there is a tag value in the first and second tag values ​​that is the same as the target tag value, the controller feeds back the read data and stores the tag values ​​in the first and second tag values ​​that are different from the target tag value in the register.

[0052] Here, cache refers to a high-speed cache that includes controller 101, address memory 102 and data memory 103.

[0053] The controller 101 is used to parse the access instruction, read the corresponding tag value from the address memory 102, and read the corresponding data from the data memory 103.

[0054] Address memory 102 refers to an improved TAG memory used to store addresses. Address memory 102 includes a register and at least one way. The register stores a tag value, such as a reference. Figure 2 The register is used to store the (n+1)th tag value: TAG(n+1), where n is an even number greater than or equal to 0. When the controller 101 reads the nth tag value from the address memory 102, it also reads the (n+1)th tag value and stores it in the register, so that the register can store the (n+1)th tag value TAG(n+1) and the corresponding VLD value VLD(n+1). For example, refer to... Figure 2 When the controller 101 reads the tag value (such as TAG2) of the second cache line, it will also read the tag value (such as TAG3) of the third cache line and store TAG3 in the register so as to save TAG3 and VLD3 through the register.

[0055] The tag value refers to the storage address, which consists of multiple binary digits, such as 10000100000010000111000. It should be noted that if the value of the first binary digit in the tag value is 0, it means that the decimal number corresponding to the tag value is even; if the value of the first binary digit in the tag value is 1, it means that the decimal number corresponding to the tag value is odd.

[0056] Here, "entry" refers to an item, and each entry consists of two consecutive cache lines. A cache line is a data unit; each cache line stores a vld value and a tag value. The vld value indicates whether the corresponding tag value is valid; for example, a vld value of 1 indicates that the corresponding tag value is valid, and a vld value of 0 indicates that the corresponding tag value is invalid. For example, see reference... Figure 2 The second entry includes the cache lines containing VLD2 and TAG2, as well as the cache lines containing VLD3 and TAG3.

[0057] Each entry stores the tag values ​​of two consecutive cache lines. The address identifier (e.g., number) corresponding to the tag value in the left cache line is even, and the address identifier corresponding to the tag value in the right cache line is odd, and the address identifiers corresponding to these two tag values ​​are consecutive. For example, see reference... Figure 2 In the first entry, the tag value of the left cache line is TAG0, and the address identifier corresponding to TAG0 is 0; the tag value of the right cache line is TAG1, and the address identifier corresponding to TAG1 is 1. In the second entry, the tag value of the left cache line is TAG2, and the address identifier corresponding to TAG2 is 2; the tag value of the right cache line is TAG3, and the address identifier corresponding to TAG3 is 3. Of course, the address identifier corresponding to the tag value of the left cache line can also be odd, and the address identifier corresponding to the tag value of the right cache line can also be even; this application does not impose specific limitations here.

[0058] Here, "way" refers to a storage unit, and each storage unit includes multiple entries, such as... Figure 2 In this context, WAY0 includes (n+2) / 2 entries.

[0059] Here, data memory 103 refers to the DATA memory used for storing data. Data memory 103 stores data that corresponds one-to-one with each tag value in address memory 102; for example, reference... Figure 2 The data corresponding to TAG0 is DATA0, the data corresponding to TAG1 is DATA1, and so on, the data corresponding to TAGn is DATAn.

[0060] It should be noted that the cache in this application refers to an improved cache located inside the chip where the processor resides. In conventional technology, the TAG memory in the cache does not include a register for storing the tag value TAG(n+1) of the (n+1)th cache line, and each entry in the TAG memory only includes the tag value of one cache line, for example, the first entry includes TAG0, the second entry includes TAG1, and so on, the nth entry includes TAG(n-1).

[0061] Among them, access instructions refer to access instructions initiated by the processor (such as the CPU), for example... Figure 2 The `request` directive in the `<request>` directive carries the access address, for example... Figure 2 The M_ADDR in the memory contains various information. By parsing the access address, the target tag value, entry index information, and data address information can be obtained. The target tag value refers to the target storage address, specifically the specific address the processor needs to access. The entry index information refers to the index information of the entry the processor needs to access, specifically... Figure 2 In the context of Index1, for example, if the entry index is 2, it means the processor needs to access the second entry in address memory 102. Data address information refers to the storage address of the data the processor needs to read, used to store the data corresponding to the target tag value. Specifically, it refers to... Figure 2 Index2 in the reference; for example, see Index2. Figure 2 If the target tag value is TAG2, then the address corresponding to Index2 stores DATA2.

[0062] The first preset condition for a target tag value is that the decimal number corresponding to the target tag value is odd and greater than 0; the second preset condition for a target tag value is that the decimal number corresponding to the target tag value is even. It should be noted that satisfying the first preset condition can also mean that the decimal number corresponding to the target tag value is even; and failing to satisfy the first preset condition can also mean that the decimal number corresponding to the target tag value is odd. The specific conditions can be adjusted according to the actual situation, and this application does not impose specific limitations here.

[0063] When the target tag value meets the first preset condition, the controller 101 can read the saved tag value from the register since the register stores the previously saved tag value, such as TAG(n+1).

[0064] In this case, when the target tag value is the same as the stored tag value, data is read from the address corresponding to the stored tag value in the data memory 103. This means that the controller 101 determines that the target tag value is the same as the tag value stored in the register, indicating that the data to be accessed by the processor is cached in the data memory 103. Therefore, the data is read from the address corresponding to the stored tag value in the data memory 103 and returned to the processor. This avoids the drawback of reading data from the address corresponding to the data address information in the data memory 103 when it is unclear whether there is a tag value with the same target tag value in the first tag value and the second tag value, which would cause high power consumption in the data access process. This reduces the power consumption of the data access process.

[0065] Specifically, when the target tag value does not meet the first preset condition, the left cache line in the entry corresponding to the entry index information stores the first tag value, such as TAGn, and the right cache line stores the second tag value, such as TAG(n+1). Reading consecutive first and second tag values ​​according to the entry index information and reading data from the address corresponding to the data address information in the data memory 103 means that when the processor 101 reads the first tag value from the entry corresponding to the entry index information in the address memory 102, it also reads the second tag value at the same time, and simultaneously reads data from the address corresponding to the data address information in the data memory 103. If there is a tag value in the first tag value and the second tag value that is the same as the target tag value, the data read back means that the controller 101 determines that the target tag value is the same as one of the first tag value and the second tag value (such as the first tag value), and the data memory 103 stores the data corresponding to the tag value in the address memory 102. This means that the data that the processor needs to access is cached in the data memory 103. Therefore, the previously read data is directly returned to the processor. There is no need to determine the tag hit and then read the data from the address corresponding to the data address information in the data memory 103 and then return the data to the processor, thereby reducing the processor's data read latency.

[0066] It should be noted that reading consecutive first tag values ​​and second tag values ​​based on entry index information and reading data from the address corresponding to the data address information in data storage 103 are performed simultaneously, and there is no sequential order between these two processes.

[0067] Specifically, when one of the first tag values ​​and the second tag value is the same as the target tag value, it means that the data previously read from the address corresponding to the data address information in the data memory 103 is the data corresponding to the target tag value. Therefore, the data previously read from the address corresponding to the data address information in the data memory 103 can be directly returned to the processor. At the same time, the controller 101 stores the tag values ​​(such as the second tag value) that are different from the target tag value in the first tag value and the second tag value into a register. This is to temporarily save the tag values ​​that are different from the target tag value in the first tag value and the second tag value through the register, so that the saved tag value can be directly read from the register when the target tag value meets the first preset condition. When the target tag value is the same as the saved tag value, the data is read from the address corresponding to the saved tag value in the data memory 103 and the read data is fed back. This eliminates the need to read data from the address corresponding to the data address information in the data memory 103 every time it is unclear whether there is a tag value in the first tag value and the second tag value that is the same as the target tag value, which causes a large power consumption defect in the data access process, thereby reducing the power consumption of the data access process.

[0068] Specifically, the controller 101 receives the access instruction sent by the processor and parses the instruction to obtain the target tag value, entry index information, and data address information. Based on the decimal number corresponding to the target tag value, it determines whether the target tag value meets a first preset condition. If the target tag value meets the first preset condition, it reads the stored tag value from the register, such as TAG(n+1), and determines whether the target tag value is the same as the stored tag value. If the target tag value is the same as the stored tag value, it reads the data from the address corresponding to the stored tag value in the data memory 103 and returns the data to the processor. If the target tag value does not meet the first preset condition, the controller 101 reads consecutive first and second tag values, such as TAGn and TAG(n+1), from the entry corresponding to the entry index information in the address memory 102, and simultaneously reads the data from the address corresponding to the data address information in the data memory 103. Next, the controller 101 determines whether there is a tag value that is the same as the target tag value among the first tag value and the second tag value. If there is a tag value that is the same as the target tag value among the first tag value and the second tag value, such as the target tag value being the same as the first tag value, the data previously read from the address corresponding to the data address information in the data memory 103 is directly returned to the processor, and the tag values ​​that are different from the target tag value among the first tag value and the second tag value are stored in the register, so as to temporarily save the tag values ​​that are different from the target tag value among the first tag value and the second tag value, such as the second tag value.

[0069] The aforementioned cache includes a controller, an address memory, and a data memory. The address memory includes a register and at least one way. Each way includes multiple entries, and each entry stores the tag value of two consecutive cache lines. The controller is used to receive and parse access instructions to obtain the target tag value, entry index information, and data address information. If the target tag value meets a first preset condition, it reads the stored tag value from the register. If the target tag value is the same as the stored tag value, it reads data from the data memory at the data address corresponding to the stored tag value and feeds back the read data. If the target tag value does not meet the first preset condition, it reads consecutive first and second tag values ​​according to the entry index information and reads data from the data memory at the address corresponding to the data address information. If there is a tag value in the first and second tag values ​​that is the same as the target tag value, it feeds back the read data and stores the tag values ​​in the first and second tag values ​​that are different from the target tag value into the register. In this way, when the target tag value in the received access instruction does not meet the first preset condition, the controller in the cache reads consecutive first tag values ​​and second tag values ​​from the address memory according to the entry index information, and at the same time reads data from the address corresponding to the data address information in the data memory. This is beneficial because if there is a tag value in the first tag value and second tag value that is the same as the target tag value in the access instruction, the read data can be returned directly without causing data reading delay, avoiding processor performance loss, and thus improving processor performance. Furthermore, based on the entry index information, consecutive first tag values ​​and second tag values ​​are read from the address memory, and tag values ​​that are different from the target tag value are stored in a register. This allows the stored tag value to be read directly from the register when the target tag value meets the first preset condition, and to read data from the address corresponding to the stored tag value when the target tag value is the same as the stored tag value. The read data is then returned. This eliminates the need to read consecutive first tag values ​​and second tag values ​​from the address memory and read data from the address corresponding to the data address information simultaneously. This avoids the drawback of high power consumption during data access when it is unclear whether there is a tag value in the first and second tags that is the same as the target tag value. Thus, the goal of improving processor performance while reducing power consumption is achieved.

[0070] In one embodiment, such as Figure 1As shown, the controller 101 is also used to read consecutive third and fourth tag values ​​according to the entry index information when the target tag value is different from the stored tag value, and read data from the address corresponding to the data address information in the data memory 103. If there is a tag value in the third and fourth tag values ​​that is the same as the target tag value, the controller 101 will feed back the read data and store the tag values ​​in the third and fourth tag values ​​that are different from the target tag value into the register.

[0071] Specifically, when the target tag value meets the first preset condition and is different from the stored tag value, the left cache line in the entry corresponding to the entry index information stores the third tag value, such as TAG2, and the right cache line stores the fourth tag value, such as TAG3. Reading consecutive third and fourth tag values ​​according to the entry index information and reading data from the address corresponding to the data address information in the data memory 103 means that when the processor 101 reads the third tag value from the entry corresponding to the entry index information in the address memory 102, it also reads the fourth tag value simultaneously, and reads data from the address corresponding to the data address information in the data memory 103. If there is a tag value in the third and fourth tag values ​​that is the same as the target tag value, the data read in the feedback means that the controller 101 determines that the target tag value is the same as one of the third and fourth tag values ​​(such as the third tag value), and the data memory 103 stores the data corresponding to the tag value in the address memory 102. This means that the data that the processor needs to access is cached in the data memory 103. Therefore, the previously read data is directly returned to the processor. There is no need to determine the tag hit and then read the data from the address corresponding to the data address information in the data memory 103 and then return the data to the processor, thereby reducing the processor's data read latency.

[0072] It should be noted that reading consecutive third and fourth tag values ​​based on the entry index information and reading data from the address corresponding to the data address information in the data storage 103 are performed simultaneously, and there is no sequential order between these two processes.

[0073] Specifically, when one of the third and fourth tag values ​​is the same as the target tag value, it means that the data previously read from the address corresponding to the data address information in the data memory 103 is the data corresponding to the target tag value. Therefore, the data previously read from the address corresponding to the data address information in the data memory 103 can be directly returned to the processor. At the same time, the controller 101 stores the tag values ​​(such as the fourth tag value) that are different from the target tag value in the third and fourth tag values ​​into a register. This is to temporarily save the tag values ​​that are different from the target tag value in the third and fourth tag values ​​through the register, so that the saved tag value can be directly read from the register when the target tag value meets the first preset condition. When the target tag value is the same as the saved tag value, data is read from the address corresponding to the saved tag value in the data memory 103, and the read data is fed back.

[0074] Specifically, refer to Figure 1 If the target tag value meets the first preset condition, the controller 101 reads the stored tag value from the register and determines whether the target tag value is the same as the stored tag value. If the target tag value is different from the stored tag value, it reads consecutive third and fourth tag values ​​(e.g., TAG2 and TAG3) from the entry corresponding to the entry index information in the address memory 102, and simultaneously reads data from the address corresponding to the data address information in the data memory 103. Next, the controller 101 determines whether there is a tag value in the third and fourth tag values ​​that is the same as the target tag value. If there is a tag value in the third and fourth tag values ​​that is the same as the target tag value (e.g., the target tag value is the same as the third tag value), it directly returns the data previously read from the address corresponding to the data address information in the data memory 103 to the processor, and stores the tag values ​​in the third and fourth tag values ​​that are different from the target tag value in the register, so as to temporarily save the tag values ​​in the third and fourth tag values ​​that are different from the target tag value (e.g., the fourth tag value).

[0075] For example, see reference. Figure 2 Assuming the entry index information is 2; if the target tag value is different from the saved tag value, the controller 101 reads TAG2 and TAG3 from the second entry, and reads DATA2 from the data memory 103; if the target tag value is the same as TAG2, the previously read DATA2 is directly returned to the processor, and TAG3 is stored in the register.

[0076] In this embodiment, when the target tag value meets the first preset condition and the target tag value is different from the stored tag value, consecutive third and fourth tag values ​​are read from the entry corresponding to the entry index information. At the same time, data is read from the address corresponding to the data address information in the data storage. This ensures that if there is a tag value in the third and fourth tag values ​​that is the same as the target tag value, the previously read data is directly returned without causing data reading delay, thereby avoiding processor performance loss and improving processor performance. Simultaneously, while reading the third tag value, a fourth tag value that is consecutive to it is also read. The tag values ​​in the third and fourth tags that are different from the target tag value are stored in a register. This allows the stored tag value to be read directly from the register when the target tag value meets the first preset condition. If the target tag value is the same as the stored tag value, data is read from the address corresponding to the stored tag value in the data memory, and the read data is fed back. This achieves accurate data reading and avoids the drawback of reading data from the address corresponding to the data address information in the data memory when it is unclear whether two consecutive tag values ​​read out are the same as the target tag value, which would result in high power consumption during the data access process.

[0077] In one embodiment, such as Figure 1 As shown, the controller 101 is also used to read data from the address corresponding to the target tag value in the target memory when there is no tag value in the third tag value and the fourth tag value that is the same as the target tag value, and to feed back the read data.

[0078] The target memory refers to memory located outside the processor, such as DDR (DDR SDRAM, Double Data Rate Synchronous Dynamic Random Access Memory).

[0079] Specifically, refer to Figure 1 If the target tag value is different from the stored tag value, the controller 101 reads the consecutive third tag value and fourth tag value from the entry corresponding to the entry index information in the address memory 102, and at the same time reads the data from the address corresponding to the data address information in the data memory 103; it determines whether there is a tag value in the third tag value and fourth tag value that is the same as the target tag value. If there is no tag value in the third tag value and fourth tag value that is the same as the target tag value, it reads the data from the address corresponding to the target tag value in the target memory and returns the data to the processor.

[0080] For example, see reference. Figure 2Assuming that two consecutive tag values ​​are read as TAG2 and TAG3; if there is no tag value in TAG2 and TAG3 that is the same as the target tag value, the controller 101 reads the corresponding data from the address in DDR that corresponds to the target tag value and returns the data to the processor.

[0081] In this embodiment, if there is no tag value in the third tag value and the fourth tag value that is the same as the target tag value, the data is read from the address corresponding to the target tag value in the target memory and the read data is fed back. This avoids the defect that the data reading will fail if the data memory does not store the data corresponding to the target tag value, thereby ensuring the successful reading of the data.

[0082] In one embodiment, reference Figure 1 The controller 101 is also used to read data from the address corresponding to the target tag value in the target memory and to feed back the read data when there is no tag value in the first tag value and the second tag value that is the same as the target tag value.

[0083] Specifically, refer to Figure 1 If the target tag value does not meet the first preset condition, the controller 101 reads consecutive first and second tag values, such as TAGn and TAG(n+1), from the entry corresponding to the entry index information in the address memory 102, and simultaneously reads data from the address corresponding to the data address information in the data memory 103. Next, the controller 101 determines whether there is a tag value identical to the target tag value among the first and second tag values. If there is no tag value identical to the target tag value among the first and second tag values, the controller reads data from the address corresponding to the target tag value in the target memory and returns the data to the processor.

[0084] For example, see reference. Figure 2 If the target tag value does not meet the first preset condition, and the two consecutive tag values ​​read are TAG4 and TAG5; if there is no tag value in TAG4 and TAG5 that is the same as the target tag value, the controller 101 reads the corresponding data from the address in DDR corresponding to the target tag value and returns the data to the processor.

[0085] In this embodiment, if there is no tag value in the first tag value and the second tag value that is the same as the target tag value, the data is read from the address corresponding to the target tag value in the target memory and the read data is fed back. This avoids the defect that the data reading will fail if the data memory does not store the data corresponding to the target tag value, thereby ensuring the successful reading of the data.

[0086] In one embodiment, reference Figure 1 Each entry also stores a status identifier corresponding to the tag value; the status identifier is used to indicate whether the corresponding tag value is valid; the controller 101 is also used to read the status identifier corresponding to the first tag value and the status identifier corresponding to the second tag value according to the entry index information when the target tag value does not meet the first preset condition, and to determine that there is a tag value that is the same as the target tag value among the first tag value and the second tag value when both the status identifier corresponding to the first tag value and the status identifier corresponding to the second tag value are valid.

[0087] Within each entry, the tag value in the left cache line corresponds to a status identifier, such as VLD2, and the tag value in the right cache line also corresponds to a status identifier, such as VLD3. The status identifier corresponding to each tag value is used to indicate whether the tag value is valid; for example, if the status identifier of tag value TAG2 is the preset status identifier, such as VLD2=1, it means that the tag value TAG2 is valid; if the status identifier of tag value TAG2 is not the preset status identifier, such as VLD2=0, it means that the tag value TAG2 is invalid.

[0088] Specifically, refer to Figure 1 If the target tag value does not meet the first preset condition, the controller 101 reads consecutive first and second tag values, as well as the status flags corresponding to the first and second tag values, from the entry corresponding to the entry index information in the address memory 102. Simultaneously, it reads data from the address corresponding to the data address information in the data memory 103. Next, the controller 101 determines whether both the status flags corresponding to the first and second tag values ​​are valid. If both are valid, the controller 101 confirms that both the first and second tag values ​​are valid. It further determines whether there is a tag value identical to the target tag value among the first and second tag values. If so, the controller directly returns the data previously read from the address corresponding to the data address information in the data memory 103 to the processor.

[0089] Furthermore, if the controller 101 detects that both the status flag corresponding to the first tag value and the status flag corresponding to the second tag value are invalid, it confirms that both the first tag value and the second tag value are invalid, then reads the data from the address corresponding to the target tag value in the target memory, and returns the data to the processor.

[0090] Furthermore, if the target tag value meets the first preset condition and is different from the stored tag value, the controller 101 reads consecutive third and fourth tag values, as well as the status flags corresponding to the third and fourth tag values, from the entry corresponding to the entry index information in the address memory 102. Simultaneously, it reads data from the address corresponding to the data address information in the data memory 103. Next, the controller 101 determines whether the status flags corresponding to the third and fourth tag values ​​are both valid. If both are valid, the controller 101 confirms that both the third and fourth tag values ​​are valid. It further determines whether there is a tag value in the third and fourth tag values ​​that is the same as the target tag value. If there is, the controller directly returns the data previously read from the address corresponding to the data address information in the data memory 103 to the processor. If the controller 101 detects that the status flags corresponding to the third tag value and the fourth tag value are both invalid, it confirms that both the third tag value and the fourth tag value are invalid, reads the data from the address corresponding to the target tag value in the target memory, and returns the data to the processor.

[0091] In this embodiment, only when the target tag value is found to not meet the first preset condition, and both the status identifiers corresponding to the first tag value and the status identifiers corresponding to the second tag value are valid, is it determined whether there is a tag value in the first tag value and the second tag value that is the same as the target tag value. This avoids the defect of high power consumption in the data access process caused by returning the data previously read from the address corresponding to the data address information in the data memory 103 to the processor when the read tag value is invalid. This reduces the power consumption of the data access process.

[0092] In one embodiment, such as Figure 3 As shown, a data processing method is provided, which can be applied in a controller, and includes the following steps:

[0093] Step S301: Receive and parse the access command to obtain the target tag value, entry index information and data address information.

[0094] Step S302: If the target tag value meets the first preset condition, read the saved tag value from the register; if the target tag value is the same as the saved tag value, read the data from the address corresponding to the saved tag value in the data memory and feed back the read data.

[0095] Step S303: If the target tag value does not meet the first preset condition, read consecutive first tag values ​​and second tag values ​​according to the entry index information, and read data from the address corresponding to the data address information in the data storage. If there is a tag value in the first tag value and second tag value that is the same as the target tag value, feed back the read data, and store the tag values ​​in the first tag value and second tag value that are different from the target tag value in the register.

[0096] Specifically, the controller 101 receives the access instruction sent by the processor and parses the instruction to obtain the target tag value, entry index information, and data address information. Based on the decimal number corresponding to the target tag value, it determines whether the target tag value meets a first preset condition. If the target tag value meets the first preset condition, it reads the stored tag value from the register, such as TAG(n+1), and determines whether the target tag value is the same as the stored tag value. If the target tag value is the same as the stored tag value, it reads the data from the address corresponding to the stored tag value in the data memory 103 and returns the data to the processor. If the target tag value does not meet the first preset condition, the controller 101 reads consecutive first and second tag values, such as TAGn and TAG(n+1), from the entry corresponding to the entry index information in the address memory 102, and simultaneously reads the data from the address corresponding to the data address information in the data memory 103. Next, the controller 101 determines whether there is a tag value that is the same as the target tag value among the first tag value and the second tag value. If there is a tag value that is the same as the target tag value among the first tag value and the second tag value, such as the target tag value being the same as the first tag value, the data previously read from the address corresponding to the data address information in the data memory 103 is directly returned to the processor, and the tag values ​​that are different from the target tag value among the first tag value and the second tag value are stored in the register, so as to temporarily save the tag values ​​that are different from the target tag value among the first tag value and the second tag value, such as the second tag value.

[0097] It should be noted that for specific limitations regarding the above steps, please refer to [the relevant documentation / reference]. Figure 1 and Figure 2 The relevant implementation examples of cache will not be described in detail here.

[0098] In the above data processing method, if the target tag value in the received access instruction does not meet the first preset condition, while reading consecutive first tag values ​​and second tag values ​​from the address memory according to the entry index information, data is read from the address corresponding to the data address information in the data memory. This is beneficial because if there is a tag value in the first tag value and second tag value that is the same as the target tag value in the access instruction, the read data can be returned directly without causing data reading delay, avoiding processor performance loss, and thus improving processor performance. Furthermore, based on the entry index information, consecutive first tag values ​​and second tag values ​​are read from the address memory, and tag values ​​that are different from the target tag value are stored in a register. This allows the stored tag value to be read directly from the register when the target tag value meets the first preset condition, and to read data from the address corresponding to the stored tag value when the target tag value is the same as the stored tag value. The read data is then returned. This eliminates the need to read consecutive first tag values ​​and second tag values ​​from the address memory and read data from the address corresponding to the data address information simultaneously. This avoids the drawback of high power consumption during data access when it is unclear whether there is a tag value in the first and second tags that is the same as the target tag value. Thus, the goal of improving processor performance while reducing power consumption is achieved.

[0099] In one embodiment, such as Figure 4 As shown, in step S302 above, after reading the saved tag value from the register when the target tag value meets the first preset condition, the following steps are also included:

[0100] Step S401: If the target tag value is different from the saved tag value, read the consecutive third and fourth tag values ​​according to the entry index information, and read the data from the address corresponding to the data address information in the data storage.

[0101] In step S402, if there is a tag value in the third tag value and the fourth tag value that is the same as the target tag value, the read data is fed back, and the tag values ​​in the third tag value and the fourth tag value that are different from the target tag value are stored in the register.

[0102] In this embodiment, when the target tag value meets the first preset condition and the target tag value is different from the stored tag value, consecutive third and fourth tag values ​​are read from the entry corresponding to the entry index information. At the same time, data is read from the address corresponding to the data address information in the data storage. This ensures that if there is a tag value in the third and fourth tag values ​​that is the same as the target tag value, the previously read data is directly returned without causing data reading delay, thereby avoiding processor performance loss and improving processor performance. Simultaneously, while reading the third tag value, a fourth tag value that is consecutive to it is also read. The tag values ​​in the third and fourth tags that are different from the target tag value are stored in a register. This allows the stored tag value to be read directly from the register when the target tag value meets the first preset condition. If the target tag value is the same as the stored tag value, data is read from the address corresponding to the stored tag value in the data memory, and the read data is fed back. This achieves accurate data reading and avoids the drawback of reading data from the address corresponding to the data address information in the data memory when it is unclear whether two consecutive tag values ​​read out are the same as the target tag value, which would result in high power consumption during the data access process.

[0103] In one embodiment, after reading consecutive third and fourth tag values ​​based on the entry index information and reading data from the address corresponding to the data address information in the data storage, step S401 above further includes the following steps:

[0104] In step S403, if there is no tag value in the third tag value and the fourth tag value that is the same as the target tag value, read the data from the address corresponding to the target tag value in the target memory and return the read data.

[0105] In this embodiment, if there is no tag value in the third tag value and the fourth tag value that is the same as the target tag value, the data is read from the address corresponding to the target tag value in the target memory and the read data is fed back. This avoids the defect that the data reading will fail if the data memory does not store the data corresponding to the target tag value, thereby ensuring the successful reading of the data.

[0106] In one embodiment, step S303, after reading consecutive first tag values ​​and second tag values ​​according to the entry index information and reading data from the address corresponding to the data address information in the data storage, further includes the following: if there is no tag value in the first tag value and second tag value that is the same as the target tag value, read data from the address corresponding to the target tag value in the target storage and feed back the read data.

[0107] In this embodiment, if there is no tag value in the first tag value and the second tag value that is the same as the target tag value, the data is read from the address corresponding to the target tag value in the target memory and the read data is fed back. This avoids the defect that the data reading will fail if the data memory does not store the data corresponding to the target tag value, thereby ensuring the successful reading of the data.

[0108] In one embodiment, the data processing method provided by this application further includes the following: when the target tag value does not meet the first preset condition, reading the status identifier corresponding to the first tag value and the status identifier corresponding to the second tag value according to the entry index information; the status identifier is used to indicate whether the corresponding tag value is valid; when both the status identifier corresponding to the first tag value and the status identifier corresponding to the second tag value are valid, determining that there is a tag value that is the same as the target tag value among the first tag value and the second tag value.

[0109] In this embodiment, only when the target tag value is found to not meet the first preset condition, and both the status identifiers corresponding to the first tag value and the status identifiers corresponding to the second tag value are valid, is it determined whether there is a tag value in the first tag value and the second tag value that is the same as the target tag value. This avoids the defect of high power consumption in the data access process caused by returning the data previously read from the address corresponding to the data address information in the data memory 103 to the processor when the read tag value is invalid. This reduces the power consumption of the data access process.

[0110] In one embodiment, such as Figure 5 As shown, another data processing method is provided, which can be applied to a data processing system, and includes the following steps:

[0111] Step S501: Receive and parse the access command to obtain the target tag value, entry index information and data address information.

[0112] It should be noted that if the target tag value meets the first preset condition, then step S502 is executed; if the target tag value does not meet the first preset condition, then step S507 is executed.

[0113] Step S502: If the target tag value meets the first preset condition, read the saved tag value from the register.

[0114] It should be noted that if the target tag value is the same as the saved tag value, then step S503 is executed; if the target tag value is not the same as the saved tag value, then step S504 is executed.

[0115] Step S503: If the target tag value is the same as the saved tag value, read the data from the address corresponding to the saved tag value in the data storage and return the read data.

[0116] Step S504: If the target tag value is different from the saved tag value, read the consecutive third and fourth tag values ​​according to the entry index information, and read the data from the address corresponding to the data address information in the data storage.

[0117] It should be noted that if there is a tag value in the third tag value and the fourth tag value that is the same as the target tag value, then step S505 is executed; if there is no tag value in the third tag value and the fourth tag value that is the same as the target tag value, then step S506 is executed.

[0118] In step S505, if there is a tag value in the third tag value and the fourth tag value that is the same as the target tag value, the read data is fed back, and the tag values ​​in the third tag value and the fourth tag value that are different from the target tag value are stored in the register.

[0119] Step S506: If there is no tag value in the third tag value and the fourth tag value that is the same as the target tag value, read data from the address corresponding to the target tag value in the target memory and return the read data.

[0120] Step S507: If the target tag value does not meet the first preset condition, read the consecutive first tag value and second tag value according to the entry index information, and read the data from the address corresponding to the data address information in the data storage.

[0121] It should be noted that if there is a tag value in the first tag value and the second tag value that is the same as the target tag value, then step S508 is executed; if there is no tag value in the first tag value and the second tag value that is the same as the target tag value, then step S509 is executed.

[0122] In step S508, if there is a tag value in the first tag value and the second tag value that is the same as the target tag value, the read data is fed back, and the tag values ​​in the first tag value and the second tag value that are different from the target tag value are stored in the register.

[0123] In step S509, if there is no tag value in the first tag value and the second tag value that is the same as the target tag value, data is read from the address corresponding to the target tag value in the target memory and the read data is fed back.

[0124] In the above data processing method, if the target tag value in the received access instruction does not meet the first preset condition, while reading consecutive first tag values ​​and second tag values ​​from the address memory according to the entry index information, data is read from the address corresponding to the data address information in the data memory. This is beneficial because if there is a tag value in the first tag value and second tag value that is the same as the target tag value in the access instruction, the read data can be returned directly without causing data reading delay, avoiding processor performance loss, and thus improving processor performance. Furthermore, based on the entry index information, consecutive first tag values ​​and second tag values ​​are read from the address memory, and tag values ​​that are different from the target tag value are stored in a register. This allows the stored tag value to be read directly from the register when the target tag value meets the first preset condition, and to read data from the address corresponding to the stored tag value when the target tag value is the same as the stored tag value. The read data is then returned. This eliminates the need to read consecutive first tag values ​​and second tag values ​​from the address memory and read data from the address corresponding to the data address information simultaneously. This avoids the drawback of high power consumption during data access when it is unclear whether there is a tag value in the first and second tags that is the same as the target tag value. Thus, the goal of improving processor performance while reducing power consumption is achieved.

[0125] In one embodiment, to more clearly illustrate the data processing method provided in this application, the following detailed description uses a specific embodiment. In one embodiment, refer to... Figure 2The TAGmemory has been restructured. Each entry contains the tag values ​​of two consecutive cache lines. When reading the tag value of the nth cache line, the tag value of the (n+1)th cache line is also read and stored in the register buffer to temporarily store the tag value of the (n+1)th (odd-numbered) cache line. When the CPU accesses the (n+1)th cache line, it can directly read the tag value of the (n+1)th cache line from the register buffer and compare the target tag value in the data read request with the tag value of the (n+1)th cache line. If there is a hit (i.e., the target tag value in the data read request is the same as the tag value of the (n+1)th cache line), it means that the data that the CPU wants to access is cached. In this case, the data corresponding to the stored tag value is directly read from the data memory and returned to the CPU. Therefore, speculative reads of data memory are not required, effectively reducing speculative reads by about 50%, thereby reducing power consumption. Furthermore, different processing procedures are selected depending on whether the tag value of the accessed cacheline is n (even number) or n+1 (odd number); if it is n, the tag value is directly read from the address memory and a hit / miss determination is performed; if it is n+1, the tag value stored in the register buffer is read first and a hit / miss determination is performed.

[0126] Figure 6 A flowchart illustrating an improved cache-based data processing method is provided. (Reference) Figure 6The controller in the cache first receives the data read request sent by the CPU and parses the data read request to obtain the target tag value, entry index information and data address information; it then judges the target tag value. If the decimal number corresponding to the target tag value is n+1 (odd number), it reads the stored tag value from the register buffer; if it hits, that is, the target tag value is the same as the tag value stored in the register buffer, it reads the data corresponding to the tag value stored in the register buffer from the data memory and returns the data to the CPU. If it misses (i.e., the target tag value is different from the tag value stored in the register buffer), the tag values ​​of two consecutive cache lines, namely TAGn and TAG(n+1), are read from the entry corresponding to the entry index information. TAG(n+1) is then stored in the register buffer, and a speculative read is performed on the data memory, i.e., the data corresponding to TAGn is read from the address corresponding to the data address information in the data memory. If it hits (i.e., the target tag value is the same as TAGn), it means that the data that the CPU wants to access is cached, so the data corresponding to TAGn that was previously read is directly returned to the CPU. If it misses (i.e., the target tag value is different from TAGn), it means that the data that the CPU wants to access is not cached, so the data corresponding to the target tag value is read from the lower-level memory (such as DDR) and the data is returned to the CPU.

[0127] Furthermore, when the decimal number corresponding to the target tag value is n (an even number), the controller reads the tag values ​​of two consecutive cache lines, namely TAGn and TAG(n+1), from the entry corresponding to the entry index information, and stores TAG(n+1) in the register buffer. At the same time, it performs a data speculative read operation, that is, it reads the data corresponding to TAGn from the address corresponding to the data address information in the data memory. If it hits, that is, the target tag value is the same as TAGn, it means that the data that the CPU wants to access is cached, and the previously read data corresponding to TAGn is directly returned to the CPU. If it misses, that is, the target tag value is different from TAGn, it means that the data that the CPU wants to access is not cached, and the data corresponding to the target tag value is read from the lower-level memory (such as DDR) and the data is returned to the CPU.

[0128] The aforementioned data processing method improves processor performance by performing speculative data reads while simultaneously reading tag values. This allows the previously read data to be directly returned to the CPU in the event of a hit. Furthermore, when the CPU accesses the (n+1)th cacheline, it can directly read the tag value of the (n+1)th cacheline from the register buffer. If a hit occurs, the corresponding data is directly read from the data memory and returned to the CPU. This effectively reduces speculative data reads by approximately 50%, thereby lowering power consumption and ultimately improving processor performance while reducing power consumption.

[0129] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0130] In one embodiment, such as Figure 7 As shown, this application also provides a data processing system, including: a processor 20 and a cache 10; the processor 20 is used to send access instructions to the cache 10; the processor 20 is also used to receive data returned by the cache 10 based on the access instructions.

[0131] Here, cache 10 can refer to Figure 1 or Figure 2 The cache in the middle.

[0132] Specifically, refer to Figure 7 The processor 20 sends the access instruction to the cache 10; the cache 10 performs a series of processes based on the received access instruction, obtains the corresponding data, and returns the data to the processor 20.

[0133] In the aforementioned data processing system, when the target tag value does not meet the first preset condition, while reading consecutive first tag values ​​and second tag values ​​from the address memory according to the entry index information, data is also read from the address corresponding to the data address information in the data memory. This is beneficial because if there is a tag value in the first tag value and second tag value that is the same as the target tag value in the access instruction, the read data can be returned directly without causing data reading delay, avoiding processor performance loss, and thus improving processor performance. Furthermore, based on the entry index information, consecutive first tag values ​​and second tag values ​​are read from the address memory, and tag values ​​that are different from the target tag value are stored in a register. This allows the stored tag value to be read directly from the register when the target tag value meets the first preset condition, and to read data from the address corresponding to the stored tag value when the target tag value is the same as the stored tag value. The read data is then returned. This eliminates the need to read consecutive first tag values ​​and second tag values ​​from the address memory and read data from the address corresponding to the data address information simultaneously. This avoids the drawback of high power consumption during data access when it is unclear whether there is a tag value in the first and second tags that is the same as the target tag value. Thus, the goal of improving processor performance while reducing power consumption is achieved.

[0134] In one embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be as follows: Figure 8 As shown, the computer device includes a processor, memory, and a network interface connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The database stores information such as addresses and data. The network interface is used for communication with external terminals via a network connection. When the computer program is executed by the processor, it implements a data processing method.

[0135] Those skilled in the art will understand that Figure 8The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0136] In one embodiment, a computer device is also provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above method embodiments.

[0137] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the steps in the above method embodiments.

[0138] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above method embodiments.

[0139] It should be noted that the data involved in this application (including but not limited to data used for analysis, stored data, and displayed data) are all information and data authorized by the user or fully authorized by all parties.

[0140] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.

[0141] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0142] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A cache, characterized in that, The cache includes: a controller, an address memory, and a data memory. The address memory includes registers and at least one way. The way includes multiple entries, and each entry stores the tag value of two consecutive cache lines. The controller is configured to receive and parse access instructions to obtain target tag values, entry index information, and data address information. If the target tag value meets a first preset condition, it reads a stored tag value from the register. If the target tag value is the same as the stored tag value, it reads data from the address corresponding to the stored tag value in the data memory and feeds back the read data. If the target tag value does not meet the first preset condition, it reads consecutive first and second tag values ​​according to the entry index information and reads data from the address corresponding to the data address information in the data memory. If there is a tag value in the first and second tags that is the same as the target tag value, it feeds back the read data and stores the tag values ​​in the first and second tags that are different from the target tag value into the register.

2. The cache according to claim 1, characterized in that, The controller is further configured to, when the target tag value is different from the stored tag value, read consecutive third and fourth tag values ​​according to the entry index information, and read data from the address corresponding to the data address information in the data memory; when there is a tag value in the third and fourth tag values ​​that is the same as the target tag value, feed back the read data, and store the tag values ​​in the third and fourth tag values ​​that are different from the target tag value into the register.

3. The cache according to claim 2, characterized in that, The controller is further configured to, when there is no tag value in the third tag value and the fourth tag value that is the same as the target tag value, read data from the address corresponding to the target tag value in the target memory and feed back the read data.

4. The cache according to claim 1, characterized in that, The controller is further configured to read data from the address corresponding to the target tag value in the target memory and to feed back the read data if there is no tag value identical to the target tag value among the first tag value and the second tag value.

5. The cache according to claim 1, characterized in that, Each entry also stores a status flag corresponding to the tag value; the status flag is used to indicate whether the corresponding tag value is valid. The controller is further configured to, when the target tag value does not meet the first preset condition, read the status identifier corresponding to the first tag value and the status identifier corresponding to the second tag value according to the entry index information, and determine that there is a tag value that is the same as the target tag value among the first tag value and the second tag value when both the status identifier corresponding to the first tag value and the status identifier corresponding to the second tag value are valid.

6. A data processing system, characterized in that, include: The processor and the cache according to any one of claims 1 to 5; The processor is used to send access instructions to the cache; The processor is also configured to receive data returned by the cache based on the access instruction.

7. A data processing method, characterized in that, The method includes: Receive and parse the access command to obtain the target tag value, entry index information, and data address information; If the target tag value meets the first preset condition, the saved tag value is read from the register; if the target tag value is the same as the saved tag value, data is read from the address corresponding to the saved tag value in the data memory, and the read data is fed back. If the target tag value does not meet the first preset condition, the first tag value and the second tag value are read consecutively according to the entry index information, and data is read from the address corresponding to the data address information in the data memory. If there is a tag value in the first tag value and the second tag value that is the same as the target tag value, the read data is fed back, and the tag values ​​in the first tag value and the second tag value that are different from the target tag value are stored in the register.

8. The method according to claim 7, characterized in that, After reading the saved tag value from the register when the target tag value meets the first preset condition, the method further includes: If the target tag value is different from the saved tag value, the third and fourth consecutive tag values ​​are read according to the entry index information, and the data is read from the address corresponding to the data address information in the data storage. If there is a tag value in the third tag value and the fourth tag value that is the same as the target tag value, the read data is fed back, and the tag values ​​in the third tag value and the fourth tag value that are different from the target tag value are stored in the register.

9. The method according to claim 8, characterized in that, After reading consecutive third and fourth tag values ​​according to the entry index information, and reading data from the address corresponding to the data address information in the data storage, the process further includes: If there is no tag value in the third tag value and the fourth tag value that is the same as the target tag value, data is read from the address corresponding to the target tag value in the target memory, and the read data is fed back.

10. The method according to claim 7, characterized in that, After reading consecutive first tag values ​​and second tag values ​​according to the entry index information, and reading data from the address corresponding to the data address information in the data storage, the process further includes: If there is no tag value that is the same as the target tag value among the first tag value and the second tag value, data is read from the address corresponding to the target tag value in the target memory, and the read data is fed back.

11. The method according to claim 7, characterized in that, The method further includes: If the target tag value does not meet the first preset condition, the status identifier corresponding to the first tag value and the status identifier corresponding to the second tag value are read according to the entry index information; the status identifier is used to indicate whether the corresponding tag value is valid. If both the status identifier corresponding to the first tag value and the status identifier corresponding to the second tag value are valid, it is determined that there is a tag value among the first tag value and the second tag value that is the same as the target tag value.

12. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 7 to 11.

13. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 7 to 11.

14. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 7 to 11.

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