High-speed driving display device and driving method thereof

Abstract

Disclosed herein is a display apparatus including a display panel including a plurality of pixels; a timing controller configured to generate current control information based on a degree of transition of image data applied to a corresponding pixel among the plurality of pixels; and a plurality of output buffers configured to output a target data voltage corresponding to the image data to a data output channel connected to the plurality of pixels, wherein each of the output buffers includes an amplifier output circuit configured to apply a pre-set rising current or falling current for outputting the target data voltage to an output node connected to one of the data output channels, and a slew rate adjustment circuit configured to selectively and further apply an additional rising current or an additional falling current to the output node based on the current control information to increase an output slew rate of the target data voltage.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2021-0081480, filed on June 23, 2021, which is incorporated herein by reference as if its contents were fully set forth herein. Technical Field

[0003] This disclosure relates to a high-speed driving display device and a driving method thereof. Background Technology

[0004] Recently, a high-speed driving display device suitable for high resolution and high-speed driving has been proposed.

[0005] There is a trade-off between the power consumption characteristics and data charging / discharging characteristics required for high-speed driving display devices. In high-speed driving display devices based on related technologies, it is difficult to satisfy both power consumption characteristics and data charging / discharging characteristics. Summary of the Invention

[0006] In order to overcome the above-mentioned problems of the related technologies, this disclosure can provide a display device and its driving method that can enhance both power consumption characteristics and data charging / discharging characteristics.

[0007] To achieve these objectives and other advantages, and in accordance with the purposes of this disclosure, as embodied and broadly described herein, a display device includes: a display panel including a plurality of pixels; a timing controller configured to generate current control information based on the slew rate of image data applied to corresponding pixels among the plurality of pixels; and a plurality of output buffers configured to output a target data voltage corresponding to the image data to data output channels connected to the plurality of pixels, wherein each of the output buffers includes: an amplifier output circuit configured to apply a pre-set rising current or falling current for outputting the target data voltage to an output node connected to one of the data output channels; and a slew rate adjustment circuit configured to selectively and further apply an additional rising current or an additional falling current to the output node based on the current control information to increase the output slew rate of the target data voltage.

[0008] In another aspect of this disclosure, a driving method for a display device includes: generating current control information based on the slew rate of image data applied to a pixel; and outputting a target data voltage corresponding to the image data to a data output channel connected to the pixel, wherein the output of the target data voltage includes: applying a pre-set rising current or falling current for outputting the target data voltage to an output node connected to one of the data output channels; and selectively and further applying an additional rising current or an additional falling current to the output node based on the current control information to increase the output slew rate of the target data voltage. Attached Figure Description

[0009] The accompanying drawings, which are included to provide a further understanding of this disclosure and are incorporated into and constitute a part of this application, illustrate (multiple) embodiments of the disclosure and, together with the specification, serve to explain the principles of the disclosure. In the drawings:

[0010] Figure 1 A diagram illustrating a display device according to an embodiment of the present disclosure;

[0011] Figure 2 A diagram illustrating the connection relationship between the source driver integrated circuit (IC) and the data lines in a display device according to an embodiment of the present disclosure;

[0012] Figure 3 A diagram illustrating a source driver IC in a display device according to an embodiment of the present disclosure;

[0013] Figure 4 A diagram illustrating the output circuitry included in the source driver IC of a display device according to an embodiment of the present disclosure;

[0014] Figure 5 To show Figure 4 The diagram shows the relationship between the power control signal and the amplifier bias current in the main bias circuit included in the output circuit.

[0015] Figure 6 A graph showing the relationship between amplifier bias current and transition time;

[0016] Figure 7 and Figure 8 A graph illustrating how the output slew rate, used to describe the target data voltage, increases with the addition of a rising current based on current control information (clock edge information + switching direction information).

[0017] Figure 9 and Figure 10 A graph illustrating how the output slew rate, used to describe the target data voltage, increases with an additional decreasing current based on current control information (clock edge information + switching direction information).

[0018] Figure 11 A diagram illustrating the operation of a timing controller that generates current control information based on the slew rate of image data and the operation of an output circuit that selectively increases the output slew rate of the target data voltage based on the current control information;

[0019] Figure 12 A diagram illustrating the data format transmitted by the first embedded panel interface (EPI), which includes current control information;

[0020] Figure 13 To illustrate the additional current based on included Figure 12 A diagram showing the on or off state of the clock edge information in the current control information;

[0021] Figure 14 A diagram illustrating the second EPI transmission data format, including current control information;

[0022] Figure 15 To illustrate the additional current based on included Figure 14 A diagram showing the on or off state of the clock edge information in the current control information;

[0023] Figure 16 A diagram illustrating the third EPI transmission data format, including current control information;

[0024] Figure 17 The diagram illustrates an example of current control information including clock edge information and vertical polarity control signal when the display device is a liquid crystal display device;

[0025] Figure 18 A graph illustrating the on or off state of the additional current of each output channel based on the logic value of the vertical polarity control signal when the clock edge information is the first clock edge information;

[0026] Figure 19 To illustrate the on / off state of the additional current of each output channel based on the logic value of the vertical polarity control signal when the clock edge information is the second clock edge information; and

[0027] Figure 20 and Figure 21 A graph showing the rate of reduction in transition time before and after the application of this disclosure is provided for each of the various power control modes. Detailed Implementation

[0028] The present disclosure will now be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the disclosure are illustrated. However, the present disclosure may be embodied in many different ways and should not be construed as limiting itself to the embodiments set forth herein; rather, these embodiments are provided to make the disclosure exhaustive and complete, and to fully convey the concepts of the disclosure to those skilled in the art.

[0029] The advantages and features of this disclosure and its implementation methods will be illustrated by the following embodiments described with reference to the accompanying drawings. However, this disclosure may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to make this disclosure exhaustive and complete, and to fully convey the scope of this disclosure to those skilled in the art. Furthermore, this disclosure is defined only by the scope of the claims.

[0030] The shapes, dimensions, scales, angles, quantities, etc., disclosed in the accompanying drawings used to describe various embodiments of this disclosure are merely exemplary and are not intended to limit the scope of this disclosure. Similar reference numerals always refer to similar elements. Throughout the specification, the same elements are represented by the same reference numerals. As used herein, the terms "comprising," "having," "including," etc., imply that additional parts may be added, unless the term "only" is used. As used herein, the singular forms "a" and "described" are intended to also include the plural forms, unless the context clearly indicates otherwise.

[0031] Even if not explicitly stated otherwise, the elements in the various embodiments of this disclosure should be interpreted as including error margins.

[0032] When describing positional relationships, for example, when the positional relationship between two parts is described as "above", "over", "below", and "beside", one or more other parts may be located between the two parts, unless "exactly" or "directly" is used.

[0033] It should be understood that although the terms "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0034] In the following description, detailed descriptions of relevant known functions or configurations will be omitted when they are determined to unnecessarily obscure the essential points of this disclosure. Hereinafter, embodiments of this disclosure will be described in detail with reference to the accompanying drawings.

[0035] Figure 1 A diagram illustrating a display device according to an embodiment of the present disclosure. Figure 2A diagram illustrating the connection relationship between the source driver integrated circuit (IC) and the data lines in a display device according to an embodiment of the present disclosure.

[0036] refer to Figure 1 and Figure 2 The display device according to the embodiments of the present disclosure can be implemented as an electroluminescent display device or a liquid crystal display device, which includes a display panel PNL, a timing controller CONT, a data driving circuit DDRV and a gate driving circuit GDRV.

[0037] A display panel PNL can provide multiple data lines DL and multiple gate lines GL, and multiple pixels PIX can be arranged in multiple intersection areas between the gate lines GL and the data lines DL. By using pixels PIX arranged in a matrix type, a pixel array can be provided in the display area of ​​the display panel PNL.

[0038] In a pixel array, pixels (PIX) can be arranged in a horizontal line to make them adjacent. The number of horizontal lines can be the vertical resolution of the display panel (PNL). Pixels forming the same horizontal line can be connected to the same gate line (GL) and different data lines (DL). Each pixel (PIX) can be implemented as an emitting unit including a light-emitting diode (LED) or a liquid crystal unit including a liquid crystal layer.

[0039] The timing controller CONT can generate a data timing control signal DDC for controlling the operation timing of the data drive circuit DDRV, and a gate timing control signal GDC for controlling the operation timing of the gate drive circuit GDRV, based on timing signals input from the host system (e.g., vertical synchronization signal Vsync, horizontal synchronization signal Hsync, and data enable signal DE). The gate timing control signal GDC may include a gate start signal and a gate shift clock. The data timing control signal DDC may include a source start pulse, a source sampling clock, and a source output enable signal.

[0040] The timing controller CONT can transmit image data DATA input from the host system to the data driver circuit DDRV via an internal interface circuit. The image data DATA can be used to display images using pixels (PIX); and the data driver circuit DDRV can convert the image data DATA into data voltage and supply the data voltage to the pixels (PIX). The internal interface circuit can be an embedded panel interface (EPI) circuit.

[0041] The timing controller CONT can compare image data DATA on a horizontal line basis, thereby calculating the degree of transition of image data DATA on a pixel basis. Then, it can generate current control information based on the degree of transition of image data DATA. The timing controller CONT can configure the data timing control signal DDC, current control information, and image data DATA in EPI data transmission format, and can transmit the configured timing control signal DDC, current control information, and image data DATA to the data driver circuit DDRV.

[0042] The gate drive circuit GDRV can generate a scan signal SCAN based on the gate timing control signal GDC from the timing controller CONT, and can supply the scan signal SCAN to the gate line GL. The horizontal line to which the data voltage is to be applied can be selected by the scan signal SCAN. The gate drive circuit GDRV can be embedded in the non-display area of ​​the display panel PNL based on the gate in-panel (GIP) type. This non-display area can be located outside the panel array in the display panel PNL.

[0043] The data driver circuit DDRV may include at least one source driver integrated circuit (IC) SD-IC. The source driver IC SD-IC can separate the data timing control signal DDC, current control information, and image data DATA from the EPI data transmission format transmitted by the timing controller CONT. The source driver IC SD-IC can convert the image data DATA into a data voltage based on the data timing control signal DDC, and can supply the data voltage to the data lines DL1 to DLm through data output channels CH1 to CHm. At this time, the source driver IC SD-IC can selectively and additionally control the output conversion rate of each of the data voltages based on the current control information in the data output channels CH1 to CHm, thereby enhancing both power consumption characteristics and data charge / discharge characteristics.

[0044] Figure 3 A diagram illustrating the source driver IC SD-IC in a display device according to an embodiment of the present disclosure.

[0045] refer to Figure 3 The source driver IC SD-IC may include a control logic circuit 300, a latch circuit 310, a digital-to-analog (D / A) conversion circuit 320, and an output circuit 330.

[0046] The control logic circuit 300 can sample one bit of control data from the signal received via the EPI data transmission format based on the internal clock timing, and can recover the data timing control signal DDC for controlling the operation of the source driver IC SD-IC from the sampled control data.

[0047] The control logic circuit 300 can sample image data from signals received via the serial EPI data transmission format based on internal clock timing. The control logic circuit 300 can also sample and recover current control information blocks CON1 to CONn from signals received via the EPI data transmission format based on internal clock timing. Current control information blocks CON1 to CONn can be set and recovered independently for each data output channel. Current control information blocks CON1 to CONn can include first clock edge information for enabling additional current in the output circuit 330 and second clock edge information for disabling additional current in the output circuit 330.

[0048] In an electroluminescent display device, the current control information blocks CON1 to CONn may further include transition direction information. The transition direction information can be a criterion for fundamentally selecting the target to be enabled from the rising current and falling current in the output circuit 330. Furthermore, when an additional current is enabled in the output circuit 330 (i.e., corresponding to the first clock edge information), the transition direction information can be further considered; this transition direction information can be a criterion for selecting the target to be enabled from the additional rising current and the additional falling current. The transition direction information may include first state information indicating an upward transition and second state information indicating a downward transition. When a rising current is enabled in the output circuit 330 based on the first state information, an upward transition of the data voltage can be performed; and when an additional rising current is enabled based on the first clock edge information and the first state information, the upward transition time of the data voltage can be reduced. When a falling current is enabled in the output circuit 330 based on the second state information, a downward transition of the data voltage can be performed; and when an additional falling current is enabled based on the first clock edge information and the second state information, the downward transition time of the data voltage can be reduced. Furthermore, when the second clock edge information is input, all additional rising and falling currents can be disabled, regardless of the direction change information.

[0049] In the liquid crystal display device, the current control information blocks CON1 to CONn may further include a vertical polarity control signal. The polarity of the data voltage can be reversed by the vertical polarity control signal in horizontal units. When the data voltage is higher than the common voltage, the polarity of the data voltage can be positive; and when the data voltage is lower than the common voltage, the polarity of the data voltage can be negative. The vertical polarity control signal can be a criterion for fundamentally selecting the target to be enabled from the rising current and falling current in the output circuit 330. Furthermore, when an additional current is enabled in the output circuit 330 (i.e., corresponding to the first clock edge information), the vertical polarity control signal can be further considered, which can be a criterion for selecting the target to be enabled from the additional rising current and the additional falling current. The vertical polarity control signal may include a first logic value indicating an upward transition and a second logic value indicating a downward transition. When the rising current is enabled in the output circuit 330 based on the first logic value, an upward transition of the data voltage can be performed; and when the additional rising current is enabled based on the first clock edge information and the first logic value, the upward transition time of the data voltage can be reduced. When the falling current is enabled in the output circuit 330 based on the second logic value, a downward transition of the data voltage can be performed; and when the additional falling current is enabled based on the first clock edge information and the second logic value, the downward transition time of the data voltage can be reduced. Furthermore, when the second clock edge information is input, all additional rising and falling currents can be disabled, regardless of the vertical polarity control signal.

[0050] The latch circuit 310 can convert the image data bits sampled by the control logic circuit 300 into a parallel data format. The latch circuit 310 can be synchronized based on an internal clock output from the control logic circuit 300.

[0051] The D / A conversion circuit 320 can convert image data, which has been converted to a parallel data format, into a gamma-compensated voltage to generate a data voltage.

[0052] The output circuit 330 may include multiple output buffers 330-1 to 330-n, and may output a target data voltage corresponding to the image data to data output channels CH1 to CHn. The output circuit 330 may also include a main bias circuit MBB commonly connected to the output buffers 330-1 to 330-n. The output slewing rate of each of the output buffers 330-1 to 330-n may be controlled based on current control information blocks CON1 to CONn input sequentially from the control logic circuit 300.

[0053] Figure 4 A diagram illustrating the output circuitry included in the source driver IC in a display device according to an embodiment of the present disclosure. Figure 5 To show Figure 4The diagram shows the relationship between the power control signal in the main bias circuit and the amplifier bias current in the output circuit.

[0054] Figure 6 A graph showing the relationship between amplifier bias current and transition time. Figure 7 and Figure 8 This is a diagram illustrating how the output conversion rate for describing the target data voltage increases with the addition of a rising current, based on current control information (clock edge information + switching direction information). Figure 9 and Figure 10 This is a diagram illustrating an example of how the output conversion rate, used to describe the target data voltage, increases with the addition of a decreasing current based on current control information (clock edge information + switching direction information).

[0055] refer to Figure 4 The output circuit 330 may include multiple output buffers 330-1 to 330-n that are commonly connected to the main bias circuit MBB.

[0056] The main bias circuit MBB can determine the level of the amplifier bias current Isum based on the predetermined power control signals LLL to HHH, and can apply the amplifier bias current Isum to the output buffers 330-1 to 330-n.

[0057] The main bias circuit MBB may include a reference current source connected between a high-level voltage source NH and a low-level voltage source NL to generate a reference current Iref, and a bias circuit that outputs an amplifier bias current Isum based on the reference current Iref. This bias circuit may include multiple mirror units M1 and M2 that mirror the reference current Iref, and a current regulation circuit that determines the level of the bias current Isum based on a power control signal PWRC. The channel capacities of the multiple transistors (e.g., first to nth transistors) A1 to Ak configuring the current regulation circuit may be different, and for example, the channel capacity of the first transistor A1 may be greater than the channel capacity of the kth transistor Ak.

[0058] For example, it can be used as Figure 5The eight control signals LLL to HHH shown configure the power control signal PWRC. Each of the eight control signals LLL to HHH corresponds to one of eight power control modes and can activate one of transistors A1 to A8. In the first power control mode, the first transistor A1 can be activated based on the control signal LLL, and the amplifier bias current Isum can be the reference current Iref. In the fifth power control mode, the fifth transistor A5 can be activated based on the control signal HLL, and the amplifier bias current Isum can be 5 × the reference current Iref. Similarly, in the eighth power control mode, the eighth transistor A8 can be activated based on the control signal HHH, and the amplifier bias current Isum can be 8 × the reference current Iref.

[0059] As in Figure 6 In this context, the power control signal PWRC determines the transition time for shifting the amplifier output from output buffers 330-1 to 330-n to the target voltage level TL. The transition time can be shortened as the amplifier bias current Isum increases. For example, the transition time can be t1 in the control signal HHH, t2 (t2>t1) in the control signal HLL, and t3 (t3>t2) in the control signal LLL.

[0060] Each of the output buffers 330-1 to 300-n may include: an amplifier AMP, which includes an input stage ISTG and multiple amplifier output circuits TA and TB; and multiple slew rate regulation circuits (rising current source, falling current source, SA, and SB) that generate an additional rising current Iadd-IR and an additional falling current Iadd-IF. Here, TA may be one of TA1 to TAn, TB may be one of TB1 to TBn, and AMP may be one of AMP1 to AMPn. Furthermore, Iadd-IR may be one of Iadd-IR1 to Iadd-IRn, Iadd-IF may be one of Iadd-IF1 to Iadd-IFn, SA may be one of SA1 to SAn, and SB may be one of SB1 to SBn.

[0061] The input stage ISTG can sink the bias current Isum. The input stage ISTG can be implemented using a single-ended differential amplifier, but is not limited to this. The amplifier output circuits TA and TB can apply a rising or falling current corresponding to the bias current Isum to the output node NO connected to one of the data output channels CH1 to CHn, based on the direction-of-reversal information or the vertical polarity control signal. Here, NO can be one of NO1 to NOn.

[0062] The amplifier output circuits TA and TB may include a pull-up transistor TA for supplying rising current from a high-level voltage source NH to the output node NO, and a pull-down transistor TB for supplying falling current from the output node NO to a low-level voltage source NL.

[0063] The pull-up transistor TA can be turned on for the upward transition of the data voltage and can supply rising current to the output node NO, while the pull-down transistor TB can be turned on for the downward transition of the data voltage and can supply falling current to the low-level voltage source NL.

[0064] The slew rate adjustment circuit can receive current control information CON from the control logic circuit 300. Here, CON can be one of CON1 to CONn. Based on the current control information CON, the slew rate adjustment circuit can selectively and further apply an additional rising current Iadd-IR or an additional falling current Iadd-IF to the output node NO, thereby increasing the output slew rate of the target data voltage.

[0065] The conversion rate regulation circuit may include a first additional current source that generates an additional rising current Iadd-IR, a first additional switch SA that is turned on / off based on current control information CON and controls the current flow between the first additional current source and the output node NO, a second additional current source that generates an additional falling current Iadd-IF, and a second additional switch SB that is turned on / off based on current control information CON and controls the current flow between the second additional current source and the output node NO.

[0066] Based on the current control information CON, the first auxiliary switch SA and the second auxiliary switch SB can be selectively turned on, or both can be turned off simultaneously. However, based on the current control information CON, the first auxiliary switch SA and the second auxiliary switch SB may not be turned on simultaneously.

[0067] As in Figure 7 In this configuration, when the first additional switch SA is turned on, the first additional current source and the first additional switch SA can be connected in series between the high-level voltage source NH and the output node NO. At this time, the first additional current source and the pull-up transistor TA can be connected in parallel between the high-level voltage source NH and the output node NO. Therefore, the total rising current "IR+(Iadd-IR)", which is the sum of the rising current IR based on the pull-up transistor TA and the additional rising current Iadd-IR based on the first additional current source, can be applied to the output node NO. For example, in... Figure 8In the total rising current “IR+(Iadd-IR)”, compared with the rising current IR, the transition time of the amplifier output to the first target voltage level TL1 can be reduced by more, that is, ΔT is reduced, so the output switching rate of the data voltage can be improved.

[0068] As in Figure 9 In this configuration, when the second additional switch SB is turned on, the second additional current source and the second additional switch SB can be connected in series between the low-level voltage source NL and the output node NO. At this time, the second additional current source and the pull-down transistor TB can be connected in parallel between the low-level voltage source NL and the output node NO. Therefore, the total falling current "IF+(Iadd-IF)"—the sum of the falling current IF based on the pull-down transistor TB and the additional falling current Iadd-IF based on the second additional current source—can be applied to the output node NO. For example, in... Figure 10 In the total drop current “IF+(Iadd-IF)”, compared with the drop current IF, the transition time of the amplifier output to the second target voltage level TL2 can be reduced by more, that is, ΔT is reduced, so the output slew rate of the data voltage can be improved.

[0069] As described above, in this embodiment, the amplifier bias current Isum can be set based on normal transition conditions rather than worst-case transition conditions, and additional current sources can be selectively enabled only for output channels that meet worst-case transition conditions, thereby enhancing both power consumption characteristics and data charge / discharge characteristics.

[0070] Figure 11 The diagram illustrates the operation of a timing controller that generates current control information based on the transition of image data, and the operation of an output circuit that selectively increases the output transition rate of the target data voltage based on the current control information. Figure 12 A diagram illustrating the first EPI transmission data format, which includes current control information. Figure 13 To illustrate the additional current based on included Figure 12 A diagram showing the on or off state of the clock edge information in the current control information. Figure 14 A diagram illustrating the second EPI transmission data format, which includes current control information. Figure 15 To illustrate the additional current based on included Figure 14 A diagram showing the on or off state of the clock edge information in the current control information. Figure 16 A diagram illustrating the third EPI transmission data format, which includes current control information.

[0071] refer to Figure 11In an electroluminescent display device, a timing controller can compare the (N-1)th row of image data (where N is a natural number) with the Nth row of image data through a data output channel circuit. As a result of the comparison, under the first condition that the data transition degree DATA_△ is greater than a predetermined threshold VT, a first clock edge information "10" or "0010" or a transition direction information is generated as current control information CON. As a result of the comparison, under the second condition that the data transition degree DATA_△ is less than or equal to the threshold VT, a second clock edge information "01" or "0011" and a transition direction information are generated as current control information CON (S1 to S5).

[0072] In an electroluminescent display device, the timing controller can format the current control information CON into EPI transmission data and transmit the EPI transmission data format to the source driver IC (S6). For example, in... Figure 12 and Figure 14 In this context, the first clock edge information "10" or "0010" and the second clock edge information "01" or "0011" can be implemented as delimiter information with different logic values ​​in the EPI data transmission format. This delimiter information can be located before the image data and can be implemented, for example, with 2 or 4 bits, but is not limited to these. For example, in... Figure 16 In this context, the direction change information may include several control bits from the last part of each of the R / G / B data bits in the image data located in the EPI transmission data format.

[0073] refer to Figure 11 In a liquid crystal display device, a timing controller can compare the (N-1)th row of image data (where N is a natural number) with the Nth row of image data through a data output channel circuit. As a result of the comparison, under the first condition that the data transition degree DATA_△ is greater than a predetermined threshold VT, a first clock edge information "10" or "0010" or a vertical polarity control signal is generated as current control information CON. As a result of the comparison, under the second condition that the data transition degree DATA_△ is less than or equal to the threshold VT, a second clock edge information "01" or "0011" and a vertical polarity control signal are generated as current control information CON (S1 to S5).

[0074] In a liquid crystal display device, the timing controller can format the current control information CON into EPI transmission data, and can transmit the EPI transmission data format to the source driver IC (S6). For example, in... Figure 12 and Figure 14In this context, the first clock edge information "10" or "0010" and the second clock edge information "01" or "0011" can be implemented as delimiter information with different logic values ​​using the EPI data transmission format. The delimiter information can be located before the image data and can be implemented, for example, with 2 or 4 bits, but is not limited to these. For example, in... Figure 16 In this context, the direction change information may include several control bits from the last part of each of the R / G / B data bits in the image data located in the EPI transmission data format.

[0075] refer to Figure 11 The source driver IC can receive EPI transmission data and can recover the current control information CON (S7) in the EPI transmission data.

[0076] refer to Figure 11 , such as in Figure 13 and Figure 15 In this circuit, the source driver IC can selectively turn on the additional switches in the output buffer based on the first clock edge information "10" or "0010", and can turn off all the additional switches in the output buffer based on the second clock edge information "01" or "0011".

[0077] The source driver IC can selectively turn on an additional switch of the output buffer based on transition direction information or a vertical polarity control signal. The source driver IC can turn on a first additional switch of the output buffer based on transition direction information indicating an upward transition or a vertical polarity control signal, and can turn on a second additional switch of the output buffer based on transition direction information indicating a downward transition or a vertical polarity control signal.

[0078] Figure 17 This diagram illustrates an example of current control information including clock edge information and vertical polarity control signal when the display device is a liquid crystal display device. Figure 18 This is a diagram illustrating the on or off state of the additional current of each output channel based on the logic value of the vertical polarity control signal when the clock edge information is the first clock edge information. Figure 19 This is a diagram illustrating the on or off state of the additional current of each output channel based on the logic value of the vertical polarity control signal when the clock edge information is the second clock edge information.

[0079] refer to Figure 17The clock edge information CES and the vertical polarity control signal POL can both correspond to the first output channel (e.g., CH1) and the second output channel (e.g., CH2), where different polarities (i.e., opposite polarities) are implemented in the liquid crystal display device. In this case, the selectively activated additional switches among the first additional switch for enabling the additional rising current and the second additional switch for enabling the additional falling current in the output buffers 330-1 to 330-n can be opposite in the first output channel CH1 and the second output channel CH2.

[0080] For example, as in Figure 18 In this configuration, when the first clock edge displays the information "10" or "0010" and the vertical polarity control signal POL with a high logic value H corresponds to the first output channel CH1 and the second output channel CH2, the first auxiliary switch corresponding to the first output channel CH1 and the second auxiliary switch corresponding to the second output channel CH2 can be turned on, and the second auxiliary switch corresponding to the first output channel CH1 and the first auxiliary switch corresponding to the second output channel CH2 can be turned off. In this case, an additional rising current can be enabled in the first output channel CH1, and an additional falling current can be enabled in the second output channel CH2.

[0081] Similarly, as in Figure 18 In this configuration, when the first clock edge displays the information "10" or "0010" and the vertical polarity control signal POL with a low logic value L corresponds to the first output channel CH1 and the second output channel CH2, the second auxiliary switch corresponding to the first output channel CH1 and the first auxiliary switch corresponding to the second output channel CH2 can be turned on, and the first auxiliary switch corresponding to the first output channel CH1 and the second auxiliary switch corresponding to the second output channel CH2 can be turned off. In this case, an additional falling current can be enabled in the first output channel CH1, and an additional rising current can be enabled in the second output channel CH2.

[0082] In addition, such as in Figure 19 When the second clock edge information "01" or "0011" corresponds to the first output channel CH1 and the second output channel CH2, all additional switches corresponding to the first output channel CH1 and the second output channel CH2 can be turned off, regardless of the vertical polarity control signal POL. In this case, additional current can be disabled in the first output channel CH1 and the second output channel CH2.

[0083] Figure 20 and Figure 21 A graph showing the rate of reduction in transition time before and after applying this disclosure in each of the various power control modes.

[0084] refer to Figure 20and Figure 21 In this embodiment, the additional current source can be selectively enabled only for output channels that meet the worst transition condition (where the data transition degree is greater than a threshold). Therefore, the transition time of the corresponding output channel can be reduced, thereby increasing the output conversion rate of the target data voltage.

[0085] The embodiments disclosed herein can achieve the following effects.

[0086] In embodiments of this disclosure, the amplifier bias current Isum can be set based on normal transition conditions rather than worst-case transition conditions, and additional current sources can be selectively enabled only for output channels that meet worst-case transition conditions, thereby enhancing both power consumption characteristics and data charge / discharge characteristics.

[0087] In embodiments of this disclosure, the dynamic current of the source driver IC can be reduced because additional current sources are selectively enabled only for output channels with high data transition rates.

[0088] In embodiments of this disclosure, the additional current source of the individual output buffer can be controlled by using the clock edge in the EPI protocol, thus avoiding the overhead of the EPI data transmission format.

[0089] The effects of this disclosure are not limited to the examples described above, and various other effects may be included in the specification.

[0090] Although this disclosure has been specifically shown and described with reference to exemplary embodiments thereof, those skilled in the art will understand that various changes may be made to the form and details of this disclosure without departing from the spirit and scope of this disclosure as set forth in the following claims.

Claims

1. A display device, comprising: The display panel includes multiple pixels; A timing controller is configured to generate current control information based on the degree of transition of image data applied to corresponding pixels among the plurality of pixels; as well as Multiple output buffers are configured to output target data voltages corresponding to the image data to data output channels connected to the multiple pixels. Each of the output buffers includes: The amplifier output circuit is configured to apply a pre-set rising or falling current for outputting the target data voltage to an output node connected to one of the data output channels; and A slew rate regulation circuit is configured to selectively and further apply an additional rising current or an additional falling current to the output node based on the current control information, thereby increasing the output slew rate of the target data voltage. Specifically, a first clock edge is generated under the condition that the transition degree of the image data is greater than a threshold, and a first additional switch and a second additional switch included in the conversion rate adjustment circuit are selectively turned on based on the first clock edge information to apply the additional rising current or the additional falling current to the output node. A second clock edge information is generated under the second condition that the degree of transition of the image data is less than or equal to the threshold, and both the first additional switch and the second additional switch are turned off based on the second clock edge information.

2. The display device according to claim 1, wherein, The amplifier output circuit includes: A pull-up transistor is configured to supply the rising current from a high-level voltage source to the output node; and The pull-down transistor is configured to channel the decreasing current from the output node into a low-level voltage source.

3. The display device according to claim 2, wherein, The conversion rate adjustment circuit includes: A first additional current source is configured to generate the additional rising current; and A second additional current source is configured to generate the additional falling current; The first additional switch is configured to control the current flow between the first additional current source and the output node, and the second additional switch is configured to control the current flow between the second additional current source and the output node.

4. The display device according to claim 3, wherein, The first additional current source and the first additional switch are connected in series between the high-level voltage source and the output node, and The second additional current source and the second additional switch are connected in series between the output node and the low-level voltage source.

5. The display device according to claim 3, wherein, When the first additional switch is turned on The pull-up transistor and the first additional current source are connected in parallel between the high-level voltage source and the output node, and The total rising current, which is the sum of the rising current and the additional rising current, is applied to the output node.

6. The display device according to claim 3, wherein, When the second auxiliary switch is turned on The pull-down transistor and the second additional current source are connected in parallel between the output node and the low-level voltage source, and The total drop current, which is the sum of the drop current and the additional drop current, is applied to the output node.

7. The display device according to claim 1, wherein, The timing controller compares the (N-1)th (where N is a natural number)th row of image data with the Nth row of image data according to the data output channel unit. As the result of the comparison, under the first condition that the data transition degree is greater than a threshold, the first clock edge information and transition direction information are generated as the current control information. Furthermore, as a result of the comparison, under the second condition that the data transition degree is less than or equal to the threshold, the second clock edge information and the transition direction information are generated as the current control information. The first and second auxiliary switches are selectively turned on based on the first clock edge information and the change direction information, and regardless of the change direction information, the first and second auxiliary switches are turned off based on the second clock edge information.

8. The display device according to claim 7, wherein, The direction change information includes first state information indicating an upward change and second state information indicating a downward change. Based on the first clock edge information and the first status information, the first auxiliary switch is turned on and the second auxiliary switch is turned off, and Based on the first clock edge information and the second status information, the first auxiliary switch is turned off and the second auxiliary switch is turned on.

9. The display device according to claim 7, further comprising a source driver integrated circuit including the plurality of output buffers, in, The timing controller transmits the current control information to the source driver integrated circuit via an embedded panel interface (EPI) data transmission format, and The first clock edge information and the second clock edge information are implemented as delimiter information with different logic values ​​in the EPI transmission data format.

10. The display device according to claim 1, wherein, The plurality of pixels are configured as liquid crystal cells that selectively implement a first polarity and a second polarity. The timing controller also generates a vertical polarity control signal for controlling the polarity of the liquid crystal cell. The timing controller compares the (N-1)th (where N is a natural number)th row of image data with the Nth row of image data according to the data output channel unit. As the result of the comparison, under the first condition that the data transition degree is greater than a threshold, the controller generates the first clock edge information and the vertical polarity control signal as the current control information. Furthermore, as a result of the comparison, under the second condition that the data transition degree is less than or equal to the threshold, the second clock edge information and the vertical polarity control signal are generated as the current control information. The first and second auxiliary switches are selectively turned on based on the first clock edge information and the vertical polarity control signal, and regardless of the vertical polarity control signal, the first and second auxiliary switches are turned off based on the second clock edge information.

11. The display device according to claim 10, wherein, When the first clock edge information and the vertical polarity control signal together correspond to the first output channel and the second output channel implementing different polarities, the auxiliary switches that are selectively turned on in the first auxiliary switch and the second auxiliary switch are opposite in the first output channel and the second output channel.

12. The display device according to claim 11, wherein, When the first clock edge information and the vertical polarity control signal with a high logic value correspond to the first output channel and the second output channel, the first additional switch corresponding to the first output channel and the second additional switch corresponding to the second output channel are turned on, and the second additional switch corresponding to the first output channel and the first additional switch corresponding to the second output channel are turned off.

13. The display device according to claim 11, wherein, When the first clock edge information and the vertical polarity control signal with a low logic value correspond to the first output channel and the second output channel, the second additional switch corresponding to the first output channel and the first additional switch corresponding to the second output channel are turned on, and the first additional switch corresponding to the first output channel and the second additional switch corresponding to the second output channel are turned off.

14. The display device of claim 1, further comprising a main bias circuit configured to determine the level of the amplifier bias current based on a power control signal. in, The levels of the rising current and the falling current are proportional to the level of the amplifier bias current.

15. A driving method for a display device, the driving method comprising: Current control information is generated based on the degree of transformation of the image data applied to the pixels; as well as The target data voltage corresponding to the image data is output to the data output channel connected to the pixel. The output of the target data voltage includes: A pre-set rising or falling current for outputting the target data voltage is applied to an output node connected to one of the data output channels; and Based on the current control information, an additional rising current or an additional falling current is selectively and further applied to the output node to increase the output conversion rate of the target data voltage. Specifically, a first clock edge is generated under the condition that the transition degree of the image data is greater than a threshold, and the additional rising current or the additional falling current is selectively applied to the output node based on the first clock edge information. A second clock edge information is generated under the second condition that the transition degree of the image data is less than or equal to the threshold, and based on the second clock edge information, neither the additional rising current nor the additional falling current is applied to the output node.

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