Display device

Abstract

The present invention relates to a display device, in which a stable display operation is realized. A display device comprises: a first transistor having an oxide semiconductor layer, a first gate electrode opposite to the oxide semiconductor layer, and a first gate insulating layer between the oxide semiconductor layer and the first gate electrode; a first transparent conductive layer disposed above the first transistor; a second transparent conductive layer disposed above the first transparent conductive layer, insulated from the first transparent conductive layer, and opposite to the first transparent conductive layer; and a third transparent conductive layer disposed above the second transparent conductive layer, insulated from the second transparent conductive layer, connected to the first transparent conductive layer, and opposite to the second transparent conductive layer.

Description

Technical Field

[0001] One embodiment of the present invention relates to a display device. In particular, one embodiment of the present invention relates to a display device using a transistor including an oxide semiconductor. Background Art

[0002] Recently, transistors using oxide semiconductors for channels instead of amorphous silicon, low-temperature polysilicon, and single-crystal silicon are being developed (for example, Patent Documents 1 and 2). Transistors using oxide semiconductors for channels are the same as transistors using amorphous silicon for channels, and are formed by a simple structure and a low-temperature process. Transistors using oxide semiconductors for channels are known to have higher mobility than transistors using amorphous silicon for channels, and have very low off-state current.

[0003] In recent years, in order to further improve the resolution of display devices, the pixel size has been continuously reduced. As the pixel size is reduced, the reduction of wiring width and transistor size has been explored. However, their reduction is limited, and the configuration of the metal layer and semiconductor layer constituting the pixel circuit leads to a smaller aperture ratio. Therefore, development is underway to use transistors in the channel using an oxide semiconductor layer that can obtain characteristics sufficient to drive the pixel circuit even if the transistor size is small for the pixel circuit.

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Publication No. 2014-146819

[0007] Patent Document 2: Japanese Patent Application Publication No. 2015-159315 Summary of the invention

[0008] Technical problem to be solved by the invention

[0009] As the pixel size decreases, the area for configuring the capacitor element used in the pixel circuit is limited. Therefore, it is difficult to form a capacitor element large enough to drive the pixel circuit. Under this influence, the charge retention characteristics in the pixel circuit are reduced, and the display operation of the display device becomes unstable.

[0010] One of the problems of one embodiment of the present invention is to realize a stable display operation in a display device.

[0011] Technical solutions for solving technical problems

[0012] A display device involved in one embodiment of the present invention comprises: a first transistor, comprising an oxide semiconductor layer, a first gate electrode opposite to the oxide semiconductor layer, and a first gate insulating layer between the oxide semiconductor layer and the first gate electrode; a first transparent conductive layer, arranged above the first transistor; a second transparent conductive layer, arranged above the first transparent conductive layer, insulated from the first transparent conductive layer, and opposite to the first transparent conductive layer; and a third transparent conductive layer, arranged above the second transparent conductive layer, insulated from the second transparent conductive layer, connected to the first transparent conductive layer, and opposite to the second transparent conductive layer.

[0013] A display device involved in one embodiment of the present invention comprises: a first transistor, comprising an oxide semiconductor layer, a first gate electrode opposite to the oxide semiconductor layer, and a first gate insulating layer between the oxide semiconductor layer and the first gate electrode; a first transparent conductive layer, arranged above the first transistor; a second transparent conductive layer, arranged above the first transparent conductive layer, insulated from the first transparent conductive layer, and overlapping with the first transparent conductive layer in a light-transmitting area of ​​a pixel; and a third transparent conductive layer, arranged above the second transparent conductive layer, insulated from the second transparent conductive layer, connected to the first transparent conductive layer, and overlapping with the second transparent conductive layer in the light-transmitting area. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 This is a cross-sectional view schematically showing a display device according to an embodiment of the present invention.

[0015] Figure 2 It is a plan view schematically showing a display device according to one embodiment of the present invention.

[0016] Figure 3 It is a plan view illustrating the layout of each layer in the display device according to one embodiment of the present invention.

[0017] Figure 4 It is a plan view illustrating the layout of each layer in the display device according to one embodiment of the present invention.

[0018] Figure 5 It is a plan view illustrating the layout of each layer in the display device according to one embodiment of the present invention.

[0019] Figure 6 It is a plan view illustrating the layout of each layer in the display device according to one embodiment of the present invention.

[0020] Figure 7It is a plan view illustrating the layout of each layer in the display device according to one embodiment of the present invention.

[0021] Figure 8 It is a plan view illustrating the layout of each layer in the display device according to one embodiment of the present invention.

[0022] Fig. 9 It is a plan view illustrating the layout of each layer in the display device according to one embodiment of the present invention.

[0023] Fig.10 It is a plan view illustrating the layout of each layer in the display device according to one embodiment of the present invention.

[0024] Fig.11 It is a plan view illustrating the layout of each layer in the display device according to one embodiment of the present invention.

[0025] Fig.12 It is a plan view illustrating the layout of each layer in the display device according to one embodiment of the present invention.

[0026] Fig.13 It is a plan view illustrating the layout of each layer in the display device according to one embodiment of the present invention.

[0027] Fig.14 It is a plan view illustrating the layout of each layer in the display device according to one embodiment of the present invention.

[0028] Fig.15 It is a plan view schematically showing a display device according to one embodiment of the present invention.

[0029] Fig.16 This is a block diagram showing a circuit configuration of a display device according to an embodiment of the present invention.

[0030] Fig.17 : is a circuit diagram showing a pixel circuit of a display device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0031] Below, various embodiments of the present invention are described with reference to the accompanying drawings. The following disclosure is for illustrative purposes only. Configurations that are easily conceivable by those skilled in the art by appropriately changing the configuration of the embodiment while maintaining the gist of the invention are of course also included in the scope of the present invention. In the accompanying drawings, in order to explain more clearly, the width, thickness, shape, etc. of each part may be only schematically shown compared to the actual scheme. However, the shapes shown in the drawings are only examples and do not limit the interpretation of the present invention. In this specification and the various figures, as the same configuration as the aforementioned configuration described in the already mentioned figures, Arabic letters are placed after the same symbols, and detailed descriptions may be appropriately omitted.

[0032] In various embodiments of the present invention, the direction from the substrate to the oxide semiconductor layer is referred to as up or above. Conversely, the direction from the oxide semiconductor layer to the substrate is referred to as down or below. In this way, for the convenience of explanation, although the expressions above or below are used for explanation, for example, the up-and-down relationship between the substrate and the oxide semiconductor layer can also be configured in a different direction from the diagram. In the following description, as described above, for example, the expression of the oxide semiconductor layer on the substrate only illustrates the up-and-down relationship between the substrate and the oxide semiconductor layer, and other components can also be configured between the substrate and the oxide semiconductor layer. Above or below indicates the stacking order in a structure formed by stacking multiple layers, and in the case of expressing the pixel electrode above the transistor, it can also be a positional relationship in which the transistor and the pixel electrode do not overlap when viewed from above. On the other hand, in the case of expressing the pixel electrode vertically above the transistor, it indicates the positional relationship in which the transistor and the pixel electrode overlap when viewed from above.

[0033] A "display device" refers to a structure that uses a photoelectric layer to display an image. For example, the term display device sometimes refers to a display panel including a photoelectric layer, or a structure in which other optical components (for example, a polarizing component, a backlight, a touch panel, etc.) are installed on a display unit. As long as it does not cause a technical conflict, the "photoelectric layer" may include a liquid crystal layer, an electroluminescent (EL) layer, an electrochromic (EC) layer, and an electrophoretic layer. Therefore, in the embodiments described below, as a display device, a liquid crystal display device including a liquid crystal layer is described as an example, but the structure in this embodiment can also be applied to a display device including other photoelectric layers mentioned above.

[0034] In this specification, unless otherwise specified, the expressions “α includes A, B or C”, “α includes any one of A, B and C”, and “α includes one selected from the group consisting of A, B and C” do not exclude the case where α includes multiple combinations of A to C. Furthermore, these expressions do not exclude the case where α includes other elements.

[0035] It should be noted that the following implementation modes can be combined with each other as long as no technical conflict occurs.

[0036] [1. First Implementation Method]

[0037] [1-1. Configuration of Display Device 10]

[0038] use Figure 1 to Figure 14 The configuration of a display device 10 according to one embodiment of the present invention will be described. Figure 1 This is a cross-sectional view schematically showing a display device according to an embodiment of the present invention. Figure 2 It is a plan view schematically showing a display device according to one embodiment of the present invention. Figure 3 to Figure 14 It is a plan view illustrating the layout of each layer in the display device according to one embodiment of the present invention. Figure 1 The cross-sectional view is a cross-sectional view used to illustrate the layer structure of the display device 10, and is sometimes also used in conjunction with Figure 2 The top view is not completely consistent.

[0039] like Figure 1 As shown, the display device 10 is arranged above the substrate SUB. The display device 10 has a transistor Tr1, a transistor Tr2 (Tr2-1, Tr2-2), wiring W (W1, W2), a connecting electrode ZTCO, a pixel electrode PTCO1, a common auxiliary electrode CMTL, a common electrode CTCO, and a pixel electrode PTCO2. TCO is an abbreviation of Transparent Conductive Oxide. The transistor Tr1 is a transistor (for example, a selection transistor) included in the pixel circuit of the display device 10. The transistor Tr2 is a transistor included in the peripheral circuit. The peripheral circuit is a driving circuit that drives the pixel circuit, and the details will be described below.

[0040] [1-2. Configuration of transistor Tr1]

[0041] The transistor Tr1 has an oxide semiconductor layer OS (OS1, OS2), a gate insulating layer GI1, and a gate electrode GL1. The gate electrode GL1 is opposite to the oxide semiconductor layer OS. The gate insulating layer GI1 is provided between the oxide semiconductor layer OS and the gate electrode GL1. In the present embodiment, a top-gate transistor is illustrated in which an oxide semiconductor layer OS is provided on the substrate SUB side relative to the gate electrode GL1 in a pixel circuit provided in a display area, but a bottom-gate transistor in which the positional relationship between the gate electrode GL1 and the oxide semiconductor layer OS is opposite may also be used. The gate insulating layer GI1 is sometimes referred to as a "first gate insulating layer". The gate electrode GL1 is sometimes referred to as a "first gate electrode".

[0042] The oxide semiconductor layer OS includes oxide semiconductor layers OS1 and OS2. The oxide semiconductor layer OS1 is an oxide semiconductor layer in a region overlapping with the gate electrode GL1 when viewed from above. The oxide semiconductor layer OS1 functions as a semiconductor layer, and switches between a conductive state and a non-conductive state according to a voltage supplied to the gate electrode GL1. That is, the oxide semiconductor layer OS1 functions as a channel of the transistor Tr1. The oxide semiconductor layer OS2 functions as a conductive layer. The oxide semiconductor layers OS1 and OS2 are layers formed of the same oxide semiconductor layer. For example, the oxide semiconductor layer OS2 is an oxide semiconductor layer whose resistance is reduced by doping impurities in a layer having the same physical properties as the oxide semiconductor layer OS1.

[0043] The insulating layer IL2 is provided on the gate electrode GL1. The wiring W1 is provided on the insulating layer IL2. The wiring W1 is connected to the oxide semiconductor layer OS2 via an opening WCON provided in the insulating layer IL2 and the gate insulating layer GI1. A data signal related to the grayscale of the pixel is transmitted to the wiring W1 connected to the oxide semiconductor layer OS2. The insulating layer IL3 is provided on the insulating layer IL2 and the wiring W1.

[0044] The connection electrode ZTCO is provided on the insulating layer IL3. The connection electrode ZTCO is connected to the oxide semiconductor layer OS2 via an opening ZCON provided in the insulating layers IL3, IL2, and the gate insulating layer GI1. The connection electrode ZTCO is in contact with the oxide semiconductor layer OS2 at the bottom of the opening ZCON. The connection electrode ZTCO is a transparent conductive layer.

[0045] The area where the connection electrode ZTCO is in contact with the oxide semiconductor layer OS2 is called the first contact area CON1. ​​The connection electrode ZTCO is sometimes called the "fourth transparent conductive layer". The details will be described below. When viewed from above, the connection electrode ZTCO includes: a portion (first portion PT1) overlapping with the gate electrode GL1 and the oxide semiconductor layer OS1, and a portion (second portion PT2) in the first contact area CON1 that does not overlap with the gate electrode GL1 and the wiring W1 and is in contact with the oxide semiconductor layer OS2 (see Fig. 9 ). When viewed from above, the first contact area CON1 is included in the display area (light-transmitting area) of the pixel.

[0046] As described above, in the first contact area CON1, the connecting electrode ZTCO is directly connected to the oxide semiconductor layer OS2. After a transparent conductive layer such as an ITO layer is formed in contact with a semiconductor layer such as a silicon layer, the surface of the semiconductor layer is oxidized by the process gas and oxygen ions during the ITO film formation. The resistance of the oxide layer formed on the surface of the semiconductor layer is high, so the contact resistance between the semiconductor layer and the transparent conductive layer becomes high. As a result, the electrical contact between the semiconductor layer and the transparent conductive layer fails. On the other hand, even if the above-mentioned transparent conductive layer is formed in contact with the oxide semiconductor layer, a high-resistance oxide layer as described above will not be formed on the surface of the oxide semiconductor layer. Therefore, the electrical contact between the oxide semiconductor layer and the transparent conductive layer will not fail.

[0047] The insulating layer IL4 is provided on the connecting electrode ZTCO. A height difference is formed by a structure provided at a lower layer than the insulating layer IL4. The insulating layer IL4 mitigates the height difference. The insulating layer IL4 is sometimes referred to as a planarization film. The pixel electrode PTCO1 is provided on the insulating layer IL4. That is, the pixel electrode PTCO1 is provided above the transistor Tr1. The opening PCON is provided in the insulating layer IL4. The pixel electrode PTCO1 is connected to the connecting electrode ZTCO via the opening PCON. The area where the connecting electrode ZTCO and the pixel electrode PTCO1 are connected is referred to as the second contact area CON2. When viewed from above, the second contact area CON2 overlaps with the gate electrode GL1 (see Fig.10 ). More specifically, when viewed from above, the second contact region CON2 overlaps with the pattern end of the gate electrode GL1. The pixel electrode PTCO1 is a transparent conductive layer. In the above-mentioned configuration, the pixel electrode PTCO1 is connected to the transistor Tr1 via the connecting electrode ZTCO. The pixel electrode PTCO1 is sometimes referred to as a "first transparent conductive layer".

[0048] The insulating layer PIL1 is disposed on the pixel electrode PTCO1. The common auxiliary electrode CMTL and the common electrode CTCO are disposed on the insulating layer PIL1. The common electrode CTCO is insulated from the pixel electrode PTCO1 and is opposite to the pixel electrode PTCO1. The common electrode CTCO is disposed in a manner common to a plurality of pixels. The details will be described below. In this embodiment, the common electrode CTCO is disposed in a manner common to the pixels arranged in the row direction (see Fig.13 ). Sometimes the common electrode CTCO is referred to as a "second transparent conductive layer". The details will be described below. The common auxiliary electrode CMTL and the common electrode CTCO have different planar patterns (see Fig.12 and Fig.13 ).

[0049] The common auxiliary electrode CMTL is a metal layer. The common electrode CTCO is a transparent conductive layer. The resistance of the common auxiliary electrode CMTL is smaller than the resistance of the common electrode CTCO. The common auxiliary electrode CMTL also functions as a light shielding layer. In the above-mentioned configuration, above the transistor Tr1, a light shielding layer (common auxiliary electrode CMTL) is provided to limit the respective regions of a plurality of pixels. The light shielding layer suppresses the occurrence of color mixing by blocking light from adjacent pixels. In addition, the common auxiliary electrode CMTL has the same function as the common electrode CTCO. Therefore, the common auxiliary electrode CMTL and the common electrode CTCO are sometimes collectively referred to as "common electrodes".

[0050] The insulating layer PIL2 is disposed on the common electrode CTCO. The pixel electrode PTCO2 is disposed on the insulating layer PIL2. The pixel electrode PTCO2 is insulated from the common electrode CTCO and is opposite to the common electrode CTCO. The pixel electrode PTCO2 is connected to the pixel electrode PTCO1 via an opening ACON disposed in the insulating layers PIL1 and PIL2. The pixel electrode PTCO2 is sometimes referred to as a "third transparent conductive layer". The area where the pixel electrode PTCO2 is connected to the pixel electrode PTCO1 is referred to as a third contact area CON3. When viewed from above, the third contact area CON3 does not overlap with the common auxiliary electrode CMTL (see Fig.12 ). That is, the pixel electrode PTCO2 is in contact with the pixel electrode PTCO1 in the light-transmitting region of the pixel.

[0051] As described above, between the opposing pixel electrode PTCO1 and the common electrode (common electrode CTCO and common auxiliary electrode CMTL), a first capacitor element CAP1 having an insulating layer PIL1 is formed as a dielectric. Between the opposing pixel electrode PTCO2 and the common electrode (common electrode CTCO and common auxiliary electrode CMTL), a second capacitor element CAP2 having an insulating layer PIL2 is formed as a dielectric. The first capacitor element CAP1 is stacked with the second capacitor element CAP2. The details will be described below. When viewed from above, the first capacitor element CAP1 overlaps with the second capacitor element CAP2 (see FIG. 1 ). Fig.14 ). These capacitor elements function as holding capacitors in the pixel circuit.

[0052] The spacer SP is disposed on the pixel electrode PTCO2. The spacer SP is disposed for some pixels. For example, the spacer SP may be disposed for any one of the blue pixel, the red pixel, and the green pixel. The spacer SP may also be disposed for all pixels. The height of the spacer SP is half the height of the liquid crystal box. It should be noted that the spacer is also disposed on the opposing substrate, and when viewed from above, the spacer of the opposing substrate overlaps with the above-mentioned spacer SP.

[0053] A light shielding layer LS is provided between the transistor Tr1 and the substrate SUB. In the present embodiment, light shielding layers LS1 and LS2 are provided as the light shielding layer LS. The light shielding layer LS may also be formed by only the light shielding layer LS1 or only the light shielding layer LS2. When viewed from above, the light shielding layer LS is provided in the region where the gate electrode GL1 overlaps with the oxide semiconductor layer OS. That is, when viewed from above, the light shielding layer LS is provided in the region where the gate electrode GL1 overlaps with the oxide semiconductor layer OS1 (see FIG. Figure 5 ). The light shielding layer LS prevents light incident from the substrate SUB side from reaching the oxide semiconductor layer OS1. When a conductive layer is used as the light shielding layer LS, a voltage can be applied to the light shielding layer LS to control the oxide semiconductor layer OS1. When a voltage is applied to the light shielding layer LS, the light shielding layer LS and the gate electrode GL1 can be connected in the peripheral area of ​​the pixel circuit. When viewed from above, the first contact area CON1 is provided in an area that does not overlap with the light shielding layer LS (see Figure 2 ).

[0054] [1-3. Configuration of transistor Tr2]

[0055] The transistor Tr2 includes a p-type transistor Tr2 - 1 and an n-type transistor Tr2 - 2 .

[0056] The p-type transistor Tr2-1 and the n-type transistor Tr2-2 both have a gate electrode GL2, a gate insulating layer GI2, and a semiconductor layer S (S1, S2, S3). The gate electrode GL2 is opposite to the semiconductor layer S. The gate insulating layer GI2 is provided between the semiconductor layer S and the gate electrode GL2. In this embodiment, as the transistor Tr2 used in these peripheral circuits, a bottom-gate transistor having a gate electrode GL2 closer to the substrate SUB side than the semiconductor layer S is exemplified, but a top-gate transistor having a reverse positional relationship between the semiconductor layer S and the gate electrode GL2 may also be used. The gate electrode GL2 is sometimes referred to as a "second gate electrode". The gate insulating layer GI2 is sometimes referred to as a "second gate insulating layer".

[0057] The semiconductor layer S of the p-type transistor Tr2-1 includes semiconductor layers S1 and S2. The semiconductor layer S of the n-type transistor Tr2-2 includes semiconductor layers S1, S2, and S3. The semiconductor layer S1 is a semiconductor layer in a region overlapping with the gate electrode GL2 when viewed from above. The semiconductor layer S1 functions as a channel of the transistors Tr2-1 and Tr2-1. The semiconductor layer S2 functions as a conductive layer. The semiconductor layer S3 functions as a conductive layer having a higher resistance than the semiconductor layer S2. The semiconductor layer S3 suppresses hot carrier degradation by attenuating hot carriers invading toward the semiconductor layer S1.

[0058] The insulating layer IL1 and the insulating layer IL5 are provided on the semiconductor layer S. The insulating layer IL5 is the same layer as the gate insulating layer GI1 of the transistor Tr1. That is, the insulating layer IL5 is directly continuous with the gate insulating layer GI1 without an interface. The wiring W2 is provided on the insulating layer IL5. The wiring W2 is connected to the semiconductor layer S2 via openings provided in the insulating layer IL1 and the insulating layer IL5. The insulating layer IL2 is provided on the wiring W2. The wiring W1 is provided on the insulating layer IL2. The wiring W1 is connected to the wiring W2 via an opening provided in the insulating layer IL2. The insulating layer IL5 is sometimes referred to as the "first insulating layer".

[0059] The gate electrode GL2 and the light shielding layer LS2 are the same layer. The wiring W2 and the gate electrode GL1 are the same layer. The same layer means that multiple components arranged at different positions on the substrate are components formed by the same process. Therefore, multiple components described as the same layer are made of the same material and are connected to a common layer. The same material means that the multiple components are formed of the same single material. Alternatively, it means that when the multiple components are formed by stacking multiple layers, the materials of the multiple layers are the same, and the stacking structure of the multiple layers is also the same.

[0060] Figure 1 In the embodiment, the gate electrode GL2 and the light shielding layer LS2 are connected to the gate insulating layer GI2. The wiring W2 and the gate electrode GL1 are connected to the gate insulating layer GI1 and the insulating layer IL5. In other words, the gate electrode GL2 and the light shielding layer LS2 are connected to a layer or component that is continuous without an interface. Similarly, the wiring W2 and the gate electrode GL1 are connected to a layer or component that is continuous without an interface.

[0061] [1-4. Planar Layout of Display Device 10]

[0062] use Figure 2 to Figure 14 The planar layout of pixels of the display device 10 will be described. Figure 2 In the figure, the pixel electrodes PTCO1, PTCO2, the common auxiliary electrode CMTL, the common electrode CTCO and the spacer SP are omitted. Their planar layouts are shown in FIG. Figure 11 to Figure 14 .

[0063] like Figure 2 and Figure 3 As shown in FIG. 1 , the light shielding layer LS extends in the direction D1. The shape of the light shielding layer LS varies depending on the pixel. In this embodiment, a protrusion PJT is provided that protrudes from a portion of the light shielding layer LS extending in the direction D1 toward the direction D2. Figure 5 As shown in FIG. 1 , the light shielding layer LS is provided in a region including a region where the gate electrode GL1 overlaps with the oxide semiconductor layer OS in a plan view. The gate electrode GL1 may also be referred to as a “gate line”.

[0064] like Figure 2 , Figure 4 and Figure 5 As shown, the oxide semiconductor layer OS extends in the direction D2. The gate electrode GL1 extends in the direction D1 in a manner intersecting the oxide semiconductor layer OS. The pattern of the gate electrode GL1 is provided inside the pattern of the light shielding layer LS. In other words, the oxide semiconductor layer OS is formed in a strip shape intersecting the gate electrode GL1.

[0065] like Figure 2 , Figure 6 and Figure 7 As shown, the opening WCON is provided in a region overlapping with the wiring W1 (W1-1, W1-2) near the upper end of the pattern of the oxide semiconductor layer OS. The main portion of the pattern of the oxide semiconductor layer OS extends along the D2 direction between adjacent wirings W1 (between W1-1 and W1-2). The remaining portion of the pattern of the oxide semiconductor layer OS extends from the main portion in a direction inclined relative to the D1 direction and the D2 direction, and overlaps with the opening WCON.

[0066] like Figure 2 and Figure 7 As shown, a plurality of wirings W1 extend in the D2 direction. When it is necessary to distinguish adjacent wirings W1 for explanation, the adjacent wirings W1 are referred to as wirings W1-1 (first wiring) and wirings W1-2 (second wiring). In this case, a main portion of the oxide semiconductor layer OS extends in the D2 direction between the first wiring W1-1 and the second wiring W1-2, and may intersect the gate electrode GL1. With respect to the above-mentioned configuration, the oxide semiconductor layer OS is provided in a strip shape (a shape having long sides) in the D2 direction, and is connected to the wiring W1-1 (first wiring) at one end of the oxide semiconductor layer OS in the long side direction.

[0067] like Figure 2 , Figure 8 and Fig. 9 As shown, the opening ZCON is provided near the lower end of the pattern of the oxide semiconductor layer OS. The opening ZCON is provided in a region overlapping with the pattern of the oxide semiconductor layer OS and in a region not overlapping with the gate electrode GL1. The opening ZCON is provided in a region overlapping with the connection electrode ZTCO. The first portion PT1 of the connection electrode ZTCO overlaps with the gate electrode GL1 and the oxide semiconductor layer OS between the first wiring W1-1 and the second wiring W1-2. Thus, the second portion PT2 of the connection electrode ZTCO is in contact with the oxide semiconductor layer OS at the opening ZCON (first contact region CON1) not overlapping with the gate electrode GL1 and the wiring W1.

[0068] In the above configuration, the oxide semiconductor layer OS is connected to the connection electrode ZTCO at the other end of the oxide semiconductor layer OS in the long side direction. The connection electrode ZTCO is formed in a strip shape extending along the D2 direction like the oxide semiconductor layer OS. In the D1 direction, the width of the connection electrode ZTCO is smaller than the width of the oxide semiconductor layer OS.

[0069] like Figure 2 , Figure 7 and Figure 8 As shown, the oxide semiconductor layer OS is in contact with the wiring W1 on the opposite side of the opening ZCON with respect to the gate electrode GL1. The opening ZCON does not overlap with the light shielding layer LS.

[0070] like Figure 2 , Fig.10 and Fig.11 As shown, the opening PCON is provided near the upper end of the pattern of the connecting electrode ZTCO. The opening PCON is provided in an area including the pattern end of the gate electrode GL1. Similarly, the opening PCON is provided in an area including the pattern end of the connecting electrode ZTCO. In other words, the opening PCON is provided in an area overlapping with the patterns of both the gate electrode GL1 and the connecting electrode ZTCO, an area overlapping with only the pattern of the gate electrode GL1, or an area overlapping with only the pattern of the connecting electrode ZTCO, and an area not overlapping with either the pattern of the gate electrode GL1 or the connecting electrode ZTCO. The opening PCON is provided for each pixel. In detail, the opening PCON is provided in an area overlapping with the pixel electrode PTCO1. The pixel electrode PTCO1 overlaps with a portion of the gate electrode GL1, a portion of the oxide semiconductor layer OS, and the connecting electrode ZTCO between the wiring W1-1 and the wiring W1-2. Thus, the pixel electrode PTCO1 is connected to the connecting electrode ZTCO at the opening PCON (second contact area CON2).

[0071] The pixel electrode PTCO1 extends to the light-transmitting area described below. In the above-mentioned configuration, the pixel electrode PTCO1 is formed into a strip extending along the D2 direction similarly to the oxide semiconductor layer OS and the wiring W1-1 (first wiring). In the D1 direction, the width of the pixel electrode PTCO1 on the portion where the opening PCON is provided is greater than the width of the oxide semiconductor layer OS.

[0072] like Fig.11 As shown, the connection electrode ZTCO is formed in a strip shape extending along the wiring W1-1. In the D1 direction, the width of the opening PCON constituting the second contact region CON2 is larger than the width of the connection electrode ZTCO. In a plan view, the connection electrode ZTCO entirely overlaps with the pixel electrode PTCO1.

[0073] like Fig.11As shown, the pixel electrodes PTCO1 are arranged along the direction D2. Sometimes, one of the pixels adjacent to each other in the direction D2 is referred to as a "first pixel" and the other pixel is referred to as a "second pixel". For example, the first pixel is adjacent to Fig.11 The first pixel corresponds to the upper pixel electrode PTCO1 of the pixel electrodes PTCO1 arranged along the D2 direction, and the second pixel corresponds to the lower pixel electrode PTCO1 of the pixel electrodes PTCO1 arranged along the D2 direction. In this case, pixel signals are provided from the wiring W1-1 to the first pixel and the second pixel.

[0074] In addition, the pixel electrode PTCO1 is arranged along the D1 direction. The pixel adjacent to the first pixel in the D1 direction is called the "third pixel", and the pixel adjacent to the second pixel in the D1 direction is called the "fourth pixel". The third pixel and the fourth pixel are adjacent in the D2 direction. The pixel signal is provided to the third pixel and the fourth pixel from the wiring W1-2 (second wiring) adjacent to the wiring W1-1.

[0075] As described above, the first pixel, the second pixel, the third pixel, and the fourth pixel each include the transistor Tr1 (pixel transistor), the connection electrode ZTCO, and the pixel electrode PTCO1.

[0076] The transistor Tr1 includes an oxide semiconductor layer OS, a gate electrode GL1 opposite to the oxide semiconductor layer OS, and a gate insulating layer GI1 between the oxide semiconductor layer OS and the gate electrode GL1. When viewed from above, the connection electrode ZTCO overlaps with the gate electrode GL1 and the oxide semiconductor layer OS, and is connected to the oxide semiconductor layer OS at an opening ZCON (first contact area CON1) that does not overlap with the gate electrode GL1. When viewed from above, the pixel electrode PTCO1 overlaps with the gate electrode GL1, the oxide semiconductor layer OS, and the connection electrode ZTCO, and is connected to the connection electrode ZTCO at an opening PCON (second contact area CON2) that overlaps with the gate electrode GL1.

[0077] When looking down, Fig.11 The pixel electrode PTCO1 of the first pixel on the upper side overlaps the oxide semiconductor layer OS of the first pixel and the oxide semiconductor layer OS of the second pixel provided below the first pixel. In addition, the pixel electrode PTCO1 of the first pixel also overlaps a portion of the oxide semiconductor layer OS of the fourth pixel when viewed from above.

[0078] like Fig.12As shown, the common auxiliary electrode CMTL is arranged in a grid shape in a manner surrounding the periphery of the pixel area. That is, the common auxiliary electrode CMTL is arranged in common for a plurality of pixels, and is arranged in a manner defining the respective areas of the plurality of pixels. In other words, the common auxiliary electrode CMTL has an opening OP corresponding to each pixel (light-transmitting area). The opening OP is arranged in a manner exposing the pixel electrode PTCO1. The opening ACON is arranged near the lower end of the opening OP of the common auxiliary electrode CMTL. The area in which the opening OP is provided is equivalent to the display area. That is, the opening ZCON (first contact area CON1) and the opening ACON (third contact area CON3) are included in the opening area. The opening area indicates an area that contributes to the image display by transmitting light (e.g., backlight) from below the substrate SUB. On the other hand, an area that does not transmit the above light, for example, by shielding the light through a metal layer, is not included in the opening area. The above-mentioned opening area is sometimes referred to as a "light-transmitting area."

[0079] like Fig.13 As shown, the common electrode CTCO is commonly provided for a plurality of pixels. In the present embodiment, the common electrode CTCO is commonly provided for pixels (or pixel electrodes PTCO1) arranged along the D1 direction. That is, the common electrode CTCO has a long side in the D1 direction and is arranged along the D2 direction. A slit SL is provided between the common electrodes CTCO adjacent to each other in the D2 direction. When viewed from above, the slit SL overlaps with the opening ACON. In other words, when viewed from above, at the opening ACON, the pixel electrode PTCO1 exposed from the insulating layers PIL1 and PIL2 is also exposed from the common electrode CTCO. Reference Fig.12 and Fig.13 In a plan view, the pixel electrode PTCO1 does not overlap with the common auxiliary electrode CMTL in a region that does not overlap with the common auxiliary electrode CMTL. The common electrode CTCO separated from the top and bottom by the slit SL (see FIG. Fig.13 ) is configured as a grid-like common auxiliary electrode CMTL (reference Fig.12 ) and electrically connected.

[0080] like Fig.14 As shown, a pixel electrode PTCO2 is provided for each pixel. That is, the pixel electrode PTCO1 and the pixel electrode PTCO2 are provided in pairs. When viewed from above, the pixel electrode PTCO2 overlaps with the opening PCON and the opening ACON. That is, the pixel electrode PTCO2 is opposite to the common electrode CTCO in the area overlapping with the opening PCON when viewed from above, and is connected to the pixel electrode PTCO1 in the area overlapping with the opening ACON when viewed from above.

[0081] refer to Fig.12 and Fig.14In a plan view, the pixel electrode PTCO2 overlaps the common electrode CTCO in a region that does not overlap with the common auxiliary electrode CMTL. One or more cutouts CT are provided in the pixel electrode PTCO2 from the first side ED1 extending along the direction D2 toward the second side ED2 opposite to the first side ED1.

[0082] In this embodiment, two cutouts CT are provided on the pixel electrode PTCO2 in the D2 direction. This configuration makes the pixel electrode PTCO2 present a shape in which a rectangular portion provided on the first side ED1 and a rectangular portion provided on the second side ED2 are connected to a central portion CENT via an arm portion ARM. In other words, the arm portion ARM is provided at a position corresponding to the cutout CT. In other words, in the D1 direction, the arm portion ARM protrudes slightly to the opposite side (opposite direction to the D1 direction) of the side on which the cutout CT is formed.

[0083] Regarding the above aspects, when viewing two pixel electrodes PTCO2 adjacent to each other in the D1 direction, the arm portion ARM has a convex portion CONV that slightly protrudes toward the cutout CT of the adjacent pixel electrode PTCO2. When viewed from above, the convex portion CONV overlaps with the common auxiliary electrode CMTL. The convex portion CONV is sometimes referred to as a bridge. A pair of convex portions CONV adjacent to each other in the D2 direction is sometimes referred to as a pair of bridges. Several concave portions CONC formed by the pair of bridges (a pair of convex portions CONV) are opposed to the central portion CENT of the adjacent pixel electrode PTCO2. Through the above configuration, a transverse electric field is formed above the pixel electrode PTCO2 along the edge of the cutout CT. As described above, by forming the convex portions and concave portions of the bridge, the response speed of the liquid crystal molecules can be increased.

[0084] [1-5. Materials of Components of Display Device 10]

[0085] As the substrate SUB, a glass substrate, a quartz substrate, a sapphire substrate, or other rigid substrate having light transmittance but no flexibility can be used. On the other hand, when the substrate SUB needs to be flexible, a flexible substrate containing resin and having flexibility, such as a polyimide substrate, an acrylic substrate, a siloxane-based substrate, or a fluorine-based resin substrate can be used as the substrate SUB. In order to improve the heat resistance of the substrate SUB, impurities may be introduced into the above-mentioned resin.

[0086] As the gate electrodes GL1, GL2, the wirings W1, W2, the light shielding layer LS, and the common auxiliary electrode CMTL, ordinary metal materials can be used. For example, as the above-mentioned electrodes and other components, aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), and silver (Ag), or their alloys or compounds are used. As the above-mentioned electrodes and other components, the above-mentioned materials can be used as a single layer or in a stacked state.

[0087] For example, a stacked structure of Ti / Al / Ti is used as the gate electrode GL1. In the present embodiment, the cross-sectional shape of the pattern end of the gate electrode GL1 having the stacked structure is a forward tapered shape.

[0088] As the gate insulating layers GI1 and GI2 and the insulating layers IL1 to IL5 and PIL1 to PIL2, a common insulating layer material can be used. For example, as the insulating layers IL1 to IL3, IL5 and PIL1 to PIL2, silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), silicon nitride (S i N x ), silicon oxynitride (S i N x O y ), aluminum oxide (AlO x ), aluminum oxynitride (AlO x N y ), aluminum oxynitride (AlN x O y ), aluminum nitride (AlN x ) and other inorganic insulating layers. As these insulating layers, insulating layers with fewer defects can be used.

[0089] The above SiO x N y and AlO x N y It is a silicon compound or an aluminum compound containing nitrogen (N) at a ratio smaller than that of oxygen (O) (x>y). i N x O y and AlN x O y These are silicon compounds and aluminum compounds containing oxygen in a smaller proportion than nitrogen (x>y).

[0090] As the insulating layer IL4, an organic insulating material such as polyimide resin, acrylic resin, epoxy resin, silicone resin, fluorine resin, or siloxane resin can be used. It should be noted that the above-mentioned organic insulating materials can be used as the gate insulating layers GI1 and GI2 and the insulating layers IL1 to IL3 and IL5. As the above-mentioned insulating layer and other components, the above-mentioned materials can be used as a single layer or in a stacked form.

[0091] As an example of the insulating layer, SiO having a thickness of 100 nm can be used. x As the gate insulating layer GI1, SiO with a total thickness of 600 nm to 700 nm is used. x / S i N x / SiO x As the insulating layer IL1, SiO with a total thickness of 60 to 100 nm is used. x / S i N x As the gate insulating layer GI2, SiO with a total thickness of 300 nm to 500 nm is used. x / S i N x / SiO x As the insulating layer IL2, SiO with a total thickness of 200 nm to 500 nm is used. x (Single layer), S i N x (single layer), or a stack of these layers as the insulating layer IL3. An organic layer with a thickness of 2 μm to 4 μm is used as the insulating layer IL4. S with a thickness of 50 nm to 150 nm is used. i N x (Single layer) serves as the insulating layers PIL1 to PIL2.

[0092] As the oxide semiconductor layer OS, an oxide metal having semiconductor properties can be used. The oxide semiconductor layer OS is light-transmitting. For example, an oxide semiconductor containing indium (In), gallium (Ga), zinc (Zn), and oxygen (O) can be used. In particular, an oxide semiconductor having a composition ratio of In:Ga:Zn:O=1:1:1:4 can be used. Among them, the oxide semiconductor containing In, Ga, Zn, and O used in this embodiment is not limited to the above composition, and an oxide semiconductor having a composition different from the above can also be used. For example, in order to improve mobility, the ratio of In can be made greater than the above ratio. In addition, in order to increase the band gap and reduce the influence of light, the ratio of Ga can be made greater than the above ratio.

[0093] Other elements may be added to the oxide semiconductor containing In, Ga, Zn and O. For example, metal elements such as Al and Sn may be added to the oxide semiconductor. In addition to the above-mentioned oxide semiconductors, an oxide semiconductor containing In and Ga (IGO), an oxide semiconductor containing In and Zn (IZO), an oxide semiconductor containing In, Sn and Zn (ITZO), and an oxide semiconductor containing In and W may be used as the oxide semiconductor layer OS. The oxide semiconductor layer OS may be amorphous or crystalline. The oxide semiconductor layer OS may also be a mixed phase of amorphous and crystalline.

[0094] A transparent conductive layer is used as the connection electrode ZTCO, the pixel electrodes PTCO1 and PTCO2, and the common electrode CTCO. As the transparent conductive layer, a mixture of indium oxide and tin oxide (ITO) and a mixture of indium oxide and zinc oxide (IZO) can be used. As the transparent conductive layer, materials other than the above can also be used.

[0095] In summary, according to the display device 10 involved in this embodiment, the retention capacitor (first capacitor element CAP1 and second capacitor element CAP2) of the pixel circuit can be stacked above the selection transistor (transistor Tr1). As a result, a capacitor element with a smaller area and a larger capacitance can be formed. Therefore, even a display device with a reduced pixel size can achieve a stable display operation.

[0096] Furthermore, by making the oxide semiconductor layer OS of the transistor Tr1 and the connecting electrode ZTCO directly contact each other, conduction between the two can be ensured. Therefore, there is no need to provide a metal layer between the oxide semiconductor layer OS and the connecting electrode ZTCO. With this configuration, even in the case where the opening ZCON is provided in the display area in order not to shield light at the opening ZCON (first contact area CON1), the reduction in the aperture ratio can be suppressed. The oxide semiconductor layer is light-transmitting. Therefore, in this embodiment, although an oxide semiconductor layer is provided in the opening area in the pixel area, light incident on the substrate SUB from the backlight passes through the oxide semiconductor layer. Therefore, the reduction in the transmittance of the opening area caused by the oxide semiconductor layer being provided in the opening area is minimized. The oxide semiconductor layer OS is light-transmitting, so unlike the silicon layer, it is not easy to cause unevenness in the transmitted light. By providing the oxide semiconductor layer OS in the display area, the generation of display unevenness can be suppressed.

[0097] [2. Second Embodiment]

[0098] use Figure 15 to Figure 17 , the overall structure of the display device described in the above-mentioned first embodiment is described.

[0099] [2-1. Overview of Display Device 20]

[0100] Fig.15 1 is a top view showing an overview of a display device according to an embodiment of the present invention. Fig.15 As shown, the display device 20 has an array substrate 300, a sealing portion 400, an opposing substrate 500, a flexible printed circuit substrate 600 (FPC600), and an IC chip 700. The array substrate 300 and the opposing substrate 500 are bonded together by the sealing portion 400. In the display area 22 surrounded by the sealing portion 400, a plurality of pixel circuits 310 are arranged in a matrix. The portion in the display area 22 where a plurality of pixel circuits are provided and which contributes to the image display is the display area. In addition, the display area is an area that overlaps with the liquid crystal element 410 described later when viewed from above. In addition, the area surrounding the display area is referred to as a peripheral area. The above-mentioned transistor Tr1 (first transistor) is provided in the liquid crystal area 22B (display area).

[0101] The display device 20 has a sealing area 24 in which a sealing portion 400 is provided in the peripheral area. The display area 22 is surrounded by the sealing area 24. The FPC 600 is provided in the terminal area 26 which is a part of the peripheral area. The terminal area 26 is formed in an area of ​​the array substrate 300 that does not overlap with the opposing substrate 500. The IC chip 700 is provided on the FPC 600. The IC chip 700 provides a signal for driving each pixel circuit 310. The sealing area 24 or the area formed by combining the sealing area 24 and the terminal area 26 is an area surrounding the display area 22. These areas are sometimes referred to as "frame areas". The above-mentioned transistor Tr2 (second transistor) is provided in the frame area.

[0102] [Circuit Configuration of Display Device 20]

[0103] Fig.16 1 is a block diagram showing a circuit configuration of a display device according to an embodiment of the present invention. Fig.16 As shown, for the display area 22 in the peripheral area where the pixel circuit 310 is configured, a source driving circuit 320 is provided at a position adjacent to the display area 22 in the D2 direction (column direction). In addition, for the display area 22 in the peripheral area, a gate driving circuit 330 is provided at a position adjacent to the display area 22 in the D1 direction (row direction). The source driving circuit 320 and the gate driving circuit 330 can be overlapped in the above-mentioned sealing area 24. Among them, the area where the source driving circuit 320 and the gate driving circuit 330 are provided is not limited to the sealing area 24, as long as it is outside the area (peripheral area) where the pixel circuit 310 is provided, it can be any area.

[0104] The source wiring 321 extends from the source driving circuit 320 in the direction D2 and is connected to the plurality of pixel circuits 310 arranged in the direction D2. The gate wiring 331 extends from the gate driving circuit 330 in the direction D1 and is connected to the plurality of pixel circuits 310 arranged in the direction D1.

[0105] A terminal portion 333 is provided in the terminal region 26. The terminal portion 333 and the source driving circuit 320 are connected via a connection wiring 341. Similarly, the terminal portion 333 and the gate driving circuit 330 are connected via a connection wiring 341. An external device connected to the terminal portion 333 via the FPC 600 and to which the FPC 600 is connected is connected to the display device 20, and each pixel circuit 310 provided in the display device 20 is driven by a signal from the external device.

[0106] The transistor Tr1 shown in the first embodiment is used in the pixel circuit 310. The transistor Tr2 shown in the first embodiment is used as a transistor included in the source driving circuit 320 and the gate driving circuit 330.

[0107] [Pixel Circuit 310 of Display Device 20]

[0108] Fig.17 1 is a circuit diagram showing a pixel circuit of a display device according to an embodiment of the present invention. Fig.17 As shown, the pixel circuit 310 includes components such as a transistor 800, a holding capacitor 890, and a liquid crystal element 410. The holding capacitor 890 includes a first capacitor element CAP1 and a second capacitor element CAP2. The electrode of the first capacitor element CAP1 on the transistor 800 side is a pixel electrode PTCO1. The electrode of the second capacitor element CAP2 on the transistor 800 side is a pixel electrode PTCO2. The electrodes on the GND potential side of the first capacitor element CAP1 and the second capacitor element CAP2 are a common electrode CTCO.

[0109] One electrode (on the transistor 800 side) of the liquid crystal element 410 is a pixel electrode PTCO2, and the other electrode is a common electrode CTCO. The transistor 800 has a first gate electrode 810, a first source electrode 830, and a first drain electrode 840. The first gate electrode 810 is connected to the gate wiring 331. The first source electrode 830 is connected to the source wiring 321. The first drain electrode 840 is connected to the holding capacitor 890 and the liquid crystal element 410. The transistor Tr1 shown in the first embodiment is suitable for Fig.17 The transistor 800 is shown. It should be noted that, in this embodiment, for the convenience of description, 830 is referred to as a source electrode and 840 is referred to as a drain electrode, and the function of each electrode as a source and a drain can be interchangeable.

[0110] As long as the various embodiments described above as embodiments of the present invention do not contradict each other, they can be appropriately combined for implementation. In addition, as long as the spirit of the present invention is possessed, those skilled in the art can appropriately add, delete or change the design of components, or add, omit or change the conditions of processes based on the display device of each embodiment, which are also included in the scope of the present invention.

[0111] As for other effects different from the effects brought about by the schemes of the above-mentioned embodiments, as long as they are clear from the description of this specification or can be easily thought of by those skilled in the art, they can of course be understood to be brought about by the present invention.

[0112] Description of Reference Numerals

[0113] 10: display device; 20: display device; 22: display area; 24: sealing area; 26: terminal area; 300: array substrate; 310: pixel circuit; 320: source driving circuit; 321: source wiring; 330: gate driving circuit; 331: gate wiring; 333: terminal portion; 341: connection wiring; 400: sealing portion; 410: liquid crystal element; 500: opposing substrate; 600: flexible printed circuit substrate; 700: chip; 800: transistor; 810: first gate electrode; 830: first source electrode; 840: first drain electrode; 890: holding capacitor; CMTL: common auxiliary electrode; CON1: first contact area; CON2: second contact area; CTCO: common electrode; GI1, GI2: gate insulating layer; GL1, GL2: gate electrodes; IL1~IL5: insulating layer; LS: light shielding layer; OP: opening; OS: oxide semiconductor layer; ACON, PCON, WCON, ZCON: openings; PJT: protrusion; PTCO1, PTCO2: pixel electrodes; S: semiconductor layer; SL: slit; SP: spacer; SUB: substrate; Tr1, Tr2: transistors; W: wiring; ZTCO: connecting electrode.

Claims

1. A display device comprising: A first transistor including an oxide semiconductor layer, a first gate electrode opposed to the oxide semiconductor layer, and a first gate insulating layer between the oxide semiconductor layer and the first gate electrode; A first transparent conductive layer, disposed above the first transistor; a second transparent conductive layer, disposed above the first transparent conductive layer, insulated from the first transparent conductive layer, and opposite to the first transparent conductive layer; as well as A third transparent conductive layer is disposed above the second transparent conductive layer, is insulated from the second transparent conductive layer, is connected to the first transparent conductive layer, and is opposite to the second transparent conductive layer. The display device further comprises: a light shielding layer configured to define regions of a plurality of pixels above the first transistor; In a plan view, in a region not overlapping with the light shielding layer, the first transparent conductive layer overlaps with the second transparent conductive layer, and the second transparent conductive layer overlaps with the third transparent conductive layer.

2. The display device according to claim 1, wherein: The first transparent conductive layer is connected to the first transistor.

3. The display device according to claim 2, wherein: The second transparent conductive layer is provided in a manner shared by a plurality of pixels.

4. The display device according to claim 3, wherein: The display device further comprises: a fourth transparent conductive layer, wherein, when viewed from above, the fourth transparent conductive layer comprises: a first portion overlapping the first gate electrode and the oxide semiconductor layer; and a second portion contacting the oxide semiconductor layer in a first contact region not overlapping the first gate electrode, In a plan view, the first transparent conductive layer is in contact with the fourth transparent conductive layer in a second contact region overlapping with the first gate electrode.

5. The display device according to claim 1, wherein: When viewed from above, the third transparent conductive layer is in contact with the first transparent conductive layer in a third contact region that does not overlap with the light shielding layer.

6. The display device according to any one of claims 1 to 4, wherein: The display device further comprises: a first dielectric between the first transparent conductive layer and the second transparent conductive layer; and A second dielectric is provided between the second transparent conductive layer and the third transparent conductive layer.

7. A display device comprising: A first transistor including an oxide semiconductor layer, a first gate electrode opposed to the oxide semiconductor layer, and a first gate insulating layer between the oxide semiconductor layer and the first gate electrode; A first transparent conductive layer, disposed above the first transistor; a second transparent conductive layer, disposed above the first transparent conductive layer, insulated from the first transparent conductive layer, and overlapping with the first transparent conductive layer in a light-transmitting area of ​​the pixel; as well as A third transparent conductive layer is provided above the second transparent conductive layer, is insulated from the second transparent conductive layer, is connected to the first transparent conductive layer, and overlaps with the second transparent conductive layer in the light-transmitting region. The display device further comprises: a light shielding layer, which is provided above the first transistor in a manner common to a plurality of pixels, and the light shielding layer is provided with an opening corresponding to the light-transmitting area, In the light-transmitting region, the first transparent conductive layer overlaps with the second transparent conductive layer, and the second transparent conductive layer overlaps with the third transparent conductive layer.

8. The display device according to claim 7, wherein: The first transparent conductive layer is connected to the first transistor.

9. The display device according to claim 8, wherein: The second transparent conductive layer is provided in a manner shared by a plurality of pixels.

10. The display device according to claim 9, wherein: The display device further comprises: a fourth transparent conductive layer, wherein, when viewed from above, the fourth transparent conductive layer comprises: a first portion overlapping the first gate electrode and the oxide semiconductor layer; and a second portion contacting the oxide semiconductor layer in a first contact region not overlapping the first gate electrode, The first transparent conductive layer is in contact with the fourth transparent conductive layer in the light-transmitting region.

11. The display device according to any one of claims 7 to 10, wherein: The third transparent conductive layer is in contact with the first transparent conductive layer in a third contact area included in the light-transmitting area.

12. The display device according to any one of claims 7 to 10, wherein: The display device further comprises: a first dielectric between the first transparent conductive layer and the second transparent conductive layer; and A second dielectric is provided between the second transparent conductive layer and the third transparent conductive layer.

13. The display device according to any one of claims 1 to 4 and 7 to 10, wherein: The display device further comprises: A second transistor comprising a semiconductor layer, a second gate electrode opposite to the semiconductor layer, and a second gate insulating layer between the semiconductor layer and the second gate electrode; as well as A first insulating layer is disposed above the semiconductor layer, The first insulating layer is continuous with the gate insulating layer without an interface.

14. The display device according to claim 13, wherein: The first transistor is included in a pixel circuit provided in a pixel, The second transistor is included in a driving circuit that drives the pixel circuit.

15. The display device according to claim 1 or 7, wherein: The third transparent conductive layer has one or more cutouts.

16. The display device according to claim 15, wherein: The third transparent conductive layer has an arm portion at a position corresponding to the cutout. The arm portion protrudes to a side opposite to a side where the cutout is formed.

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