Display panel and display device

Abstract

The application discloses a display panel and a display device. The display panel comprises a thin film transistor; the display panel further comprises a substrate, a first metal layer, an active layer, a spacer layer and a second metal layer; the first metal layer is arranged on the substrate and comprises a gate electrode of the thin film transistor; the active layer is arranged on a side of the first metal layer away from the substrate and comprises an active part of the thin film transistor, and the active part is arranged on a side of the gate electrode away from the substrate; the spacer layer is arranged on a side of the active layer away from the first metal layer and comprises a plurality of contact holes; the second metal layer is arranged on a side of the spacer layer away from the active layer and comprises a source electrode and a drain electrode of the thin film transistor, and the source electrode and the drain electrode are both overlapped with the active part through the contact holes; wherein a normal projection of the gate electrode on the substrate covers a normal projection of at least part of the contact holes on the substrate. The application can reduce the photo-generated leakage current generated by the thin film transistor and improve the yield of the overlap of the source electrode, the drain electrode and the active part.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a display device having the same. BACKGROUND

[0002] Thin Film Transistor (TFT) is a main driving element in current Liquid Crystal Display (LCD) and Active Matrix / Organic Light-Emitting Diode (AMOLED), which is directly related to the development direction of high-performance flat panel display. There are various materials for preparing the active layer of the thin film transistor, and Low Temperature Poly-silicon (LTPS) is a relatively preferred one. Since the atoms of the low temperature poly-silicon are regularly arranged, the carrier mobility is high. For the voltage-driven liquid crystal display, the low temperature poly-silicon thin film transistor can realize the deflection driving of the liquid crystal molecules by using a smaller thin film transistor, greatly reducing the volume occupied by the thin film transistor, increasing the light transmission area, and obtaining higher brightness and resolution. For the current-driven active matrix organic electroluminescent display, the low temperature poly-silicon thin film transistor can better meet the driving current requirement.

[0003] At present, the thin film transistor includes a bottom gate transistor and a top gate transistor. Compared with the top gate transistor, the bottom gate transistor can save a mask in the doping process of the active layer, and the bottom gate electrode is located below the active layer, which can save the preparation of the light shielding layer, further saving the mask and cost. However, since the bottom gate electrode is usually arranged corresponding to the channel region of the active layer, the shielding effect of the bottom gate electrode on the light on the back side of the active layer is limited, and it is difficult to ensure the stability of the bottom gate transistor. SUMMARY

[0004] The display panel and the display device provided by the embodiments of the present application can improve the shielding effect of the first gate electrode and the second gate electrode on light, and improve the stability of the first transistor and the second transistor.

[0005] The display panel provided by the embodiments of the present application includes a thin film transistor.

[0006] The display panel further includes:

[0007] a substrate;

[0008] a first metal layer arranged on the substrate and including a gate electrode of the thin film transistor;

[0009] an active layer disposed on a side of the first metal layer distal to the substrate and comprising an active portion of the thin film transistor, the active portion disposed on a side of the gate distal to the substrate;

[0010] a spacer layer disposed on a side of the active layer distal to the first metal layer and comprising a plurality of contact holes;

[0011] a second metal layer disposed on a side of the spacer layer distal to the active layer and comprising a source and a drain of the thin film transistor, and the source and the drain both overlap the active portion through the contact holes;

[0012] wherein a footprint of the gate on the substrate covers at least part of a footprint of the contact holes on the substrate.

[0013] In an embodiment of the present application, the display panel further comprises a display area, and the thin film transistor comprises a first transistor disposed in the display area.

[0014] The first metal layer comprises a first gate of the first transistor, the active layer comprises a first active portion of the first transistor, the second metal layer comprises a first source and a first drain of the first transistor, the first active portion is located on a side of the first gate distal to the substrate, the plurality of contact holes comprises a first contact hole and a second contact hole, the first source overlaps the first active portion through the first contact hole, and the first drain overlaps the first active portion through the second contact hole.

[0015] wherein a footprint of the first contact hole on the substrate and a footprint of the second contact hole on the substrate are both within a coverage range of a footprint of the first gate on the substrate.

[0016] In an embodiment of the present application, a footprint of the first active portion on the substrate is within the coverage range of the footprint of the first gate on the substrate.

[0017] In an embodiment of the present application, the first metal layer further comprises a scan line connected to the first gate, and a width of the first gate along a first direction is greater than a width of the scan line along the first direction, the first direction being perpendicular to an extension direction of the scan line.

[0018] In an embodiment of the present application, the display panel further comprises a non-display area, and the thin film transistor comprises a second transistor disposed in the non-display area.

[0019] The first metal layer comprises a second gate of the second transistor, the active layer comprises a second active part of the second transistor, the second metal layer comprises a second source and a second drain of the second transistor, the second active part is located on a side of the second gate away from the substrate, and the plurality of contact holes comprise a third contact hole and a fourth contact hole, the second source is overlapped with the second active part through the third contact hole, and the second drain is overlapped with the second active part through the fourth contact hole.

[0020] The second gate is at least partially overlapped with the third contact hole on the substrate, and / or the second gate is at least partially overlapped with the fourth contact hole on the substrate.

[0021] In an embodiment of the present application, the second gate is at least partially overlapped with the third contact hole on the substrate, and / or the second gate is at least partially overlapped with the fourth contact hole on the substrate.

[0022] In an embodiment of the present application, the thin film transistor further comprises a third transistor arranged in the non-display area, the first metal layer comprises a third gate of the third transistor, the active layer comprises a third active part of the third transistor, the third active part is arranged on a side of the third gate away from the substrate, and the third gate is at least partially overlapped with the third active part on the substrate.

[0023] The second transistor and the third transistor share the second source or the second drain.

[0024] In an embodiment of the present application, the second metal layer comprises a third source of the third transistor, the third transistor shares the second drain with the second transistor, and the third active part is connected with the second active part.

[0025] The fourth contact hole is at least partially overlapped with the second gate on the substrate, and the fourth contact hole is at least partially overlapped with the third gate on the substrate.

[0026] In an embodiment of the present application, the plurality of contact holes further comprise a fifth contact hole, the third source is connected with the third active part through the fifth contact hole, and the third gate is at least partially overlapped with the fifth contact hole on the substrate.

[0027] In an embodiment of the present application, the second metal layer includes a third drain of a third transistor, the third transistor sharing the second source with the second transistor, and the third active part is connected to the second active part.

[0028] The third contact hole has a projection on the substrate that partially overlaps with a projection of the second gate on the substrate, and the third contact hole has a projection on the substrate that partially overlaps with a projection of the third gate on the substrate.

[0029] In an embodiment of the present application, the plurality of contact holes further include a sixth contact hole, the third drain is connected to the third active part through the sixth contact hole, and a projection of the third gate on the substrate covers at least part of a projection of the sixth contact hole on the substrate.

[0030] In an embodiment of the present application, the second gate is spaced apart from the third gate.

[0031] In an embodiment of the present application, the second transistor shares the second source with the third transistor, a projection of the third contact hole on the substrate is within a coverage range of a projection of the second gate on the substrate, or a projection of the third contact hole on the substrate is within a coverage range of a projection of the third gate on the substrate.

[0032] In an embodiment of the present application, the second transistor shares the second drain with the third transistor, a projection of the fourth contact hole on the substrate is within a coverage range of a projection of the second gate on the substrate, or a projection of the fourth contact hole on the substrate is within a coverage range of a projection of the third gate on the substrate.

[0033] According to the above-mentioned purpose of the present application, an embodiment of the present application further provides a display device, wherein the display device includes the display panel.

[0034] The beneficial effects of the present application are as follows: the present application increases the area of the gate located below the active part, so that the orthographic projection of the gate on the substrate covers the orthographic projection of the contact hole of the source and the drain on the substrate, that is, the shielding range of the gate to the active part is increased, and the photo-generated leakage current generated by the thin film transistor is effectively reduced; in addition, since the edge of the gate has a ramp, if the active part covers the edge of the gate, breakage is prone to occur at the ramp, and the present application sets the orthographic projection of the gate on the substrate to cover the orthographic projection of the contact hole of the source and the drain on the substrate, so that at least part of the contact hole of the source and the drain is located in the area corresponding to the upper surface of the gate and not at the ramp, thereby ensuring that at least part of the active part in contact with the source and the drain is not located at the ramp, improving the bonding yield of the source, the drain and the active part, improving the signal transmission stability of the thin film transistor, and improving the display effect of the display panel. BRIEF DESCRIPTION OF DRAWINGS

[0035] The technical solutions and other beneficial effects of the present application will become apparent through the following detailed description of the specific embodiments of the present application in conjunction with the accompanying drawings.

[0036] Figure 1 A structural schematic diagram of a display panel provided for an embodiment of the present application is shown in the figure.

[0037] Figure 2 A planar structural schematic diagram of a first gate and a first active part in a display panel provided for an embodiment of the present application is shown in the figure.

[0038] Figure 3 A structural schematic diagram of a display panel corresponding to a non-display area provided for an embodiment of the present application is shown in the figure.

[0039] Figure 4 A planar structural schematic diagram of a display panel corresponding to a non-display area provided for an embodiment of the present application is shown in the figure.

[0040] Figure 5 Another planar structural schematic diagram of a display panel corresponding to a non-display area provided for an embodiment of the present application is shown in the figure.

[0041] Figure 6 Another structural schematic diagram of a display panel corresponding to a non-display area provided for an embodiment of the present application is shown in the figure.

[0042] Figure 7 Another structural schematic diagram of a display panel corresponding to a non-display area provided for an embodiment of the present application is shown in the figure.

[0043] Figure 8 Another structural schematic diagram of a display panel corresponding to a non-display area provided for an embodiment of the present application is shown in the figure.

[0044] Figure 9Another structural schematic view of a display panel according to an embodiment of the present application is provided.

[0045] Figure 10 Another structural schematic view of a display panel according to an embodiment of the present application is provided. DETAILED DESCRIPTION

[0046] The technical solutions in the embodiments of the present application will be apparently and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by a person skilled in the art without any creative work fall within the protection scope of the present application.

[0047] The following disclosure provides many different embodiments, or examples, for implementing different structures of the present application. For the purpose of simplification, the components and arrangements of specific examples are described in the following. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeatedly refer to the numbers and / or letters in different examples, and such repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or arrangements discussed. In addition, the present application provides various specific examples of processes and materials, but a person skilled in the art can realize the application of other processes and / or the use of other materials.

[0048] An embodiment of the present application provides a display panel, please refer to Figure 1 The display panel includes a thin film transistor.

[0049] Further, the display panel further includes a substrate 10, a first metal layer 20, an active layer 30, a spacer layer 70, and a second metal layer 40.

[0050] The first metal layer 20 is disposed on the substrate 10 and includes a gate of the thin film transistor; the active layer 30 is disposed on a side of the first metal layer 20 away from the substrate 10 and includes an active part of the thin film transistor, the active part is disposed on a side of the gate away from the substrate 10; the spacer layer 70 is disposed on a side of the active layer 30 away from the first metal layer 20 and includes a plurality of contact holes; the second metal layer 40 is disposed on a side of the spacer layer 70 away from the active layer 30 and includes a source and a drain of the thin film transistor, and the source and the drain are both connected to the active part through the contact holes.

[0051] The orthogonal projection of the gate on the substrate 10 covers at least part of the orthogonal projection of the contact hole on the substrate 10.

[0052] In the application process, the embodiment of the present application increases the area of the gate located below the active part, so that the orthographic projection of the gate on the substrate 10 covers the orthographic projection of the contact hole of the source and the drain on the substrate 10, that is, the shielding range of the gate to the active part is increased, the photo-generated leakage current of the thin film transistor is effectively reduced, and meanwhile; in addition, since the edge of the gate has a ramp, if the active part covers the edge of the gate, the breakage is prone to occur at the ramp, and the present application sets the orthographic projection of the gate on the substrate 10 to cover the orthographic projection of the contact hole of the source and the drain on the substrate 10, so that at least part of the contact hole of the source and the drain is located in the area corresponding to the upper surface of the gate and not in the ramp, thereby ensuring that at least part of the active part in contact with the source and the drain is not located in the ramp, improving the lapping yield of the source, the drain and the active part, improving the signal transmission stability of the thin film transistor, and improving the display effect of the display panel.

[0053] It should be noted that the display panel provided by the embodiment of the present application includes a display area 101 and a non-display area 102 adjacent to the display area 101, and the thin film transistor includes a first transistor T1 located in the display area 101 and a second transistor T2 located in the non-display area 102, and the gate area of the first transistor T1 and the second transistor T2 is increased in the embodiment of the present application to reduce the photo-generated leakage current generated in the first transistor T1 and the second transistor T2, and the shielding range of the gate in the first transistor T1 and the second transistor T2 can be set differently to further realize a display panel with a narrow frame, and specific reference can be made to subsequent embodiments.

[0054] In an embodiment of the present application, please refer to Figure 1 The display panel includes a display area 101 and a non-display area 102 adjacent to the display area 101, wherein the non-display area 102 can be a frame area, and can also include a GOA driving circuit area and a wire fan-out area located on one side of the display panel.

[0055] The display panel further includes a substrate 10, a buffer layer 50 disposed on the substrate 10, a first metal layer 20 disposed on the side of the buffer layer 50 away from the substrate 10, a gate insulating layer 60 disposed on the side of the first metal layer 20 away from the buffer layer 50, an active layer 30 disposed on the side of the gate insulating layer 60 away from the buffer layer 50, a spacer layer 70 disposed on the side of the active layer 30 away from the gate insulating layer 60, and a second metal layer 40 disposed on the side of the spacer layer 70 away from the active layer 30.

[0056] Further, the display panel further comprises a plurality of thin film transistors disposed on the substrate 10, and the plurality of thin film transistors comprise a first transistor T1 disposed in the display area 101 and a second transistor T2 disposed in the non-display area 102; wherein the first metal layer 20 comprises a first gate 21 of the first transistor T1 and a second gate 22 of the second transistor T2, the active layer 30 comprises a first active part 31 of the first transistor T1 and a second active part 32 of the second transistor T2, and the second metal layer 40 comprises a first source 41 and a first drain 42 of the first transistor T1, and a second source 43 and a second drain 44 of the first transistor T1.

[0057] The first active part 31 comprises a first channel sub-area 311, a first source contact sub-area 312 and a first drain contact sub-area 313 located on both sides of the first channel sub-area 311, and two first lightly doped regions 314 located between the first channel sub-area 311 and the first source contact sub-area 312 and between the first channel sub-area 311 and the first drain contact sub-area 313 respectively; the spacer layer 70 comprises a plurality of contact holes, and the plurality of contact holes comprise a first contact hole 71 corresponding to the first source contact sub-area 312 and a second contact hole 72 corresponding to the first drain contact sub-area 313, and the first source 41 is overlapped with the part of the first active part 31 in the first source contact sub-area 312 through the first contact hole 71, and the first drain 42 is overlapped with the part of the first active part 31 in the first drain contact sub-area 313 through the second contact hole 72; in addition, in the embodiment of the present application, the orthographic projection of the first contact hole 71 on the substrate 10 and the orthographic projection of the second contact hole 72 on the substrate 10 are both located within the coverage range of the orthographic projection of the first gate 21 on the substrate 10; since the gate insulating layer 60 covers the first gate 21, a protrusion (not shown in the figure) will be formed at the first gate 21 by the gate insulating layer 60, that is, a ramp will be formed at the edge of the first gate 21 by the gate insulating layer 60, and the embodiment of the present application makes at least part of the first active part 31 overlapped with the first source 41 and the first drain 42 not located at the ramp formed by the edge of the first gate 21, thereby improving the overlay yield of the first source 41, the first drain 42 and the first active part 31, improving the signal transmission stability of the first transistor T1, improving the display effect of the display panel, and can increase the light shielding effect of the first gate 21 on the back side (i.e. the side close to the substrate 10) of the first active part 31, effectively improving the phenomenon of photo-generated leakage current of the first active part 31 in the first transistor T1 due to back side light irradiation, improving the potential holding capacity of the first transistor T1, improving the stability of the first transistor T1, reducing the probability of crosstalk and flicker of the display panel, and improving the display effect of the display panel.

[0058] Further, the orthographic projection of the first active part 31 on the substrate 10 is located within the coverage range of the orthographic projection of the first gate 21 on the substrate 10, and further, the first active part 31 is located on the flat surface on which the gate insulating layer 60 forms a protrusion, and will not cover the ramp of the gate insulating layer 60, that is, the embodiment of the present application also improves the flatness of the film layer forming the first active part 31, reduces the probability of fracture of the first active part 31 due to covering the ramp, so that the first source 41 and the first drain 42 can be well overlapped with the first active part 31, realizing good transmission of signals, and further improving the electrical properties and stability of the first transistor T1.

[0059] It should be noted that, please refer to Figure 1 and Figure 2 , the first metal layer 20 further comprises a scan line 34, and the scan line 34 is connected to the first gate 21 to provide a scan signal for the first gate 21; wherein the width of the first gate 21 along the first direction X is greater than the width of the scan line 34 along the first direction X, and the first direction X is perpendicular to the extension direction of the scan line 34. In the embodiment of the present application, the first gate 21 and the scan line 34 are integrally formed, and the width of the first gate 21 and the scan line 34 along the first direction X is differentially set, so as to improve the light shielding effect of the first gate 21 on the first active part 31, and at the same time, the area ratio of the scan line 34 will not be increased, that is, the aperture ratio of the display panel will not be reduced.

[0060] The second active part 32 comprises a second channel sub-region 321, a second source contact sub-region 322 and a second drain contact sub-region 323 located on both sides of the second channel sub-region 321, and two second lightly doped regions 324, and the two second lightly doped regions 324 are respectively located between the second channel sub-region 321 and the second source contact sub-region 322 and between the second channel sub-region 321 and the second drain contact sub-region 323; the spacer layer 70 comprises a third contact hole 73 arranged corresponding to the second source contact sub-region 322 and a fourth contact hole 74 arranged corresponding to the second drain contact sub-region 323, and the second source electrode 43 passes through the third contact hole 73 to be overlapped with the second active part 32 in the second source contact sub-region 322, and the second drain electrode 44 passes through the fourth contact hole 74 to be overlapped with the second active part 32 in the second drain contact sub-region 323; in addition, in the embodiment of the present application, the orthographic projection of the second gate electrode 22 on the active layer 30 covers the second channel sub-region 321, the orthographic projection of the second gate electrode 22 on the substrate 10 covers at least part of the orthographic projection of the third contact hole 73 on the substrate 10, and / or the orthographic projection of the second gate electrode 22 on the substrate 10 covers at least part of the orthographic projection of the fourth contact hole 74 on the substrate 10, thereby the light shielding effect of the first gate electrode 21 on the back side (i.e. the side close to the substrate 10) of the first active part 31 can be increased, the phenomenon of photo-generated leakage current of the first active part 31 due to back side light irradiation in the second transistor T2 is effectively improved, the potential holding capability of the second transistor T2 is improved, and the stability of the second transistor T2 is improved. Further, the boundary of the orthographic projection of the second gate electrode 22 on the active layer 30 is located in the second source contact sub-region 322 and the second drain contact sub-region 323, and the boundary of the orthographic projection of the second gate electrode 22 on the substrate 10 does not exceed the boundary of the orthographic projection of the second active part 32 on the substrate 10, and the coverage range of the second gate electrode 22 in the embodiment of the present application will not exceed the coverage range of the second active part 32, that is, the embodiment of the present application will not increase the size and occupied space of the second transistor T2. At present, with the demand for narrow frame of the display panel, the area of the non-display area 102 of the display panel is also gradually reduced, and thus on the basis of improving the stability of the second transistor T2, the embodiment of the present application can also be beneficial to realize the narrow frame of the display panel.

[0061] In the embodiment of the present application, the orthogonal projection of the second gate 22 on the substrate 10 covers at least part of the orthogonal projection of the third contact hole 73 on the substrate 10, and the orthogonal projection of the second gate 22 on the substrate 10 covers at least part of the orthogonal projection of the fourth contact hole 74 on the substrate 10; since the gate insulating layer 60 covers the second gate 22, the gate insulating layer 60 will form a protrusion (not shown in the figure) at the second gate 22, that is, the gate insulating layer 60 will form a ramp at the edge of the second gate 22, and in the embodiment of the present application, even when the second active part 32 covering the part of the ramp is broken, the second active part 32 corresponding to the overlapping part of the third contact hole 73 and the fourth contact hole 74 and the second gate 22 is located on the flat surface of the protrusion formed by the gate insulating layer 60, so that the probability of the second active part 32 corresponding to the overlapping part of the third contact hole 73 and the fourth contact hole 74 and the second gate 22 being broken can be reduced, so that the second source electrode 43 and the second drain electrode 44 can still be connected to the second active part 32 through the third contact hole 73 and the fourth contact hole 74 to realize the transmission of electrical signals, thereby improving the electrical properties and stability of the second transistor T2.

[0062] Optionally, the overlapping area of the orthogonal projection of the third contact hole 73 on the substrate 10 and the orthogonal projection of the second gate 22 on the substrate 10 accounts for half of the area of the orthogonal projection of the third contact hole 73 on the substrate 10, and the overlapping area of the orthogonal projection of the fourth contact hole 74 on the substrate 10 and the orthogonal projection of the second gate 22 on the substrate 10 accounts for half of the area of the orthogonal projection of the fourth contact hole 74 on the substrate 10.

[0063] Optionally, the orthogonal projection of the third contact hole 73 on the substrate 10 is located within the coverage range of the orthogonal projection of the second gate 22 on the substrate 10; or the orthogonal projection of the fourth contact hole 74 on the substrate 10 is located within the coverage range of the orthogonal projection of the second gate 22 on the substrate 10; or both the orthogonal projection of the third contact hole 73 on the substrate 10 and the orthogonal projection of the fourth contact hole 74 on the substrate 10 are located within the coverage range of the orthogonal projection of the second gate 22 on the substrate 10; thereby the contact part of the second active part 32 and the second source electrode 43 and the second drain electrode 44 can be located on the flat surface of the gate insulating layer 60, the probability of the contact part of the second active part 32 and the second source electrode 43 and the second drain electrode 44 being broken can be reduced, and the electrical properties and stability of the second transistor T2 can be further improved.

[0064] Further, please refer to Figure 1 , Figure 3 , Figure 4 and Figure 5 , wherein Figure 3 , Figure 4 and Figure 5For a structural schematic diagram of the display panel located in the non-display area 102, for example, a structural schematic diagram in a GOA driving circuit region. Among them, the plurality of thin film transistors in the display panel further includes a third transistor T3 disposed in the non-display area 102.

[0065] The first metal layer 20 includes a third gate 23 of the third transistor T3, the active layer 30 includes a third active part 33 of the third transistor T3, and the third active part 33 is disposed on the side of the third gate 23 away from the substrate 10. The third active part 33 includes a third channel sub-region 331, a third source contact sub-region 332 and a third drain contact sub-region 333 located on both sides of the third channel sub-region 331, and two third light doping regions 334, and the two third light doping regions 334 are respectively disposed between the third source contact sub-region 332 and the third channel sub-region 331, and between the third drain contact sub-region 333 and the third channel sub-region 331. Further, the second transistor T2 and the third transistor T3 share the second source 43 or the second drain 44; wherein the orthographic projection of the third gate 23 on the active layer 30 covers the third channel sub-region 331, and the boundary of the orthographic projection of the third gate 23 on the active layer 30 is located within the third source contact sub-region 332 and the third drain contact sub-region 333, that is, the boundary of the orthographic projection of the third gate 23 on the substrate 10 does not exceed the boundary of the orthographic projection of the third active part 33 on the substrate 10.

[0066] In the embodiments shown in Figure 3 , Figure 4 and Figure 5 , the second transistor T2 and the third transistor T3 share the second drain 44. At this time, the second metal layer 40 includes a third source 45 of the third transistor T3, and the third active part 33 is connected with the second active part 32; specifically, the part of the third active part 33 located in the third drain contact sub-region 333 is connected with the part of the second active part 32 located in the second drain contact sub-region 323, so that the second drain 44 is simultaneously overlapped with the part of the second active part 32 located in the second drain contact sub-region 323 and the part of the third active part 33 located in the third drain contact sub-region 333, to realize that the second transistor T2 and the third transistor T3 share the second drain 44.

[0067] It should be noted that the second gate 22 and the third gate 23 are spaced apart to achieve the purpose of separately controlling the second transistor T2 and the third transistor T3 respectively.

[0068] The fourth contact hole 74 is partially overlapped with the orthogonal projection of the second gate 22 on the substrate 10, and is partially overlapped with the orthogonal projection of the third gate 23 on the substrate 10. Thus, the overlap part of the second active part 32 and the second drain 44, and the overlap part of the third active part 33 and the second drain 44 can be located on the flat surface of the gate insulating layer 60, which reduces the probability of the contact part of the second active part 32, the third active part 33 and the second drain 44 being broken, and further improves the electrical property and stability of the second transistor T2 and the third transistor T3.

[0069] Further, the spacer layer 70 further comprises a fifth contact hole 75 corresponding to the third source contact sub-area 332, and the third source 45 is connected with the part of the third active part 33 in the third source contact sub-area 332 through the fifth contact hole 75, and the orthogonal projection of the third gate 23 on the substrate 10 covers at least part of the orthogonal projection of the fifth contact hole 75 on the substrate 10. Thus, at least part of the third active part 33 overlapped with the third source 45 can be located on the flat surface of the gate insulating layer 60, which reduces the probability of the contact part of the third active part 33 and the third source 45 being broken, and further improves the electrical property and stability of the third transistor T3.

[0070] Optionally, the orthogonal projection of the fifth contact hole 75 on the substrate 10 is located within the coverage range of the orthogonal projection of the third gate 23 on the substrate 10, so as to reduce the probability of the contact part of the third active part 33 and the third source 45 being broken to the greatest extent, and improve the electrical property and stability of the third transistor T3.

[0071] As described above, in the embodiment of the present application, by increasing the shielding range of the first gate 21 to the back side of the first active part 31, and increasing the shielding range of the second gate 22 to the back side of the second active part 32, the photo-generated leakage current of the first transistor T1 and the second transistor T2 is effectively reduced, and meanwhile, the occupied space of the second transistor T2 in the non-display area 102 is not increased, so that a narrow frame display panel can be realized. In addition, the first active part 31 overlapped with at least part of the first source 41 and the first drain 42, the second active part 32 overlapped with at least part of the second source 43 and the second drain 44, and the third active part 33 overlapped with at least part of the third source 45 and the second drain 44 are arranged at the flat surface of the gate insulating layer 60, so that the probability of the second active part 32 and the third active part 33 being broken at the overlap part with the source and drain is effectively reduced, and the electrical property and stability of the second transistor T2 and the third transistor T3 are improved.

[0072] In another embodiment of the present application, please refer to Figure 6The difference between the embodiment and the previous embodiment is that in the embodiment, the orthogonal projection of the fourth contact hole 74 on the substrate 10 is within the coverage range of the orthogonal projection of the third gate 23 on the substrate 10, and the orthogonal projection of the fourth contact hole 74 on the substrate 10 does not overlap with the orthogonal projection of the second gate 22 on the substrate 10.

[0073] In the embodiment, the shielding range of the first gate 21 on the back side of the first active part 31 is increased, and the shielding range of the second gate 22 on the back side of the second active part 32 is increased, so that the photo-generated leakage current of the first transistor T1 and the second transistor T2 is effectively reduced, and the occupied space of the second transistor T2 in the non-display area 102 is not increased, so that a narrow-frame display panel can be realized. In addition, in the non-display area 102, the first active part 31 at least partially overlapped with the first source electrode 41 and the first drain electrode 42, the second active part 32 at least partially overlapped with the second source electrode 43 and the second drain electrode 44, and the third active part 33 at least partially overlapped with the third source electrode 45 and the second drain electrode 44 are arranged at the flat surface of the gate insulating layer 60, so that the probability of fracture of the second active part 32 and the third active part 33 at the overlapped position with the source and drain electrodes can be effectively reduced, and the electrical properties and stability of the second transistor T2 and the third transistor T3 are improved.

[0074] In another embodiment of the present application, please refer to Figure 7 The difference between the embodiment and the previous embodiment is that in the embodiment, the orthogonal projection of the fourth contact hole 74 on the substrate 10 is within the coverage range of the orthogonal projection of the second gate 22 on the substrate 10, and the orthogonal projection of the fourth contact hole 74 on the substrate 10 does not overlap with the orthogonal projection of the third gate 23 on the substrate 10.

[0075] In the embodiment, the shielding range of the first gate 21 on the back side of the first active part 31 is increased, and the shielding range of the second gate 22 on the back side of the second active part 32 is increased, so that the photo-generated leakage current of the first transistor T1 and the second transistor T2 is effectively reduced, and the occupied space of the second transistor T2 in the non-display area 102 is not increased, so that a narrow-frame display panel can be realized. In addition, in the non-display area 102, the first active part 31 at least partially overlapped with the first source electrode 41 and the first drain electrode 42, the second active part 32 at least partially overlapped with the second source electrode 43 and the second drain electrode 44, and the third active part 33 at least partially overlapped with the third source electrode 45 and the second drain electrode 44 are arranged at the flat surface of the gate insulating layer 60, so that the probability of fracture of the second active part 32 and the third active part 33 at the overlapped position with the source and drain electrodes can be effectively reduced, and the electrical properties and stability of the second transistor T2 and the third transistor T3 are improved.

[0076] In another embodiment of the present application, please refer toFigure 8 The difference between the embodiment and the first embodiment is that the second transistor T2 shares the second source 43 with the third transistor T3, and the part of the second active part 32 located in the second source contact sub-area 322 is connected with the part of the third active part 33 located in the third source contact sub-area 332.

[0077] In the embodiment, the orthogonal projection of the third contact hole 73 on the substrate 10 partially overlaps the orthogonal projection of the second gate 22 on the substrate 10, and the orthogonal projection of the third contact hole 73 on the substrate 10 partially overlaps the orthogonal projection of the third gate 23 on the substrate 10. Thus, the overlap part of the second active part 32 and the second source 43 and the overlap part of the third active part 33 and the second source 43 can be located on the flat surface of the gate insulation layer 60, which reduces the probability of the contact part of the second active part 32, the third active part 33 and the second source 43 being broken, and further improves the electrical property and stability of the second transistor T2 and the third transistor T3.

[0078] Further, the second metal layer 40 includes the third drain 46 of the third transistor T3, the spacer layer 70 further includes a sixth contact hole 76 arranged corresponding to the third drain contact sub-area 333, and the third drain 46 is connected with the part of the third active part 33 located in the third drain contact sub-area 333 through the sixth contact hole 76, and the orthogonal projection of the third gate 23 on the substrate 10 covers at least part of the orthogonal projection of the sixth contact hole 76 on the substrate 10, thus at least part of the third active part 33 overlapped with the third drain 46 can be located on the flat surface of the gate insulation layer 60, which reduces the probability of the contact part of the third active part 33 and the third drain 46 being broken, and further improves the electrical property and stability of the third transistor T3.

[0079] Optionally, the orthogonal projection of the sixth contact hole 76 on the substrate 10 is within the coverage range of the orthogonal projection of the third gate 23 on the substrate 10, so as to reduce the probability of the contact part of the third active part 33 and the third drain 46 being broken to the greatest extent, and improve the electrical property and stability of the third transistor T3.

[0080] In the embodiment of the present application, the first gate 21 is increased to shield the back side of the first active part 31, and the second gate 22 is increased to shield the back side of the second active part 32, so that the photo-generated leakage current of the first transistor T1 and the second transistor T2 is effectively reduced, and meanwhile, the occupied space of the second transistor T2 in the non-display area 102 is not increased, so that a narrow frame display panel can be realized. In addition, in the non-display area 102, the first active part 31 at least partially overlapped with the first source 41 and the first drain 42, the second active part 32 at least partially overlapped with the second source 43 and the second drain 44, and the third active part 33 at least partially overlapped with the third source 45 and the second drain 44 are arranged at the flat surface of the gate insulating layer 60, so that the probability of breakage of the second active part 32 and the third active part 33 at the overlapped position with the source and the drain is effectively reduced, and the electrical property and stability of the second transistor T2 and the third transistor T3 are improved.

[0081] In another embodiment of the present application, referring to Figure 9 The difference between the present embodiment and the previous embodiment is that, in the present embodiment, the orthographic projection of the third contact hole 73 on the substrate 10 is located within the coverage range of the orthographic projection of the second gate 22 on the substrate 10, and the orthographic projection of the third contact hole 73 on the substrate 10 does not overlap with the orthographic projection of the third gate 23 on the substrate 10.

[0082] In the embodiment of the present application, the first gate 21 is increased to shield the back side of the first active part 31, and the second gate 22 is increased to shield the back side of the second active part 32, so that the photo-generated leakage current of the first transistor T1 and the second transistor T2 is effectively reduced, and meanwhile, the occupied space of the second transistor T2 in the non-display area 102 is not increased, so that a narrow frame display panel can be realized. In addition, in the non-display area 102, the first active part 31 at least partially overlapped with the first source 41 and the first drain 42, the second active part 32 at least partially overlapped with the second source 43 and the second drain 44, and the third active part 33 at least partially overlapped with the third source 45 and the second drain 44 are arranged at the flat surface of the gate insulating layer 60, so that the probability of breakage of the second active part 32 and the third active part 33 at the overlapped position with the source and the drain is effectively reduced, and the electrical property and stability of the second transistor T2 and the third transistor T3 are improved.

[0083] In another embodiment of the present application, referring to Figure 10 The difference between the present embodiment and the previous embodiment is that, in the present embodiment, the orthographic projection of the third contact hole 73 on the substrate 10 is located within the coverage range of the orthographic projection of the third gate 23 on the substrate 10, and the orthographic projection of the third contact hole 73 on the substrate 10 does not overlap with the orthographic projection of the second gate 22 on the substrate 10.

[0084] In the embodiment of the present application, by increasing the shielding range of the first gate 21 on the back side of the first active part 31 and increasing the shielding range of the second gate 22 on the back side of the second active part 32, the photo-generated leakage current of the first transistor T1 and the second transistor T2 is effectively reduced, and the occupied space of the second transistor T2 in the non-display area 102 is not increased, so that a narrow frame display panel can be realized. In addition, in the non-display area 102, the first active part 31 at least partially overlapped with the first source 41 and the first drain 42, the second active part 32 at least partially overlapped with the second source 43 and the second drain 44, and the third active part 33 at least partially overlapped with the third source 45 and the second drain 44 are arranged at the flat surface of the gate insulating layer 60, so that the probability of fracture of the second active part 32 and the third active part 33 at the overlap position with the source and drain can be effectively reduced, and the electrical properties and stability of the second transistor T2 and the third transistor T3 are improved.

[0085] In addition, the embodiment of the present application further provides a display device, which comprises a device main body and a display panel.

[0086] The device main body can comprise a middle frame, frame glue and the like, and the display device can be a mobile phone, a tablet computer, a television and the like, which are not limited herein.

[0087] In the above embodiments, the description of each embodiment has its own emphasis, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.

[0088] The display panel and the display device provided by the embodiment of the present application are described in detail above, and the principle and implementation manner of the present application are described by applying specific examples in this paper. The above description of the embodiments is only used to help understand the technical solutions and the core idea of the present application; those skilled in the art should understand that the technical solutions recorded in the above embodiments can be modified, or some technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, characterized in that, The display panel also includes a non-display area, and the display panel includes thin-film transistors, the thin-film transistors including a second transistor and a third transistor disposed in the non-display area; The display panel also includes: substrate; A first metal layer is disposed on the substrate and includes the gate of the thin-film transistor. The first metal layer includes the second gate of the second transistor and the third gate of the third transistor. An active layer is disposed on the side of the first metal layer away from the substrate and includes the active portion of the thin-film transistor. The active portion is disposed on the side of the gate away from the substrate. The active layer includes a second active portion of the second transistor and a third active portion of the third transistor. A spacer layer is disposed on the side of the active layer away from the first metal layer and includes a plurality of contact holes; A second metal layer is disposed on the side of the spacer layer away from the active layer, and includes the source and drain of the thin film transistor. The source and drain both pass through the contact hole and overlap with the active portion. The second metal layer includes the second source and the second drain of the second transistor. The second transistor and the third transistor share the second source or the second drain. Wherein, the orthogonal projection of the gate on the substrate covers at least a portion of the orthogonal projection of the contact hole on the substrate.

2. The display panel according to claim 1, characterized in that, The display panel further includes a display area, and the thin-film transistor includes a first transistor disposed within the display area; The first metal layer includes the first gate of the first transistor, the active layer includes the first active portion of the first transistor, the second metal layer includes the first source and the first drain of the first transistor, the first active portion is located on the side of the first gate away from the substrate, and the plurality of contact holes include the first contact hole and the second contact hole, the first source passes through the first contact hole and overlaps with the first active portion, and the first drain passes through the second contact hole and overlaps with the first active portion. Wherein, the orthographic projection of the first contact hole on the substrate and the orthographic projection of the second contact hole on the substrate are both located within the coverage area of ​​the orthographic projection of the first gate on the substrate.

3. The display panel according to claim 2, characterized in that, The orthographic projection of the first active portion on the substrate is within the coverage area of ​​the orthographic projection of the first gate on the substrate.

4. The display panel according to claim 2, characterized in that, The first metal layer further includes a scan line connected to the first gate, and the width of the first gate along a first direction is greater than the width of the scan line along the first direction, the first direction being perpendicular to the extension direction of the scan line.

5. The display panel according to claim 1, characterized in that, The second active portion is located on the side of the second gate away from the substrate. The plurality of contact holes include a third contact hole and a fourth contact hole. The second source electrode passes through the third contact hole and overlaps with the second active portion. The second drain electrode passes through the fourth contact hole and overlaps with the second active portion. Wherein, the orthogonal projection of the second gate on the substrate covers at least a portion of the orthogonal projection of the third contact hole on the substrate, and / or, the orthogonal projection of the second gate on the substrate covers at least a portion of the orthogonal projection of the fourth contact hole on the substrate.

6. The display panel according to claim 5, characterized in that, The orthographic projection boundary of the second gate on the substrate does not exceed the orthographic projection boundary of the second active portion on the substrate.

7. The display panel according to claim 5, characterized in that, The third active portion is disposed on the side of the third gate away from the substrate, and the orthographic projection boundary of the third gate on the substrate does not exceed the orthographic projection boundary of the third active portion on the substrate.

8. The display panel according to claim 7, characterized in that, The second metal layer includes the third source of the third transistor, the third transistor and the second transistor share the second drain, and the third active portion is connected to the second active portion; Wherein, the orthographic projection of the fourth contact hole on the substrate partially overlaps with the orthographic projection of the second gate on the substrate, and the orthographic projection of the fourth contact hole on the substrate partially overlaps with the orthographic projection of the third gate on the substrate.

9. The display panel according to claim 8, characterized in that, The plurality of contact holes also include a fifth contact hole, through which the third source electrode passes and is connected to the third active portion, and the orthogonal projection of the third gate electrode on the substrate covers at least a portion of the orthogonal projection of the fifth contact hole on the substrate.

10. The display panel according to claim 7, characterized in that, The second metal layer includes the third drain of the third transistor, the third transistor shares the second source with the second transistor, and the third active portion is connected to the second active portion; Wherein, the orthographic projection of the third contact hole on the substrate partially overlaps with the orthographic projection of the second gate on the substrate, and the orthographic projection of the third contact hole on the substrate partially overlaps with the orthographic projection of the third gate on the substrate.

11. The display panel according to claim 10, characterized in that, The plurality of contact holes also include a sixth contact hole, through which the third drain electrode passes and is connected to the third active portion, and the orthogonal projection of the third gate electrode on the substrate covers at least a portion of the orthogonal projection of the sixth contact hole on the substrate.

12. The display panel according to claim 7, characterized in that, The second gate is spaced apart from the third gate.

13. The display panel according to claim 7, characterized in that, The second transistor and the third transistor share the second source electrode. The orthographic projection of the third contact hole on the substrate is located within the coverage area of ​​the orthographic projection of the second gate on the substrate, or the orthographic projection of the third contact hole on the substrate is located within the coverage area of ​​the orthographic projection of the third gate on the substrate.

14. The display panel according to claim 7, characterized in that, The second transistor and the third transistor share the second drain. The orthographic projection of the fourth contact hole on the substrate is located within the coverage area of ​​the orthographic projection of the second gate on the substrate, or the orthographic projection of the fourth contact hole on the substrate is located within the coverage area of ​​the orthographic projection of the third gate on the substrate.

15. A display device, characterized in that, The display device includes a display panel as described in any one of claims 1 to 14.

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