Back contact solar cell and method for preparing the same

Abstract

The present invention discloses a back-contact solar cell and a method for preparing the same. The back-contact solar cell comprises: a semiconductor substrate having a first surface and a second surface relative to each other, the first surface comprising a plurality of first regions, a second region and an interlaced overlapping region; a tunneling oxide layer and a P-type doped crystalline silicon layer; a first intrinsic amorphous silicon layer and an N-type doped amorphous silicon layer; an isolation structure, the isolation structure comprising an isolation layer and an isolation groove. The present invention combines the different temperature selective passivation contact technology with the IBC structure to obtain a hybrid back-contact cell technology, thereby solving the problem of easy damage to the n-region due to the narrow process window of the HBC structure n-region and the high cost and complex preparation process of the traditional HBC cell manufacturing process, thereby reducing the process difficulty and manufacturing cost.

Description

Technical Field

[0001] The present invention belongs to the technical field of solar cells, and in particular relates to a back contact solar cell and a preparation method thereof. Background Art

[0002] In recent years, with the continuous development of photovoltaic related technologies, the mass production efficiency of crystalline silicon cells of major manufacturers has been continuously improved. As the oldest crystalline silicon cell technology, IBC cell technology not only has a cell structure with the highest conversion efficiency potential, but also has the ability to be inclusive and constantly absorb the process advantages and passivation technologies of other crystalline silicon technology routes to continuously improve conversion efficiency. IBC has absorbed the advantages of the PERC technology development stage, and the conversion efficiency has been increased to 24%-25%; it has absorbed the TOPCON passivation contact technology and evolved into a TBC (Tunnel oxide Back Contact) cell, with a conversion efficiency of 25%-26%; it has absorbed the amorphous silicon passivation technology of HJT and evolved into an HBC (Hetero-Junction Back Contact) cell, with a conversion efficiency of 26%-27%. However, IBC cell technology has been limited by the high mass production cost and its development has been relatively tortuous.

[0003] Compared with IBC cells, HBC cells use a-Si∶H as a double-sided passivation layer, which has excellent passivation effect and can achieve higher open circuit voltage. In the process of growing PN junctions, they use regional mask doping to reduce carrier recombination losses. The logic of the evolution of high-efficiency crystalline silicon cell technology is to use lower-cost large-scale process means to reduce the recombination of battery carriers, thereby improving open circuit voltage and conversion efficiency.

[0004] The back n-region and p-region of the traditional HBC battery structure are formed of i / n a-Si:H and i / p a-Si:H to form a cross-finger pattern. During the manufacturing process, the damage of the laser to the n-region and p-region needs to be strictly controlled, especially for the n-region, the laser process window is narrow, which increases the process difficulty. HBC batteries also have the following disadvantages in the manufacturing process: a large number of masks and mask removal technologies are used to form patterns, such as the commonly used photolithography technology in the semiconductor field, which has high production costs and difficult process control; in the process of intrinsic and doped amorphous silicon coating operations, the process cleanliness requirements are extremely high due to the narrow process window; amorphous silicon will cause serious parasitic absorption on the negative side of the battery. In addition, the negative velvet structure in this process requires a smoother pyramid to ensure good amorphous silicon passivation, resulting in an increase in negative reflectivity and affecting the photoelectric conversion efficiency; in terms of equipment fixed investment, the CVD equipment for depositing amorphous silicon thin films is expensive and has low production capacity. These aspects restrict the efficiency improvement and cost reduction of HBC batteries and limit its industrial application. Summary of the invention

[0005] The present invention aims to solve at least one of the technical problems in the related art to a certain extent. To this end, the purpose of the present invention is to provide a back-contact solar cell and a method for preparing the same. The present invention combines the different temperature selective passivation contact technology with the IBC structure to obtain a hybrid back-contact cell technology, thereby solving the problem of easy damage to the n-region due to the narrow process window of the n-region of the HBC structure and the high cost and complex preparation process of the traditional HBC cell manufacturing process, thereby reducing the process difficulty and manufacturing cost.

[0006] In one aspect of the present invention, the present invention provides a back-contact solar cell. According to an embodiment of the present invention, the back-contact solar cell comprises:

[0007] A semiconductor substrate, the semiconductor substrate comprising a first surface and a second surface opposite to each other, the first surface comprising a first region, a second region and a staggered overlapping region, the staggered overlapping region being between the first region and the second region, the distance between the first region and a center line of the semiconductor substrate along the width direction being greater than the distance between the second region and the center line of the semiconductor substrate along the width direction, and the distance between the staggered overlapping region and the center line of the semiconductor substrate along the width direction being equal to the distance between the first region and the center line of the semiconductor substrate along the width direction;

[0008] A first tunneling oxide layer and a first P-type doped crystalline silicon layer, wherein the first tunneling oxide layer is on the first region, and the first P-type doped crystalline silicon layer is on a surface of the first tunneling oxide layer away from the semiconductor substrate;

[0009] a first sub-intrinsic amorphous silicon layer and a first N-type doped amorphous silicon layer, wherein the first P-type doped crystalline silicon layer and the first N-type doped amorphous silicon layer have opposite conductivity types, the first sub-intrinsic amorphous silicon layer is on the second region, and the first N-type doped amorphous silicon layer is on a surface of the first sub-intrinsic amorphous silicon layer away from the semiconductor substrate;

[0010] A staggered stacking layer, wherein the staggered stacking layer comprises a second tunneling oxide layer, a second P-type doped crystalline silicon layer, a second sub-intrinsic amorphous silicon layer, and a second N-type doped amorphous silicon layer in the staggered stacking region, wherein the second P-type doped crystalline silicon layer has a conductivity type opposite to that of the second N-type doped amorphous silicon layer;

[0011] The isolation structure includes an isolation layer and an isolation groove, wherein the isolation layer is between the second sub-intrinsic amorphous silicon layer and the second P-type doped crystalline silicon layer, and the isolation groove runs through the second N-type doped amorphous silicon layer and the second sub-intrinsic amorphous silicon layer.

[0012] According to the back contact solar cell of the embodiment of the present invention, compared with the HBC cell structure in the prior art, the present invention adopts a tunneling oxide layer + p-poly-Si layer passivation contact to replace the intrinsic a-si:H + a-si:H(P) film layer passivation in the existing HBC cell structure. Since the tunneling oxide layer + p-poly-Si layer is relatively less sensitive to laser thermal damage, the influence on the passivation effect of the P region can be reduced during the laser film opening process, further increasing the process window and reducing the process difficulty. Compared with the TBC cell structure in the prior art, the present invention adopts an intrinsic amorphous silicon layer ia-Si + na-Si layer passivation contact to replace the SiOx + n-poly-Si in the existing TBC cell structure, avoiding the problem of serious concentric circles of silicon wafers caused by high-temperature preparation of p poly and n poly in TBC cells, thereby improving the surface passivation effect of the N region and improving the electrical performance of the solar cell. Therefore, the back-contact solar cell not only increases the preparation process window of the back-contact solar cell, reduces the process difficulty, but also improves the surface passivation effect of the P region, so that the energy conversion efficiency Eta, open circuit voltage Uoc, short circuit current Isc and fill factor FF of the solar cell can reach the same level as the existing HBC battery structure. In addition, the present invention uses a BSG (borosilicate glass) layer to replace the SiNx mask layer, reducing the coating process required when preparing the SiNx mask layer, thereby reducing the overall manufacturing cost of the battery.

[0013] In addition, the back contact solar cell according to the above embodiment of the present invention may also have the following additional technical features:

[0014] In some embodiments of the present invention, the second area is a suede structure; and / or, the first area is a suede structure; and / or, the second surface is a suede structure.

[0015] In some embodiments of the present invention, the back-contact solar cell also includes: a first electrode layer and a second electrode layer, the first electrode layer is on one side of the isolation groove, and the first electrode layer covers the first N-type doped amorphous silicon layer and a portion of the second N-type doped amorphous silicon layer, and the second electrode layer is on the other side of the isolation groove, and the second electrode layer covers a portion of the second N-type doped amorphous silicon layer and the first P-type doped crystalline silicon layer.

[0016] In some embodiments of the present invention, the first electrode layer and the second electrode layer are transparent conductive layers, and the materials of the first electrode layer and the second electrode layer are independently selected from at least one of indium tin oxide, aluminum zinc oxide, indium hydroxide-doped indium and indium tungsten oxide.

[0017] In some embodiments of the present invention, the isolation layer includes a BSG layer, and the BSG layer is between the second sub-intrinsic amorphous silicon layer and the second P-type doped crystalline silicon layer.

[0018] In some embodiments of the present invention, the thickness of the BSG layer is 80-120 nm.

[0019] In some embodiments of the present invention, a passivation layer is further included, the passivation layer including a third intrinsic amorphous silicon layer and a silicon nitride passivation layer, the third intrinsic amorphous silicon layer is on the second surface, and the silicon nitride passivation layer is on the surface of the third intrinsic amorphous silicon layer away from the semiconductor substrate.

[0020] In some embodiments of the present invention, the first tunneling oxide layer and the second tunneling oxide layer are both tunneling SiO2 layers; and / or, the thickness of the first tunneling oxide layer and the second tunneling oxide layer are both 1.2-1.8 nm; and / or, the thickness of the first P-type doped crystalline silicon layer and the second P-type doped crystalline silicon layer are both 80-200 nm; and / or, the diffusion square resistance of the first P-type doped crystalline silicon layer and the second P-type doped crystalline silicon layer are both 80-120 Ω / sq; and / or, the thickness of the first sub-intrinsic amorphous silicon layer and the second sub-intrinsic amorphous silicon layer are both 5-30 nm; and / or, the thickness of the first N-type doped amorphous silicon layer and the second N-type doped amorphous silicon layer are both 10-30 nm; and / or, the element doping concentration in the first N-type doped amorphous silicon layer and the second N-type doped amorphous silicon layer is both 10e20 cm -3 ~10e21cm -3 .

[0021] In another aspect of the present invention, the present invention provides a method for preparing a back-contact solar cell. According to an embodiment of the present invention, the method comprises:

[0022] Providing a semiconductor substrate, the semiconductor substrate having a first surface and a second surface opposite to each other, the first surface comprising a first region, a second region and an alternating overlapping region, the alternating overlapping region being between the first region and the second region;

[0023] forming a tunneling oxide layer, a P-type doped crystalline silicon layer and an isolation layer in sequence on the first surface;

[0024] Using laser to open the second area to expose a portion of the second area;

[0025] sequentially forming a first intrinsic amorphous silicon layer and an N-type doped amorphous silicon layer on a surface of the prepared intermediate member away from the second surface;

[0026] removing the first intrinsic amorphous silicon layer, the N-type doped amorphous silicon layer and the isolation layer corresponding to the surface of the first region;

[0027] The staggered overlapping regions are etched so that the N-type doped amorphous silicon layer and the first intrinsic amorphous silicon layer in at least a portion of the staggered overlapping regions are etched through to form isolation grooves.

[0028] According to the method of the embodiment of the present invention, compared with the preparation process of HBC cells in the prior art, the method adopts tunneling oxide layer + p-poly-Si layer passivation contact to replace the intrinsic a-si:H + a-si:H(P) film layer passivation in the existing HBC cell structure. Since the tunneling oxide layer + p-poly-Si layer is relatively less sensitive to laser thermal damage, the influence on the passivation effect of the P region can be reduced during the laser film opening process, further increasing the process window and reducing the process difficulty. Compared with the preparation process of TBC cells in the prior art, the method adopts intrinsic amorphous silicon layer ia-Si + na-Si layer passivation contact to replace SiOx + n-poly-Si in the existing TBC cell structure, avoiding the problem of serious concentric circles of silicon wafers caused by high-temperature preparation of p poly and n poly in TBC cells, thereby improving the surface passivation effect of the N region and improving the electrical performance of solar cells. At the same time, this method uses a BSG layer instead of a SiNx mask layer, which reduces the coating process required when preparing the SiNx mask layer. The process is simple and reduces the overall manufacturing cost of the battery. Compared with the SiNx mask layer, the BSG layer has a higher density. During P3 etching, the BSG layer is more stable and not easy to fall off. In addition, this method combines the texturing process with local etching, saving the previous texturing process.

[0029] In some embodiments of the present invention, the method further comprises: performing alkali texturing on the semiconductor substrate after exposing the second region, so as to form a pyramid-like textured structure on the second surface and the second region.

[0030] In some embodiments of the present invention, after a pyramid-like velvet structure is formed on the second surface and the second region, a third intrinsic amorphous silicon layer and a silicon nitride passivation layer are sequentially formed on the second surface.

[0031] In some embodiments of the present invention, after etching the staggered overlapping region, two sides of the isolation trench of the staggered overlapping region are separated into a first staggered overlapping region and a second staggered overlapping region.

[0032] In some embodiments of the present invention, a first electrode layer is formed on one side of the isolation groove, and the first electrode layer covers the N-type doped amorphous silicon layer in the second region and the N-type doped amorphous silicon layer in the staggered overlapping region, respectively, and a second electrode layer is formed on the other side of the isolation groove, and the second electrode layer covers the N-type doped amorphous silicon layer in the staggered overlapping region and the P-type doped crystalline silicon layer in the staggered overlapping region.

[0033] In some embodiments of the present invention, a first gate line is formed on a portion of the surface of the first electrode layer, and a second gate line is formed on a portion of the surface of the second electrode layer.

[0034] In some embodiments of the present invention, the tunneling oxide layer and the P-type doped crystalline silicon layer are deposited by LPCVD.

[0035] In some embodiments of the present invention, the isolation layer includes BSG.

[0036] In some embodiments of the present invention, the step of sequentially forming a tunneling oxide layer, a P-type doped crystalline silicon layer and an isolation layer on the first surface comprises:

[0037] depositing a polysilicon layer after the tunnel oxide layer is formed;

[0038] Diffusion of boron on the polysilicon layer at high temperature to convert the polysilicon layer into the P-type doped crystalline silicon layer;

[0039] The predetermined annealing time is extended to form the BSG layer.

[0040] In some embodiments of the present invention, the temperature for boron diffusion into the polysilicon layer is 980-1050° C.; and / or

[0041] The predetermined annealing time is 40±5 min.

[0042] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0044] Figure 1 A schematic structural diagram of a back-contact solar cell according to an embodiment of the present invention;

[0045] Figure 2 A schematic diagram of the structure of an intermediate component in a process of preparing a back-contact solar cell according to an embodiment of the present invention;

[0046] Figure 3 A schematic diagram of the structure of an intermediate component in a process of preparing a back-contact solar cell according to an embodiment of the present invention;

[0047] Figure 4 A schematic diagram of the structure of an intermediate component in a process of preparing a back-contact solar cell according to an embodiment of the present invention;

[0048] Figure 5 A schematic diagram of the structure of an intermediate component in a process of preparing a back-contact solar cell according to an embodiment of the present invention;

[0049] Figure 6 A schematic diagram of the structure of an intermediate component in a process of preparing a back-contact solar cell according to an embodiment of the present invention;

[0050] Figure 7 A schematic diagram of the structure of an intermediate component in a process of preparing a back-contact solar cell according to an embodiment of the present invention;

[0051] Figure 8 A schematic diagram of the structure of an intermediate component in a process of preparing a back-contact solar cell according to an embodiment of the present invention;

[0052] Fig. 9 It is a schematic structural diagram of an intermediate component in the process of preparing a back-contact solar cell according to an embodiment of the present invention.

[0053] Figure annotation:

[0054] 1-silicon nitride passivation layer, 2-third intrinsic amorphous silicon layer, 3-semiconductor substrate, 3-1-first surface, 3-2-second surface, 4-tunneling oxide layer, 4-1-first tunneling oxide layer, 4-2-second tunneling oxide layer, 5-P-type doped crystalline silicon layer, 5-1-first P-type doped crystalline silicon layer, 5-2-second P-type doped crystalline silicon layer, 6-second electrode layer, 7-second gate line, 8-first intrinsic amorphous silicon layer, 8- 1-first sub-intrinsic amorphous silicon layer, 8-2-second sub-intrinsic amorphous silicon layer, 9-N-type doped amorphous silicon layer, 9-1-first N-type doped amorphous silicon layer, 9-2-second N-type doped amorphous silicon layer, 10-first gate line, 11-isolation layer, 12-isolation groove, 13-first electrode layer, B-first region, C-second region, A-interlaced overlapping region, A1-first interlaced overlapping region, A2-second interlaced overlapping region. DETAILED DESCRIPTION

[0055] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and should not be construed as limiting the present invention.

[0056] In one aspect of the present invention, the present invention provides a back contact solar cell. Figure 1The back-contact solar cell comprises: a semiconductor substrate 3, the semiconductor substrate 3 comprises a first surface 3-1 and a second surface 3-2 relative to each other, the first surface 3-1 comprises a first region (region B), a second region (region C) and an alternating overlapping region (region A), the alternating overlapping region (region A) is between the first region (region B) and the second region (region C), the distance between the first region (region B) and the center line of the semiconductor substrate 3 along the width direction is greater than the distance between the second region (region C) and the center line of the semiconductor substrate 3 along the width direction, and the distance between the alternating overlapping region (region A) and the center line of the semiconductor substrate 3 along the width direction is equal to the distance between the first region (region B) and the center line of the semiconductor substrate 3 along the width direction; a first tunneling oxide layer 4-1 and a first P-type doped crystalline silicon layer 5-1, the first tunneling oxide layer 4-1 is on the first region (region B), the first P-type doped crystalline silicon layer 5-1 is on the first tunneling oxide layer 4-1 away from the semiconductor substrate 3 On the surface; a first sub-intrinsic amorphous silicon layer 8-1 and a first N-type doped amorphous silicon layer 9-1, the first P-type doped crystalline silicon layer 5-1 and the first N-type doped amorphous silicon layer 9-1 have opposite conductivity types, the first sub-intrinsic amorphous silicon layer 8-1 is on the second region (region C), and the first N-type doped amorphous silicon layer 9-1 is on the surface of the first sub-intrinsic amorphous silicon layer 8-1 away from the semiconductor substrate 3; staggered stacking layers, the staggered stacking layers include second tunneling oxides in the staggered stacking region (region A) in sequence Layer 4-2, a second P-type doped crystalline silicon layer 5-2, a second sub-intrinsic amorphous silicon layer 8-2 and a second N-type doped amorphous silicon layer 9-2, the second P-type doped crystalline silicon layer 5-2 and the second N-type doped amorphous silicon layer 9-2 have opposite conductivity types; an isolation structure, the isolation structure includes an isolation layer and an isolation groove, the isolation layer is between the second sub-intrinsic amorphous silicon layer 8-2 and the second P-type doped crystalline silicon layer 5-2, and the isolation groove runs through the second N-type doped amorphous silicon layer 9-2 and the second sub-intrinsic amorphous silicon layer 8-2. Therefore, compared with the HBC battery structure in the prior art, the present invention adopts a tunneling oxide layer + p-poly-Si layer passivation contact to replace the intrinsic a-si:H + a-si:H (P) film layer passivation in the existing HBC battery structure. Since the tunneling oxide layer + p-poly-Si layer is relatively less sensitive to laser thermal damage, the influence on the passivation effect of the P region can be reduced during the laser film opening process, further increasing the process window and reducing the process difficulty. Compared with the TBC battery structure in the prior art, the present invention adopts intrinsic amorphous silicon layer ia-Si+na-Si layer passivation contact to replace SiOx+n-poly-Si in the existing TBC battery structure, avoiding the problem of serious concentric circles of silicon wafers caused by high-temperature preparation of p poly and n poly in TBC batteries, thereby improving the surface passivation effect of the N region and improving the electrical performance of the solar cell.Therefore, the back-contact solar cell not only increases the preparation process window of the back-contact solar cell and reduces the process difficulty, but also improves the surface passivation effect of the P zone, so that the energy conversion efficiency Eta, open circuit voltage Uoc, short circuit current Isc, and fill factor FF of the solar cell can reach a level comparable to that of the existing HBC battery structure.

[0057] In an embodiment of the present invention, the distance between the first region (region B) and the center line of the semiconductor substrate 3 along the width direction is greater than the distance between the second region and the center line of the semiconductor substrate 3 along the width direction, and the distance between the staggered overlapping region and the center line of the semiconductor substrate 3 along the width direction is equal to the distance between the first region (region B) and the center line of the semiconductor substrate 3 along the width direction. The reason for this is that during the preparation of the back-contact solar cell, the second region (region C) is etched to form a depression in the second region (region C), so the boundary area between the second region (region C) and the staggered overlapping region is discontinuous, for example, the second region (region C) and the staggered overlapping region are offset up and down, while the first region (region B) and the staggered overlapping region are continuous.

[0058] In some examples, the interface between the second region (region C) and the staggered overlapping region is an inclined intersection. It should be explained that the back contact solar cell includes a plurality of first regions (region B) (region B), staggered overlapping regions and a plurality of second regions (region C), which are alternately arranged on the first surface 3-1, and the attached Figure 1 Only a first region (region B), an interlaced overlapping region and a second region (region C) are schematically drawn.

[0059] In the embodiment of the present invention, the material of the semiconductor substrate 3 can be selected from materials such as silicon (Si) or germanium (Ge) or materials such as gallium arsenide (GaAs). It should be noted that the first surface 3-1 of the semiconductor substrate 3 refers to the backlight surface, and the second surface 3-2 of the semiconductor substrate 3 refers to the light-facing surface.

[0060] In an embodiment of the present invention, the specific types of the first tunneling oxide layer and the second tunneling oxide layer are not particularly limited. As a specific example, the first tunneling oxide layer and the second tunneling oxide layer are both tunneling SiO2 layers. According to some specific embodiments of the present invention, the thickness of the first tunneling oxide layer and the second tunneling oxide layer is 1.2 to 1.8 nm, thereby further ensuring a better surface passivation effect and ensuring the multi-sub-tunneling effect.

[0061] According to some specific embodiments of the present invention, the thickness of the first P-type doped crystalline silicon layer 5-1 and the second P-type doped crystalline silicon layer 5-2 are both 80-200 nm, thereby minimizing the poly thickness and reducing parasitic absorption while ensuring a good field passivation effect.

[0062] According to some further specific embodiments of the present invention, the diffusion square resistance of the doped crystalline silicon layer in the first P-type doped crystalline silicon layer 5-1 and the second P-type doped crystalline silicon layer 5-2 is 80 to 120 Ω / sq. Thus, while ensuring a better field passivation effect, the contact performance between the subsequent metal paste and the poly is also improved.

[0063] According to some specific embodiments of the present invention, the thickness of the first sub-intrinsic amorphous silicon layer 8-1 and the second sub-intrinsic amorphous silicon layer 8-2 are both 5-30 nm, thereby having a good passivation effect on the silicon-based surface.

[0064] According to some further specific embodiments of the present invention, the thickness of the first N-type doped amorphous silicon layer 9 - 1 and the second N-type doped amorphous silicon layer 9 - 2 are both 10 to 30 nm, which is beneficial for matching the subsequent laser and cleaning steps.

[0065] According to some specific embodiments of the present invention, the element doping concentrations in the first N-type doped amorphous silicon layer 9-1 and the second N-type doped amorphous silicon layer 9-2 are both 10e20cm -3 ~10e21cm -3 Therefore, while taking into account the passivation effect, there is also good contact performance.

[0066] According to some other specific embodiments of the present invention, the isolation layer includes a BSG layer, and the BSG layer is between the second sub-intrinsic amorphous silicon layer 8-2 and the second P-type doped crystalline silicon layer. The BSG layer is a borosilicate glass layer, and its composition is silicon oxide doped with boron. As a laser energy absorption layer and a mask layer, the BSG layer has the function of reducing the influence of the laser film opening process on the passivation effect of the P region, and also has the function of providing a hydrogen source to further passivate the polysilicon and the substrate, thereby improving the passivation effect, and protecting the P-type doped crystalline silicon layer from alkali corrosion during the texturing process. Compared with the SiNx layer as a mask, the process steps can be simplified to avoid repeated masking during the operation. It should be noted that the isolation groove may pass through the above-mentioned BSG layer, or may not pass through the above-mentioned BSG layer.

[0067] According to some specific embodiments of the present invention, the thickness of the BSG layer is 80-120 nm, thereby further ensuring the effect of the BSG layer as a laser energy absorption layer and a mask layer.

[0068] Further, see Attachment Figure 1The back contact solar cell further includes: a first electrode layer 13 and a second electrode layer 6, wherein the first electrode layer 13 is on one side of the isolation groove and covers the first N-type doped amorphous silicon layer, and the second electrode layer 6 is on the other side of the isolation groove and covers a portion of the second N-type doped amorphous silicon layer 9-2 and the first P-type doped crystalline silicon layer 5-1. The first electrode layer 13 enhances the conductivity between the N-type doped amorphous silicon layer and the first gate line, and the second electrode layer 6 enhances the conductivity between the P-type doped crystalline silicon layer and the second gate line.

[0069] In the embodiment of the present invention, the first electrode layer 13 and the second electrode layer 6 are transparent conductive layers. The specific materials of the first electrode layer 13 and the second electrode layer 6 are not particularly limited. As some specific examples, the materials of the first electrode layer 13 and the second electrode layer 6 are independently selected from at least one of indium tin oxide, aluminum zinc oxide, indium hydroxide-doped indium and indium tungsten oxide. In some examples, the thickness of the first electrode layer 13 and the second electrode layer 6 can be 60 to 100 nm.

[0070] Further, see Attachment Figure 1 , the back contact solar cell also includes: a passivation layer, the passivation layer includes a third intrinsic amorphous silicon layer 2 and a silicon nitride passivation layer 1, the third intrinsic amorphous silicon layer 2 is on the second surface, and the silicon nitride passivation layer 1 is on the surface of the third intrinsic amorphous silicon layer 2 away from the semiconductor substrate. The silicon nitride passivation layer 11 has the function of being a reflection prevention film and a protective film, and also has the function of being a passivation film that inhibits the recombination of photocarriers. The third intrinsic amorphous silicon layer 2 has the function of inhibiting the recombination of photocarriers at the bonding interface with the second surface 3-2. In some examples, at least part of the second surface 3-2 is provided with a velvet structure, that is, at least part of the second surface 3-2 is provided with a lot of pyramids, thereby increasing the light receiving surface of the second surface 3-2. In some other examples, the first area is a velvet structure; and / or, the second area is a velvet structure, and the velvet structures on the first area and the second area are formed in the cleaning step of the preparation process of the back contact solar cell.

[0071] In another aspect of the present invention, the present invention provides a method for preparing a back-contact solar cell. According to an embodiment of the present invention, the method comprises:

[0072] S100: Provide semiconductor substrate

[0073] In this step, a semiconductor substrate 3 is provided. The semiconductor substrate may be an N-type substrate or a P-type substrate. The semiconductor substrate 3 has a first surface 3-1 and a second surface 3-2 opposite to each other. Figure 2As shown. The first surface 3-1 of the semiconductor substrate 3 refers to the backlight surface, and the second surface 3-2 of the semiconductor substrate 3 refers to the frontlight surface. The first surface includes a first area, a second area, and an interlaced overlapping area, and the interlaced overlapping area is between the first area and the second area.

[0074] In the embodiment of the present invention, the material of the semiconductor substrate 3 may be selected from materials such as silicon (Si) or germanium (Ge) or materials such as gallium arsenide (GaAs).

[0075] In order to ensure the cleanliness of the semiconductor substrate 3 and remove the cutting damage layer of the silicon wafer, the bare silicon wafer can be put into a tank polishing and cleaning machine for a polishing process. In some examples, the cleaning solution is a KOH solution with a mass concentration of 5.5-6.5%, the solution temperature during cleaning is 81-87°C, the cleaning time is 290-310s, and a block with a size of 20±3μm is obtained. The reflectivity of the backlight surface of the silicon wafer is 40-44%.

[0076] S200: forming a tunneling oxide layer, a P-type doped crystalline silicon layer and an isolation layer in sequence on the first surface

[0077] In this step, low pressure chemical vapor deposition furnaces such as LPCVD, PECVD, PVD, and PEALD can be used to prepare the tunnel oxide layer 4 and the intrinsic or in-situ doped poly Si. Preferably, LPCVD is used to deposit the back tunnel oxide layer 4 and the polysilicon (poly) layer. The deposition temperature of the tunnel oxide layer 4 is 590±20°C, and the deposition temperature of the polysilicon (poly) layer is 590±20°C. The deposition of the intrinsic a-si:H+a-si:H(N) film layer in the existing HBC battery structure mostly uses expensive CVD equipment, while the present application uses inexpensive LPCVD equipment to replace the expensive CVD equipment, effectively reducing the equipment investment cost.

[0078] Then, the intermediate after the polysilicon (poly) layer is deposited is placed in a tubular diffusion furnace, and a boron-containing compound is introduced to convert the polysilicon into a P-type doped crystalline silicon layer 5 at a high temperature of 980-1050° C., and an isolation layer 11 (i.e., a BSG layer) is formed during the annealing process by extending the annealing time. In some examples, the annealing time may be 40±5 minutes.

[0079] In some examples, the diffusion square resistance of the P-type doped crystalline silicon layer 5 is 80 to 120 Ω / sq. In some examples, the thickness of the P-type doped crystalline silicon layer 5 is 80 to 200 nm. In some examples, the thickness of the tunneling oxide layer 4 is 1.2 to 1.8 nm. In an embodiment of the present invention, the specific type of the tunneling oxide layer 4 is not particularly limited, for example, the tunneling oxide layer 4 is a tunneling SiO2 layer.

[0080] The BSG layer, as a laser energy absorption layer and mask layer, has the function of reducing the influence of the laser film opening process on the passivation effect of the P region, and also has the function of providing a hydrogen source to further passivate the polysilicon and the substrate, thereby improving the passivation effect and protecting the P-type doped crystalline silicon layer 5 from being corroded by alkali during the texturing process. In some examples, the thickness of the BSG layer 11 is 80 to 120 nm, thereby further ensuring the above-mentioned effect of the BSG layer 11.

[0081] S300: Using laser to open the isolation layer, P-type doped crystalline silicon layer, and tunnel oxide layer in the second region

[0082] In this step, the isolation layer in the second region is opened by laser to expose the semiconductor substrate 3 in the second region on the first surface, and the remaining tunnel oxide layer and the P-type doped crystalline silicon layer are in the first region and the staggered overlapping region. Figure 4 As shown, the tunneling oxide layer 4 and the P-type doped crystalline silicon layer 5 in the first region (region B) are the first tunneling oxide layer 4-1 and the first P-type doped crystalline silicon layer 5-1, respectively, and the tunneling oxide layer 4 and the P-type doped crystalline silicon layer 5 in the staggered overlapping region (region A) are the second tunneling oxide layer 4-2 and the second P-type doped crystalline silicon layer 5-2, respectively. In this step, the laser process can be directly used to open the film, and there is no need to use the mask and mask removal technology for multiple times to form a pattern, which reduces the process difficulty. In the existing HBC battery structure, this step generally uses a large number of mask and mask removal technologies to form a pattern, which has high production costs and is difficult to control the process. The present invention saves the mask and mask removal steps in the process of laser film opening in this step, thereby improving production efficiency.

[0083] In the embodiment of the present invention, a graphic corresponding to a silk screen pattern may be used for design, and the laser type may be green light nanosecond, ultraviolet picosecond, green light picosecond or ultraviolet nanosecond.

[0084] S400: forming a first intrinsic amorphous silicon layer and an N-type doped amorphous silicon layer in sequence on a surface of the intermediate member prepared in step S300 away from the second surface

[0085] In this step, a first intrinsic amorphous silicon layer 8 and an N-type doped amorphous silicon layer 9 are sequentially formed on the surface of the intermediate member prepared in step S300 away from the second surface 3-2 by using a CVD device. The intermediate member prepared is as shown in the attached figure. Figure 6As shown. Specifically, the deposition temperature of the first intrinsic amorphous silicon layer 8 is 180-300°C, and the deposition temperature of the N-type doped amorphous silicon layer 9 is 180-300°C. The present application adopts the first intrinsic amorphous silicon layer and the N-type doped amorphous silicon layer passivation contact to replace the SiOx+ doped crystalline silicon layer in the existing TBC battery structure, thereby improving the surface passivation effect of the first doping region, thereby improving the electrical performance of the solar cell. In some examples, the thickness of the first intrinsic amorphous silicon layer is 5 to 30 nm. In some examples, the thickness of the N-type doped amorphous silicon layer is 10 to 30 nm. In some examples, the element doping concentration in the N-type doped amorphous silicon layer is 10e20cm -3 ~10e21cm -3 .

[0086] According to a specific embodiment of the present invention, step S400 further includes: before forming the first intrinsic amorphous silicon layer 8 and the N-type doped amorphous silicon layer 9, first forming a third intrinsic amorphous silicon layer 2 and a silicon nitride passivation layer 1 in sequence on the second surface 3-2. The silicon nitride passivation layer 1 has the function of being a reflection prevention film and a protective film, and also has the function of being a passivation film for suppressing photocarrier recombination. The third intrinsic amorphous silicon layer 2 has the function of suppressing photocarrier recombination at the bonding interface with the second surface 3-2.

[0087] It should be noted that the reason for depositing the third intrinsic amorphous silicon layer and the silicon nitride passivation layer before forming the first intrinsic amorphous silicon layer and the N-type doped amorphous silicon layer is that the third intrinsic amorphous silicon layer and the silicon nitride passivation layer need to be subjected to high temperature treatment, thereby preventing the N-type doped amorphous silicon layer from experiencing high temperature. In addition, the high temperature treatment of the third intrinsic amorphous silicon layer and the silicon nitride passivation layer will produce a very thin layer of silicon oxide on the velvet surface of the exposed second region, so the exposed second region subjected to high temperature can be placed in an acid solution (such as an HF solution) for about 30 seconds for etching, thereby removing the above silicon oxide.

[0088] Furthermore, between steps S300 and S400, the method further includes: performing alkali texturing on the surface of the intermediate member prepared in step S300, so as to form a pyramid-like textured surface structure on the second surface and the second region, and removing the BSG layer, tunnel oxide layer or P-type doped crystalline silicon layer remaining in the laser second region. The cleaning solution may be an acid solution, such as hydrofluoric acid. Preferably, in the cleaning step, the second surface 3-2 can be textured at the same time. Specifically, the silicon wafer is first placed in an HF tank with a HF solution concentration of 1±0.5%, treated at 25°C for 30±5s, and the laser grooved area is treated for residual BSG removal. The silicon wafer is then placed in an alkaline tank for texture treatment. The alkaline tank solution is a 3±0.5% concentration of KOH + texture additive solution, the solution temperature is 82±2°C, and the operation process time is 600±30s. Thus, a silicon wafer with an etching amount of 0.6±0.1g and a reflectivity of 11±1% is obtained. Therefore, this step not only completes the removal of the residues in the second area after the laser, but also completes the texture of the second surface 3-2. As shown in the attached Figure 5 It should be noted that, it is precisely because of the texturing step of the second area that the second area is recessed into the first area and the staggered overlapping area, that is, the distance between the first area and the center line of the semiconductor substrate along the width direction is greater than the distance between the second area and the center line of the semiconductor substrate along the width direction, and the distance between the staggered overlapping area and the center line of the semiconductor substrate along the width direction is equal to the distance between the first area and the center line of the semiconductor substrate along the width direction.

[0089] S500: removing the first intrinsic amorphous silicon layer, the N-type doped amorphous silicon layer and the isolation layer corresponding to the surface of the first region

[0090] In this step, the first intrinsic amorphous silicon layer, the N-type doped amorphous silicon layer and the isolation layer corresponding to the surface of the first region are removed, and the remaining first intrinsic amorphous silicon layer and the N-type doped amorphous silicon layer are distributed in the second region and the staggered overlapping region, and the remaining isolation layer is distributed in the staggered overlapping region.

[0091] Specifically, a laser is first used to remove the first intrinsic amorphous silicon layer and the N-type doped amorphous silicon layer corresponding to the surface of the first region to expose the isolation layer. In some examples, a green nanosecond, ultraviolet picosecond, green picosecond or ultraviolet nanosecond laser may be used to open the film. In some examples, the power of the laser is 6-12W.

[0092] Then, an acid solution (such as HF solution) is used to remove the exposed isolation layer (i.e., BSG layer) to expose the remaining P-type doped crystalline silicon layer. The remaining first intrinsic amorphous silicon layer 8 and the N-type doped amorphous silicon layer 9 are distributed in the second region (region C) and the staggered overlapping region (region A). The remaining isolation layer 11 is distributed in the staggered overlapping region (region A). The structure of the intermediate member is as shown in the attached figure. Figure 7As shown. Among them, the first intrinsic amorphous silicon layer 8 in the second region (region C) is the first sub-intrinsic amorphous silicon layer 8-1, the N-type doped amorphous silicon layer 9 in the second region (region C) is the first N-type doped amorphous silicon layer 9-1, the first intrinsic amorphous silicon layer 8 in the staggered overlapping region (region A) is the second sub-intrinsic amorphous silicon layer 8-2, and the N-type doped amorphous silicon layer 9 in the staggered overlapping region (region A) is the second N-type doped amorphous silicon layer 9-2. The purpose of step S500 is to expose the first P-type doped crystalline silicon layer 5-1 in the grooved area to facilitate the subsequent steps of preparing the second electrode layer and the second gate line. In addition, since the present application adopts a tunneling oxide layer + p-poly-Si layer passivation contact in S200 to replace the intrinsic a-si:H + a-si:H(P) film layer passivation in the existing HBC battery structure, and the tunneling oxide layer + p-poly-Si layer is relatively less sensitive to laser thermal damage, the power application range of the laser is broadened in the process of applying laser etching, that is, the process window is increased, the convenience of the process is improved, and thus the yield of the product is improved.

[0093] S600: Slotting the overlapping areas

[0094] In this step, the laser ablation technology is used to groove the staggered overlapping area (area A), so that the isolation groove penetrates the N-type doped amorphous silicon layer (i.e., the second N-type doped amorphous silicon layer 9-2) and the first intrinsic amorphous silicon layer (i.e., the second sub-intrinsic amorphous silicon layer 8-2) in the staggered overlapping area to expose part of the isolation layer 11, forming an isolation groove 12. The isolation groove 12 divides the stacking area (area A) into a first stacking area (area A1) and a second stacking area (area A2). Fig. 9 In some examples, the width of the isolation trench 12 is 20-200 μm, preferably 80-120 μm.

[0095] Further, after the staggered overlapping region is grooved, the method further includes: forming a first electrode layer 13 on one side of the isolation groove 12, and the first electrode layer 13 covers the N-type doped amorphous silicon layer 9 of the second region (region C) and the staggered overlapping region (region A), respectively, and forming a second electrode layer 6 on the other side of the isolation groove 12, and the second electrode layer 6 covers the N-type doped amorphous silicon layer 9 of the staggered overlapping region (region A) and the P-type doped crystalline silicon layer 5 of the first region (region A), wherein the structure of the intermediate member is as shown in the attached Figure 8 The first electrode layer 13 is used to enhance the conductivity between the N-type doped amorphous silicon layer 9 and the first gate line 10, and the second electrode layer 6 is used to enhance the conductivity between the P-type doped crystalline silicon layer 5 and the second gate line 7. In some embodiments, an electrode layer may be formed on the surface of the N-type doped amorphous silicon layer, and the structure of the intermediate member is as shown in the attached figure. Figure 8 As shown, the grooves are then cut in the staggered overlapping areas, as shown in the attached Fig. 9 shown.

[0096] In the embodiment of the present invention, the first electrode layer 13 and the second electrode layer 6 are transparent conductive layers. The specific materials of the first electrode layer 13 and the second electrode layer 6 are not particularly limited. As some specific examples, the materials of the first electrode layer 13 and the second electrode layer 6 are independently selected from at least one of indium tin oxide, aluminum zinc oxide, indium hydroxide-doped indium and indium tungsten oxide. In some examples, the thickness of the first electrode layer 13 and the second electrode layer 6 can be 60 to 100 nm.

[0097] Furthermore, the method further includes: forming a first gate line 10 on a partial surface of the first electrode layer 13, and forming a second gate line 7 on a partial surface of the second electrode layer 6. Specifically, the first gate line 10 can be formed on a partial surface of the first electrode layer 13, and the second gate line 7 can be formed on a partial surface of the second electrode layer 6 by screen printing, inkjet printing, laser transfer, chemical plating, electroplating or PVD.

[0098] According to the method of the embodiment of the present invention, compared with the preparation process of HBC batteries in the prior art, the method adopts tunneling oxide layer + p-poly-Si layer passivation contact to replace the intrinsic a-si:H + a-si:H(P) film layer passivation in the existing HBC battery structure. Since the tunneling oxide layer + p-poly-Si layer is relatively less sensitive to laser thermal damage, the influence on the passivation effect of the P region can be reduced during the laser film opening process. Therefore, the laser process can be directly used for film opening in steps S500 and S600. The laser film opening process can reduce the influence on the passivation effect of the P region, further increase the process window, and reduce the process difficulty. In the existing HBC battery structure, this step generally uses a large number of masks and demasking technologies to form patterns, which has high production costs and great process control difficulties. At the same time, this method uses a BSG layer instead of a SiNx mask layer, reducing the coating process required for preparing the SiNx mask layer. The process is simple, which reduces the overall manufacturing cost of the battery. Compared with the SiNx mask layer, the BSG layer has a higher density. During etching, the BSG layer is more stable and less likely to fall off. In addition, this method combines the texturing process with local etching, saving the previous texturing process. In the deposition process of the tunneling oxide layer and the P-type doped crystalline silicon layer p-poly-Si, the inexpensive LPCVD equipment is used to replace the expensive CVD equipment, effectively reducing the equipment investment cost.

[0099] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention.

[0100] The embodiments of the present invention are described in detail below. It should be noted that the embodiments described below are exemplary and are only used to explain the present invention, and cannot be interpreted as limiting the present invention. In addition, if not explicitly stated, all reagents used in the following embodiments are commercially available, or can be synthesized according to this article or known methods, and the reaction conditions not listed are also easily available to those skilled in the art.

[0101] Example 1

[0102] This embodiment provides a solar cell, and the preparation method thereof is as follows:

[0103] 1) Provide an N-type 1.3Ωcm 166*166 silicon wafer with a thickness of 165μm.

[0104] 2) Polishing and cleaning: Put the above silicon wafer into a tank-type alkaline polishing machine for polishing and cleaning. The working volume of the tank of the cleaning machine is 360L. First, pre-clean the silicon wafer to remove organic and other contaminants generated during the cutting and transportation of the silicon wafer. This embodiment uses the SC1 reagent of the standard RCA cleaning for cleaning. The main function of the SC1 reagent cleaning is alkaline oxidation to remove particles on the silicon wafer, and can oxidize and remove a small amount of organic matter and metal atomic pollution such as Au, Ag, Cu, Ni, Cd, Zn, Ca, Cr, etc. on the surface; after washing the residual chemicals with water, perform alkaline polishing treatment. The alkaline polishing formula is 5.97%wt KOH, the temperature is 80°C, and the alkaline polishing treatment time is 300s to remove damage and polish. Then perform SC1 cleaning, ozone cleaning, and finally acid washing and dehydration to complete polishing and cleaning. The temperature is controlled below 80°C during cleaning. The control below 80°C is to reduce the loss caused by the volatilization of ammonia and hydrogen peroxide.

[0105] 3) The polished silicon wafer is sent to a low-pressure vapor deposition LPCVD to deposit a tunneling SiO2 with a thickness of 1.4 nm and an intrinsic polysilicon poly Si with a thickness of 90 nm. The deposition temperature of the tunneling SiO2 is 590°C, and the deposition temperature of the intrinsic polysilicon poly Si is 590°C.

[0106] 4) The intermediate after the deposition of the polycrystalline silicon (poly) layer is placed in a tubular diffusion furnace, and BCl3 is introduced. The poly Si area is doped with boron at 1000°C and the poly is crystallized to form a P-type crystalline silicon layer p-poly-Si, whose diffusion square resistance is 100Ω / sq. During the annealing process of the P-type crystalline silicon layer p-poly-Si, a 90nm thick BSG layer is formed. The reason for the complete crystallization of poly is that poly si will turn from amorphous to crystalline at high temperature, and here, 100% crystallization can be completed due to the high temperature of boron diffusion.

[0107] 5) Use a 532nm green nanosecond laser to open the BSG film in the N region to expose the backlight side of the silicon wafer. Figure 1 Zone C in.

[0108] 6) Place the silicon wafer after laser treatment into the texturing machine. The working volume of the machine tank is 360L. Its main process and functions are as follows: ① The first functional tank uses 1%wt HF at a constant temperature of 25℃ to remove the residue. ② After cleaning, the silicon wafer enters the next texturing tank. The texturing liquid is 3.29%wt KOH solution, the texturing temperature is 82℃, and the texturing time is 570s. Thus, the texturing treatment of the front and back laser areas is completed. ③ Then perform high-efficiency SC1 cleaning. The cleaning liquid is NH4OH-H2O2-H2O. The volume ratio of the three is 1:1:5. The cleaning temperature is 65℃ and the cleaning time is 300s. ④ Use 50ppm O3 water plus HF for pyramid smoothing treatment. The hydrofluoric acid concentration is 0.31%wt. ⑤ Perform SC2 metal residue removal cleaning. The cleaning liquid is HCL-H2O2-H2O. The volume ratio of the three is 1:1:5. The cleaning temperature is 65℃ and the cleaning time is 200s. ⑥Finally, the surface is cleaned with 5% wt hydrofluoric acid to complete the texturing.

[0109] 7) On the front side, a-si:H with a thickness of 15 nm and SiNx with a thickness of 90 nm are sequentially deposited. The deposition temperature of a-si:H is 200° C., and the deposition temperature of SiNx is 550° C.

[0110] 8) Using CVD equipment, a-si:H (i.e., the first intrinsic amorphous silicon layer ia-Si) with a thickness of 10 nm and a-si:H(N) (i.e., the N-type amorphous silicon layer na-Si) with a thickness of 15 nm are deposited on the back of the silicon wafer. The deposition temperature of a-si:H is 200°C, and the deposition temperature of a-si:H(N) is 200°C.

[0111] 9) A nanosecond laser is used to open the N-type amorphous silicon layer na-Si and the first intrinsic amorphous silicon layer ia-Si on the B region to expose the BSG layer on the B region. The laser power is 12W.

[0112] 10) Using 8% wt hydrofluoric acid to clean the BSG layer exposed in step 7), thereby removing the BSG layer in the grooved area to expose a portion of the P-type doped crystalline silicon layer p-poly-Si.

[0113] 11) Deposit an ITO (Indium Tin Oxide) layer with a thickness of 80 nm on the back side.

[0114] 12) Use ultraviolet picosecond laser to open grooves to expose the BSG layer and form isolation grooves to insulate the N region and P region to prevent leakage caused by the interconnection of the N / P regions. The insulation resistance of the test isolation region is >10MΩ.

[0115] 13) Using screen printing technology, silver metal is used to prepare the back metallized electrode, and then solidified and annealed.

[0116] Example 2

[0117] This embodiment provides a solar cell. The difference between this embodiment and Embodiment 1 is that:

[0118] 3) The polished wafer is sent into a low-pressure vapor deposition (LPCVD) to deposit SiO2 with a thickness of 1.4 nm and intrinsic polysilicon (poly Si) with a thickness of 120 nm.

[0119] Example 3

[0120] This embodiment provides a solar cell. The difference between this embodiment and embodiment 1 is that:

[0121] 3) The polished wafer is sent to a low-pressure vapor deposition (LPCVD) to deposit SiO2 with a thickness of 1.4 nm and intrinsic polysilicon (poly Si) with a thickness of 150 nm.

[0122] Example 4

[0123] This embodiment provides a solar cell. The difference between this embodiment and Embodiment 1 is that:

[0124] 9) Use nanosecond laser to open the N-type amorphous silicon layer na-Si and the first intrinsic amorphous silicon layer ia-Si on the B area to expose the BSG layer on the B area, with a laser power of 10W.

[0125] Example 5

[0126] This embodiment provides a solar cell. The difference between this embodiment and embodiment 1 is that:

[0127] 9) A nanosecond laser is used to open the N-type amorphous silicon layer na-Si and the first intrinsic amorphous silicon layer ia-Si on the B region to expose the BSG layer on the B region. The laser power is 8W.

[0128] Example 6

[0129] This embodiment provides a solar cell. The difference between this embodiment and embodiment 1 is that:

[0130] 9) A nanosecond laser is used to open the N-type amorphous silicon layer na-Si and the first intrinsic amorphous silicon layer ia-Si on the B region to expose the BSG layer on the B region. The laser power is 6W.

[0131] Example 7

[0132] This embodiment provides a solar cell. The difference between this embodiment and embodiment 2 is that:

[0133] 9) Use nanosecond laser to open the N-type amorphous silicon layer na-Si and the first intrinsic amorphous silicon layer ia-Si on the B area to expose the BSG layer on the B area, with a laser power of 10W.

[0134] Example 8

[0135] This embodiment provides a solar cell. The difference between this embodiment and embodiment 3 is that:

[0136] 9) Use nanosecond laser to open the N-type amorphous silicon layer na-Si and the first intrinsic amorphous silicon layer ia-Si on the B area to expose the BSG layer on the B area, with a laser power of 10W.

[0137] Comparative Example 1

[0138] This comparative example provides a method for preparing a HBC solar cell, comprising the following steps:

[0139] 1) Provide an N-type 1.3Ωcm 166*166 silicon wafer with a thickness of 165μm.

[0140] 2) Polishing and cleaning: Put the above silicon wafer into a tank-type alkaline polishing machine for polishing and cleaning. The working volume of the tank of the cleaning machine is 360L. First, pre-clean the silicon wafer to remove organic and other contaminants generated during the silicon wafer cutting and transportation process. This embodiment uses the No. 1 solution of standard RCA cleaning for cleaning. The No. 1 solution is composed of NH4OH-H2O2-H2O. The volume ratio of the three is 1:1:5, and the temperature during cleaning is 65°C. The main function of SC-1 reagent cleaning is alkaline oxidation to remove particles on the silicon wafer, and can oxidize and remove a small amount of organic matter and metal atomic pollution such as Au, Ag, Cu, Ni, Cd, Zn, Ca, Cr, etc. on the surface; alkaline polishing treatment is performed after water washing and residual chemicals. The alkaline polishing formula is 5.97%wt KOH, the temperature is 80°C, and the alkaline polishing treatment time is 300s to remove damage and polish. Then perform SC1 cleaning, ozone cleaning, and finally acid washing and dehydration to complete polishing and cleaning.

[0141] 3) Using PECVD equipment, a layer of SiNx mask with a thickness of 200nm and a refractive index of 2.4% is deposited on the back of the silicon wafer;

[0142] 4) In the tank cleaning machine, first put the silicon wafer into the HF tank, the mass concentration of the HF solution is 1%, and it is treated at room temperature for 30 seconds to remove the SiNx plated on the side and front of the battery. Then it enters the alkaline tank for texturing treatment. The texturing solution is a KOH+texturing additive solution with a mass concentration of 2.5%. The texturing temperature is 82°C and the texturing time is 780 seconds. Then it enters the HNO3 / HF tank for velvet smoothing treatment. The solution volume ratio HNO3:HF=1:100, the total etching amount is 1.8g, the reflectivity of the front side is 12%, and the velvet pyramid size is 4um. The large velvet microstructure, finally treated in the 8%wt HF tank at room temperature for 300 seconds, completely remove the SiNx mask remaining on the back.

[0143] 5) In a CVD device, 15 nm of intrinsic a-si:H, 25 nm of phosphorus-doped a-si:H(N), 200 nm of SiNx layer and 15 nm of intrinsic a-si:H are sequentially deposited on the back of the silicon wafer.

[0144] 6) Use laser to groove the outermost layer of intrinsic a-si:H on the back side to create a P+ region, which is the area for the deposition of intrinsic a-si:H and a-si:H(P) in subsequent steps.

[0145] 7) In a tank cleaning machine, the silicon wafer is first placed in an HF tank with an HF solution concentration of 8% and a treatment time of 200 seconds to remove SiNx from the laser grooved area; then it enters an alkaline tank for etching with a solution of 0.5wt% KOH plus 0.15wt% H2O2 solution at a solution temperature of 25°C and an etching time of 400 seconds to remove the residual intrinsic a-si:H and phosphorus-doped a-si:H(N) layers.

[0146] 8) In the CVD equipment, the back side of the silicon wafer is coated with 15nm thick intrinsic a-si:H and 25nm thick B-doped a-si:H(P) in sequence.

[0147] 9) In the CVD equipment, an intrinsic a-si:H layer with a thickness of 15 nm and a SiNx layer with a thickness of 85 nm are deposited on the front side of the silicon wafer in sequence.

[0148] 10) Use laser to etch part of the intrinsic a-si:H and a-si:H(P) in the back N+ region, with a laser power of 6W.

[0149] 11) The SiNx layer leaking out of the N+ region after laser treatment was removed using HF solution with a mass concentration of 8% for 400 seconds to expose the phosphorus-doped a-si:H(N) layer.

[0150] 12) Deposit an ITO (indium tin oxide) layer on the back with a thickness of 80 nm.

[0151] 13) Use 355nm ultraviolet picosecond laser to open grooves to expose the SiNx mask layer and form isolation grooves to insulate the N region and P region to prevent leakage caused by the interconnection of the N / P regions. The insulation resistance of the test isolation region is >10MΩ, and the laser width is 100μm.

[0152] 14) Using metal silver through screen printing technology, the back metallization electrode is prepared, and then cured and annealed.

[0153] Comparative Example 2

[0154] The difference between this comparative example and comparative example 1 is only that:

[0155] 10) Use laser to etch part of the intrinsic a-si:H and a-si:H(P) in the back N+ region, with a laser power of 10W.

[0156] Comparative Example 3

[0157] The difference between this comparative example and comparative example 1 is only that:

[0158] 10) Use laser to etch part of the intrinsic a-si:H and a-si:H(P) in the back N+ region, with a laser power of 12W.

[0159] The energy conversion efficiency Eta, open circuit voltage Uoc, short circuit current Isc and fill factor FF of the solar cells prepared in Examples 1-8 and Comparative Examples 1-3 were tested for performance. The results are shown in Table 1.

[0160] Table 1

[0161]

[0162] It can be seen that the mask and mask removal techniques are used multiple times in comparative examples 1-3 to form patterning, which has high production costs and great difficulty in process control, while the tunneling SiO2 layer + P-type doped crystalline silicon layer p-poly-Si passivation contact is used in Example 1-8 to replace the intrinsic a-si:H + a-si:H(p) film layer passivation in comparative example 1. Since the tunneling SiO2 layer + P-type doped crystalline silicon layer p-poly-Si in Example 1-8 is relatively less sensitive to laser thermal damage, the laser process can be directly used to open the film in this step, and it is not necessary to use the mask and mask removal techniques multiple times to form patterning. Comparative example 1 produces higher efficiency at lower laser power, but at higher laser power, comparative examples 2-3 show a significant decrease in efficiency. It can be seen that the tunneling SiO2 layer + P-type crystalline silicon layer is relatively less sensitive to laser thermal damage, and the influence on the passivation effect of the corresponding doping area in the first region can be reduced during the laser film opening process.

[0163] It can also be seen from Table 1 that, compared with Comparative Examples 1-3, the energy conversion efficiency Eta, open circuit voltage Uoc, short circuit current Isc and fill factor FF of Examples 1-8 all reached a level comparable to that of Comparative Example 1.

[0164] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0165] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

Claims

1. A back contact solar cell, characterized in that: include: A semiconductor substrate, the semiconductor substrate comprising a first surface and a second surface opposite to each other, the first surface comprising a first region, a second region and an interleaved overlapping region, the interleaved overlapping region being between the first region and the second region, the distance between the first region and a center line of the semiconductor substrate along a width direction being greater than the distance between the second region and a center line of the semiconductor substrate along a width direction, the first region and the interleaved overlapping region being polished surfaces, the polished surface comprising a square-shaped structure, the second region being a velvet surface, and the interface between the second region and the interleaved overlapping region being intersected by an inclined surface; A first tunneling oxide layer and a first P-type doped crystalline silicon layer, wherein the first tunneling oxide layer is on the first region, and the first P-type doped crystalline silicon layer is on a surface of the first tunneling oxide layer away from the semiconductor substrate; a first sub-intrinsic amorphous silicon layer and a first N-type doped amorphous silicon layer, wherein the first P-type doped crystalline silicon layer and the first N-type doped amorphous silicon layer have opposite conductivity types, the first sub-intrinsic amorphous silicon layer is on the second region, and the first N-type doped amorphous silicon layer is on a surface of the first sub-intrinsic amorphous silicon layer away from the semiconductor substrate; A staggered stacking layer, wherein the staggered stacking layer comprises a second tunneling oxide layer, a second P-type doped crystalline silicon layer, a second sub-intrinsic amorphous silicon layer, and a second N-type doped amorphous silicon layer in the staggered stacking region, wherein the second P-type doped crystalline silicon layer has a conductivity type opposite to that of the second N-type doped amorphous silicon layer; an isolation structure, the isolation structure comprising an isolation layer and an isolation groove, the isolation layer being between the second sub-intrinsic amorphous silicon layer and the second P-type doped crystalline silicon layer, and the isolation groove penetrating the second N-type doped amorphous silicon layer and the second sub-intrinsic amorphous silicon layer; The thickness of the first tunnel oxide layer and the second tunnel oxide layer are both 1.2-1.8 nm.

2. The back contact solar cell according to claim 1, characterized in that: Also includes: A first electrode layer and a second electrode layer, wherein the first electrode layer is on one side of the isolation groove and covers the first N-type doped amorphous silicon layer and a portion of the second N-type doped amorphous silicon layer, and the second electrode layer is on the other side of the isolation groove and covers a portion of the second N-type doped amorphous silicon layer and the first P-type doped crystalline silicon layer.

3. The back contact solar cell according to claim 2, characterized in that: The first electrode layer and the second electrode layer are transparent conductive layers, and the materials of the first electrode layer and the second electrode layer are independently selected from at least one of indium tin oxide, aluminum zinc oxide, indium hydroxide-doped indium and indium tungsten oxide.

4. The back contact solar cell according to claim 1, characterized in that: The isolation layer includes a BSG layer, and the BSG layer is between the second sub-intrinsic amorphous silicon layer and the second P-type doped crystalline silicon layer.

5. The back contact solar cell according to claim 4, characterized in that: The thickness of the BSG layer is 80-120 nm.

6. The back contact solar cell according to claim 1, characterized in that: It also includes a passivation layer, which includes a third intrinsic amorphous silicon layer and a silicon nitride passivation layer. The third intrinsic amorphous silicon layer is on the second surface, and the silicon nitride passivation layer is on a surface of the third intrinsic amorphous silicon layer away from the semiconductor substrate.

7. The back contact solar cell according to any one of claims 1 to 6, characterized in that: The first tunneling oxide layer and the second tunneling oxide layer are both tunneling SiO2 layers; and / or The thickness of the first P-type doped crystalline silicon layer and the second P-type doped crystalline silicon layer are both 80-200 nm; and / or The diffusion square resistance of the first P-type doped crystalline silicon layer and the second P-type doped crystalline silicon layer are both 80-120Ω / sq; and / or The thickness of the first sub-intrinsic amorphous silicon layer and the second sub-intrinsic amorphous silicon layer are both 5-30 nm; and / or The thickness of the first N-type doped amorphous silicon layer and the second N-type doped amorphous silicon layer are both 10-30 nm; and / or The element doping concentrations in the first N-type doped amorphous silicon layer and the second N-type doped amorphous silicon layer are both 10e20cm-3 to 10e21cm-3.

8. A method for preparing a back contact solar cell, characterized in that: include: A semiconductor substrate is provided, wherein the semiconductor substrate has a first surface and a second surface opposite to each other, wherein the first surface includes a first region, a second region and an interleaved overlapping region, wherein the interleaved overlapping region is between the first region and the second region, wherein the first region and the interleaved overlapping region are polished surfaces, and wherein the polished surface includes a block-shaped structure; forming a tunneling oxide layer, a P-type doped crystalline silicon layer and an isolation layer in sequence on the first surface; The second region is opened by laser to expose a part of the second region to form an intermediate piece, and the second region is textured to form a suede surface, wherein the interface between the second region and the staggered overlapping region is obliquely connected; sequentially forming a first intrinsic amorphous silicon layer and an N-type doped amorphous silicon layer on a surface of the intermediate member away from the second surface; removing the first intrinsic amorphous silicon layer, the N-type doped amorphous silicon layer and the isolation layer corresponding to the surface of the first region; The staggered overlapping regions are etched so that the N-type doped amorphous silicon layer and the first intrinsic amorphous silicon layer in at least a portion of the staggered overlapping regions are etched through to form isolation grooves.

9. The method according to claim 8, characterized in that Also includes: After exposing the second region, the semiconductor substrate is subjected to alkali texturing to form a pyramid-like textured surface structure on the second surface and the second region.

10. The method according to claim 9, characterized in that After a pyramid-like textured structure is formed on the second surface and the second region, a third intrinsic amorphous silicon layer and a silicon nitride passivation layer are sequentially formed on the second surface.

11. The method according to claim 8, characterized in that After etching the staggered overlapping region, two sides of the isolation trench of the staggered overlapping region are separated into a first staggered overlapping region and a second staggered overlapping region.

12. The method according to claim 11, characterized in that A first electrode layer is formed on one side of the isolation groove, and the first electrode layer covers the N-type doped amorphous silicon layer in the second region and the N-type doped amorphous silicon layer in the staggered overlapping region, respectively. A second electrode layer is formed on the other side of the isolation groove, and the second electrode layer covers the N-type doped amorphous silicon layer in the staggered overlapping region and the P-type doped crystalline silicon layer in the staggered overlapping region.

13. The method according to claim 12, characterized in that A first gate line is formed on a portion of the surface of the first electrode layer, and a second gate line is formed on a portion of the surface of the second electrode layer.

14. The method according to claim 8, characterized in that The tunnel oxide layer and the P-type doped crystalline silicon layer are deposited by LPCVD.

15. The method according to claim 8, characterized in that The isolation layer includes a BSG layer.

16. The method according to claim 15, characterized in that The step of sequentially forming a tunneling oxide layer, a P-type doped crystalline silicon layer and an isolation layer on the first surface comprises: depositing a polysilicon layer after the tunnel oxide layer is formed; Diffusion of boron into the polysilicon layer at high temperature to convert the polysilicon layer into the P-type doped crystalline silicon layer; The predetermined annealing time is extended to form the BSG layer.

17. The method according to claim 16, characterized in that The temperature of the boron diffusion on the polysilicon layer is 980-1050° C.; and / or The predetermined annealing time is 40±5 min.

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