Readout unit of pixel unit and readout circuit of pixel array

Abstract

The present invention provides a readout unit of a pixel unit and a readout circuit of a pixel array, wherein the readout unit of the pixel unit comprises: a sampling module for sampling the output of the pixel unit; a conduction control unit connected to a first current source unit, the first current source unit being used to provide a first bias current; a first control signal being used to control the conduction control unit to be turned on during the sampling process of the sampling module, and to be turned off when the sampling is completed; and a second control signal being used to control the sampling module to be turned on during the sampling process of the sampling module, and to be turned off when the sampling is completed. The present invention can realize that the first current source unit provides the first bias current to the pixel unit during the sampling process, and stops supplying the first bias current when the conduction control unit is turned off, thereby saving power consumption. Moreover, because the output of the pixel unit will be unstable when the supply of the first bias current is stopped, the sampling module also needs to be turned off to avoid signal acquisition confusion.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and in particular to a readout unit of a pixel unit and a readout circuit of a pixel array. Background Art

[0002] CMOS Image Sensor (CIS) has been widely used in imaging fields such as video, surveillance, industrial manufacturing, automobiles, and home appliances. With the continuous improvement of various application requirements, CIS resolution and frame rate are also increasing, and CIS power consumption is also increasing. The increase in temperature will bring many problems, including the increase in CIS pixel dark current noise, packaging heat dissipation problems, etc., which will directly affect the final image quality. While ensuring performance, reducing CIS power consumption as much as possible has become a technical difficulty. The current mainstream CIS readout circuit is based on a column-parallel analog-to-digital converter (ADC) architecture. To reduce the overall power consumption of CIS, the most important thing is to reduce the power consumption of the column ADC.

[0003] Therefore, the present invention proposes a readout unit of a pixel unit and a readout circuit of a pixel array to reduce power consumption. Summary of the invention

[0004] The present invention provides a readout unit of a pixel unit and a readout circuit of a pixel array to solve the problem of high power consumption of the readout circuit of the existing image sensor.

[0005] In a first aspect, the present invention provides a readout unit of a pixel unit, comprising: a conduction control unit, a sampling module, a reading module, a first current source unit and a second current source unit; the first end of the conduction control unit and the first end of the sampling module are both connected to the output end of the pixel unit, and the sampling module is used to sample the output of the pixel unit; the second end of the conduction control unit is connected to the first end of the first current source unit, the second end of the first current source unit is grounded, and the third end of the first current source unit is used to receive a first bias voltage, and the first bias voltage is used to provide a first bias current; the second end of the sampling module is connected to the reading module, and the reading module is used to perform analog-to-digital conversion processing on the sampled signal; the third end of the conduction control unit is used to receive a first control signal, and the first control signal is used to control the conduction control unit to be turned on during the sampling process of the sampling module, and to be turned off when the sampling is completed; the third end of the sampling module is used to receive a second control signal, and the second control signal is used to control the sampling module to be turned on during the sampling process of the sampling module, and to be turned off when the sampling is completed; the second current source unit is used to provide a stable current to the reading module to ensure that the output of the reading module is stable when the conduction control unit is turned off.

[0006] The beneficial effect is that the conduction control unit provided by the present invention only needs to be turned on during the sampling process of the sampling module and turned off when the sampling is completed, so that the first current source unit can provide the first bias current to the pixel unit during the sampling process of the sampling module, and stop supplying the first bias current when the conduction control unit is turned off, which can save power consumption compared with the prior art. Because the output of the pixel unit will be unstable when the first bias current is stopped, the sampling module also needs to be turned off to avoid signal acquisition confusion.

[0007] Optionally, the reading module includes a comparator, a counter and a logic control unit; the first input end of the comparator is connected to the second end of the sampling module for obtaining the sampling result of the sampling module; the second input end of the comparator is used to obtain a ramp signal; the comparator is used to compare the ramp signal with the sampling result; the output end of the logic control unit and the first end of the second current source unit are both connected to the third input end of the comparator, the second end of the second current source unit is grounded, and the third end of the second current source unit is used to receive a second bias voltage, and the second bias voltage is used to provide a second bias current; the input end of the counter and the first input end of the logic control unit are both connected to the output end of the comparator, the second input end of the logic control unit is used to obtain an enable signal of a ramp generator, the first input end of the logic control unit is used to obtain the comparison result of the comparator, and the logic control unit is used to realize the conduction or disconnection of the comparator and the second current source unit by obtaining the comparison result and the enable signal.

[0008] The beneficial effect is that: the present invention uses the logic control unit to realize the switching on or off of the comparator and the second current source unit by obtaining the comparison result and the enable signal, which can further save power consumption.

[0009] Optionally, the conduction control unit includes a first switching circuit, a first end of the first switching circuit is connected to the output end of the pixel unit, a second end of the first switching circuit is connected to the first end of the first current source unit, and a third end of the first switching circuit is used to receive the first control signal.

[0010] Optionally, the first current source unit includes a first N-type transistor, the drain of the first N-type transistor is connected to the second end of the first switch circuit, the gate of the first N-type transistor is used to receive the first bias voltage, and the source of the first N-type transistor is grounded. Its beneficial effect is that the design is simple and a stable current can be provided to the output of the pixel unit.

[0011] Optionally, the sampling module includes a second switching circuit and a sampling capacitor; the first end of the second switching circuit is connected to the first end of the conduction control unit, the second end of the second switching circuit is connected to the first end of the sampling capacitor, the third end of the second switching circuit is used to receive the second control signal, and the second end of the sampling capacitor is grounded.

[0012] Optionally, the logic control unit includes a third switch circuit and an XOR gate; the first end of the third switch circuit is connected to the third input end of the comparator, and the second end of the third switch circuit is connected to the first end of the second current source unit; the first input end of the XOR gate is connected to the output end of the comparator for obtaining the comparison result, and the second input end of the XOR gate is used to obtain the enable signal; the output end of the XOR gate is connected to the third end of the third switch circuit for providing a state control signal to the third switch circuit, and the state control signal controls the third switch circuit to be turned on or off. The beneficial effect is that the present invention can provide the second bias current during the working process of the comparator, and stop providing the second bias current during the non-working stage of the comparator, so as to achieve the purpose of saving power consumption.

[0013] Optionally, the reading module further includes a buffer; an input end of the buffer is connected to an output end of the comparator, an output end of the buffer is connected to a first input end of the XOR gate, and the buffer is used to buffer the comparison result.

[0014] Optionally, the buffer comprises an even number of inverters connected in series.

[0015] Optionally, the second current source unit includes a second N-type transistor, the drain of the second N-type transistor is connected to the output terminal of the logic control unit and the third input terminal of the comparator, the gate of the second N-type transistor is used to receive a second bias voltage, the second bias voltage is used to provide the second bias current, and the source of the second N-type transistor is grounded. Its beneficial effects are: simple design, can provide a stable current to the counter.

[0016] In a second aspect, the present invention provides a readout circuit for a pixel array, comprising at least one readout unit of the pixel unit as described in any one of the first aspects, each of the readout units being respectively connected to a column of pixel units in the pixel array. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a schematic diagram of a four-tube pixel unit circuit structure;

[0018] Figure 2 A schematic diagram of the working timing of a four-tube pixel unit;

[0019] Figure 3 It is a structural schematic diagram of an image sensor readout circuit;

[0020] Figure 4 A schematic diagram of the working timing of an image sensor readout circuit;

[0021] Figure 5A schematic diagram of an embodiment of a readout unit of a pixel unit provided by the present invention;

[0022] Figure 6 The present invention is a schematic diagram of an embodiment of the working timing of a readout unit of a pixel unit provided by the present invention. DETAILED DESCRIPTION

[0023] The technical solutions in the embodiments of the present application are described below in conjunction with the drawings in the embodiments of the present application. Among them, in the description of the embodiments of the present application, the terms used in the following embodiments are only for the purpose of describing specific embodiments, and are not intended to be used as limitations on the present application. As used in the specification and the appended claims of the present application, the singular expressions "a", "the", "above", "the" and "this" are intended to also include expressions such as "one or more", unless there is a clear indication to the contrary in the context. It should also be understood that in the following embodiments of the present application, "at least one", "one or more" refer to one or more (including two). The term "and / or" is used to describe the association relationship of associated objects, indicating that three relationships can exist; for example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects before and after are in a "or" relationship.

[0024] References to "one embodiment" or "some embodiments" etc. described in this specification mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Thus, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways. The term "connection" includes direct connection and indirect connection, unless otherwise specified. "First" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated.

[0025] In the embodiments of the present application, the words "exemplarily" or "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as "exemplarily" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplarily" or "for example" is intended to present related concepts in a specific way.

[0026] Figure 1 A CIS standard four-tube pixel unit circuit structure is shown, which is widely used in CIS. It consists of a photodiode PD, a transfer transistor Mtg, a reset transistor Mrst, an amplifier transistor Msf, and a gate transistor Msel. The photodiode PD is sensitive to light and generates photoelectrons proportional to the light intensity. The function of the transfer transistor Mtg is to transfer the photoelectrons in the photodiode PD. When the transmission signal TX is at a high potential, the transfer transistor Mtg is turned on and the photoelectrons in the photodiode PD are transferred to the floating diffusion area FD. The function of the reset transistor Mrst is to reset the potential of the floating diffusion area FD when the reset signal RX is at a high potential. When the SEL signal is at a high potential, the gate transistor Msel is turned on, and the amplifier transistor Msf, the gate transistor Msel and the current source to the ground form a path. At this time, the amplifier transistor Msf follows the change in the potential of the floating diffusion area FD as the pixel signal PIX_OUT of the pixel unit for output.

[0027] Figure 2 for Figure 1 The working sequence of the four-tube pixel unit shown is divided into reset (Rst), exposure (Exp), and signal reading (Read). In the Rst stage, the transmission signal TX and the reset signal RX are high, the transmission transistor Mtg and the reset transistor Mrst are both turned on, the floating diffusion area FD is reset and its potential is pulled up to the power supply voltage VDD. After that, the reset signal RX and the transmission signal TX become low, and the Exp stage is entered. The floating diffusion area PD is sensitive to light and accumulates electrons. Then, the Read stage is entered, the SEL signal is high, the reset signal RX is high first, and after resetting the potential of the floating diffusion area FD, the reset signal RX is pulled to a low potential again, and the transmission signal TX remains at a low potential. At this time, the amplifier transistor Msf is controlled by the potential of the floating diffusion area FD and outputs the reset signal VRST. After that, the transmission signal TX is pulled to a high potential, and the electrons on the photodiode PD are transferred to the floating diffusion area FD. At this time, the amplifier transistor Msf is controlled by the potential of the floating diffusion area FD and outputs the integration signal VSIG. The difference between VRST and VSIG is the analog voltage corresponding to the photoelectrons on the photodiode PD. The potential of the reset signal VRST and the integral signal VSIG is converted into digital quantities by the analog-to-digital converter (ADC) circuit and subtracted to obtain the actual digital quantity corresponding to the photoelectrons on the photodiode PD. If the ADC is 12 bits and the ADC reference voltage range is VREF, the final output is DOUT = (VRST-VSIG) × 2 12 / VREF.

[0028] Figure 3The schematic diagram of the CIS readout circuit includes a pixel array, an analog-digital converter (ADC), a ramp generator, a timing control module, a decoding drive module, and an output signal processing module. Figure 1 The pixel array is read out row by row, and the specific order is ROW(0), ROW(1), ... ROW(k-1), ROW(k). The k is a positive integer. The ADC module is composed of a comparator and a counter. The comparator compares the output pixel signal with the ramp signal RAMP, and the comparison result determines the size of the counter count value. The ADC module also judges the above-mentioned VRST and VSIG potentials respectively, and converts the VRST-VSIG difference into a digital output.

[0029] Figure 4 for Figure 3 The working timing of the CIS readout circuit shown is Figure 2 The Read phase of the timing. Figure 4 In the timing shown, the Read phase is entered, the SEL signal is pulled to a high potential, the reset signal RX is a high potential, and the pixel unit is reset. RST_CM is the comparator reset control signal, and RST_CM is also pulled to a high potential to reset the comparators in all ADC modules. Then the reset signals RX and RST_CM change from a high potential to a low potential, and the ADC module enters a normal working state. The working process of the ADC module consists of two processes: comparison and counting. First, when the potential of the ramp signal RAMP begins to decrease, the counter CNT starts counting until the comparator signal flips from a low potential to a high potential. The counter CNT stops counting and stores the current count value. To complete the analog-to-digital conversion of the pixel signal, the ADC module needs to perform the above operation twice, that is, as the benchmark of the ADC module, two ramps will be generated. The first ramp stage (that is, Figure 4 The ADC module will determine and store the potential of the reset signal VRST, and the counter CNT will count and store the count value CN1 corresponding to the t1 period during the t1 period; the second ramp stage (i.e. Figure 4 In the "VS" phase), the ADC module will determine and store the potential of the reset signal VSIG, and the counter CNT will count and store the count value CN2 corresponding to the t2 period. Finally, the counter CNT will output the count difference ΔCN=CN2-CN1, which corresponds to the difference between VSIG and VRST.

[0030] During normal operation of a traditional CIS, the readout circuit is always in working mode, and the static power consumption mainly comes from the tail current of the pixel unit and the tail current of the comparator. Assuming that the tail current of the pixel unit is I1, and the tail current of the comparator is I2, the first N-type transistor provides a tail current I1 when driven by a first bias voltage, and the tail current tube of the comparator provides a tail current I2 when driven by a second bias voltage, then in the working state, the additional current consumed by the readout circuit is It=I1+I2. The comparator outputs a signal at the same level as the digital logic through a buffer. The tail current I1 may refer to the first bias current in this application, and the tail current I2 may refer to the second bias current in this application.

[0031] In order to solve the technical problem of high power consumption, the present application provides a readout unit of a pixel unit, which is used as an example to explain the invention of the present application in more detail. Figure 5As shown, the readout unit of the pixel unit includes: a first switch circuit S1, a first N-type transistor, a second switch circuit S2, a comparator, a third switch circuit S3, a sampling capacitor Cs, a second N-type transistor, an XOR gate X0, a buffer and a counter. The first end of the first switch circuit S1 is connected to the output end of the pixel unit, the second end of the first switch circuit S1 is connected to the drain of the first N-type transistor N1, and the third end of the first switch circuit S1 is used to receive the first control signal CTRL_1. The gate of the first N-type transistor N1 is used to receive the first bias voltage VB1, and the first bias voltage VB1 is used to provide the first bias current I1. The source of the first N-type transistor N1 is grounded. The first end of the second switch circuit S2 is connected to the first end of the first switch circuit S1, the second end of the second switch circuit S2 is connected to the first end of the sampling capacitor Cs, the third end of the second switch circuit S2 is used to receive the second control signal CTRL_2, and the second end of the sampling capacitor Cs is grounded. The second end of the second switch circuit S2 is also connected to the first input end of the counter, and the second input end of the counter is used to receive the ramp signal RAMP. The first end of the third switch circuit S3 is connected to the third input end of the comparator, and the second end of the third switch circuit S3 is connected to the drain of the second N-type transistor N2. The input end of the buffer is connected to the output end of the comparator, and the buffer is used to buffer the comparison result output by the comparator. The first input end of the XOR gate X0 is connected to the output end of the buffer for obtaining the comparison result, and the second input end of the XOR gate X0 is used to obtain the enable signal EN_RAMP; the output end of the XOR gate X0 is connected to the third end of the third switch circuit S3 for providing the state control signal CTRL_3 to the third switch circuit S3, and the state control signal CTRL_3 controls the third switch circuit S3 to be turned on or off. The gate of the second N-type transistor N2 is used to receive the second bias voltage VB2, and the second bias voltage VB2 is used to provide the second bias current I2, and the source of the second N-type transistor N2 is grounded. In some embodiments, the first switch circuit includes a switch MOS tube, the second switch circuit includes a switch MOS tube, and the third switch circuit includes a switch MOS tube. In some embodiments, the buffer includes a first inverter and a second inverter, the input end of the first inverter is connected to the output end of the comparator, the output end of the first inverter is connected to the input end of the second inverter, and the output end of the second inverter is connected to the first input end of the XOR gate and the input end of the counter. The counter outputs a signal DOUT.The first control signal CTRL_1, the second control signal CTRL_2, and the state control signal CTRL_3 are control signals of the first switch circuit S1, the second switch circuit S2, and the third switch circuit S3, respectively. When these control signals are at a high level, the corresponding switch circuit is turned on, and when these control signals are at a low level, the corresponding switch circuit is turned off. The first switch circuit S1 is turned on only a short time before the start of the read operation "VR" and "VS" stages. The XOR gate is a more preferred embodiment, and the logic control unit of the present application can also be a combination of other gates to obtain a circuit that can achieve the purpose of the present invention.

[0032] like Figure 6 As shown, the working timing of the first control signal CTRL_1 and the second control signal CTRL_2 is consistent, both are low level first and then generate two high pulses respectively. Figure 5 and Figure 6During the first high pulse "t3", the first N-type transistor N1 is turned on, and the reset signal VRST of the output signal PIX_OUT of the pixel unit is sampled by the second switch circuit S2 to the sampling capacitor Cs. After that, the first control signal CTRL_1 and the second control signal CTRL_2 are low levels, the first N-type transistor N1 is turned off, the pixel output is floating, and the sampling capacitor Cs still stores and maintains the potential of the reset signal VRST; during the second high pulse "t4", the transmission signal TX is high, the first N-type transistor N1 is turned on, and the integral signal VSIG of the output signal PIX_OUT of the pixel unit is sampled by the second switch circuit S2 to the sampling capacitor Cs. After that, the first control signal CTRL_1 and the second control signal CTRL_2 are low levels, the first N-type transistor N1 is turned off, the pixel output is floating, and the sampling capacitor Cs still stores and maintains the potential of the integral signal VSIG. The potential of the reset signal VRST and the potential of the integration signal VSIG sampled before and after the sampling capacitor Cs will be compared and converted to analog-to-digital in the "VR" and "VS" stages respectively, and the same working process is completed compared with the traditional readout circuit. The proposed readout circuit pixel tail current I1 only needs to be turned on for a short time. The comparator tail current control method is different from the above. Initially, since the enable signal EN_RAMP and the comparator output signal DCMO are both low levels, the control signal CTRL_3 output by the XOR gate X0 is low, so that the third switch circuit S3 is disconnected, and the comparator has no tail current consumption. When the ramp signal RAMP is valid, the enable signal EN_RAMP is high, and the comparator output signal DCMO is low, so the control signal CTRL_3 output by the XOR gate X0 is high, so that the second N-type transistor N2 is turned on, and the comparator flows through the tail current I2 and is in a normal working state. After the comparator completes a comparison in the "VR" stage, the comparator output signal DCMO changes from low level to high level, so that the control signal CTRL_3 output by the XOR gate X0 changes to low level, and the second N-type transistor N2 has no tail current flowing through it. The comparator is in a non-working state, so the comparator is only turned on during the t1 time and consumes the static current I2. After that, similarly, the enable signal EN_RAMP of the ramp generator changes from low level to high level again. In the "VS" stage, the comparator only consumes the static current I2 during the t2 time.

[0033] In summary, during the operation of the readout unit of the pixel unit provided in the present application, the pixel tail current I1 and the comparator tail current I2 are not always in a continuously on state like the traditional readout circuit. Instead, when the analog-to-digital conversion is completed normally, the average power consumption is reduced by switching timing control. Taking a typical CIS design as an example to explain the technical effect of the present application, I1=I2=I, t3=t4=2μs, t1=2.5μs, t2=2.5~15μs, according to the size of the pixel output signal, the smaller the output signal, the smaller t2, the larger the output signal, the larger t2, if the difference between the reset signal VRST and the integral signal VSIG reaches the maximum value, t2=15μs. If the pixel signal output is maximum, the average current: As described above, the total static current of the conventional readout circuit It=I1+I2=2I, so compared with the conventional readout circuit, the readout unit of the pixel unit provided in the present application saves (2-0.716)×I, that is, saves about 30% of power consumption.

[0034] Based on the readout unit of the pixel unit described in the above embodiments, the present application also provides a readout circuit of a pixel array, wherein the readout circuit of the pixel array includes at least one readout unit of the pixel unit as described in any one of the above embodiments, and each of the readout units is respectively connected to a column of pixel units in the pixel array.

[0035] The above is only a specific implementation of the embodiment of the present application, but the protection scope of the embodiment of the present application is not limited thereto, and any changes or replacements within the technical scope disclosed in the embodiment of the present application should be included in the protection scope of the embodiment of the present application. Therefore, the protection scope of the embodiment of the present application should be based on the protection scope of the claims.

Claims

1. A readout unit of a pixel unit, characterized in that: include: A conduction control unit, a sampling module, a reading module, a first current source unit and a second current source unit; The first end of the conduction control unit and the first end of the sampling module are both connected to the output end of the pixel unit, and the sampling module is used to sample the output of the pixel unit; The second end of the conduction control unit is connected to the first end of the first current source unit, the second end of the first current source unit is grounded, and the third end of the first current source unit is used to receive a first bias voltage, and the first bias voltage is used to provide a first bias current; The second end of the sampling module is connected to the reading module, and the reading module is used to perform analog-to-digital conversion processing on the sampled signal; The third end of the conduction control unit is used to receive a first control signal, the first control signal is used to control the conduction control unit to be turned on during the sampling process of the sampling module, and to be turned off when the sampling is completed; the third end of the sampling module is used to receive a second control signal, the second control signal is used to control the sampling module to be turned on during the sampling process of the sampling module, and to be turned off when the sampling is completed; The second current source unit is used to provide a stable current to the reading module to ensure that the output of the reading module is stable when the conduction control unit is disconnected; The conduction control unit includes a first switch circuit, a first end of the first switch circuit is connected to the output end of the pixel unit, a second end of the first switch circuit is connected to the first end of the first current source unit, and a third end of the first switch circuit is used to receive the first control signal; The first current source unit includes a first N-type transistor, a drain of the first N-type transistor is connected to the second end of the first switch circuit, a gate of the first N-type transistor is used to receive the first bias voltage, and a source of the first N-type transistor is grounded.

2. The readout unit of the pixel unit according to claim 1, characterized in that: The reading module includes a comparator, a counter and a logic control unit; The first input end of the comparator is connected to the second end of the sampling module, and is used to obtain the sampling result of the sampling module; the second input end of the comparator is used to obtain the ramp signal; The comparator is used to compare the ramp signal with the sampling result; The output terminal of the logic control unit and the first terminal of the second current source unit are both connected to the third input terminal of the comparator, the second terminal of the second current source unit is grounded, and the third terminal of the second current source unit is used to receive a second bias voltage, and the second bias voltage is used to provide a second bias current; The input end of the counter and the first input end of the logic control unit are both connected to the output end of the comparator, the second input end of the logic control unit is used to obtain the enable signal of the ramp generator, the first input end of the logic control unit is used to obtain the comparison result of the comparator, and the logic control unit is used to realize the conduction or disconnection of the comparator and the second current source unit by obtaining the comparison result and the enable signal.

3. The readout unit of the pixel unit according to claim 1, characterized in that: The sampling module includes a second switch circuit and a sampling capacitor; A first end of the second switch circuit is connected to a first end of the conduction control unit, a second end of the second switch circuit is connected to a first end of the sampling capacitor, a third end of the second switch circuit is used to receive the second control signal, and a second end of the sampling capacitor is grounded.

4. The readout unit of the pixel unit according to claim 2, characterized in that: The logic control unit includes a third switch circuit and an XOR gate; A first end of the third switch circuit is connected to the third input end of the comparator, and a second end of the third switch circuit is connected to the first end of the second current source unit; The first input end of the XOR gate is connected to the output end of the comparator for obtaining the comparison result, and the second input end of the XOR gate is used for obtaining the enable signal; The output end of the XOR gate is connected to the third end of the third switch circuit, and is used to provide a state control signal to the third switch circuit, and the state control signal controls the third switch circuit to be turned on or off.

5. The readout unit of the pixel unit according to claim 4, characterized in that: The reading module also includes a buffer; The input end of the buffer is connected to the output end of the comparator, the output end of the buffer is connected to the first input end of the XOR gate, and the buffer is used to buffer the comparison result.

6. The readout unit of the pixel unit according to claim 5, characterized in that: The buffer includes an even number of inverters connected in series.

7. The readout unit of the pixel unit according to claim 2, characterized in that: The second current source unit includes a second N-type transistor, the drain of the second N-type transistor is connected to the output end of the logic control unit and the third input end of the comparator, the gate of the second N-type transistor is used to receive a second bias voltage, the second bias voltage is used to provide the second bias current, and the source of the second N-type transistor is grounded.

8. A readout circuit for a pixel array, characterized in that: The method comprises at least one readout unit of the pixel unit according to any one of claims 1 to 7, wherein each of the readout units is respectively connected to a column of pixel units in the pixel array.

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