Insert filling units according to structural correction

By implementing yield improvement tools, extracting cell characteristics from the physical layout design of integrated circuits and selecting fill cells, the bottleneck problem in the fill cell insertion process is solved, design efficiency and rule compliance are improved, and resource waste is reduced.

CN115516457BActive Publication Date: 2026-05-26SIMENS INDASTRI SOFTVEAR INK
1 Cites 0 Cited by

Patent Information

Application Number
CN202080100370.6
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2020-04-30
Publication Date
2026-05-26
Estimated Expiration
2040-04-30

AI Technical Summary

Technical Problem

In existing technologies, the filling cell insertion process consumes a lot of time and computing resources in integrated circuit design, becoming a bottleneck in the design process. Moreover, the insertion process needs to be repeated every time the logic or timing changes, resulting in time delays and resource waste.

Method used

By implementing yield improvement tools, cell characteristics in the physical layout design of integrated circuits are extracted, empty regions are identified, and filling cells are selected based on electrical design rules and inserted into the empty regions. Design rule checks are combined to eliminate potential violations.

Benefits of technology

It improves design efficiency, reduces the consumption of computing resources, ensures compliance with design rules, and avoids time delays and resource waste caused by the insertion of fill cells.

✦ Generated by Eureka AI based on patent content.
Patent Text Reader

Abstract

This application discloses a computational system for implementing yield improvement tools. It extracts cell characteristics from a physical layout design for integrated circuits, determines the location of empty regions in the physical layout design, and applies electrical design rules for manufacturing integrated circuits to the extracted characteristics to identify cells in the physical layout design that will violate the electrical design rules. The computational system can select fill cells for empty regions based at least in part on the extracted characteristics of cells adjacent to empty regions and the electrical design rules, and insert the selected fill cells into the empty regions of the physical design layout. The computational system can perform a design rule checking operation that applies the electrical design rules to the physical design layout where the selected fill cells have been inserted.
Need to check novelty before this filing date? Find Prior Art