Insert filling units according to structural correction

Abstract

This application discloses a computational system for implementing yield improvement tools. It extracts cell characteristics from a physical layout design for integrated circuits, determines the location of empty regions in the physical layout design, and applies electrical design rules for manufacturing integrated circuits to the extracted characteristics to identify cells in the physical layout design that will violate the electrical design rules. The computational system can select fill cells for empty regions based at least in part on the extracted characteristics of cells adjacent to empty regions and the electrical design rules, and insert the selected fill cells into the empty regions of the physical design layout. The computational system can perform a design rule checking operation that applies the electrical design rules to the physical design layout where the selected fill cells have been inserted.

Description

Technical Field

[0001] This application relates generally to electronic design automation, and more specifically to correct-by-construction fill cell insertion in physical layout design. Background Technology

[0002] Designing and manufacturing integrated circuits typically involves a series of steps known as the design flow. The specific steps in the design flow often depend on the type of integrated circuit being designed, its complexity, the design team, and the manufacturer or foundry that will manufacture the circuit. The design flow usually begins with a specification for the new integrated circuit, which can be transformed into a logic design. The logic design can be modeled at the Register Transfer Level (RTL), which is typically coded in a Hardware Design Language (HDL), such as System Verilog, Very High Speed ​​Integrated Circuit Hardware Design Language (VHDL), System C, etc. The logic design of the integrated circuit can be analyzed to confirm that it will accurately perform the functions expected of the integrated circuit. This analysis is sometimes referred to as "functional verification."

[0003] After confirming the accuracy of the logic design, it can be converted into a device design using synthesis software. Device designs, typically in schematic or netlist form, describe specific components (such as transistors, resistors, and capacitors) and their interconnections that can be used in an electronic system. This device design usually corresponds to the representation hierarchy shown in a conventional circuit diagram.

[0004] Device design can be transformed into physical design data describing specific geometric elements, often referred to as physical layout design. These geometric elements (typically polygons) define the shapes that will be generated from various materials to form the specified circuit device. For example, designers using place-and-route tools can position multiple portions of a device design relative to each other in a geographic design environment. While these device design portions may correspond to code segments in a hardware description language, they are typically shown as multiple cells representing components of an integrated circuit in a geographic design environment. Once these cells are positioned relative to each other, routes can be routed between the cells. These routes represent interconnections that can be formed between circuit devices of an integrated circuit, such as data signal interconnects and clock signal interconnects.

[0005] Because physical layout designs may include open spaces between their cells (which will correspond to electrical errors in subsequent design rule checks), the place-and-route process typically includes a gap-filling process that inserts fill cells into these open spaces. Fill cells can be non-functional cells, such as non-functional transistors, which can be used, for example, for continuous voltage rails, n-wells, and / or p-wells for layer continuity and alignment. Since many different types of fill cells exist, place-and-route tools typically perform a guessing and checking process to insert fill cells, for example, iteratively performing gap-filling and design rule checks to determine if the fill cell eliminates electrical errors. This iterative process of place-and-route tools inserting fill cells and design rule checks identifying which fill cells are insufficient can often take hours to resolve, consuming processing and storage resources. Furthermore, the fill cell insertion process is repeated by the place-and-route tools and design rule checks every time the designer makes a logical or timing change to the physical layout design, exacerbating time delays and computational resource utilization, making fill cell insertion a bottleneck in the design process. Summary of the Invention

[0006] This application discloses a computational system for implementing yield improvement tools. It extracts cell characteristics from a physical layout design for integrated circuits, determines the location of empty regions in the physical layout design, and applies electrical design rules for manufacturing integrated circuits to the extracted characteristics to identify cells in the physical layout design that will violate the electrical design rules. The computational system can select filler cells for empty regions based at least in part on the extracted characteristics of cells adjacent to empty regions and the electrical design rules, and insert the selected filler cells into the empty regions of the physical design layout. The computational system can perform a design rule checking operation that applies the electrical design rules to the physical design layout where the selected filler cells have been inserted. Embodiments will be described in more detail below. Attached Figure Description

[0007] Figure 1 and Figure 2 Examples of computer systems of various types that can be used to implement various embodiments are illustrated.

[0008] Figure 3 Example systems that can be implemented according to various embodiments are illustrated, which are used to perform structurally corrected filler cell insertion for physical layout designs.

[0009] Figures 4A to 4C Examples of physical layout designs are shown, with empty areas filled with filler cells according to various embodiments.

[0010] Figure 5Flowcharts based on various examples are shown, illustrating the process of inserting fill cells for structural correction of circuit design layout.

[0011] Figure 6 Flowcharts illustrating various examples are provided, demonstrating example implementations of selecting fill cells for insertion into empty areas of a physical layout design. Detailed Implementation

[0012] Explanatory operating environment

[0013] Various examples can be implemented by executing software instructions using a computing device (such as a programmable computer). Therefore, Figure 1 An illustrative example of a computing device 101 is shown. As seen in the figure, the computing device 101 includes a computing element 103 having a processor element 105 and a system memory 107. The processor element 105 can be any type of programmable electronic device for executing software instructions, but will typically be a microprocessor. The system memory 107 may include a read-only memory (ROM) 109 and a random access memory (RAM) 111. As will be understood by those skilled in the art, both the read-only memory (ROM) 109 and the random access memory (RAM) 111 can store software instructions for execution by the processor element 105.

[0014] Processor element 105 and system memory 107 are directly connected to or indirectly connected via bus 113 or alternative communication structures to one or more peripheral devices 115-123. For example, processor element 105 or system memory 107 may be directly or indirectly connected to one or more additional memory storage devices, such as hard disk drive 117 (which may be magnetic and / or removable), removable optical disk drive 119, and / or flash memory cards. Processor element 105 and system memory 107 may also be directly or indirectly connected to one or more input devices 121 and one or more output devices 123. Input devices 121 may include, for example, a keyboard, pointing devices (e.g., mouse, touchpad, stylus, trackball, or joystick), scanner, camera, and microphone. Output devices 123 may include, for example, a monitor display, printer, and speaker. For various examples of computing device 101, one or more peripheral devices 115-123 may be housed internally with computing element 103. Alternatively, one or more peripheral devices 115-123 may be located outside the housing of computing element 103 and connected to bus 113 via, for example, a Universal Serial Bus (USB) connection.

[0015] In some implementations, computing element 103 may be directly or indirectly connected to network interface 115 to communicate with other devices forming the network. Network interface 115 may convert data and control signals from computing element 103 into network messages according to one or more communication protocols, such as Transmission Control Protocol (TCP) and Internet Protocol (IP). Furthermore, network interface 115 may use any suitable connection proxy (or combination of proxies) to connect to the network, including, for example, a wireless transceiver, modem, or Ethernet connection. Such network interfaces and protocols are well known in the art and will not be discussed in more detail here.

[0016] It should be understood that computing device 101 is merely illustrative and is not intended to be limiting. Various embodiments may be implemented using one or more computing devices, including... Figure 1 The components of the computing device 101 illustrated herein include only... Figure 1 A subset of the components illustrated herein, or including alternative combinations of components, including Figure 1 Components not shown. For example, various embodiments may be implemented using a multiprocessor computer, multiple single-processor computers and / or multiprocessor computers arranged in a network, or some combination of both.

[0017] In some implementations, processor element 105 may have more than one processor core. Therefore, Figure 2 An example of a multi-core processor element 105 that can be used with various embodiments is illustrated. As seen in the figure, processor element 105 includes a plurality of processor cores 201A and 201B. Each processor core 201A and 201B includes a computing engine 203A and a computing engine 203B, as well as memory caches 205A and 205B, respectively. As will be known to those skilled in the art, computing engines 203A and 203B may include logic devices for performing various computational functions, such as fetching software instructions and then executing actions specified in the fetched instructions. These actions may include, for example, addition, subtraction, multiplication, and comparison of numbers, performing logical operations (such as AND, OR, NOR, and XOR), and retrieving data. Each computing engine 203A and computing engine 203B may then use its corresponding memory cache 205A and memory cache 205B to quickly store and retrieve data and / or instructions for execution.

[0018] Each processor core 201A and processor core 201B is connected to interconnect 207. The specific configuration of interconnect 207 can vary depending on the architecture of processor element 105. For some processor cores 201A and 201B (e.g., the Cell microprocessors created by Sony, Toshiba, and IBM), interconnect 207 can be implemented as an interconnect bus. However, for other processor elements 201A and 201B (e.g., the Opteron available from Advanced Micro Devices, Sunnyvale, California), interconnect 207 can be used. TM and Athlon TM The interconnect 207 (a dual-core processor) can be implemented as a system request interface device. In any case, processor cores 201A and 201B communicate with input / output interface 209 and memory controller 210 via interconnect 207. Input / output interface 209 provides a communication interface to bus 113. Similarly, memory controller 210 controls the exchange of information to system memory 107. In some implementations, processor element 105 may include additional components, such as an accessible advanced cache memory shared by processor cores 201A and 201B. It should also be understood that... Figure 1 and Figure 2 The description of the illustrated computer networks is provided by way of example only and is not intended to impose any limitation on the scope or functionality of alternative embodiments.

[0019] Insert filling units according to structural correction

[0020] Figure 3 An example system 300, which can be implemented according to various embodiments, is illustrated. Example system 300 is used to perform structurally corrected fill cell insertion for a physical layout design 301. Reference Figure 3 System 300 may include a yield improvement tool 310, which, for example, receives a physical layout design 301 from a place-and-route tool that can place standard cells in a geometric layout and then place lines representing data signal interconnects, clock signal interconnects, power and ground connections, etc., between the standard cells. In some embodiments, physical layout design 301 may include the placed standard cells but not the lines; while in other embodiments, physical layout design 301 may include both standard cells and corresponding lines.

[0021] Physical layout design 301 can describe the integrated circuit using geometric information that can be used during the manufacturing of the integrated circuit, such as geometric information regarding the planar geometry corresponding to the patterns of the metal layers, oxide layers, or semiconductor layers that make up the integrated circuit. In some embodiments, physical layout design 301 can be specified in formats such as Graphics Data System II (GDSII), Open Artwork System Exchange Standard (OASIS) format, Library Exchange Format (LEF), and Design Exchange Format (DEF).

[0022] Figure 4A Example portions of a physical layout design with empty area 403 according to various embodiments are illustrated. (See references) Figure 4A This part of the physical layout design may include multiple cell rows 401 in the geometric layout region, and each cell row 401 may include multiple standard cells 402. The height of each cell row may correspond to the height of the standard cells 402. The width of the standard cells 402 in the cell row 401 may vary depending on the cell type. Each standard cell 402 may also have a varying voltage type or threshold voltage level, such as standard voltage, low voltage, ultra-low voltage, etc. This part of the physical layout design may also include an empty region 403 adjacent to at least one of the standard cells 402. The empty region 403 may lead to violations of design rules, such as due to a lack of continuity of voltage rails, n-wells, and / or p-wells.

[0023] Return to reference Figure 3 The yield improvement tool 310 can receive a filler cell library 302 to describe filler cells that can be inserted into open areas of the physical layout design 301. Filler cells can be non-functional cells, such as non-functional transistors, ECO (Engineering Change Order) metal-1 decapacitance cells, etc., which can be used, for example, for continuous voltage rails, n-wells, and / or p-wells for layer continuity and alignment. In some embodiments, the filler cell library 302 can be provided from a foundry or manufacturer capable of manufacturing the integrated circuits described in the physical layout design 301, and can be described in Graphics Data System II (GDSII) format, Open Artwork System Exchange Standard (OASIS) format, Library Exchange Format (LEF), and Design Exchange Format (DEF), etc.

[0024] The yield improvement tool 310 may include a feature extractor 311 to identify cells placed in the physical design layout 301 and determine their characteristics. For example, the feature extractor 311 may determine the voltage type or threshold voltage level of each cell in the physical layout design 301, such as standard voltage, low voltage, ultra-low voltage, etc. The feature extractor 311 may also measure the width of the cells in the physical layout design 301. The combination of voltage type and width may correspond to at least some of the characteristics of the cells in the physical layout design 301.

[0025] The yield improvement tool 310 may include an empty area locator 312, which identifies open areas or gaps between cells in the physical layout design 301, which may correspond to empty areas in the physical layout design 301. The empty area locator 312 may also determine which cells in the physical layout design 301 abut or are adjacent to empty areas in the physical layout design 301.

[0026] The yield improvement tool 310 may include a design rule element 313 to determine whether extracted characteristics of cells in the physical layout design 301 correspond to potential design rule violations. For example, when a subsequent design rule check process includes a design rule requiring a minimum width for cells in the physical layout design 301, the design rule element 313 may identify any cell in the physical layout design 301 with a width less than the minimum width. In some embodiments, the design rule element 313 may identify cells with widths that would potentially lead to design rule violations during subsequent design rule checks.

[0027] The yield improvement tool 310 may include a fill cell selector 314 to select fill cells from the fill cell library 302 to fill into empty regions identified by the empty region locator 312. Once the empty regions have been replaced with the selected fill cells, the physical layout design 301 should eliminate the design rule violations that would occur if the empty regions were retained in the physical layout design 301.

[0028] In some embodiments, the fill cell selector 314 may utilize extracted characteristics of the cells in the physical layout design 301 to select fill cells for empty areas. For example, the fill cell selector 314 may identify cells that have been marked as being smaller than a minimum width and may select fill cells for insertion into empty areas adjacent to the marked cells. In some embodiments, the fill cell selector 314 may select fill cells that have the same voltage type as the marked cells and that have a width such that the combination of the width of the marked cells and the width of the fill cells satisfies or exceeds the minimum width of the design rule. Since the fill cells can be viewed as extensions of the cells in the physical layout design 301, inserting the selected fill cells next to the marked cells can eliminate potential design rule violations during subsequent design rule checks due to failure to meet the minimum width of the marked cells.

[0029] In some embodiments, the filler cell selector 314 can expand the marked cells in the physical layout design 301 by selecting filler cells to be placed in empty areas adjacent to the marked cells before selecting filler cells for the remaining empty areas in the physical layout design 301. The filler cell selector 314 can select filler cells for the remaining empty areas based on the extracted characteristics of the cells in the physical layout design 301 and based on user priority. For example, the filler cell selector 314 can select filler cells for the remaining empty areas to have a voltage type corresponding to the cells adjacent to the empty areas, and when two different voltage type options exist, the filler cells are selected based on the priority of the voltage types. The filler cell selector 314 can also select filler cells for the remaining empty areas to minimize the number of filler cells, for example, selecting the largest possible filler cells to fill the remaining empty areas.

[0030] The yield improvement tool 310 may include a cell reference unit 315 to generate a cell reference for each selected fill cell. Each cell reference may correspond to an empty cell having the name of the corresponding selected fill cell, as used in the fill cell library 302, and optionally include the voltage type and width of the corresponding selected fill cell. The cell reference unit 315 may insert the cell reference into the physical layout design 301, which may generate a marked physical layout design 303.

[0031] Figure 4B Example portions of a physical layout design, filled with the marker 404, according to various embodiments, are illustrated. Reference Figure 4B Besides using Figure 4B The cell reference 404 is replaced with Figure 4AOutside of the empty region 403 adjacent to at least one of the standard cells in the standard cell 402 shown, this part of the marked physical layout design can be similar to the above reference. Figure 4A The physical layout design is described above. Cell references may correspond to empty cells, each empty cell having the name of a selected fill cell, as used in a fill cell library, and optionally including the voltage type and width of the selected fill cell.

[0032] Return to reference Figure 3 System 300 may include a design fill tool 320 that receives marked physical layout designs 303 from yield improvement tool 310 and fill library 302. The design fill tool 320 may traverse the marked physical layout designs 303 to identify cell references and use the cell references to locate corresponding fill cells in the fill cell library 302. In some embodiments, the design fill tool 320 may parse each cell reference to identify the corresponding name of the fill cell and optionally identify the voltage type and width of the fill cell. The design fill tool 320 may use the fill cell name (possibly along with voltage type and / or width) to search for fill cells indicated by the cell references from the fill cell library 302. The design fill tool 320 may remove cell references from the marked physical layout designs 303 and insert fill cells from the fill cell library 302 into the positions previously occupied by cell references, thus generating a filled physical layout design 304.

[0033] Figure 4C Example portions of the physical layout design of the filler cells 405 according to various embodiments are illustrated. (See reference...) Figure 4C Besides using Figure 4C The filling unit 405 is replaced Figure 4B Apart from the cell reference 404 shown, this part of the filled physical layout design can be similar to the reference above. Figure 4B The description refers to the physical layout design of the markers. Figure 4B The cell reference 404 includes the name of the fill cell 405 in this part of the physical layout design that has been filled.

[0034] Return to reference Figure 3System 300 may include a design rule checking tool 330 to receive a filled physical layout design 304, which may include cells from a physical layout design 301, wherein fill cells are filled into previously empty areas of the physical layout design 301. The design rule checking tool 330 may perform a design rule checking operation on the filled physical layout design 304, for example, by applying electrical design rules to the geometric information in the filled physical layout design 304 to determine if any violations exist. Since the yield improvement tool 310 and the design filling tool 320 select fill cells inserted into the filled physical layout design 304 based at least in part on the design rules applied by the design rule checking tool 330 during the design rule checking process, the fill cells are structurally corrected, thus eliminating potential design rule violations that would occur without inserting fill cells.

[0035] Figure 5 Flowcharts illustrating various examples demonstrate the process of inserting fill cells with structural corrections for circuit design layouts. (Reference) Figure 5 In block 501, the computational system implementing yield improvement tools can extract the characteristics of cells in the physical layout design of an integrated circuit. The physical layout design can describe the integrated circuit using geometric information that can be used during its fabrication, such as geometric information regarding the planar geometry corresponding to the patterns of metal, oxide, or semiconductor layers that make up the integrated circuit. In some embodiments, the physical layout design can be specified in formats such as Graphics Data System II (GDSII), Open Artwork System Exchange Standard (OASIS), Library Exchange Format (LEF), and Design Exchange Format (DEF).

[0036] The computational system implementing yield improvement tools can identify cells placed in a physical design layout and determine their characteristics. For example, the computational system implementing yield improvement tools can determine the voltage type or threshold voltage level of each cell in the physical layout design, such as standard voltage, low voltage, ultra-low voltage, etc. The computational system implementing yield improvement tools can also measure the width of the cells in the physical layout design. The combination of voltage type and width can correspond to at least some of the characteristics of the cells in the physical layout design.

[0037] In box 502, the computational system implementing yield improvement tools can determine the location of empty areas in the physical layout design. The computational system implementing yield improvement tools can identify open areas or gaps between cells in the physical layout design, which may correspond to empty areas in the physical layout design. The computational system implementing yield improvement tools can also determine which cells in the physical layout design abut or are adjacent to empty areas in the physical layout design.

[0038] In block 503, the computational system implementing yield improvement tools can select filler cells for empty regions based at least in part on the extracted characteristics of the cells adjacent to the empty regions and electrical design rules for manufacturing integrated circuits. The computational system implementing yield improvement tools can determine whether the extracted characteristics of cells in the physical layout design correspond to potential design rule violations. For example, when a subsequent design rule check process includes a design rule requiring a minimum width for cells in the physical layout design, the computational system implementing yield improvement tools can identify any cells in the physical layout design with a width less than the minimum width. The computational system implementing yield improvement tools can select filler cells that, when inserted into empty regions of the physical layout design, can eliminate potential design rule violations, for example, by expanding those cells with widths less than the minimum width with filler cells. In some embodiments, the selected filler cells have a voltage type that matches the voltage type in the extracted characteristics of the cells adjacent to the empty regions.

[0039] In block 504, the computational system implementing yield improvement tools can fill empty areas of the physical layout design with cell references having names corresponding to the selected fill cells. The computational system implementing yield improvement tools can generate cell references for each selected fill cell. Each cell reference can correspond to an empty cell having a name corresponding to the selected fill cell, as used in the fill cell library, and optionally including the voltage type and width of the corresponding selected fill cell. The computational system implementing yield improvement tools can then insert the cell references into the physical layout design.

[0040] In block 505, the computational system implementing the cell filling tool can replace cell references with fill cells in the physical design layout. The cell filling tool can traverse the physical layout design to identify cell references and use the cell references to find the corresponding fill cells in the fill cell library. In some embodiments, the cell filling tool can parse each cell reference to identify the corresponding name of the fill cell and optionally identify the voltage type and width of the fill cell. The cell filling tool can use the fill cell name (possibly along with the voltage type and / or width) to search for the fill cell indicated by the cell reference from the fill cell library. The cell filling tool can remove the cell reference from the physical layout design and insert the fill cell from the fill cell library into the position previously occupied by the cell reference.

[0041] Figure 6 The flowchart illustrates various examples of selecting fill cells for insertion into empty areas of a physical layout design. (Reference) Figure 6 In block 601, the computational system implementing yield improvement tools can identify standard cells in the physical layout design that are smaller than a minimum width. In some embodiments, the computational system implementing yield improvement tools can measure the width of the standard cells in the physical layout design to identify their width, and then compare that width with a minimum width associated with a design rule. In some embodiments, the computational system implementing yield improvement tools can identify standard cells that are smaller than the minimum width in the physical layout design.

[0042] In block 602, the computational system implementing yield improvement tools can select filler cells to abut against the identified standard cells based on the width and voltage type of the identified standard cells. The computational system implementing yield improvement tools can identify empty regions adjacent to the identified standard cells and identify multiple sets of filler cells that can be selected for insertion into the identified empty regions. In some embodiments, each set of filler cells may include filler cells having a voltage type matching the corresponding identified standard cell and filler cells having the correct width. The correct width may be smaller than the width of the empty region adjacent to the corresponding identified standard cell and large enough that the combination of its width and the width of the identified standard cell exceeds a minimum width. In some embodiments, the computational system implementing yield improvement tools can select filler cells from the identified sets of filler cells.

[0043] In block 603, the computational system implementing yield improvement tools can insert cell references for selected fill cells into empty regions abutting the identified standard cells. The computational system implementing yield improvement tools can generate cell references for each selected fill cell. Each cell reference can correspond to an empty cell having the name of the corresponding selected fill cell, as used in a fill cell library, and optionally including the voltage type and width of the corresponding selected fill cell. The computational system implementing yield improvement tools can insert the cell references into the physical layout design.

[0044] In box 604, the computational system implementing yield improvement tools can identify additional empty areas in the physical layout design. The computational system implementing yield improvement tools can identify open areas or gaps between cells in the physical layout design. When an open area in the box is not yet included in the cell references filled into the physical layout design in box 603, the computational system implementing yield improvement tools can determine the open space corresponding to an additional empty area in the physical layout design. The computational system implementing yield improvement tools can also determine which cells in the physical layout design abut or are adjacent to empty areas in the physical layout design.

[0045] In box 605, the computational system implementing yield improvement tools can select fill cells for additional empty areas in the physical layout design. The computational system can select fill cells for additional empty areas based on the extracted characteristics of the cells in the physical layout design and user priorities. For example, the computational system can select fill cells for additional empty areas to have a voltage type corresponding to the cells adjacent to the empty area, and when two different voltage type options exist, select fill cells based on the priority of the voltage types. The computational system can also select fill cells for additional empty areas to minimize the number of fill cells, for example, selecting the largest possible fill cells to fill the remaining empty areas.

[0046] In box 606, the calculation system implementing yield improvement tools can insert cell references for selected fill cells into additional empty areas. The calculation system implementing yield improvement tools can generate cell references for each selected fill cell. Each cell reference can correspond to an empty cell having the name of the corresponding selected fill cell, as used in a fill cell library, and optionally including the voltage type and width of the corresponding selected fill cell. The calculation system implementing yield improvement tools can insert the cell references into additional empty areas identified in the physical layout design.

[0047] The systems and apparatuses described herein may use dedicated processor systems, microcontrollers, programmable logic devices, microprocessors, or any combination thereof to perform some or all of the operations described herein. Some of the operations may be implemented in software, while others may be implemented in hardware. Any operations, processes, and / or methods described herein may be performed by apparatus, devices, and / or systems substantially similar to those described herein and with reference to the illustrated figures.

[0048] A processing device can execute instructions or "code" stored in memory. Memory can also store data. A processing device can be, but is not limited to, analog processors, digital processors, microprocessors, multi-core processors, processor arrays, network processors, etc. A processing device can be part of an integrated control system or system manager, or it can be provided as a portable electronic device configured to interface locally or remotely with a networked system via wireless transmission.

[0049] Processor memory can be integrated with the processing device, for example, RAM or flash memory disposed within an integrated circuit microprocessor. In other examples, memory can include separate devices, such as external disk drives, storage arrays, portable flash key cards, etc. Memory and processing devices can be operatively coupled together or communicate with each other, for example, via I / O ports, network connections, etc., and the processing device can read files stored on the memory. Depending on access settings, associated memory may be designed to be "read-only" (ROM) or not "read-only". Other examples of memory may include, but are not limited to, WORM, EPROM, EEPROM, flash memory, etc., which can be implemented in solid-state semiconductor devices. Other memory may include moving parts, such as known spinning disk drives. All of these memories can be "machine-readable" and can be read by the processing device.

[0050] Operating instructions or commands may be implemented or embodied in the tangible form of stored computer software (also known as a “computer program” or “code”). The program or code may be stored in digital memory and may be read by a processing device. A “computer-readable storage medium” (or alternatively, a “machine-readable storage medium”) may include all of the aforementioned types of memory as well as future technologies, provided that the memory is capable of storing digital information having the nature of a computer program or other data, at least temporarily, and provided that the stored information can be “read” by a suitable processing device. The term “computer-readable” may not be limited to the historical use of “computer” implying a complete mainframe, minicomputer, desktop, or even laptop computer. Rather, “computer-readable” may include storage media that can be read by a processor, processing device, or any computing system. Such media may be any available media that can be accessed locally and / or remotely by a computer or processor, and may include volatile and non-volatile media, removable and non-removable media, or any combination thereof.

[0051] A program stored in a computer-readable storage medium may include a computer program product. For example, the storage medium can serve as a convenient means of storing or transmitting a computer program. For convenience, operations may be described as various interconnected or coupled functional blocks or diagrams. However, there may be situations where these functional blocks or diagrams can be equivalently aggregated into a single logical device, program, or operation without clear boundaries.

[0052] in conclusion

[0053] While this application describes specific examples of embodiments of the invention, those skilled in the art will understand that many variations and substitutions of the systems and techniques described above fall within the spirit and scope of the invention as set forth in the appended claims. For example, although specific terms have been used above to refer to the design process, it should be understood that various examples of the invention can be implemented using any desired combination of electronic design automation processes.

[0054] Those skilled in the art will also recognize that the concepts taught herein can be adapted to suit a particular application in many other ways. In particular, those skilled in the art will recognize that the illustrated examples are merely one of many alternative implementations that will become apparent upon reading this disclosure.

[0055] Although the specification may mention “one,” “an,” “another,” or “some” examples in several places, this does not necessarily mean that each such reference refers to the same one or more examples or that the feature applies only to a single example.

Claims

1. A method for inserting infill units for structural correction in physical layout design, comprising: The characteristics of cells are extracted from the physical layout design of integrated circuits by the computing system; The location of empty areas in the physical layout design is determined by the computing system; The computing system selects filling cells for the empty region based at least in part on the extracted characteristics of the cells abutting the empty region and one or more electrical design rules for the manufacture of the integrated circuit, wherein the extracted characteristics of the cells abutting the empty region include the voltage type of the cell or a combination of the voltage type of the cell and the width of the cell. The computing system fills the empty areas in the physical layout design with reference cells, wherein the reference cells include the corresponding names of the selected filling cells; and The computing system inserts the selected fill cell into the empty area of ​​the physical design layout, wherein inserting the selected fill cell into the empty area of ​​the physical design layout includes: replacing the reference cell with the selected fill cell based on the name in the reference cell.

2. The method according to claim 1, wherein, Selecting the filling unit for the empty region further includes: The dimensions of one or more of the cells in the physical layout design violate at least one of the electrical design rules. Determining the size and type of the filler cells, when placed adjacent to identified cells in the physical layout design, eliminates violations of electrical design rules; and Filling cells for at least a subset of the empty regions are selected, at least in part, based on the determined size and type of the filling cells.

3. The method according to claim 2, wherein, After selecting fill cells for at least the subset of the empty areas, another subset of the empty areas in the physical layout design is identified and fill cells for the other subset of the empty areas are selected.

4. The method according to claim 1, wherein, Replacing the reference unit with the selected filling unit based on the name in the reference unit further includes: The name search library in the reference unit is used to identify the selected fill cell; and The selected fill cell from the fill cell library is inserted into the empty area of ​​the physical design layout.

5. The method of claim 1, further comprising: The computing system performs a design rule check operation, which applies the electrical design rules to the physical design layout in which the selected filler cells have been inserted.

6. A system for inserting filler cells in a structurally corrected manner in physical layout design, comprising: A storage system, configured to store computer-executable instructions; as well as A computing system, which responds to the execution of said computer-executable instructions, is configured to: Extracting cell characteristics from the physical layout design of integrated circuits; Determine the location of empty areas in the physical layout design; The filling cells for the empty region are selected at least in part based on the extracted characteristics of the cells abutting the empty region and one or more electrical design rules for the manufacture of the integrated circuit, wherein the extracted characteristics of the cells abutting the empty region include the voltage type of the cell or a combination of the voltage type of the cell and the width of the cell; The computing system fills the empty areas in the physical layout design with reference cells, wherein the reference cells include the corresponding names of the selected filling cells; and Inserting the selected fill cell into the empty area of ​​the physical design layout, wherein inserting the selected fill cell into the empty area of ​​the physical design layout includes: replacing the reference cell with the selected fill cell based on the name in the reference cell.

7. The system according to claim 6, wherein, In response to the execution of the computer-executable instructions, the computing system is further configured to select filling units for the empty region in the following manner: The dimensions of one or more of the cells in the physical layout design violate at least one of the electrical design rules. Determining the size and type of the filler unit eliminates violations of electrical design rules when the filler unit is placed adjacent to the identified units in the physical layout design. as well as Filling cells for at least a subset of the empty regions are selected, at least in part, based on the determined size and type of the filling cells.

8. The system according to claim 7, wherein, The computing system, in response to the execution of the computer-executable instructions, is further configured to: after selecting fill units for at least the subset of the empty regions, identify another subset of the empty regions in the physical layout design and select fill units for the other subset of the empty regions.

9. The system according to claim 6, wherein, In response to the execution of the computer-executable instructions, the computing system is further configured to replace the reference cell with the selected padding cell based on the name in the reference cell in the following manner: Use the name search library in the reference unit to identify the selected fill unit; as well as The selected fill cell from the fill cell library is inserted into the empty area of ​​the physical design layout.

10. The system according to claim 6, wherein, The computing system, in response to the execution of the computer-executable instructions, is further configured to perform a design rule check operation that applies the electrical design rules to the physical design layout in which the selected filler cells have been inserted.

11. An apparatus for at least one computer-readable storage device including storage instructions, the instructions being configured to cause one or more processing devices to perform an operation, the operation comprising: Extracting cell characteristics from the physical layout design of integrated circuits; Determine the location of empty areas in the physical layout design; The filling cells for the empty region are selected at least in part based on the extracted characteristics of the cells abutting the empty region and one or more electrical design rules for the manufacture of the integrated circuit, wherein the extracted characteristics of the cells abutting the empty region include the voltage type of the cell or a combination of the voltage type of the cell and the width of the cell; The empty areas in the physical layout design are filled with reference cells, wherein the reference cells include the corresponding names of the selected filling cells; and Inserting the selected fill cell into the empty area of ​​the physical design layout, wherein inserting the selected fill cell into the empty area of ​​the physical design layout includes: replacing the reference cell with the selected fill cell based on the name in the reference cell.

12. The apparatus according to claim 11, wherein, Selecting the filling unit for the empty region further includes: The dimensions of one or more of the cells in the physical layout design violate at least one of the electrical design rules. Determining the size and type of the filler cells, when placed adjacent to identified cells in the physical layout design, eliminates violations of electrical design rules; and Filling cells for at least a subset of the empty regions are selected, at least in part, based on the determined size and type of the filling cells.

13. The apparatus according to claim 12, wherein, After selecting fill cells for at least the subset of the empty areas, another subset of the empty areas in the physical layout design is identified and fill cells for the other subset of the empty areas are selected.

14. The apparatus according to claim 11, wherein, Replacing the reference unit with the selected filling unit based on the name in the reference unit further includes: The name search library in the reference unit is used to identify the selected fill cell; and The selected fill cell from the fill cell library is inserted into the empty area of ​​the physical design layout.

15. The apparatus according to claim 11, wherein, The instruction is configured to cause one or more processing devices to perform an operation, the operation further including: performing a design rule check operation, the design rule check operation applying the electrical design rules to the physical design layout in which the selected filler cells have been inserted.

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