Packet buffer overflow in network equipment

Abstract

Packets to be transmitted from the network device are buffered in a queue in a first packet memory. In response to detecting congestion in the queue in the first packet memory, a group of a plurality of packets is transferred from the first packet memory to a second packet memory, the second packet memory being configured to buffer a portion of a service bandwidth supported by the network device. Before transmitting packets in the one or more groups of the plurality of packets from the network device, the packets in the one or more groups of the plurality of packets are transferred from the second packet memory back to the first packet memory. The packets transferred from the second packet memory back to the first packet memory are retrieved from the first packet memory and forwarded to one or more network ports for transmitting packets from the network device.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. Provisional Patent Application No. 62 / 991,431, filed on March 18, 2020, entitled “Modular Spill Over in a Network Switch,” the disclosure of which is hereby expressly incorporated by reference in its entirety. Technical Field

[0003] The present disclosure relates generally to communication networks, and more particularly to buffering packets in network devices. Background Art

[0004] Network devices such as network switches, routers, edge devices, etc. often utilize packet memory to buffer packets during the congestion time experienced by the output port of the network device, while the packet is being processed by the network device and / or waiting for transmission. Usually, network devices utilize internal packet memory (for example, a packet memory implemented on the same chip as the packet processor of the network device) or external packet memory (for example, a packet memory implemented as a separate device outside the packet processor chip of the network device). Internal packet memory is usually smaller than external packet memory, but the access bandwidth possessed by internal packet memory is usually higher than external packet memory. On the other hand, external packet memory is usually larger than internal packet memory and provides more storage capacity, but the access bandwidth of external packet memory is usually lower than internal packet memory. The lower access bandwidth of external packet memory does not have enough bandwidth to support the buffering of the full bandwidth supported by many network devices at present. Summary of the invention

[0005] In one embodiment, a method for processing packets in a network device includes: receiving, at a packet processor of the network device, a packet entering via a network port among a plurality of network ports of the network device; processing the packet with the packet processor to at least determine one or more network ports among the plurality of network ports through which the packet will be transmitted from the network device; buffering the packet in a first packet memory with the packet processor; detecting congestion in a queue in the first packet memory; in response to detecting congestion in the first packet memory, dynamically transferring one or more groups of corresponding plurality of packets from the first packet memory to a second packet memory in corresponding one or more transfers, the second packet memory being configured to buffer a portion of a service bandwidth supported by the network device; after transferring a group of the plurality of packets from the first packet memory to the second packet memory and before transmitting a packet in the group of the plurality of packets from the network device, requesting with the packet processor to transfer a group of the plurality of packets from the second packet memory back to the first packet memory; retrieving with the packet processor from the first packet memory the packet transferred from the second packet memory back to the first packet memory; and forwarding with the packet processor the packet retrieved from the first packet memory to one or more network ports determined for transmitting packets from the network device.

[0006] In another embodiment, a network device includes: a plurality of network ports configured to be coupled to a plurality of network links and a packet processor coupled to the plurality of network ports. The packet processor is configured to: process packets received via a network port among the plurality of network ports of the network device to at least determine one or more network ports among the plurality of network ports through which the packet will be transmitted from the network device; buffer the packet in a queue in a first packet memory; detect congestion in the queue in the first packet memory; in response to detecting congestion in the first packet memory, dynamically transfer one or more groups of corresponding plurality of packets from the first packet memory to a second packet memory in corresponding one or more transfers, the second packet memory being configured to buffer a portion of a service bandwidth supported by the network device; after transferring a group of the plurality of packets from the first packet memory to the second packet memory and before transmitting a packet in a group of the plurality of packets from the network device, request a transfer of a group of the plurality of packets from the second packet memory back to the first packet memory; retrieve from the first packet memory the packet transferred from the second packet memory back to the first packet memory; and forward the packet retrieved from the first packet memory to one or more network ports determined for transmitting the packet from the network device. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1is a block diagram of an exemplary network device configured to implement overflow of packets from a first packet memory to one or more second packet memories, according to one embodiment.

[0008] Figure 2A-2D is a diagram illustrating a process for transferring a portion of an egress queue from a first packet memory to a second packet memory, and transferring a portion of an egress queue from the second packet memory back to the first packet memory, according to one embodiment.

[0009] Figure 3 is a flow chart illustrating an exemplary method for processing packets in a network device configured to implement overflow of packets from a first packet memory to one or more second packet memories, according to one embodiment. DETAILED DESCRIPTION

[0010] In the embodiments described below, a network device is configured to utilize a first packet memory and at least one second packet memory to buffer packets received at the network device, for example, during a congestion time experienced by an output network port of the network device, until the packets can be transmitted by the network device. The first packet memory has a relatively high access bandwidth compared to the access bandwidth of the at least one second packet memory. For example, in one embodiment, the first packet memory has a sufficiently high access bandwidth to support buffering of the full bandwidth supported by the network device, while the at least one second packet memory does not have a sufficiently high bandwidth to support buffering of the full bandwidth supported by the network device. On the other hand, in one embodiment, the first packet memory with a sufficiently high access bandwidth is relatively small in size and has a low storage capacity compared to the at least one second packet memory.

[0011] In one embodiment, the network device is configured to initially store packets in a first packet memory and transfer packets to at least one second packet memory as needed based on a congestion state at the network device. For example, in one embodiment, the network device is configured to detect congestion in an egress queue corresponding to a particular network port of the network device, for example based on detecting that the length of the egress queue in the first packet memory exceeds a threshold, and in response to detecting congestion in the egress queue, transfer one or more packets in the particular egress queue from the first packet memory to the second packet memory, thereby allowing the egress queue to "overflow" from the first packet memory to the second packet memory. In one embodiment, the buffer in the second packet memory is larger than the buffer in the first packet memory, and the network device is configured to transfer one or more groups of multiple packets from the first packet memory to the second packet memory in the corresponding one or more transfers to more efficiently utilize the larger buffer in the second packet memory. In one embodiment, the packets from the particular egress queue transferred from the first packet memory to the second packet memory are maintained in the corresponding queue in the second packet memory to maintain the storage order of the packets in the first packet memory. Subsequently, in one embodiment, before transmitting one or more packets from the network device, one or more packets are transferred from the second packet memory back to the first packet memory, and in one embodiment, relinked with the egress queue in the first packet memory so that the packet can be subsequently scheduled for transmission from the egress queue in the first packet memory. Then, in one embodiment, the network device schedules the transmission of one or more packets from the first packet memory. Because only a portion of the packets processed by the network device are transferred from the first packet memory to the second packet memory, in one embodiment, the second lower bandwidth packet memory only needs to support a portion of the bandwidth supported by the network device. In addition, in one embodiment, on a per-egress queue basis, packets are transferred from the first packet memory to the second packet memory, the order of packets from a specific egress queue is maintained in the corresponding queue of the second packet memory, and when the packets are transferred from the second packet memory back to the first packet memory, the packets are relinked with the corresponding egress queue, which ensures that the packets are transmitted from the network device without changing the order in which the packets are received by the network device.

[0012] In some embodiments, the network device is configured to support a modular buffer architecture in which the number of second low-bandwidth packet memories utilized by the network device depends on the buffer capacity required or desired by the network device, for example, the buffer capacity is determined by the location of the network device within the network. For example, in one embodiment, network devices at the edge of the network require lower buffer capacity than network devices located in the distribution layer of the network, and network devices located in the distribution layer of the network require lower buffer capacity than switches at the core of the network. Thus, for example, a network device at the core of the network is configured to utilize two second packet memories and allow traffic buffered in a first packet memory to overflow over the two second packet memories as needed. On the other hand, in various embodiments, a network device at the distribution layer of the network is configured to utilize only a single second packet memory, and a network device at the edge of the network is configured to buffer all traffic as needed only in the first packet memory without using any second packet memory. Therefore, in at least some embodiments, the modular buffer architecture of the present disclosure allows the same core chip of a network device to be deployed in network devices positioned at different locations within a network, and the number of second packet memories utilized by the network device depends on the specific location of the network device within the network.

[0013] Figure 1 1 is a block diagram of an exemplary network device 100 according to one embodiment, the network device 100 being configured to implement overflow of packets from a first packet memory to one or more second packet memories. The network device 100 includes a plurality of network ports 108, the network ports 108 being configured to be coupled to corresponding network links 110 for coupling the network device 100 to other devices in the network. The network device 100 also includes a packet processor 112 coupled to the network port 108. The packet processor 112 is configured to process packets received via the network port 108 and to determine one or more other network ports 108 via which the packets are forwarded to one or more other devices on the network. In some embodiments, a data unit corresponding to the packet, such as a packet descriptor corresponding to the packet, is generated, and the packet descriptor is provided to the packet processor 112 instead of the packet itself to process the packet. In one embodiment, the packet descriptor includes header information and other information associated with the packet. In one embodiment, the packet processor 112 is configured to update the information in the packet descriptor as needed during the processing of the packet descriptor. For ease of explanation, the term "packet" is used hereinafter to refer to the packet itself or to a packet descriptor associated with the packet.

[0014] In one embodiment, the packet processor 112 includes a memory controller 120. The memory controller 120 is coupled to a first packet memory 124. Further, in one embodiment, the memory controller 120 is coupled to one or more second packet memories 128. In one embodiment, the first packet memory 124 is implemented on the same chip as the packet processor 112. On the other hand, in one embodiment, the one or more second packet memories 128 are not implemented on the same chip as the packet processor 112. For example, in one embodiment, the one or more second packet memories 128 are implemented as one or more separate devices external to the network device 100, or are included in one or more separate devices external to the network device 100. In one embodiment, the one or more second packet memories 128 are implemented as or included in one or more memory devices that are coupled to the network device 100 via corresponding one or more network ports 108. In other words, in this embodiment, the one or more network ports 108 of the network device 100 are used to provide coupling of the network device 100 with the one or more second packet memories 128, rather than coupling of the network device 100 with other devices on the network. In another embodiment, at least one of the one or more second packet memories 128 is implemented as or included in a memory device coupled to the network device 100 via an interface other than the network port 108. For example, at least one second packet memory 128 is implemented as or included in a memory device coupled to the network device 100 via a peripheral component interconnect (PCI) interface, a PCI Express (PCIe) interface, a double data rate (DDR) memory interface, a graphics double data rate (GDDR) memory interface, a flash memory interface, or any other suitable type of memory interface.

[0015] In another embodiment, at least one of the one or more second packet memories 128 is implemented on a different chip from the packet processor 112, but the at least one of the one or more second packet memories 128 is still inside the network device 100 (e.g., packaged together with other components of the network device 100). For example, in one embodiment, the external packet memory 128 is provided to replace the network port chip corresponding to the network port 108, or is provided to replace the physical layer (PHY) chip corresponding to the port 108, and is packaged together with the packet processor 112 of the network device 100.

[0016] As an example, the first packet memory 124 is sometimes referred to herein as an "internal packet memory 124", and the one or more second packet memories 128 are sometimes referred to herein as "multiple external packet memories 128" or collectively referred to as "external packet memories 128". However, in some embodiments, both the first packet memory 124 and the one or more second packet memories 128 are internal packet memories or both are external packet memories.

[0017] In one embodiment, the internal packet memory 124 is implemented using static random access memory (SRAM) technology, and each of the one or more external packet memories 128 is implemented using dynamic random access memory (DRAM) technology. In other embodiments, the internal packet memory 124 and / or the one or more external packet memories 128 are implemented using other suitable technologies. In one embodiment, the one or more external packet memories 128 are implemented as double data rate (DDR) type memories. In other embodiments, the one or more external packet memories include any suitable combination of one or more of the following: graphic double data rate (GDDR) memory, flash memory, and any other suitable type of memory.

[0018] In various embodiments, the internal packet memory 124 has different access bandwidth, cost, size, storage capacity and other characteristics compared to the external packet memory 128. For example, in one embodiment, the internal packet memory 124 has a higher access bandwidth and can be operated at the full line speed supported by the network device 100. In contrast, in some embodiments, the external packet memory 128 has a lower access bandwidth and cannot be operated at the full line speed supported by the network device 100. However, at least in some embodiments, the internal packet memory 124 is more expensive than the external packet memory 128. In addition, for example, in one embodiment, the internal packet memory 124 will take up on-chip space suitable for adding additional processing circuits. Therefore, in some embodiments, for example, due to cost and size constraints, the size of the internal packet memory 124 is generally smaller than the external packet memory 128, and the storage capacity is lower. As just one example, in one embodiment, the internal packet memory 124 has a storage capacity on the order of megabytes (MB) or less, while each of the external packet memories in the external packet memory 128 has a storage capacity on the order of gigabytes (GB) or more.

[0019] In one embodiment, the packet processor 112 is configured to initially queue processed packets in the internal packet memory 124 and transfer packets to the external packet memory 128 as needed, thereby allowing packets to overflow into the second packet memory 128. For example, as will be explained in detail below, the packet processor 112 is configured to transfer packets in one or more congested egress queues in the internal packet memory 124 to the external packet memory 128. In one embodiment, the buffer in the external packet memory 128 is larger than the buffer in the internal packet memory 124, and the packet processor 112 is configured to transfer one or more groups of multiple packets from the internal packet memory 124 to the external packet memory 128 in the corresponding one or more transfers to more efficiently utilize the larger buffer in the external packet memory 128. In one embodiment, the packet processor 112 then requests that the packets be transferred back to the internal packet memory 124 before transmitting the packets overflowing from the first packet memory 124 to the second packet memory 128. The packet processor 112 then links the packets transferred back to the internal packet memory 124 with the corresponding egress queues in the internal packet memory 124. In one embodiment, when scheduled for transmission, the packet is then retrieved from internal packet memory 124 and forwarded to the appropriate network port for transmission by network device 100 .

[0020] In one embodiment, packets or groups of packets transferred from an egress queue in the internal packet memory 124 are stored in a corresponding queue in the external packet memory 128 to maintain the storage order of the packets in the internal packet memory 124. In one embodiment, the packet processor is configured to continue transferring packets or groups of packets from a congested egress queue in the internal packet memory 124 to the external packet memory 128 as needed while continuing to monitor the egress queue in the internal packet memory 124 for congestion. Thus, during the life of an egress queue in the network device 100, multiple transfers of packets or groups of packets occur between the internal packet memory 124 and the external packet memory 128 as packets from the head of the corresponding queue in the external packet memory 128 are transferred back to the internal packet memory 124, and additional packets from the egress queue in the internal packet memory 124 are transferred to the external memory 128 and added to the tail of the corresponding queue in the external packet memory 128.

[0021] In one embodiment, the packet processor 112 is configured to transfer only a portion of the packets stored in the internal packet memory 124 to the external packet memory 128, while other packets remain in the internal packet memory 124 for the entire time until the packet processor 112 retrieves the packet from the internal packet memory 124 for transmission of the packet via the network port 108 determined for transmission of the packet. For example, in one embodiment, the packet processor 112 is configured to transfer only packets from a congested egress queue in the internal packet memory 124, while packets in a non-congested egress queue remain in the internal packet memory 124 until the packet is retrieved from the packet memory 124 for transmission of the packet via the network port 108 determined for transmission of the packet. Thus, in one embodiment, only packets from a congested egress queue overflow to the external packet memory 128, while non-congested egress queues remain entirely in the internal packet memory 124. In at least some embodiments, because only a portion of the packets processed by network device 100 are transferred from internal packet memory 124 to external packet memory 128, external packet memory 128 need only support a portion of the bandwidth supported by network device 100. Additionally, in at least some embodiments, packets are transferred from internal packet memory 124 to external packet memory 128 on a per egress queue basis, and when packets are transferred from external packet memory 128 back to internal packet memory 124, the packets are relinked with the corresponding egress queue, which ensures that packets are transmitted from network device 100 without changing the order in which the packets were received by network device 100.

[0022] In some embodiments, the number of external packet memories 128 that the network device 100 is configured to utilize depends on the buffering capacity required or desired by the network device 100, where, for example, the buffering capacity depends on the location of the network device 100 within the network. For example, in one embodiment, if the network device 100 is deployed at the core of the network, the network device 100 is configured to utilize two external packet memories 128. In this case, in various embodiments, the two external packet memories are coupled to the network device 100 via two corresponding network ports 108, or are provided as an external chip to the packet processor 112 of the network device 100. On the other hand, in one embodiment, if the network device 100 is deployed at the distribution layer of the network, the network device 100 is configured to utilize only a single external packet memory 128. For example, in this case, in one embodiment, only a single network port 108 of the network device 100 is used to couple the network device 100 to the external packet memory 128, or only a single chip within the network device 100 implements the external packet memory 128. As yet another example, if the network device 100 is deployed as an edge device at the edge of a network, the network device 100 is configured to buffer all packets as needed only in the internal packet memory 124. In this case, the external packet memory 1288 need not be coupled to the network device 100 or otherwise provided for the network device 100. Thus, in various embodiments, the same core chip (e.g., the same core packet processor chip 112) of the network device 100 is utilized to support various buffering requirements of the network device 100, depending on, for example, the location of the network device 100 within the network.

[0023] In operation, packets received by the network device via a network port 108 are provided to the packet processor 112 for processing the packet. In one embodiment, the packet processor 112 includes a forwarding engine 130 configured to determine one or more network ports 108 via which the packet will be transmitted from the network device 100 based on information from a header of the packet. In one embodiment, the forwarding engine 130 includes or is coupled to a forwarding database (not shown) that stores forwarding information (e.g., port information) associated with addresses (e.g., media access control (MAC) addresses, Internet Protocol (IP) addresses, etc.) and / or other suitable information. In one embodiment, the forwarding engine 130 is configured to use the header information to query the forwarding database for information indicating one or more network ports 108 to which the packet will be forwarded. As just one illustrative example, the forwarding engine 130 is configured to use the destination address in the header of the packet to perform a query in a forwarding database (not shown) that stores the correspondence between the destination address and the network port 108 to determine the specific network port 108 via which the packet will be transmitted. As another illustrative example, the forwarding engine 130 is configured to use the VLAN ID in the header of the packet to perform a query in a forwarding database (not shown) that stores the correspondence between the VLAN ID and the network port 108 to determine the set of specific network ports 108 for the packet. According to one embodiment, the forwarding engine 130 is configured to store the ID of the network port (or multiple network port sets) in the packet descriptor corresponding to the packet. In one embodiment, the packet processor 112 is configured to also perform classification of the packet, such as determining the priority with which the packet is associated, the packet flow to which the packet belongs, etc.

[0024] In one embodiment, the packet processor 112 further includes an egress queue manager 132. The egress queue manager 132 is configured to queue packets processed by the packet processor 112 in one of a plurality of egress queues 136. In one embodiment, the egress queues 136 correspond to corresponding network ports 108. In another embodiment, the egress queues 136 correspond to corresponding network ports 108 and corresponding service flow priorities. For example, in one embodiment, a first subset of the egress queues 136 corresponds to the first network port 108 and is used to buffer packets to be transmitted via the first network port 108, wherein the corresponding egress queues 136 in the first subset of the egress queues 136 are used to buffer packets corresponding to service flows, which are associated with corresponding priorities. Similarly, in one embodiment, a second subset of the egress queues 136 corresponds to the second network port 108 and is used to buffer packets to be transmitted via the second network port 108, wherein the corresponding egress queues 136 in the second subset of the egress queues 136 are used to buffer packets corresponding to service flows associated with corresponding priorities, and so on. Generally speaking, in one embodiment, packets processed by packet processor 112 are queued in the appropriate egress queue or queues 136 for subsequent transmission of the packet via the network port or ports 108 determined for the packet.

[0025] In one embodiment, the egress queue manager 132 includes an egress queue monitor 134. The egress queue monitor 134 is configured to monitor metrics associated with the egress queues 136 and detect when congestion occurs in the egress queues 136 based on monitoring the metrics associated with the egress queues 136. For example, the egress queue monitor 136 is configured to monitor the fill level or length of the egress queues 136 and detect congestion in a particular egress queue 136 when the fill level or length of the particular egress queue 136 crosses (e.g., is above) a threshold. In one embodiment, packets queued in an egress queue 136 that is not congested and does not become congested while the packets are waiting to be transmitted from the network device 100 are held in the internal packet memory 124 until the packets are scheduled for transmission from the network device 100.

[0026] On the other hand, in one embodiment, when the egress queue monitor 134 detects congestion in a specific egress queue 136, the egress queue manager 132 instructs the memory controller 120 to transfer one or more packets queued in the specific egress queue 136 in the internal packet memory 124 to the external memory 128. In response, the memory controller 120 retrieves the one or more packets queued in the specific egress queue and transfers the one or more packets to the external packet memory 128. In one embodiment in which the external packet memory 128 is coupled to the network device 100 via the network port 108, the memory controller 120 forwards the one or more packets retrieved from the internal packet memory 124 to the network port 108 for transmission of the packets to the external packet memory 128. As another example, in one embodiment in which the external packet memory 128 is provided to replace a port chip or a PHY chip corresponding to the network port 108, the memory controller 120 forwards the one or more packets directly to the external packet memory 128.

[0027] In one embodiment where the network device 100 is configured to utilize multiple external packet memories 128, the memory controller 120 is configured to select a specific external packet memory 128 from among the multiple external packet memories 128 to transfer the packet to. In one embodiment, the memory controller 120 is configured to select the same memory 128 for transferring packets from a specific egress queue 136 so that the packets are queued in the specific external packet memory 128 in the order within the specific egress queue 136. On the other hand, in one embodiment, the memory controller 120 is configured to distribute the overflow of packets from different egress queues 136 among different external packet memories 128 so as to distribute the overflow traffic bandwidth among the multiple external packet memories 128. In one embodiment, the memory controller 120 is preconfigured to select a specific external packet memory 128 for transferring packets from a specific egress queue 136. In another embodiment, the memory controller 120 is configured to dynamically select a specific external packet memory 128 for transferring packets from a specific egress queue 136.

[0028] In one embodiment, when the memory controller 120 transfers a packet to the external packet memory 128, the memory controller 120 also provides to the external packet memory 128 an indication of the specific egress queue 136 to which the packet corresponds. For example, in one embodiment, the memory controller 120 adds the indication of the specific egress queue 136 to the header of the packet, such as in a tag added to the header of the packet, before forwarding the packet for transfer to the external packet memory 128. In one embodiment in which the memory controller 120 transfers a group of multiple packets to the external packet memory 128, the memory controller device 120 generates a tag to include the indication of the specific egress queue 126 to which the group of packets corresponds, and attaches the tag as a header to the group of multiple packets. In another embodiment, the memory controller 120 provides the indication of the egress queue 136 in a separate in-band control signal or out-of-band control signal that is provided from the network device 100 to the external packet memory 128, respectively, from the transfer of the packet or the group of multiple packets to the external packet memory 128. In one embodiment, external packet memory 128 is configured to maintain an egress queue corresponding to egress queue 136 from which packets are transferred to external packet memory 128. In one embodiment, external packet memory 128 is configured to queue a packet or a group of packets received from network device 100 in an egress queue corresponding to egress queue 136 from which packets are transferred to external packet memory 128.

[0029] In one embodiment, in response to an instruction from the egress queue manager 132 to transfer one or more packets from a specific egress queue 136 to the external packet memory 136, the memory controller 120 transfers the one or more packets from the middle portion of the specific egress queue 136 to the external memory 128, while the head portion and the tail portion of the egress queue 136 remain in the internal packet memory 124. While the packets from the middle portion of the specific egress queue 136 are stored in the external memory 128, the memory controller 120 continues to retrieve packets from the head portion of the specific egress queue 136 in the internal packet memory 124 and forwards the packets to the network port 108 for transmission of the packets from the network device 100. Additionally, in one embodiment, the memory controller 120 continues to queue new packets directed to the specific network port 108 at the tail portion of the egress queue 136 in the internal packet memory 124.

[0030] In one embodiment, the egress queue monitor 134 of the egress queue manager 132 is configured to monitor the head portion of the egress queue 136 in the internal packet memory 124 while the middle portion of the egress queue 136 is stored in the external memory 128. In one embodiment, in response to the egress queue monitor 134 detecting that the fill level or length of the head portion of the egress queue 136 in the internal packet memory 124 is below a threshold, the egress queue manager 132 triggers the memory controller 120 to initiate the transfer of packets in the middle portion of the egress queue 136 from the external packet memory 128 back to the internal packet memory 124. In one embodiment, the memory controller 120 is configured to initiate the transfer of packets in the middle portion of the queue 136 from the external packet memory 128 back to the internal packet memory 124 by generating a control message including an indication of a particular egress queue 136 from which to transfer the packets back to the internal packet memory 124, and providing the control message to the external packet memory 128. For example, in one embodiment, the memory controller 120 is configured to forward control information to a network port 108 coupled to an external packet memory 128 for transmission of control information to packets of the external packet memory 128 while being transmitted "in-band" to the external packet memory 12. In another embodiment, the control message is transmitted "out-of-band" to the external packet memory device 128 via a control line between the network device 100 and the external packet memory 128.

[0031] In response to receiving the control message indicating a particular egress queue 136, the external packet memory 128 (or a device housing the external packet memory 128) initiates retrieval of the packet in the corresponding egress queue in the external packet memory 128 and transmits the packet back to the network device 100. In one embodiment, the packet is received by the network device 100, e.g., via a network port 108 coupled to the external packet memory 128 or via another interface to the external packet memory 128), and provided to the memory controller 120. The memory controller 120 is configured to queue the packet back to the particular egress queue 136 in the internal packet memory 124. To do so, in one embodiment, the memory controller 120 obtains an indication of a memory location (e.g., a buffer) in the internal packet memory 124 at which to place the packet, so that the packet is linked back to the head of the egress queue 136 in the internal packet memory 124 by the egress queue manager 132. In one embodiment, when the last packet from the middle of the egress queue 136 is transferred from the external packet memory 128 to the internal packet memory 124, the last packet is also relinked with the tail portion of the queue in the internal packet memory 124. An exemplary process implemented by the packet processor 112 for transferring packets from the internal packet memory 124 to the external packet memory 128, and transferring packets from the external packet memory 128 back to the internal packet memory 124, according to one embodiment, will be described below with reference to Figure 2A-2D In other embodiments, the packet processor 112 implements other suitable processes for transferring packets to and from the external packet memory 128. Subsequently, in one embodiment, when transmission of a packet is scheduled from an egress queue 136, the memory controller 120 retrieves the packet from a specific egress queue 136 in the internal packet memory 124 and forwards the packet to a specific network port 108 for transmission of the packet from the network device 100.

[0032] Figure 2A-2D is a schematic diagram illustrating a process 200 for transferring packets from an egress queue in a first packet memory to a second packet memory, and transferring packets from the second packet memory back to the first packet memory, according to one embodiment. In one embodiment, the process 200 consists of Figure 1 The network device 100 is implemented to transfer packets from the internal packet memory 124 to the external packet memory 128, and to transfer packets from the external packet memory 128 back to the internal packet memory 124. For ease of explanation, refer to Figure 1 In some embodiments, the process 200 is described with reference to the network device 100 of FIG. Figure 1Furthermore, although process 200 is illustrated and described with reference to only one egress queue, in an embodiment, network device 100 performs process 200 for multiple egress queues maintained by network device 100 at any given time.

[0033] In one embodiment, queue 216 (such as an egress queue, for example, corresponding to Figure 1 The egress queue 216 in the egress queue manager 132 is maintained by the egress queue manager 132 as a linked list of packets in the internal packet memory 124. In order to maintain the egress queue 216 as a linked list in the internal packet memory 124, the egress queue manager 132 is configured to maintain a plurality of indicators (e.g., pointers) stored in a local memory or register included in or coupled to the egress queue manager 132 to store indications of memory locations of elements (e.g., buffers) in the egress queue 216 in the internal packet memory 124. First, referring to Figure 2A , the egress queue manager 132 is configured to maintain a "Head.head" indicator (e.g., pointer) 218 ​​to indicate the memory location (e.g., buffer) at which the packet currently at the head of the egress queue 216 is stored in the internal packet memory 124. The egress queue manager 132 is also configured to maintain a "Tail.tail" indicator (e.g., pointer) 220 to indicate the memory location in the internal packet memory 124 at which the next packet to be queued in the egress queue 216 is to be placed.

[0034] In one embodiment, each element (e.g., buffer) in the internal packet memory 124 that stores packets in the egress queue 216 also stores an indication (e.g., pointer) to the element in which the next packet in the queue 216 is stored. When the egress queue 216 is scheduled for transmission from the network device 100, the egress queue manager 132 provides the memory controller 120 with the current value of the head.head indicator 218. In response, the memory controller 120 retrieves the packet from the head of the egress queue 216 from the memory location in the internal packet memory 124 indicated by the head.head indicator 216 and forwards the packet to the corresponding network port 108 for transmission of the packet. While retrieving the packet from the internal packet memory 124, the memory controller 120 retrieves an indicator of the memory location (e.g., buffer) storing the next packet in the egress queue 216, which is now at the head of the egress queue 216. The memory controller 120 provides an indicator of the memory location (e.g., buffer) storing the next packet in the egress queue 216 to the egress queue manager 132, and the egress queue manager 132 updates the value of the head.head indicator 220 to indicate the memory location of the packet currently at the head of the egress queue 216. On the other hand, in one embodiment, when a new packet is to be queued in the egress queue 216, the egress queue manager 132 provides the current value of the tail.tail indicator 220 to the memory controller 120, and the memory controller 120 places the packet in the internal packet memory 124 at the memory location indicated by the tail.tail indicator 220, wherein the current value of the tail.tail indicator 220 is stored in the element of the internal packet memory 124 storing the previous packet in the egress queue 216. In one embodiment, Figure 2A The egress queue 216 in is relatively short, and is maintained as a single linked list formed entirely in the internal packet memory 124.

[0035] Reference now Figure 2BIn one embodiment, as the egress queue 216 grows in the internal packet memory 124 and when congestion is detected in the egress queue 216, the memory controller 120 transfers one or more packets or a group of packets from the middle portion 216b of the egress queue 216 to the external packet memory 128, while the head portion 216a and the tail portion 216c of the egress queue 216 remain in the first packet memory 124. In one embodiment, for example, the egress queue monitor 134 is configured to detect congestion in the egress queue 216 when the length (e.g., fill level) of the queue 216 crosses a threshold. In one embodiment, when the egress queue monitor 134 detects congestion in the egress queue 216 in the internal packet memory 124, the egress queue manager 132 saves the current value of the tail.tail indicator 220 as the head.tail indicator 224. In one embodiment, the egress queue manager 132 is configured to continue queuing subsequent packets at the tail of the egress queue 216 in the internal packet memory 124. Additionally, in one embodiment, the memory controller 120 is configured to continue to retrieve packets from the head of the egress queue 216 and forward the packets to the corresponding network port 108 for transmission. In one embodiment, when a group of multiple packets (e.g., a group of four packets or another suitable number of packets) that can be stored in a single buffer in the external packet memory 128 is queued in the internal packet memory 124, the memory controller 120 transfers the group of packets from the internal packet memory 124 to the external packet memory 128 in a single transfer.

[0036] Continue to refer Figure 2B In one embodiment, the memory controller 120 transfers packets from the egress queue 216 starting with the packet at the memory location indicated by the Head.tail pointer 224. In one embodiment, as the memory controller 120 retrieves a packet from the memory location indicated by the Head.tail pointer 224, the memory controller 120 obtains a pointer to the next packet in the egress queue 216 and transfers the next packet in the egress queue 216 to the external packet memory 128, and so on. In one embodiment, new packets directed to the egress queue 216 continue to be added to the tail of the egress queue 216 in the internal packet memory 124. Also, in one embodiment, packets continue to be retrieved from the head of the egress queue 216 in the internal packet memory 124 for transmission of packets from the network device 100.

[0037] In one embodiment, packets or groups of packets transferred from the middle of the egress queue 216 to the external packet memory 128 are queued as a linked list in the external packet memory 128 in the order in which the packets or groups of packets were received at the external packet memory 128. For example, the queue manager associated with the external packet memory 128 is configured to maintain a "Middle.head" indicator (e.g., pointer) 226 to indicate that the packet currently at the head of the middle portion 216b of the egress queue 216 is stored at a memory location (e.g., buffer) in the external packet memory 128. The egress queue manager associated with the external packet memory 128 is also configured to maintain a "Middle.tail" indicator (e.g., pointer) 228 to indicate the memory location in the internal packet memory 124 where the next packet to be queued in the egress queue 216 is to be placed. In addition, in one embodiment, each element (e.g., buffer) in the external packet memory 128 that stores packets from the middle portion 216b of the egress queue 216 also stores an indication (e.g., pointer) of the element that stores the next packet from the middle portion 216b of the egress queue 216. In one embodiment, a queue manager associated with the external packet memory 128 is included internal to the packet processor 112. For example, in one embodiment, the external packet memory 128 is a simple word-based read / write memory that does not include queuing functionality. In another embodiment, the queue manager associated with the external packet memory 128 is external to the packet processor 110. For example, in one embodiment, the queue manager associated with the external packet memory 128 is included in an external device that houses the external packet memory 128.

[0038] Reference now Figure 2C, for example, the egress queue monitor 134 detects that the number of packets in the head portion of the queue in the internal memory 124 has dropped below a threshold. In response to detecting that the number of packets in the head portion of the egress queue 216 is below the threshold, the memory controller 120 requests to transfer one or more packets or a group of packets from the middle portion of the egress queue 216 to be transferred from the external packet memory 128 back to the internal packet memory 124. For example, the memory controller 120 generates a request signal indicating a specific egress queue 216 for which packets are to be transferred. In one embodiment, the request signal also indicates the number of packets from the specific egress queue 216 to be transferred from the external packet memory 128 to the internal packet memory 124. In another embodiment, the request signal indicates a buffer address that stores a group of packets at the head of the middle portion of the specific egress queue 216b in the external packet memory 128. Then, in one embodiment, packets are transferred starting with the packet or group of packets currently at the head of the middle portion 216b of the egress queue 216 (as indicated by the current value of the middle.head indicator 226) and continuing down the middle portion 216b until the last packet from the middle portion 216b is transferred to the internal packet memory 124. Subsequently, the memory controller 120 requests that additional packets or groups of packets be transferred from the middle portion 216b to the internal packet memory 124 as needed for transmission of packets from the network device 100. In one embodiment, in response to subsequent requests, the packet or group of packets at the head of the middle portion 216b in the external packet memory 128 is transferred back to the internal packet memory 124, and so on. Also, in one embodiment, the memory control device 120 continues to transfer additional packets or groups of packets from the queue 216 in the internal packet memory 124 to the middle portion of the queue 216b in the external packet memory 128.

[0039] Reference now Figure 2DIn one embodiment, packets transferred from the external packet memory 128 to the internal packet memory 124 are linked to the tail of the head portion 218 of the egress queue 216 in the internal packet memory 124. For example, in one embodiment, the egress manager 132 links packets transferred from the external packet memory to the internal packet memory 124 by linking the first packet transferred to the external packet memory 128 to the packet in the internal packet 124 indicated by the current value of the head.tail indicator 222, thereby updating the head.tail indicator 222, thereby linking the next packet transferred to the external packet memory to the packet in the internal packet 124 indicated by the current value of the head.tail indicator 222, and so on. Furthermore, in one embodiment, packets at the tail of the middle portion of the egress queue 216 are linked to the head of the tail portion of the egress queue 216 in the internal packet memory 124.

[0040] Figure 3 is a flow chart illustrating an exemplary method 300 for processing packets in a network device according to one embodiment. In one embodiment, Figure 1 The network device 100 implements the method 300 to process packets. For example, in one embodiment, the packet processor 112 of the network device 100 implements at least a portion of the method 300 to process packets. For ease of explanation, refer to Figure 1 The method 300 is described with reference to the network device 100. In other embodiments, the method 300 is implemented by other suitable network devices.

[0041] At block 302, a packet is received by a network device. In one embodiment, the packet is received via a network port 108 of the network device 100. In one embodiment, the packet received by the network device is provided to a packet processor (e.g., packet processor 112) for processing the packet.

[0042] At block 304, the packet is processed by a packet processor to at least determine one or more network ports among a plurality of network ports of the network device via which the packet is to be transmitted from the network device. In one embodiment, the packet is processed by a packet processor 112 (e.g., a forwarding engine 130) of the network device to determine one or more ports 108 via which the packet is to be transmitted.

[0043] In frame 306, in the first packet memory, the packet is buffered, for example because the port is not immediately available for the transmission of the packet. In one embodiment, in the first packet memory (for example, packet memory 124) inside the network device, the packet is buffered. In one embodiment, the first packet memory has a sufficiently high access bandwidth to support the total bandwidth supported by the network device. For example, in one embodiment, the first packet memory supports writing and retrieving packets at a speed corresponding to the line rate supported by the network device. In one embodiment, in the first packet memory, the packet is buffered in the outlet queues included in the multiple outlet queues formed in the first packet memory, and the corresponding outlet queues correspond to the corresponding ports of the network device and / or the corresponding priorities of the packets.

[0044] At block 308, congestion is detected in the queue in the first packet memory. In one embodiment, the egress queue monitor 134 detects congestion in the queue in the first packet memory. In one embodiment, congestion is detected in a specific egress queue formed in the first packet memory. For example, congestion is detected in the specific egress queue when the fill level or length of the specific egress queue exceeds a threshold. In other embodiments, congestion is detected in other suitable ways.

[0045] In block 310, in response to detecting congestion in a queue in a first packet memory, one or more groups of a plurality of packets from the first packet memory are transferred to a second packet memory in one or more corresponding transfers. In one embodiment, one or more groups of a plurality of packets are transferred to a packet memory (e.g., packet memory 128) that is outside a packet processor of a network device or is placed in a separate memory device outside the network device. The second packet memory is configured to buffer a portion of a service bandwidth supported by the network device. In one embodiment, the second packet memory does not have a sufficiently high access bandwidth to support the full bandwidth supported by the network device. For example, in one embodiment, the second packet memory does not support writing and retrieving packets at a rate corresponding to a line rate supported by the network device. In one embodiment, one or more packets are transferred from an egress queue detected to be congested in the first packet memory to a corresponding egress queue in the second packet memory. For example, in one embodiment, a middle portion of an egress queue is transferred from a first packet memory to a corresponding egress queue in a second packet memory, while a head portion and a tail portion of the egress queue are retained in the first packet memory.

[0046] At block 312, after transferring a group of the plurality of packets from the first packet memory to the second packet memory and before transmitting a packet in the group of the plurality of packets from the network device, request to transfer the group of the plurality of packets back to the first packet memory. For example, the memory controller 120 generates a request to transfer the group of the plurality of packets from the second packet memory and provides the request to the second packet memory to request to transfer the group of the plurality of packets from the second packet memory to the first packet memory. In one embodiment, in response to detecting that the length of the head of the egress queue queuing the group of the plurality of packets in the first packet memory is below a threshold, requesting to transfer the group of the plurality of packets from the second packet memory to the first packet memory. In one embodiment, when the group of the plurality of packets is transferred from the second packet memory to the first packet memory, the group of the plurality of packets is relinked with the tail of the head of the egress queue in the first packet memory.

[0047] At block 314, the packet transferred from the second packet memory back to the first packet memory is retrieved from the first packet memory. For example, the packet is retrieved from the first packet memory when the packet is at the head of an egress queue in the first packet memory and when the egress queue is scheduled for transmission from the network device 100. At block 318, the packet retrieved from the first packet memory is forwarded to one or more network ports determined for transmission of one or more packets from the network device.

[0048] In one embodiment, a method for processing packets in a network device includes: receiving, at a packet processor of the network device, a packet entering via a network port among a plurality of network ports of the network device; processing the packet with the packet processor to at least determine one or more network ports among the plurality of network ports through which the packet will be transmitted from the network device; buffering the packet in a first packet memory with the packet processor; detecting congestion in a queue in the first packet memory; in response to detecting congestion in the first packet memory, dynamically transferring one or more groups of corresponding plurality of packets from the first packet memory to a second packet memory in corresponding one or more transfers, the second packet memory being configured to buffer a portion of a service bandwidth supported by the network device; after transferring a group of the plurality of packets from the first packet memory to the second packet memory and before transmitting a packet in the group of the plurality of packets from the network device, requesting with the packet processor to transfer a group of the plurality of packets from the second packet memory back to the first packet memory; retrieving, with the packet processor, from the first packet memory the packet transferred from the second packet memory back to the first packet memory; and forwarding, with the packet processor, the packet retrieved from the first packet memory to one or more network ports determined for transmitting packets from the network device.

[0049] In other embodiments, the method includes any suitable combination of one or more of the following features.

[0050] Buffering the packet in the queue in the first packet memory includes buffering the packet in an egress queue formed in the first packet memory, the egress queue corresponding to a network port through which the packet is to be transmitted by the network device.

[0051] Detecting congestion in a queue in the first packet memory includes detecting congestion in a specific egress queue corresponding to a specific network port of the network device.

[0052] Transferring the one or more groups of the plurality of packets to the second packet memory includes transferring the one or more groups of the plurality of packets from the particular egress queue to the second packet memory.

[0053] Transferring one or more groups of the plurality of packets from the particular egress queue to the second packet memory includes transferring the one or more groups of the plurality of packets from a middle portion of the particular egress queue while at least a head portion of the particular egress queue remains in the first packet memory.

[0054] The method also includes queuing one or more additional packets at a tail portion of the particular egress queue stored in the first packet memory while one or more groups of the plurality of packets from the middle of the particular egress queue are stored in the second packet memory.

[0055] The method also includes: retrieving packets from a head portion of a specific egress queue in a first packet memory while one or more groups of the plurality of packets from the middle of the specific egress queue are stored in a second packet memory, and transmitting the packets retrieved from the head portion of the specific egress queue in the first packet memory from a specific network port of the network device.

[0056] Requesting to transfer packets from one or more groups of the plurality of packets comprises: in response to detecting that the length of a head portion of a specific egress queue stored in the first packet memory is below a threshold, requesting to transfer packets from a middle portion of a specific egress queue in the second packet memory to the first packet.

[0057] The method further includes linking the packet transferred from the second packet memory back to the first packet memory with the tail of the head portion of the specific egress queue in the first packet memory.

[0058] Buffering packets in a queue in a first packet memory includes buffering packets in a queue in a first memory device internal to a packet processor, and transferring one or more packets from the first packet memory to a second packet memory includes transferring one or more packets to a second memory device external to the packet processor.

[0059] The second packet memory device is coupled to the network device via a particular network port among a plurality of network ports of the network device.

[0060] Transferring one or more groups of the plurality of packets to the second memory device includes retrieving a group of the plurality of packets from the first memory device and forwarding the group of the plurality of packets to a particular network port for transmission as a single transfer to the second memory device via the network port.

[0061] The second packet memory is one of a plurality of second packet memories external to the packet processor, and the corresponding second packet memory is configured to cache a corresponding portion of a service bandwidth supported by the network device.

[0062] The method further includes selecting, with a packet processor, a specific second memory from among a plurality of second memories, and in corresponding transfers, transferring one or more groups of the plurality of packets to the specific second packet memory selected from among the plurality of second memories.

[0063] In another embodiment, a network device includes a plurality of network ports configured to be coupled to a plurality of network links and a packet processor coupled to the plurality of network ports. The packet processor is configured to: process packets received via a network port among the plurality of network ports of the network device to at least determine one or more network ports among the plurality of network ports through which the packet will be transmitted from the network device; buffer the packet in a queue in a first packet memory; detect congestion in the queue in the first packet memory; in response to detecting congestion in the first packet memory, dynamically transfer one or more groups of corresponding plurality of packets from the first packet memory to a second packet memory in corresponding one or more transfers, the second packet memory being configured to buffer a portion of a service bandwidth supported by the network device; after transferring a group of the plurality of packets from the first packet memory to the second packet memory and before transmitting a packet in the group of the plurality of packets from the network device, request a transfer of the group of the plurality of packets from the second packet memory back to the first packet memory; retrieve from the first packet memory the packet transferred from the second packet memory back to the first packet memory; and forward the packet retrieved from the first packet memory to one or more network ports determined for transmitting the packet from the network device.

[0064] In other embodiments, the network device includes any suitable combination of one or more of the following features.

[0065] The packet processor is configured to: buffer packets in an egress queue formed in a first packet memory, the egress queue corresponding to a network port through which the packets are to be transmitted by the network device, detect congestion in a queue in the first packet memory at least by detecting congestion in a specific egress queue corresponding to a specific network port of the network device, and transfer one or more groups of the plurality of packets to the second packet memory at least by transferring one or more groups of the plurality of packets from the specific egress queue to the second packet memory.

[0066] The packet processor is configured to transfer one or more groups of the plurality of packets from a middle portion of a particular egress queue while at least a head portion of the particular egress queue is retained in the first packet memory.

[0067] The packet processor is further configured to queue one or more additional packets at a tail portion of the particular egress queue stored in the first packet memory when one or more groups of a middle plurality of packets from the particular egress queue are stored in the second packet memory.

[0068] The packet processor is further configured to retrieve one or more packets from a head portion of a specific egress queue in the first packet memory and cause the one or more packets retrieved from the head portion of the specific egress queue in the first packet memory to be transmitted from a specific network port of the network device.

[0069] The packet processor is configured to request that packets from one or more groups of multiple packets be transferred from a middle portion of a specific egress queue of the second packet memory to the first packet memory in response to detecting that the length of a header portion of a specific egress queue stored in the first packet memory is below a threshold.

[0070] The packet processor is further configured to link the packet transferred from the second packet memory back to the first packet memory with a tail of a head portion of a specific egress queue in the first packet memory.

[0071] The first packet memory resides in a first memory device within the packet processor.

[0072] The second packet memory resides in a second memory device external to the packet processor.

[0073] The second packet memory device is coupled to the network device via a particular network port among a plurality of network ports of the network device.

[0074] The packet processor is configured to transfer a group of the plurality of packets to the second memory device by at least retrieving the group of the plurality of packets from the first memory device and forwarding the group of the plurality of packets to a specific network port for transmission of the group of the plurality of packets as a single transfer to the second memory device via the network port.

[0075] The second packet memory is one of a plurality of second packet memories external to the packet processor, and the corresponding second packet memory is configured to buffer a corresponding portion of a service bandwidth supported by the network device.

[0076] The packet processor is further configured to select a specific second memory from among the plurality of second memories and transfer one or more groups of the plurality of packets to the specific second packet memory selected from among the plurality of second memories.

[0077] At least some of the various blocks, operations, and techniques described above may be suitably implemented using dedicated hardware, such as one or more of discrete components, integrated circuits, application specific integrated circuits (ASICs), programmable logic devices (PLDs), processors that execute firmware instructions, processors that execute software instructions, or any combination thereof. When implemented using a processor that executes software or firmware instructions, the software or firmware instructions may be stored in any suitable computer-readable memory, such as on a disk, optical disk, or other storage medium. The software or firmware instructions may include machine-readable instructions that, when executed by one or more processors, cause the one or more processors to perform various actions.

[0078] Although the present invention has been described with reference to specific examples, this is only for illustration rather than limitation of the present invention, and changes, additions and / or deletions may be made to the disclosed embodiments without departing from the scope of the present invention.

Claims

1. A method for processing a packet in a network device, the method comprising: receiving, at a packet processor of the network device, a packet entering via a network port among a plurality of network ports of the network device, processing the packet with the packet processor to at least determine one or more network ports among the plurality of network ports through which the packet is to be transmitted from the network device, Buffering the packets in a first packet memory in a plurality of queues with the packet processor includes: buffering the packets in a first queue among the plurality of queues as a linked list, detecting congestion in a queue in said first packet memory, In response to detecting congestion in the first packet memory, dynamically transferring one or more groups of a corresponding plurality of packets from the first packet memory to a second packet memory in corresponding one or more transfers, the second packet memory being configured to buffer a portion of a traffic bandwidth supported by the network device, maintaining, at the packet processor, the linked list of packets in the first queue across the first packet memory and the second packet memory, after transferring a group of the plurality of packets in the first queue from the first packet memory to the second packet memory and before transmitting a packet in the group of the plurality of packets from the network device, requesting with the packet processor to transfer the group of the plurality of packets in the first queue from the second packet memory back to the first packet memory, retrieving, with said packet processor, from said first packet memory said packets transferred from said second packet memory back to said first packet memory; and The packet retrieved from the first packet memory is forwarded, with the packet processor, to the one or more network ports determined for transmission of the packet from the network device.

2. The method according to claim 1, wherein: Buffering the packets in the queue in the first packet memory includes: buffering the packets in an egress queue formed in the first packet memory, the egress queue corresponding to a network port through which the packets are to be transmitted by the network device, wherein buffering the packets in the first queue includes: buffering the packets in a specific egress queue corresponding to a specific network port of the network device, Detecting congestion in the queue in the first packet memory comprises: detecting congestion in the specific egress queue, and Transferring the one or more groups of the plurality of packets to the second packet memory includes transferring the one or more groups of the plurality of packets from the particular egress queue to the second packet memory.

3. The method of claim 2, wherein transferring one or more groups of the plurality of packets from the particular egress queue to the second packet memory comprises: One or more groups of the plurality of packets are transferred from a middle portion of the particular egress queue, while at least a head portion of the particular egress queue remains in the first packet memory.

4. The method according to claim 3, further comprising: One or more additional packets at a tail portion of the particular egress queue stored in the first packet memory are queued while one or more groups of the plurality of packets from the middle of the particular egress queue are stored in the second packet memory.

5. The method according to claim 3, further comprising: while one or more groups of the plurality of packets from the middle of the particular egress queue are stored in the second packet memory, retrieving a packet from the head portion of the particular egress queue in the first packet memory, and The packet retrieved from the header portion of the particular egress queue in the first packet memory is transmitted from the particular network port of the network device.

6. The method of claim 3, wherein requesting to transfer the packets within one or more groups of the plurality of packets comprises: In response to detecting that the length of the head portion of the specific egress queue stored in the first packet memory is below a threshold, requesting to transfer the packet from the middle portion of the specific egress queue in the second packet memory to the first packet.

7. The method according to claim 3, further comprising: The packet transferred back from the second packet memory to the first packet memory is linked to a tail of the head portion of the specific egress queue in the first packet memory.

8. The method according to claim 1, wherein: Buffering the packet in a queue in the first packet memory includes: buffering the packet in a first memory device within the packet processor, and Transferring the one or more packets from the first packet memory to the second packet memory includes transferring the one or more packets to a second memory device external to the packet processor.

9. The method according to claim 3, wherein: The second packet memory is coupled to the network device via a specific network port among the plurality of network ports of the network device, and Transferring one or more groups of the plurality of packets to the second packet memory comprises: retrieving a group of a plurality of packets from said first packet memory, and The one group of the plurality of packets is forwarded to the particular network port for transmission as a single transfer to the second packet memory via the network port.

10. The method of claim 1, wherein: The second packet memory is one of a plurality of second packet memories external to the packet processor, the corresponding second packet memory being configured to cache a corresponding portion of a service bandwidth supported by the network device, and The method further comprises: selecting, with the packet processor, a specific second packet memory from among the plurality of second packet memories, and In a corresponding transfer, one or more groups of the plurality of packets are transferred to the specific second packet memory selected from among the plurality of second packet memories.

11. A network device comprising: a plurality of network ports configured to be coupled to a plurality of network links; as well as a packet processor coupled to the plurality of network ports, the packet processor being configured to: processing packets received via a network port among the plurality of network ports of the network device to at least determine one or more network ports among the plurality of network ports through which the packets are to be transmitted from the network device, Buffering the packets in a first packet memory in a plurality of queues comprises: buffering the packets in a first queue among the plurality of queues as a linked list, detecting congestion in a queue in said first packet memory, In response to detecting congestion in the first packet memory, dynamically transferring one or more groups of a corresponding plurality of packets from the first packet memory to a second packet memory in corresponding one or more transfers, the second packet memory being configured to buffer a portion of a traffic bandwidth supported by the network device, maintaining the linked list of packets in the first queue across the first packet memory and the second packet memory, after transferring the one group of the plurality of packets in the first queue from the first packet memory to the second packet memory and before transmitting a packet in the one group of the plurality of packets in the first queue from the network device, requesting that the one group of the plurality of packets be transferred from the second packet memory back to the first packet memory, retrieving from said first packet memory said packets transferred from said second packet memory back to said first packet memory, and The packet retrieved from the first packet memory is forwarded to the one or more network ports determined for transmission of the packet from the network device.

12. The network device according to claim 11, wherein the packet processor is configured to: Buffering the packets in an egress queue formed in the first packet memory, the egress queue corresponding to a network port through which the packets are to be transmitted by a network device, wherein buffering the packets in the first queue in order comprises: Buffering packets in a specific egress queue corresponding to a specific network port, detecting congestion in said queue in said first packet memory at least by detecting congestion in said particular egress queue, and The one or more groups of the plurality of packets are transferred to the second packet memory at least by transferring the one or more groups of the plurality of packets from the particular egress queue to the second packet memory.

13. The network device of claim 12, wherein the packet processor is configured to transfer one or more groups of the plurality of packets from a middle portion of the particular egress queue while at least a head portion of the particular egress queue remains in the first packet memory.

14. A network device according to claim 13, wherein the packet processor is further configured to: when one or more groups of the plurality of packets from the middle of the specific egress queue are stored in the second packet memory, queue one or more additional packets at the tail of the tail portion of the specific egress queue stored in the first packet memory.

15. The network device according to claim 13, wherein the packet processor is further configured to: retrieving one or more packets from the head portion of the particular egress queue in the first packet memory, and The one or more packets retrieved from the head portion of the particular egress queue in the first packet memory are caused to be transmitted from the particular network port of the network device.

16. The network device of claim 13, wherein the packet processor is configured to request that packets from one or more groups of the plurality of packets be transferred from the middle portion of the specific egress queue in the second packet memory to the first packet in response to detecting that the length of the header portion of the specific egress queue stored in the first packet memory is lower than a threshold.

17. The network device of claim 13, wherein the packet processor is further configured to link the packet transferred from the second packet memory back to the first packet memory with a tail of the head portion of the specific egress queue in the first packet memory.

18. The network device according to claim 11, wherein: The first packet memory resides in a first memory device within the packet processor, and The second packet memory resides in a second memory device external to the packet processor.

19. The network device according to claim 11, wherein: The second packet memory is coupled to the network device via a specific network port among the plurality of network ports of the network device, and The packet processor is configured to transfer a group of a plurality of packets to the second packet memory at least by: retrieving the one group of the plurality of packets from the first packet memory, and The one group of the plurality of packets is forwarded to the particular network port for transmission as a single transfer to the second packet memory via the network port.

20. The network device according to claim 11, wherein: The second packet memory is one of a plurality of second packet memories external to the packet processor, the corresponding second packet memory being configured to buffer a corresponding portion of a service bandwidth supported by the network device, and The packet processor is further configured to: selecting a specific second packet memory from among the plurality of second packet memories, and One or more groups of the plurality of packets are transferred to the particular second packet memory selected from among the plurality of second packet memories.

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