A full life cycle aircraft multimodal on-orbit control system

Abstract

The application provides a full-life-cycle aircraft multi-mode on-orbit switching control system for traversing various mode control states involved in the whole service life of the aircraft. The on-orbit switching control system comprises an FPGA control unit, a DSP control unit, a first digital power supply unit, a second digital power supply unit, a third digital power supply unit, a fourth digital power supply unit, a fifth digital power supply unit, an analog power supply unit, external data acquisition, first internal data acquisition, second internal data acquisition, a decision unit and an execution unit. The application changes the traditional single working mode scheme after the aircraft takes off. The mode demand of the aircraft under various working conditions in the whole service life can be met.

Description

Technical Field

[0001] This application relates to the field of aircraft control technology, specifically to an on-orbit control system for a multi-modal aircraft throughout its entire life cycle. Background Technology

[0002] In response to the development needs of next-generation advanced aircraft, we will focus on solving major core technologies and bottlenecks that restrict the development of control systems, such as technologies and standards, testing, verification and evaluation. We will research a full-process multi-mode autonomous switching and integrated testing system suitable for next-generation aircraft to achieve an overall improvement in aircraft control capabilities and meet daily maintenance and usage requirements. Summary of the Invention

[0003] To address the aforementioned technical problems, this invention provides an on-orbit control system for multi-modal operation of a spacecraft throughout its entire lifecycle. The technical solution adopted by this invention is as follows:

[0004] An on-orbit switching control system for multi-modal operation of a full-lifecycle spacecraft, comprising an FPGA control unit, a DSP control unit, a first digital power supply unit, a second digital power supply unit, a third digital power supply unit, a fourth digital power supply unit, a fifth digital power supply unit, an analog power supply unit, an external data acquisition unit, a first internal data acquisition unit, a second internal data acquisition unit, a decision-making unit, and an execution unit;

[0005] The on-orbit switching control system provides 10 modes to meet the mode requirements under various operating conditions throughout the entire life cycle of the spacecraft.

[0006] Furthermore, the 10 modes include full-speed operation mode in flight state, full-speed operation mode in standby state, full-speed operation mode in parked state, standby mode for external sensors, standby mode for internal health acquisition, sleep mode for DSP, sleep mode for FPGA, standby mode for system, shallow sleep mode for system, and deep sleep mode for system.

[0007] Furthermore, the control method for the full-speed flight mode includes:

[0008] The FPGA control unit uses a 1.0V power supply for its core, high-speed read / write for DDR data, high-speed transmit / receive for GTX data, and high-speed acquisition for internal data.

[0009] The DSP control unit is powered by 1.2V for the core and is operating normally, while the peripherals are powered by 3.3V.

[0010] The first digital power supply unit, the second digital power supply unit, the third digital power supply unit, the fourth digital power supply unit, the fifth digital power supply unit, and the analog power supply unit are all powered normally.

[0011] External data acquisition, first internal data acquisition, and second internal data acquisition are normal acquisition processes.

[0012] The decision-making and execution units are functioning normally.

[0013] Furthermore, the control method for the full-speed operation mode in standby state includes:

[0014] The FPGA control unit uses a 1.0V power supply for its core, disables high-speed read / write for DDR data read / write processing, enables high-speed GTX data transmission and reception, and allows high-speed acquisition of internal data.

[0015] The DSP control unit is powered by 1.2V for the core and is operating normally, while the peripherals are powered by 3.3V.

[0016] The first digital power supply unit, the second digital power supply unit, the third digital power supply unit, the fourth digital power supply unit, the fifth digital power supply unit, and the analog power supply unit are all powered normally.

[0017] External data acquisition, first internal data acquisition, and second internal data acquisition are normal acquisition processes.

[0018] The decision-making and execution units are functioning normally.

[0019] Furthermore, the control method for the full-speed operation mode in the parking state includes:

[0020] The FPGA control unit uses a 1.0V power supply for its core, disables high-speed read / write for DDR data read / write processing, disables high-speed transmit / receive for GTX data, and enables high-speed data acquisition within the device.

[0021] The DSP control unit is powered by 1.2V for the core and is operating normally, while the peripherals are powered by 3.3V.

[0022] The first digital power supply unit, the second digital power supply unit, the third digital power supply unit, the fourth digital power supply unit, the fifth digital power supply unit, and the analog power supply unit are all powered normally.

[0023] External data acquisition, first internal data acquisition, and second internal data acquisition are normal acquisition processes.

[0024] The decision-making and execution units are functioning normally.

[0025] Furthermore, the control method for the standby mode of the external sensor includes:

[0026] The FPGA control unit uses a 1.0V power supply for its core, disables high-speed read / write for DDR data read / write processing, disables high-speed transmit / receive for GTX data, and enables high-speed data acquisition within the device.

[0027] The DSP control unit is powered by 1.2V for the core and is operating normally, while the peripherals are powered by 3.3V.

[0028] The first digital power supply unit, the second digital power supply unit, the third digital power supply unit, the fifth digital power supply unit, and the analog power supply unit are all powered normally.

[0029] The fourth digital power supply unit shuts off power to external sensor devices;

[0030] External data acquisition, first internal data acquisition, and second internal data acquisition are normal acquisition processes.

[0031] The decision-making and execution units are functioning normally.

[0032] Furthermore, the control method for the internal health acquisition standby mode includes:

[0033] The FPGA control unit uses a 1.0V power supply for its core, and features high-speed read / write disabled for DDR data read / write processing, high-speed transmit / receive disabled for GTX data high-speed transmission and reception, and high-speed acquisition disabled for internal device data.

[0034] The DSP control unit is powered by 1.2V for the core and is operating normally, while the peripherals are powered by 3.3V.

[0035] The first digital power supply unit, the second digital power supply unit, the third digital power supply unit, the fifth digital power supply unit, and the analog power supply unit are all powered normally.

[0036] The fourth digital power supply unit shuts off power to external sensor devices and also shuts off the internal temperature field;

[0037] External data acquisition, first internal data acquisition, and second internal data acquisition are normal acquisition processes.

[0038] The decision-making and execution units are functioning normally.

[0039] Furthermore, the control method for the DSP sleep mode includes:

[0040] The FPGA control unit uses a 1.0V power supply for its core, and features high-speed read / write disabled for DDR data read / write processing, high-speed transmit / receive disabled for GTX data high-speed transmission and reception, and high-speed acquisition disabled for internal device data.

[0041] The DSP control unit is powered by a 1.2V core and operates in system sleep mode. The peripheral devices are powered by FLASH and SDRAM operating at low speed.

[0042] The first digital power supply unit, the second digital power supply unit, the third digital power supply unit, the fifth digital power supply unit, and the analog power supply unit are all powered normally.

[0043] The fourth digital power supply unit shuts off power to external sensor devices and also shuts off the internal temperature field;

[0044] External data acquisition, first internal data acquisition, and second internal data acquisition are normal acquisition processes.

[0045] The decision-making and execution units are functioning normally.

[0046] Furthermore, the control method for the FPGA sleep mode includes:

[0047] The FPGA control unit uses a 1.0V power supply for its core, and features high-speed read / write disabled for DDR data read / write processing, high-speed transmit / receive disabled for GTX data high-speed transmission and reception, and high-speed acquisition disabled for internal device data.

[0048] The DSP control unit is powered by a core of 1.2V and operates in a system reset state. The peripheral power supply uses FLASH and SDRAM to stop working.

[0049] The first digital power supply unit, the fifth digital power supply unit, and the analog power supply unit are all powered normally.

[0050] The second digital power supply unit is for FPGA 1.5V power-off and FPGA 2.5V power-off;

[0051] The third digital power supply unit is powered normally, and the DSP 3.3V is powered off;

[0052] The fourth digital power supply unit shuts off power to external sensor devices and also shuts off the internal temperature field;

[0053] External data acquisition, first internal data acquisition, and second internal data acquisition are normal acquisition processes.

[0054] The decision-making and execution units are functioning normally.

[0055] Furthermore, the control method for the system standby mode includes:

[0056] The FPGA control unit uses a 0.9V power supply for its core, and features high-speed read / write disabled for DDR data read / write processing, high-speed transmit / receive disabled for GTX data high-speed transmission and reception, and high-speed acquisition disabled for internal device data.

[0057] The DSP control unit is powered by a core of 1.2V and operates in a system reset state. The peripheral power supply uses FLASH and SDRAM to stop working.

[0058] The first digital power supply unit is powered by 0.9V;

[0059] The second digital power supply unit is for FPGA 1.5V power-off and FPGA 2.5V power-off;

[0060] The third digital power supply unit is powered normally, and the DSP 3.3V is powered off;

[0061] The fourth digital power supply unit shuts off power to external sensor devices and also shuts off the internal temperature field;

[0062] The fifth digital power supply unit and the analog power supply unit are powered normally;

[0063] External data acquisition, first internal data acquisition, and second internal data acquisition are in standby mode.

[0064] The decision-making and execution units are functioning normally.

[0065] Furthermore, the control method for the system's shallow sleep mode includes:

[0066] The FPGA control unit uses a 0.9V power supply for its core, and features high-speed read / write disabled for DDR data read / write processing, high-speed transmit / receive disabled for GTX data high-speed transmission and reception, and high-speed acquisition disabled for internal device data.

[0067] The DSP control unit is powered by a core of 1.2V and operates in a system reset state. The peripheral power supply uses FLASH and SDRAM to stop working.

[0068] The first digital power supply unit is powered by 0.9V;

[0069] The second digital power supply unit is for FPGA 1.5V power-off and FPGA 2.5V power-off;

[0070] The third digital power supply unit is powered normally, and the DSP 3.3V is powered off;

[0071] The fourth digital power supply unit shuts off power to external sensor devices and also shuts off the internal temperature field;

[0072] The fifth digital power supply unit and the analog power supply unit are powered normally;

[0073] External data acquisition is in shutdown mode, while the first and second internal data acquisitions are in power-off mode.

[0074] The decision-making and execution units are functioning normally.

[0075] Furthermore, the control method for the system's deep sleep mode includes:

[0076] The FPGA control unit uses a 0.9V power supply for its core, and features high-speed read / write disabled for DDR data read / write processing, high-speed transmit / receive disabled for GTX data high-speed transmission and reception, and high-speed acquisition disabled for internal device data.

[0077] The DSP control unit is powered by a core of 1.2V and operates in a system reset state. The peripheral power supply uses FLASH and SDRAM to stop working.

[0078] The first digital power supply unit is powered by 0.9V;

[0079] The second digital power supply unit enables FPGA 1.5V power-off, FPGA 2.5V power-off, FPGA 1.8V power-off, and FPGA 3.3V power-off.

[0080] The third digital power supply unit cuts off DSP 3.3V, FPGA 0.75V, and FPGA 1.2V.

[0081] The fourth digital power supply unit shuts off power to external sensor devices and also shuts off the internal temperature field;

[0082] The fifth digital power supply unit is powered off, while the analog power supply unit is powered on normally.

[0083] External data acquisition is in shutdown mode, while the first and second internal data acquisitions are in power-off mode.

[0084] The decision-making and execution units have entered a dormant state.

[0085] The embodiments of this application achieve the following technical effects: This invention changes the traditional single-mode operation of aircraft after takeoff. It can meet the mode requirements of various operating conditions throughout the entire life cycle of the aircraft. Attached Figure Description

[0086] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0087] Figure 1 This is a schematic diagram illustrating the functional division of the system of the present invention;

[0088] Figure 2 A schematic diagram of the control method for full-speed operation in flight mode;

[0089] Figure 3 A schematic diagram of the control method for full-speed operation mode in standby mode;

[0090] Figure 4 A schematic diagram of the control method for full-speed operation mode when parked;

[0091] Figure 5 A schematic diagram illustrating the control method for the standby mode of an external sensor;

[0092] Figure 6 A schematic diagram illustrating the control method for standby mode of internal health data collection;

[0093] Figure 7 This is a schematic diagram illustrating the control method for DSP sleep mode.

[0094] Figure 8 This is a schematic diagram illustrating the control method for FPGA sleep mode.

[0095] Figure 9 This is a schematic diagram illustrating the control method for the system's standby mode.

[0096] Figure 10 This is a schematic diagram illustrating the control method for the system's shallow sleep mode.

[0097] Figure 11 This is a schematic diagram illustrating the control method for the system's deep sleep mode. Detailed Implementation

[0098] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0099] Figure 1 This is a functional diagram of the system of the present invention. The on-orbit switching control system includes an FPGA control unit, a DSP control unit, a first digital power supply unit, a second digital power supply unit, a third digital power supply unit, a fourth digital power supply unit, a fifth digital power supply unit, an analog power supply unit, an external data acquisition unit, a first internal data acquisition unit, a second internal data acquisition unit, a decision-making unit, and an execution unit.

[0100] The on-orbit switching control system provides 10 modes to meet the mode requirements under various operating conditions throughout the entire life cycle of the spacecraft.

[0101] The 10 modes include full-speed operation mode in flight state, full-speed operation mode in standby state, full-speed operation mode in parked state, standby mode for external sensors, standby mode for internal health acquisition, sleep mode for DSP, sleep mode for FPGA, standby mode for system, shallow sleep mode for system, and deep sleep mode for system.

[0102] Figure 2 This is a schematic diagram illustrating the control method for full-speed operation in flight mode. The control method for full-speed operation in flight mode includes:

[0103] The FPGA control unit uses a 1.0V power supply for its core, high-speed read / write for DDR data, high-speed transmit / receive for GTX data, and high-speed acquisition for internal data.

[0104] The DSP control unit is powered by 1.2V for the core and is operating normally, while the peripherals are powered by 3.3V.

[0105] The first digital power supply unit (digital power supply unit 1), the second digital power supply unit (digital power supply unit 2), the third digital power supply unit (digital power supply unit 3), the fourth digital power supply unit (digital power supply unit 4), the fifth digital power supply unit (digital power supply unit 5), and the analog power supply unit are powered normally;

[0106] External data acquisition, first internal data acquisition (internal data acquisition 1), and second internal data acquisition (internal data acquisition 2) are normal acquisitions;

[0107] The decision-making and execution units are functioning normally.

[0108] The control method for full-speed operation mode in flight status is shown in the table below.

[0109]

[0110]

[0111] Figure 3 This is a schematic diagram illustrating the control method for the full-speed operation mode in standby mode. The control method for the full-speed operation mode in standby mode includes:

[0112] The FPGA control unit uses a 1.0V power supply for its core, disables high-speed read / write for DDR data read / write processing, enables high-speed GTX data transmission and reception, and allows high-speed acquisition of internal data.

[0113] The DSP control unit is powered by 1.2V for the core and is operating normally, while the peripherals are powered by 3.3V.

[0114] The first digital power supply unit, the second digital power supply unit, the third digital power supply unit, the fourth digital power supply unit, the fifth digital power supply unit, and the analog power supply unit are all powered normally.

[0115] External data acquisition, first internal data acquisition, and second internal data acquisition are normal acquisition processes.

[0116] The decision-making and execution units are functioning normally.

[0117] The control method for the full-speed operation mode in standby mode is shown in the table below.

[0118]

[0119] Figure 4 This is a schematic diagram illustrating the control method for the full-speed operation mode while parked. The control method for the full-speed operation mode while parked includes:

[0120] The FPGA control unit uses a 1.0V power supply for its core, disables high-speed read / write for DDR data read / write processing, disables high-speed transmit / receive for GTX data, and enables high-speed data acquisition within the device.

[0121] The DSP control unit is powered by 1.2V for the core and is operating normally, while the peripherals are powered by 3.3V.

[0122] The first digital power supply unit, the second digital power supply unit, the third digital power supply unit, the fourth digital power supply unit, the fifth digital power supply unit, and the analog power supply unit are all powered normally.

[0123] External data acquisition, first internal data acquisition, and second internal data acquisition are normal acquisition processes.

[0124] The decision-making and execution units are functioning normally.

[0125] The control method for the full-speed operation mode while parked is shown in the table below.

[0126]

[0127] Figure 5 This is a schematic diagram illustrating the control method for the standby mode of an external sensor. The control method for the standby mode of the external sensor includes:

[0128] The FPGA control unit uses a 1.0V power supply for its core, disables high-speed read / write for DDR data read / write processing, disables high-speed transmit / receive for GTX data, and enables high-speed data acquisition within the device.

[0129] The DSP control unit is powered by 1.2V for the core and is operating normally, while the peripherals are powered by 3.3V.

[0130] The first digital power supply unit, the second digital power supply unit, the third digital power supply unit, the fifth digital power supply unit, and the analog power supply unit are all powered normally.

[0131] The fourth digital power supply unit shuts off power to external sensor devices;

[0132] External data acquisition, first internal data acquisition, and second internal data acquisition are normal acquisition processes.

[0133] The decision-making and execution units are functioning normally.

[0134] The control method for the standby mode of external sensors is shown in the table below.

[0135]

[0136] Figure 6 This is a schematic diagram illustrating the control method for the internal health data acquisition standby mode. The control method for the internal health data acquisition standby mode includes:

[0137] The FPGA control unit uses a 1.0V power supply for its core, and features high-speed read / write disabled for DDR data read / write processing, high-speed transmit / receive disabled for GTX data high-speed transmission and reception, and high-speed acquisition disabled for internal device data.

[0138] The DSP control unit is powered by 1.2V for the core and is operating normally, while the peripherals are powered by 3.3V.

[0139] The first digital power supply unit, the second digital power supply unit, the third digital power supply unit, the fifth digital power supply unit, and the analog power supply unit are all powered normally.

[0140] The fourth digital power supply unit shuts off power to external sensor devices and also shuts off the internal temperature field;

[0141] External data acquisition, first internal data acquisition, and second internal data acquisition are normal acquisition processes.

[0142] The decision-making and execution units are functioning normally.

[0143] The control method for the internal health data collection standby mode is shown in the table below.

[0144]

[0145] Figure 7 This is a schematic diagram illustrating the control method for DSP sleep mode. The control method for DSP sleep mode includes:

[0146] The FPGA control unit uses a 1.0V power supply for its core, and features high-speed read / write disabled for DDR data read / write processing, high-speed transmit / receive disabled for GTX data high-speed transmission and reception, and high-speed acquisition disabled for internal device data.

[0147] The DSP control unit is powered by a 1.2V core and operates in system sleep mode. The peripheral devices are powered by FLASH and SDRAM operating at low speed.

[0148] The first digital power supply unit, the second digital power supply unit, the third digital power supply unit, the fifth digital power supply unit, and the analog power supply unit are all powered normally.

[0149] The fourth digital power supply unit shuts off power to external sensor devices and also shuts off the internal temperature field;

[0150] External data acquisition, first internal data acquisition, and second internal data acquisition are normal acquisition processes.

[0151] The decision-making and execution units are functioning normally.

[0152] The control method for DSP sleep mode is shown in the table below.

[0153]

[0154] Figure 8 This is a schematic diagram illustrating the control method for FPGA sleep mode. The control method for FPGA sleep mode includes:

[0155] The FPGA control unit uses a 1.0V power supply for its core, and features high-speed read / write disabled for DDR data read / write processing, high-speed transmit / receive disabled for GTX data high-speed transmission and reception, and high-speed acquisition disabled for internal device data.

[0156] The DSP control unit is powered by a core of 1.2V and operates in a system reset state. The peripheral power supply uses FLASH and SDRAM to stop working.

[0157] The first digital power supply unit, the fifth digital power supply unit, and the analog power supply unit are all powered normally.

[0158] The second digital power supply unit is for FPGA 1.5V power-off and FPGA 2.5V power-off;

[0159] The third digital power supply unit is powered normally, and the DSP 3.3V is powered off;

[0160] The fourth digital power supply unit shuts off power to external sensor devices and also shuts off the internal temperature field;

[0161] External data acquisition, first internal data acquisition, and second internal data acquisition are normal acquisition processes.

[0162] The decision-making and execution units are functioning normally.

[0163] The control method for FPGA sleep mode is shown in the table below.

[0164]

[0165]

[0166] Figure 9 This is a schematic diagram of the control method for the system standby mode. The control method for the system standby mode includes:

[0167] The FPGA control unit uses a 0.9V power supply for its core, and features high-speed read / write disabled for DDR data read / write processing, high-speed transmit / receive disabled for GTX data high-speed transmission and reception, and high-speed acquisition disabled for internal device data.

[0168] The DSP control unit is powered by a core of 1.2V and operates in a system reset state. The peripheral power supply uses FLASH and SDRAM to stop working.

[0169] The first digital power supply unit is powered by 0.9V;

[0170] The second digital power supply unit is for FPGA 1.5V power-off and FPGA 2.5V power-off;

[0171] The third digital power supply unit is powered normally, and the DSP 3.3V is powered off;

[0172] The fourth digital power supply unit shuts off power to external sensor devices and also shuts off the internal temperature field;

[0173] The fifth digital power supply unit and the analog power supply unit are powered normally;

[0174] External data acquisition, first internal data acquisition, and second internal data acquisition are in standby mode.

[0175] The decision-making and execution units are functioning normally.

[0176] The control methods for the system standby mode are shown in the table below.

[0177]

[0178]

[0179] Figure 10 This is a schematic diagram illustrating the control method for the system's shallow sleep mode. The control method for the system's shallow sleep mode includes:

[0180] The FPGA control unit uses a 0.9V power supply for its core, and features high-speed read / write disabled for DDR data read / write processing, high-speed transmit / receive disabled for GTX data high-speed transmission and reception, and high-speed acquisition disabled for internal device data.

[0181] The DSP control unit is powered by a core of 1.2V and operates in a system reset state. The peripheral power supply uses FLASH and SDRAM to stop working.

[0182] The first digital power supply unit is powered by 0.9V;

[0183] The second digital power supply unit is for FPGA 1.5V power-off and FPGA 2.5V power-off;

[0184] The third digital power supply unit is powered normally, and the DSP 3.3V is powered off;

[0185] The fourth digital power supply unit shuts off power to external sensor devices and also shuts off the internal temperature field;

[0186] The fifth digital power supply unit and the analog power supply unit are powered normally;

[0187] External data acquisition is in shutdown mode, while the first and second internal data acquisitions are in power-off mode.

[0188] The decision-making and execution units are functioning normally.

[0189] The control method for the system's shallow sleep mode is shown in the table below.

[0190]

[0191] Figure 11 This is a schematic diagram illustrating the control method for the system's deep sleep mode. The control method for the system's deep sleep mode includes:

[0192] The FPGA control unit uses a 0.9V power supply for its core, and features high-speed read / write disabled for DDR data read / write processing, high-speed transmit / receive disabled for GTX data high-speed transmission and reception, and high-speed acquisition disabled for internal device data.

[0193] The DSP control unit is powered by a core of 1.2V and operates in a system reset state. The peripheral power supply uses FLASH and SDRAM to stop working.

[0194] The first digital power supply unit is powered by 0.9V;

[0195] The second digital power supply unit enables FPGA 1.5V power-off, FPGA 2.5V power-off, FPGA 1.8V power-off, and FPGA 3.3V power-off.

[0196] The third digital power supply unit cuts off DSP 3.3V, FPGA 0.75V, and FPGA 1.2V.

[0197] The fourth digital power supply unit shuts off power to external sensor devices and also shuts off the internal temperature field;

[0198] The fifth digital power supply unit is powered off, while the analog power supply unit is powered on normally.

[0199] External data acquisition is in shutdown mode, while the first and second internal data acquisitions are in power-off mode.

[0200] The decision-making and execution units have entered a dormant state.

[0201] The control methods for the system's deep sleep mode are shown in the table below.

[0202]

[0203]

[0204] The functions described above in this application can be performed at least in part by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that can be used include: field programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload programmable logic devices (CPLDs), and so on.

[0205] Furthermore, although the operations are described in a specific order, this should be understood as requiring that such operations be performed in the specific order shown or in sequential order, or requiring that all illustrated operations be performed to achieve the desired result. In certain environments, multitasking and parallel processing may be advantageous. Similarly, although several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of this disclosure. Certain features described in the context of individual embodiments may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may also be implemented individually or in any suitable sub-combination in multiple implementations.

[0206] Although the subject matter has been described using language specific to structural features and / or device logic, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are merely illustrative examples of implementing the claims.

Claims

1. A full life cycle aircraft multimodal on-orbit handoff control system, comprising: The on-orbit switching control system comprises an FPGA control unit, a DSP control unit, a first digital power supply unit, a second digital power supply unit, a third digital power supply unit, a fourth digital power supply unit, a fifth digital power supply unit, an analog power supply unit, external data acquisition, first internal data acquisition, second internal data acquisition, a decision unit and an execution unit; The on-orbit switching control system meets the mode requirements of the aircraft in various working conditions in the whole life cycle through 10 modes; The 10 modes comprise a flight state full-speed running mode, a standby state full-speed running mode, a parking state full-speed running mode, an external sensor standby mode, an internal health acquisition standby mode, a DSP sleep mode, an FPGA sleep mode, a system standby mode, a system light sleep mode and a system deep sleep mode.

2. The system of claim 1, wherein, The control mode of the flight state full-speed running mode comprises: The FPGA control unit adopts 1.0V power supply for the kernel, high-speed reading and writing for DDR data reading and writing processing, high-speed transceiving for GTX data high-speed transceiving, and high-speed acquisition for internal data high-speed acquisition of the device; The DSP control unit adopts 1.2V power supply for the kernel and 3.3V power supply for peripheral devices; The first digital power supply unit, the second digital power supply unit, the third digital power supply unit, the fourth digital power supply unit, the fifth digital power supply unit and the analog power supply unit are normally powered; The external data acquisition, the first internal data acquisition and the second internal data acquisition are normally acquired, and the decision unit and the execution unit are normally worked.

3. The system of claim 1, wherein, The control mode of the standby state full-speed running mode comprises: The FPGA control unit adopts 1.0V power supply for the kernel, high-speed reading and writing for DDR data reading and writing processing, high-speed transceiving for GTX data high-speed transceiving, and high-speed acquisition for internal data high-speed acquisition of the device; The DSP control unit adopts 1.2V power supply for the kernel and 3.3V power supply for peripheral devices; The first digital power supply unit, the second digital power supply unit, the third digital power supply unit, the fourth digital power supply unit, the fifth digital power supply unit and the analog power supply unit are normally powered; The external data acquisition, the first internal data acquisition and the second internal data acquisition are normally acquired, and the decision unit and the execution unit are normally worked.

4. The system of claim 1, wherein, The control mode of the parking state full-speed running mode comprises: The FPGA control unit adopts 1.0V power supply for the kernel, high-speed reading and writing for DDR data reading and writing processing, high-speed transceiving for GTX data high-speed transceiving, and high-speed acquisition for internal data high-speed acquisition of the device; The DSP control unit adopts 1.2V power supply for the kernel and 3.3V power supply for peripheral devices; The first digital power supply unit, the second digital power supply unit, the third digital power supply unit, the fourth digital power supply unit, the fifth digital power supply unit and the analog power supply unit are normally powered; The external data acquisition, the first internal data acquisition and the second internal data acquisition are normally acquired, and the decision unit and the execution unit are normally worked.

5. The system of claim 1, wherein, The control mode of the external sensor standby mode comprises: The FPGA control unit, the kernel adopts 1.0V power supply, the high-speed read-write of DDR data read-write processing adopts closed, the high-speed transceiver of GTX data high-speed transceiver adopts closed, the high-speed collection of equipment internal data is high-speed collection closed; The DSP control unit, the kernel power supply is 1.2V, the running state is normal, the peripheral power supply adopts 3.3V; The first digital power supply unit, the second digital power supply unit, the third digital power supply unit, the fifth digital power supply unit, the analog power supply unit are normal power supply; The fourth digital power supply unit is closed for external sensor equipment power supply, and the internal temperature field is closed; the external data collection, the first internal data collection, the second internal data collection are normal collection; the decision unit and the execution unit are normal work. The control mode of the internal health collection standby mode includes:

6. The system of claim 1, wherein, The FPGA control unit, the kernel adopts 1.0V power supply, the high-speed read-write of DDR data read-write processing adopts closed, the high-speed transceiver of GTX data high-speed transceiver adopts closed, the high-speed collection of equipment internal data is high-speed collection closed; The DSP control unit, the kernel power supply is 1.2V, the running state is normal, the peripheral power supply adopts 3.3V; The first digital power supply unit, the second digital power supply unit, the third digital power supply unit, the fifth digital power supply unit, the analog power supply unit are normal power supply; The fourth digital power supply unit is closed for external sensor equipment power supply, and the internal temperature field is closed; the external data collection, the first internal data collection, the second internal data collection are normal collection; the decision unit and the execution unit are normal work. The control mode of the DSP sleep mode includes:

7. The system of claim 1, wherein, The FPGA control unit, the kernel adopts 1.0V power supply, the high-speed read-write of DDR data read-write processing adopts closed, the high-speed transceiver of GTX data high-speed transceiver adopts closed, the high-speed collection of equipment internal data is high-speed collection closed; The DSP control unit, the kernel power supply is 1.2V, the running state is system sleep, the peripheral power supply adopts FLASH, SDRAM low-speed work; The first digital power supply unit, the second digital power supply unit, the third digital power supply unit, the fifth digital power supply unit, the analog power supply unit are normal power supply; The fourth digital power supply unit is closed for external sensor equipment power supply, and the internal temperature field is closed; the external data collection, the first internal data collection, the second internal data collection are normal collection; the decision unit and the execution unit are normal work. The control mode of the FPGA sleep mode includes:

8. The system of claim 1, wherein, The FPGA control unit, the kernel adopts 1.0V power supply, the high-speed read-write of DDR data read-write processing adopts closed, the high-speed transceiver of GTX data high-speed transceiver adopts closed, the high-speed collection of equipment internal data is high-speed collection closed; The DSP control unit, the kernel power supply is 1.2V, the running state is system reset, the peripheral power supply adopts FLASH, SDRAM stop working; The first digital power supply unit, the fifth digital power supply unit, the analog power supply unit are normal power supply; The second digital power supply unit is FPGA 1.5V power failure, FPGA 2.5V power failure; The third digital power supply unit is normal power supply, and DSP 3.3V power failure; ​ The fourth digital power supply unit is powered off for the external sensor device, and the internal temperature field is closed; the external data acquisition, the first internal data acquisition, and the second internal data acquisition are normally acquired; the decision unit and the execution unit are normally worked.

9. The system of claim 1, wherein, The control mode of the system standby mode comprises: The FPGA control unit, the kernel adopts 0.9V power supply, the DDR data read-write processing adopts high-speed read-write closing, the GTX data high-speed transceiver adopts high-speed transceiver closing, and the device internal data high-speed acquisition is high-speed acquisition closing; The DSP control unit, the kernel power supply is 1.2V, the running state is system reset, and the peripheral power supply adopts FLASH and SDRAM stop working; The first digital power supply unit is 0.9V power supply; The second digital power supply unit is FPGA1.5V power-off, FPGA2.5V power-off; The third digital power supply unit is normally powered, and DSP3.3V is powered off; The fourth digital power supply unit is powered off for the external sensor device, and the internal temperature field is closed; The fifth digital power supply unit and the analog power supply unit are normally powered; The external data acquisition, the first internal data acquisition, and the second internal data acquisition are in standby mode; the decision unit and the execution unit are normally worked.

10. The system of claim 1, wherein, The control mode of the system shallow sleep mode comprises: The FPGA control unit, the kernel adopts 0.9V power supply, the DDR data read-write processing adopts high-speed read-write closing, the GTX data high-speed transceiver adopts high-speed transceiver closing, and the device internal data high-speed acquisition is high-speed acquisition closing; The DSP control unit, the kernel power supply is 1.2V, the running state is system reset, and the peripheral power supply adopts FLASH and SDRAM stop working; The first digital power supply unit is 0.9V power supply; The second digital power supply unit is FPGA1.5V power-off, FPGA2.5V power-off; The third digital power supply unit is normally powered, and DSP3.3V is powered off; The fourth digital power supply unit is powered off for the external sensor device, and the internal temperature field is closed; The fifth digital power supply unit and the analog power supply unit are normally powered; The external data acquisition is off, the first internal data acquisition and the second internal data acquisition are power-off mode; The decision unit and the execution unit are normally worked.

11. The system of claim 1, wherein, The control mode of the system deep sleep mode comprises: The FPGA control unit, the kernel adopts 0.9V power supply, the DDR data read-write processing adopts high-speed read-write closing, the GTX data high-speed transceiver adopts high-speed transceiver closing, and the device internal data high-speed acquisition is high-speed acquisition closing; The DSP control unit, the kernel power supply is 1.2V, the running state is system reset, and the peripheral power supply adopts FLASH and SDRAM stop working; The first digital power supply unit is 0.9V power supply; The second digital power supply unit is FPGA1.5V power-off, FPGA2.5V power-off, FPGA1.8V power-off, FPGA3.3V power-off; The third digital power supply unit is DSP3.3V power-off, FPGA0.75V power-off, FPGA1.2V power-off; The fourth digital power supply unit is powered off for the external sensor device, and the internal temperature field is closed; The fifth digital power supply unit is for closing power supply, and the analog power supply unit is for normal power supply; The external data acquisition is in the off mode, the first internal data acquisition and the second internal data acquisition are in the power-off mode; The decision unit and the execution unit enter the sleep work.

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