Threshold-crossing time discrimination circuit for low power supply voltage

Abstract

The present invention provides a threshold-crossing time discrimination circuit suitable for low power supply voltages. The circuit comprises a main feedback network and a threshold feedback network, each with a fully differential structure. The main feedback network comprises a differential pair of N-type MOS transistors M1a and M1b, current sources I1a and I1b, a load feedback network, a first feedback network, and a transconductance amplifier Gm. The threshold feedback network comprises a differential pair of N-type MOS transistors M2a and M2b, current sources I2a and I2b, and a second feedback network. The present invention specifically addresses the shortcomings of common-mode feedback and threshold setting circuits in conventional threshold-crossing time discrimination circuit systems. In particular, the present invention's most significant advantage is its effective resolution of the conflict between picosecond-level high time resolution and low power supply voltage.

Description

Technical Field

[0001] The present invention belongs to the technical field of high-precision time measurement integrated circuits, and in particular relates to a threshold-crossing time discrimination circuit suitable for low power supply voltage. Background Art

[0002] Applications such as 3D recognition, automotive LiDAR, nuclear medicine imaging, and particle physics require not only charge measurement but also increasingly stringent time-resolution performance from detector systems. Current time-resolution requirements have reached picoseconds. While conventional detector readout integrated circuits (ICs) based on time-over-threshold (ToT) technology can simultaneously measure both charge and time, they are increasingly unable to meet the demand for higher time-resolution performance. As feature sizes in bulk complementary metal-oxide-semiconductor (CMOS) processes decrease, device intrinsic speeds increase, significantly improving time-resolution performance. However, this also reduces supply voltages, posing significant challenges to the design of readout ICs.

[0003] Existing high time resolution cross-threshold time discrimination circuit systems are generally based on transimpedance amplifiers. Figure 1 The architecture of a differential transimpedance amplifier system is presented. This fully differential system uses the detector's output differential currents (Iinp and Iinn) as input signals and differential voltages (Voutp and Voutn) as output signals. The differential threshold voltages (Vthp and Vthn) are externally input. The system consists of four components: a transimpedance amplifier circuit, a high-speed comparator circuit, a low-voltage differential signaling (LVDS) circuit, and a common-mode feedback and threshold setting circuit. The transimpedance amplifier converts the detector's output differential current (i.e., Iinp and Iinn) into a differential voltage; the high-speed comparator performs open-loop amplification on the differential weak voltage output by the transimpedance amplifier; the LVDS circuit converts the large-swing differential voltage (V2p and V2n) output by the high-speed comparator into low-voltage differential signals (Voutp and Voutn); the common-mode feedback and threshold setting circuit converts the differential voltage (V1p and V1n) and differential threshold voltage (Vthp and Vthn) output by the high-speed comparator into differential currents (Ifbp and Ifbn) that are fed into the transimpedance amplifier, forming a negative feedback structure in the system to stabilize the system's common-mode voltage and implement a threshold adjustment function based on the time-over-threshold (ToT) discrimination method.

[0004] The traditional implementation of common mode feedback and threshold setting circuit in the threshold time discrimination circuit system is as follows Figure 2As shown, two N-type MOS transistor differential pairs, M1a and M1b, receive differential voltages V1p and V1n from a high-speed comparator. A load feedback network extracts the common-mode signal and converts the differential current output by the M1 differential pair into a differential voltage. A transconductance amplifier (Gm) converts this differential voltage into a differential current. Two N-type MOS transistor differential pairs, M2a and M2b, receive external differential threshold voltages Vthp and Vthn. These are converted into differential currents by the M1a and M1b differential pair, the load feedback network, and the transconductance amplifier (Gm). The first and second feedback networks improve system linearity and dynamic range. Current sources I1a and I1b provide bias currents for the two branches. The differential currents Ifbp and Ifbn output by the transconductance amplifier (Gm) are the product of the differential voltages V1p and V1n and the differential threshold voltages Vthp and Vthn. The circuit is characterized in that the tube M1 and the tube M2 are cascaded, that is, the drain end of the tube M2 is connected to the source end of the tube M1.

[0005] Traditional common-mode feedback and threshold setting circuits have three drawbacks: First, the cascade connection of transistors M1 and M2 consumes voltage margin, making the circuit inoperable in low-supply voltage applications. In particular, when system time resolution is required at the picosecond level, smaller feature-size processes are required to reduce parasitics and increase the device's intrinsic speed. As feature sizes decrease, the supply voltage also decreases. However, when the supply voltage drops below 1.2V, the circuit becomes inoperable. In other words, traditional common-mode feedback and threshold setting circuits face an irreconcilable conflict between high time resolution and low supply voltage. Second, transistors M1 and M2 share a current branch, which limits the common-mode voltages of V1 and Vth. Third, when transistors M1 and M2 are cascaded, transistor M2 affects the effectiveness of the first feedback network. Summary of the Invention

[0006] In order to utilize the high-speed characteristics of advanced processes (i.e., small feature size processes) while alleviating the limitations of low power supply voltages, the present invention provides a threshold crossing time discrimination circuit suitable for low power supply voltages, which specifically addresses the shortcomings of common-mode feedback and threshold setting circuits in traditional threshold crossing time discrimination circuit systems.

[0007] In order to achieve the above object, the technical solution adopted by the present invention is:

[0008] A threshold-crossing time discrimination circuit suitable for low power supply voltage is a common-mode feedback and threshold setting circuit, comprising a main feedback network and a threshold feedback network, and having a fully differential structure; wherein the main feedback network is composed of an N-type MOS transistor differential pair M1a and M1b, a current source I1a and a current source I1b, a load feedback network, a first feedback network, and a transconductance amplifier Gm; the gates of the N-type MOS transistor differential pair M1a and M1b are connected to the input differential voltages V1p and V1n, and their drains are connected to the load feedback network and The transconductance amplifier Gm is connected to the gates of the N-type MOS transistor differential pair M2a and M2b, the current sources I2a and I2b, and the second feedback network, and the drains are connected to the load feedback network and the transconductance amplifier Gm.

[0009] Furthermore, the current source I1a, the current source I1b, the current source I2a, and the current source I2b are all implemented by N-type MOS transistors.

[0010] Furthermore, a single-ended form is adopted, including a main feedback network and a threshold feedback network, wherein the main feedback network is composed of an N-type MOS transistor M1, a current source I1, a load feedback network, a first feedback network, and a transconductance amplifier Gm; the gate of the N-type MOS transistor M1 is connected to the differential input voltage V1, its drain is connected to the load feedback network and the transconductance amplifier Gm, and its source is connected to the current source I1 and the first feedback network; the threshold feedback network is composed of an N-type MOS transistor M2, a current source I2, and a second feedback network; the gate of the N-type MOS transistor M2 is connected to the single-ended threshold voltage Vth, its source is connected to the current source I2 and the second feedback network, and its drain is connected to the load feedback network and the transconductance amplifier Gm.

[0011] Furthermore, the main feedback network converts the differential input voltage V1 output by the high-speed comparator into a single-ended current Ifb1, which is fed into the transimpedance amplifier to form a common-mode negative feedback closed-loop structure; the threshold feedback network converts the single-ended threshold voltage Vth into a single-ended current Ifb2, which is fed into the transimpedance amplifier to form a common-mode negative feedback closed-loop structure; the output single-ended current Ifb of the transconductance amplifier Gm is the superposition of Ifb1 and Ifb2, that is, Ifb=Ifb1+Ifb2.

[0012] Furthermore, the N-type MOS transistor differential pair M1a and M1b is replaced by the P-type MOS transistor differential pair M1c and M1d, and the N-type MOS transistor differential pair M2a and M2b is replaced by the P-type MOS transistor differential pair M2c and M2d. Beneficial effects

[0013] The present invention specifically addresses the following three shortcomings of the common-mode feedback and threshold setting circuits in conventional threshold-crossing time discrimination circuit systems. In particular, the most significant advantage of the present invention is the effective resolution of the contradiction between picosecond-level high time resolution performance and low power supply voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 A differential transimpedance amplifier system architecture in the prior art;

[0015] Figure 2 It is a traditional common-mode feedback and threshold setting circuit;

[0016] Figure 3 A differential common-mode feedback and threshold setting circuit suitable for low power supply voltage according to the present invention;

[0017] Figure 4 The present invention is a single-ended common-mode feedback and threshold setting circuit suitable for low power supply voltage;

[0018] Figure 5 It is a single-ended transimpedance amplifier system architecture;

[0019] Figure 6 This is a differential common-mode feedback and threshold setting circuit (mainly based on P-type MOS transistors) suitable for low power supply voltage. DETAILED DESCRIPTION

[0020] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely for the purpose of explaining the present invention and are not intended to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.

[0021] like Figure 3As shown, the common-mode feedback and threshold setting circuit for a low-power supply voltage threshold crossing time discrimination circuit of the present invention includes a main feedback network and a threshold feedback network, and is a fully differential structure. The main feedback network is composed of an N-type MOS transistor differential pair M1a and M1b, current sources I1a and I1b, a load feedback network, a first feedback network, and a transconductance amplifier Gm. The gates of the N-type MOS differential pair M1a and M1b are connected to the input differential voltages V1p and V1n, their drains are connected to the load feedback network 1 and the transconductance amplifier Gm, and their sources are connected to the current sources I1a, I1b, and the first feedback network. The threshold feedback network is composed of an N-type MOS transistor differential pair M2a and M2b, current sources I2a and I2b, and a second feedback network. The gates of the N-type MOS transistor differential pair M2a and M2b are connected to the differential threshold voltages Vthp and Vthn, their sources are connected to the current sources I2a and I2b and the second feedback network, and their drains are connected to the load feedback network 1 and the transconductance amplifier Gm.

[0022] The main feedback network will pass the threshold time discrimination circuit (such as Figure 1 (As shown in Figure 2), the differential voltages V1p and V1n output by the high-speed comparator are converted into differential currents Ifb1p and Ifb1n, which are then fed into the transimpedance amplifier Gm, forming a common-mode negative feedback closed loop. The threshold feedback network converts the differential threshold voltages Vthp and Vthn into differential currents Ifb2p and Ifb2n, which are then fed into the transimpedance amplifier Gm, forming a common-mode negative feedback closed loop. As a result, the differential output currents Ifbp and Ifbn of the transconductance amplifier Gm are in phase with each other: Ifbp = Ifb1p + Ifb2p, and Ifbn = Ifb1n + Ifb2n.

[0023] The branch containing the N-type MOS transistor differential pair M2a and M2b is completely separated from the branch containing the N-type MOS transistor differential pair M1a and M1b. The drain terminals of the N-type MOS transistor differential pair M2a and M2b are connected to the drain terminals of the N-type MOS transistor differential pair M1a and M1b. A pair of current sources I2a and I2b are simultaneously provided to provide bias currents for the separated branches of the N-type MOS transistor differential pair M2a and M2b. Specifically, the source terminals of the N-type MOS transistor differential pair M1a and M1b are connected to the current sources I1a and I1b, respectively, while the source terminals of the N-type MOS transistor differential pair M2a and M2b are connected to the current sources I2a and I2b, respectively.

[0024] In the above circuit, each current source is generally implemented using an N-type MOS tube.

[0025] The above technical solution can be extended to single-ended form, such as Figure 4As shown, the circuit includes a main feedback network and a threshold feedback network, and is a single-ended structure. The main feedback network consists of an N-type MOS transistor M1, a current source I1, a load feedback network, a first feedback network, and a transconductance amplifier Gm. The gate of the N-type MOS transistor M1 is connected to the differential input voltage V1, its drain is connected to the load feedback network and the transconductance amplifier Gm, and its source is connected to the current source I1 and the first feedback network. The threshold feedback network consists of an N-type MOS transistor M2, a current source I2, and a second feedback network. The gate of the N-type MOS transistor M2 is connected to the single-ended threshold voltage Vth, its source is connected to the current source I2 and the second feedback network, and its drain is connected to the load feedback network and the transconductance amplifier Gm.

[0026] like Figure 5 As shown in Figure 1, the main feedback network converts the differential input voltage V1 output by the high-speed comparator into a single-ended current Ifb1, which is fed into the transimpedance amplifier (TA), forming a common-mode negative feedback closed-loop structure. The threshold feedback network converts the single-ended threshold voltage Vth into a single-ended current Ifb2, which is fed into the TIA, forming a common-mode negative feedback closed-loop structure. Consequently, the single-ended current Ifb output by the transconductance amplifier Gm is the sum of Ifb1 and Ifb2, i.e., Ifb = Ifb1 + Ifb2.

[0027] The input signal is the detector's output single-ended current Iin, and the output signal is a single-ended voltage Vout, where the threshold voltage Vth is input from the outside. The system consists of four parts: a transimpedance amplifier circuit, a high-speed comparator circuit, a low-voltage differential signal (LVDS) circuit, and a common-mode feedback and threshold setting circuit. The transimpedance amplifier converts the detector's output current Iin into a voltage; the high-speed comparator performs open-loop amplification on the weak voltage output by the transimpedance amplifier to form a variety of voltage signals V1 and V2; the LVDS circuit converts the large-swing voltage signal V2 output by the high-speed comparator into low-voltage differential signals Voutp and Voutn; the common-mode feedback and threshold setting circuit converts the voltage signal V1 and the threshold voltage Vth into a current Ifb and feeds it into the transimpedance amplifier, and forms a negative feedback structure for the system to stabilize the system's common-mode voltage and realize the threshold adjustment function based on the threshold time (ToT) discrimination method. The significance of the above expansion is that the output of the detector is a single-ended signal in most cases. Therefore, for detectors with single-ended output, the use of Figure 5 The single-ended transimpedance amplifier system architecture shown allows for direct connection of detection and readout electronics. Figure 3 The circuit in this example cannot be used directly for Figure 5 The system architecture is shown.

[0028] The above technical solution can be further extended to the case where P-type MOS tubes are the main ones, such as Figure 6As shown in Figure 2 . Similar to the case primarily based on N-type MOS transistors, this extended circuit includes a main feedback network and a threshold feedback network, and is a fully differential structure. The main feedback network consists of a P-type MOS transistor differential pair M1c and M1d, current sources I1c and I1d, a load feedback network, a first feedback network, and a transconductance amplifier Gm. The gates of the differential pair M1c and M1d are connected to the input differential voltages V1p and V1n, their drains are connected to the load feedback network and transconductance amplifier Gm, and their sources are connected to current sources I1c, I1d, and the first feedback network. The threshold feedback network consists of a P-type MOS transistor differential pair M2c and M2d, current sources I2c and I2d, and a second feedback network. The gates of the differential pair M2c and M2d are connected to the differential threshold voltages Vthp and Vthn, their sources are connected to current sources I2c and I2d and the second feedback network, and their drains are connected to the load feedback network and transconductance amplifier Gm. The main feedback network converts the differential voltages V1p and V1n output by the high-speed comparator into differential currents Ifb1p and Ifb1n, which are then fed into the transimpedance amplifier (TA), forming a common-mode negative feedback closed-loop structure. The threshold feedback network converts the differential threshold voltages Vthp and Vthn into differential currents Ifb2p and Ifb2n, which are then fed into the TIA, forming a common-mode negative feedback closed-loop structure. As a result, the differential currents Ifbp and Ifbn output by the transconductance amplifier Gm are summed in phase, i.e., Ifbp = Ifb1p + Ifb2p, and Ifbn = Ifb1n + Ifb2n. This extension improves design flexibility and allows for matching different input signal polarities.

[0029] The branch containing the P-type MOS transistor differential pair M2c and M2d is completely separated from the branch containing the P-type MOS transistor differential pair M1c and M1d, that is, the drain terminals of the P-type MOS transistor differential pair M2c and M2d are connected to the drain terminals of the P-type MOS transistor differential pair M1c and M1d (instead of the traditional cascade connection (sharing in the same current branch), that is, the drain terminals of the P-type MOS transistor differential pair M2c and M2d are connected to the source terminals of the P-type MOS transistor differential pair M1c and M1d). At the same time, a pair of bias current sources I2c and I2d are provided to provide bias current for the separated P-type MOS transistor differential pair M1c and M1d branch and the M2d branch, respectively (that is, two pairs of current sources I1c / d and I2c / d are required, where I1c / d still provides bias current for the M1c / d transistor, instead of the traditional one pair).

[0030] Because the two branches are no longer cascaded, no additional voltage margin is consumed, allowing the circuit to operate with a supply voltage of 1.2V or even lower, effectively resolving the conflict between high time resolution and low supply voltage. Furthermore, the complete separation of the two branches relaxes restrictions on the common-mode level of the high-speed comparator's output voltage and threshold voltage, increasing design freedom. Finally, the two differential pairs reside in independent current branches, so the P-type MOS transistor differential pair M2c and M2d does not affect the effectiveness of the first feedback network.

[0031] It will be easily understood by those skilled in the art that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A threshold-crossing time discrimination circuit suitable for low power supply voltage, characterized in that: The present invention relates to a common-mode feedback and threshold setting circuit, comprising a main feedback network and a threshold feedback network, and adopts a fully differential structure. The main feedback network is composed of an N-type MOS transistor differential pair M1a and M1b, current sources I1a and I1b, a load feedback network, a first feedback network, and a transconductance amplifier Gm. The gates of the N-type MOS transistor differential pair M1a and M1b are connected to the input differential voltages V1p and V1n, their drains are connected to the load feedback network and the transconductance amplifier Gm, and their sources are connected to the current sources I1a and I1b and the first feedback network. The threshold feedback network is composed of an N-type MOS transistor differential pair M2a and M2b, current sources I2a and I2b, and a second feedback network. The gates of the N-type MOS transistor differential pair M2a and M2b are connected to the differential threshold voltages Vthp and Vthn, their sources are connected to the current sources I2a and I2b and the second feedback network, and their drains are connected to the load feedback network and the transconductance amplifier Gm.

2. The threshold crossing time discrimination circuit for low power supply voltage according to claim 1, characterized in that: The current sources I1a and I1b, and the current sources I2a and I2b are all implemented using N-type MOS transistors.

3. The threshold crossing time discrimination circuit applicable to low power supply voltage according to claim 1, characterized in that: The N-type MOS transistor differential pair M1a and M1b is replaced by the P-type MOS transistor differential pair M1c and M1d, and the N-type MOS transistor differential pair M2a and M2b is replaced by the P-type MOS transistor differential pair M2c and M2d.

4. A threshold-crossing time discrimination circuit suitable for low power supply voltage, characterized in that: A single-ended circuit is used, comprising a main feedback network and a threshold feedback network. The main feedback network consists of an N-type MOS transistor M1, a current source I1, a load feedback network, a first feedback network, and a transconductance amplifier Gm. The gate of the N-type MOS transistor M1 is connected to the differential input voltage V1, its drain is connected to the load feedback network and the transconductance amplifier Gm, and its source is connected to the current source I1 and the first feedback network. The threshold feedback network consists of an N-type MOS transistor M2, a current source I2, and a second feedback network. The gate of the N-type MOS transistor M2 is connected to the single-ended threshold voltage Vth, its source is connected to the current source I2 and the second feedback network, and its drain is connected to the load feedback network and the transconductance amplifier Gm.

5. The threshold crossing time discrimination circuit applicable to low power supply voltage according to claim 4, characterized in that: The main feedback network converts the differential input voltage V1 output by the high-speed comparator into a single-ended current Ifb1, which is fed into the transimpedance amplifier to form a common-mode negative feedback closed-loop structure; the threshold feedback network converts the single-ended threshold voltage Vth into a single-ended current Ifb2, which is fed into the transimpedance amplifier to form a common-mode negative feedback closed-loop structure; the output single-ended current Ifb of the transconductance amplifier Gm is the superposition of Ifb1 and Ifb2, that is, Ifb=Ifb1+Ifb2.

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