A hardware spinlock logic interval checking apparatus supporting multiprocessor programming

Abstract

The application discloses a kind of hardware spinlock logic interval check devices supporting multiprocessor programming, including interface control module and logic control module, interface control module includes bus interface, n input message queue, n return message queue and register control module, logic control module includes spinlock control module, logic interval check control module, logic interval information storage array and spin queue.N input message queue is connected with external n microprocessor respectively, for receiving and storing input message from microprocessor, spinlock control module is connected with n input message queue, register control module, logic interval check control module, spin queue, n return message queue, register control module is connected with bus interface.The application reduces the software overhead in solid state disk controller, including reducing the node queue, inter-core interaction queue in software maintenance on-chip cache resource occupation, improve the efficiency of interval check.

Description

Technical Field

[0001] This invention relates to the field of solid-state drives, specifically a hardware spinlock logic interval checking device that supports multiprocessor programming. Background Technology

[0002] Solid-state drive (SSD) controllers are large-scale, complex system designs. They utilize logic circuits to implement signal transmission through physical interfaces, an on-chip microprocessor (MCU), and internal interconnect buses, among other hardware functions. Firmware code programming enables the scheduling of various on-chip modules and controls the flow of data across different nodes on the chip. As the functional and performance requirements of SSD controllers increase, on-chip control units often employ multi-core microprocessor architectures to enhance the controller's computing power. Simultaneously, to reduce the microprocessor's workload and establish an event-driven asynchronous processing flow, dedicated hardware circuits are often designed on-chip to perform specific software tasks.

[0003] In the software scheduling algorithm of a solid-state drive (SSD) controller, the software processing flow is generally divided into a data path and a control path, which are processed separately. In the control path processing, the commands to be executed from the host computer are first acquired and categorized, such as read, write, and delete operations. Then, the logical space covered by each command is checked to ensure the execution order of each command, preventing later commands from being executed before earlier commands, which would cause processing chaos. Finally, based on the check results, each command is sequentially passed to the next execution unit for further processing. Therefore, when using the software in the SSD controller to perform the logical interval check function, after analyzing and identifying the commands in the received host computer instructions, the interval information of each command needs to be stored in the system cache, such as the DRAM in the chip. Each host computer command occupies an interval information node, and as the number of host computer commands increases, a chain of interval information nodes is formed. Each interval information node added to the chain needs to be checked against the information already existing in the chain. As the length of the interval information chain increases, the uncertainty of system latency increases, causing performance fluctuations in the command processing process.

[0004] With the development of hardware, the number of multi-core processors is increasing, and the conflicts between multi-core processors are becoming more and more intense. Disorderly competition will make it impossible to guarantee the order of event processing, which can easily cause system disorder. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a hardware spinlock logic interval checking device that supports multiprocessor programming, reduces the software scheduling work in solid-state drive controllers, and supports multiprocessor architecture to ensure the exclusivity of command execution. It can be used as a dedicated hardware accelerator in solid-state drive controllers.

[0006] To solve the aforementioned technical problem, the technical solution adopted by the present invention is: a hardware spinlock logic interval checking device supporting multiprocessor programming, comprising an interface control module and a logic control module. The interface control module includes a bus interface, n input message queues, n return message queues, and a register control module. The logic control module includes a spinlock control module, a logic interval checking control module, a logic interval information storage array, and a spin queue.

[0007] n input message queues are connected to n external microprocessors to receive and store input messages from the microprocessors. A spinlock control module is connected to the n input message queues, a register control module, a logical interval check control module, a spin queue, and n return message queues. The register control module is connected to the bus interface and enables or disables the spinlock function of the spinlock control module according to bus commands. The spinlock control module receives input messages from the input message queues and determines whether to process the input message or pass it to the spin queue based on whether the spinlock function is enabled. When processing messages, the spinlock control module determines the operating mode based on the command operator in the input message, and then inputs the logical interval descriptor in the input message to the logical interval check control module. The logical interval check control module is connected to the logical interval information storage array, which stores logical intervals. The logical interval check control module compares the logical interval in the input message with the logical intervals stored in the logical interval information storage array, completes the corresponding operating mode, and then returns the execution result to the return message queue through the logical interval check module and the spinlock control module.

[0008] n is a positive integer.

[0009] Furthermore, the input message includes command operators, logical interval descriptors, and message identifiers. The command operators include four working modes: logical interval check, logical tag request, logical tag request with spin, and logical tag deletion. The logical interval descriptors include logical interval start value and logical interval offset value. The message identifier is the message code to be processed, used for the generation and recycling of message commands managed by the on-chip software.

[0010] Furthermore, after the register control module enables the spinlock function of the spinlock module, the spinlock control module first determines the lock flag bit in the input message. If the lock flag bit in an input message in a certain input message queue is set, messages from other input message queues will enter the spin queue, waiting for the unlock flag bit in the input message queue where the lock flag bit is set. The input message queue where the lock flag bit is set is called the locked input message queue. After the spinlock control module retrieves the input message from the locked input message queue, it adds queue information and continues to pass it to the logical interval check control module. The logical interval check control module controls the logical interval comparison, completes the corresponding working mode, and returns information to the spinlock control module. The spinlock control module parses the queue information and distributes it to the corresponding return message queue.

[0011] Furthermore, the logical interval check is used to check whether the logical interval information in the input message overlaps with the logical interval information in the logical interval storage array. Its operation process is as follows: the logical interval is placed in the input message and added to the input message queue through the bus interface to wait for execution. The spinlock control module obtains the logical interval descriptor from the input message queue, and then performs an interval check on all columns of the starting row in the logical interval information storage array to determine whether the logical interval of the input information overlaps with the stored logical interval. The judgment result is then returned to the spinlock control module, distributed to the return message queue through the message identifier, and finally the microprocessor obtains the return message to get the logical interval check result.

[0012] Furthermore, the logical tag application is used to add logical interval information from the input message to the logical interval information storage array. The operation process is as follows: the logical interval is placed in the input message and added to the input message queue through the bus interface to wait for execution. The spinlock control module obtains the logical interval descriptor from the input message queue, and then performs an interval check on all columns of the starting row in the logical interval information storage array to determine whether the logical interval of the input message overlaps with the stored logical interval. If the result is no overlap, the logical interval information is added to the logical interval information storage array, and the row and column positions of the newly added logical interval information are added as logical tags to the return message. Otherwise, the result is directly returned to the spinlock control module and distributed to the return message queue through the message identifier.

[0013] Furthermore, the application of a spin-based logical tag is used to add logical interval information from the input message to the logical interval information storage array. If the interval judgment result is overlapping, the input message is distributed to the spin queue for waiting. The operation process is as follows: the logical interval is placed in the input message and added to the input message queue through the bus interface for execution. The spin lock control module obtains the logical interval descriptor from the input message queue, and then checks the interval from all columns of the starting row in the logical interval information storage array to determine whether the logical interval of the input information overlaps with the stored logical interval. If the judgment result is no overlap, the logical interval information is added to the logical interval information storage array, and the row and column positions of the newly added logical interval information are added as logical tags to the return message. If the judgment result is overlapping, the input information is distributed to the spin queue for subsequent operations. Then the judgment result is returned to the spin lock control module and distributed to the return message queue through the message identifier.

[0014] Furthermore, the logical tag deletion function is used to reclaim logical tags and clear the information at the corresponding position in the logical interval information storage array. Its operation process is as follows: A logical tag is placed in the input message, and the logical tag is bound to the row and column information of the logical interval information storage array. It is added to the input message queue via the bus interface to await execution. The spinlock control module retrieves the logical tag from the input message queue, then parses the row and column position corresponding to the logical interval information storage array based on the logical tag, deletes the information at the corresponding position, and then checks the pending input information in the spin queue. If the spin queue is empty, the deletion result is returned to the spinlock. The control module distributes messages to the return message queue via message identifiers. If the spin queue is not empty, it retrieves the input information sequentially from the spin queue. Then, it checks the intervals of all columns in the starting row of the logical interval information storage array to determine whether the logical interval of the input information overlaps with the stored logical intervals. If the determination result of the message in the spin queue indicates that there is overlap, the message is resent to the spin queue. If the determination result indicates that there is no overlap, the logical interval information in the input information is added to the logical interval information storage array, and the row and column positions of the newly added logical interval information are added as logical labels to the return message.

[0015] Furthermore, the positions in the logical interval information storage array where logical interval information is not stored are written with 0. During row-based parallel search, the minimum distance in the logical interval information storage array where logical interval information can be stored is found by checking the 0 values ​​in the array.

[0016] The beneficial effects of this invention are: 1. It reduces the software overhead in the solid-state drive controller, including reducing the on-chip cache resource occupation of the node queue and inter-core interaction queue for software maintenance, reducing the number of times the on-chip cache is accessed, and significantly improving the efficiency of interval checking;

[0017] 2. An asynchronous processing mechanism has been added to overcome the control path delay caused by synchronous software operations;

[0018] 3. A spinlock control and release mechanism has been added, which is suitable for multi-processor solid-state drive controller architectures and reduces the locking issues that need to be considered when programming software under multi-core architectures;

[0019] 4. In the logical interval information storage array, row-based parallel search is adopted, which improves the efficiency of interval checking;

[0020] 5. Binding logical tags to the row and column information of the logical interval information storage array enables rapid deletion of historical information corresponding to logical tag items. During searching, the minimum distance for storing logical interval information is found by checking the 0 values ​​in the array, ensuring fast checking. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the principle of the present invention. Detailed Implementation

[0022] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0023] Example 1

[0024] This embodiment discloses a hardware spinlock logic interval checking device supporting multiprocessor programming. A logic interval refers to a set of continuous data operated on by the solid-state drive controller software algorithm, typically an LBA (Logical Block Address). This information consists of a start value and a length, and is distributed from the host computer to the solid-state drive device. This invention allows software to submit operation commands to this checking device, specifying operations such as insertion interval, check interval, and deletion interval. Upon receiving a command, the device checks against other intervals already recorded in the device to see if there is any overlap in logical intervals, and generates a corresponding command return message based on the control bits in the command descriptor.

[0025] In operation, this invention allows the spinlock function to be enabled or disabled via the device's register control module, resolving resource access conflicts in multiprocessor architectures. With the advancement of hardware, the number of multi-core processors is increasing, and conflicts between them are becoming more severe. Unordered competition cannot guarantee the sequence of event processing, easily leading to system disorder. A spin queue is designed within the inspection device to protect the context information during process switching. When the spinlock function is enabled, the device can be held by at most one microprocessor. If another microprocessor attempts to acquire a spinlock that is already occupied, that thread will continuously perform a busy loop—spinning—waiting for the lock to become available again. If the lock is not acquired, the requesting microprocessor can immediately obtain it and continue execution.

[0026] like Figure 1 As shown, the inspection device described in this embodiment includes an interface control module and a logic control module. The interface control module includes a bus interface, n input message queues, n return message queues, and a register control module. The logic control module includes a spinlock control module, a logic interval inspection control module, a logic interval information storage array, and a spin queue.

[0027] n input message queues are connected to n external microprocessors to receive and store input messages from the microprocessors. A spinlock control module is connected to the n input message queues, a register control module, a logical interval check control module, a spin queue, and n return message queues. The register control module is connected to the bus interface and enables or disables the spinlock function of the spinlock control module according to bus commands. The spinlock control module receives input messages from the input message queues and determines whether to process the input message or pass it to the spin queue based on whether the spinlock function is enabled. When processing messages, the spinlock control module determines the operating mode based on the command operator in the input message, and then inputs the logical interval descriptor in the input message to the logical interval check control module. The logical interval check control module is connected to the logical interval information storage array, which stores logical intervals. The logical interval check control module compares the logical interval in the input message with the logical intervals stored in the logical interval information storage array, completes the corresponding operating mode, and then returns the execution result to the return message queue through the logical interval check module and the spinlock control module. n is a positive integer.

[0028] After the register control module enables the spinlock function of the spinlock module, the spinlock control module first checks the lock flag bit in the input message. If the lock flag bit in an input message in a certain input message queue is set, messages from other input message queues will enter the spin queue, waiting for the unlock flag bit in the input message queue where the lock flag bit is set. The input message queue where the lock flag bit is set is called the locked input message queue. After the spinlock control module retrieves the input message from the locked input message queue, it adds queue information and continues to pass it to the logical interval check control module. The logical interval check control module controls the logical interval comparison, and after completing the corresponding working mode, it returns information to the spinlock control module. The spinlock control module parses the queue information and distributes it to the corresponding return message queue.

[0029] The input message includes command operators, logical interval descriptors, and message identifiers. The command operators include four working modes: logical interval check, logical tag request, logical tag request with spin, and logical tag deletion. The logical interval descriptor includes the logical interval start value and logical interval offset value. The message identifier is the message code to be processed, which is used for the generation and recycling of message commands managed by the on-chip software.

[0030] The logical interval check is used to check whether the logical interval information in the input message overlaps with the logical interval information in the logical interval storage array. The operation process is as follows: the logical interval is placed in the input message and added to the input message queue through the bus interface to wait for execution. The spinlock control module obtains the logical interval descriptor from the input message queue, and then performs an interval check on all columns of the starting row in the logical interval information storage array to determine whether the logical interval of the input information overlaps with the stored logical interval. The judgment result is then returned to the spinlock control module, which distributes it to the return message queue through the message identifier. Finally, the microprocessor obtains the return message and gets the logical interval check result.

[0031] The logical tag application is used to add logical interval information from the input message to the logical interval information storage array. The operation process is as follows: the logical interval is placed in the input message and added to the input message queue through the bus interface to wait for execution. The spinlock control module obtains the logical interval descriptor from the input message queue, and then performs an interval check on all columns of the starting row in the logical interval information storage array to determine whether the logical interval of the input message overlaps with the stored logical interval. If the result is no overlap, the logical interval information is added to the logical interval information storage array, and the row and column positions of the newly added logical interval information are added as logical tags to the return message. Otherwise, the result is directly returned to the spinlock control module and distributed to the return message queue through the message identifier.

[0032] The application of a spin-based logical tag is used to add logical interval information from the input message to the logical interval information storage array. If the interval judgment result is overlapping, the input message is distributed to the spin queue for waiting. The operation process is as follows: the logical interval is placed in the input message and added to the input message queue through the bus interface for execution. The spin lock control module obtains the logical interval descriptor from the input message queue, and then checks the interval from all columns of the starting row in the logical interval information storage array to determine whether the logical interval of the input information overlaps with the stored logical intervals. If the judgment result is no overlap, the logical interval information is added to the logical interval information storage array, and the row and column positions of the newly added logical interval information are added as logical tags to the return message. If the judgment result is overlapping, the input information is distributed to the spin queue for subsequent operations. Then the judgment result is returned to the spin lock control module and distributed to the return message queue through the message identifier.

[0033] The logic tag deletion function is used to reclaim logic tags and clear the information at the corresponding position in the logic interval information storage array. Its operation process is as follows: A logic tag is placed in the input message, and the logic tag is bound to the row and column information of the logic interval information storage array. It is added to the input message queue via the bus interface to await execution. The spinlock control module retrieves the logic tag from the input message queue, then parses the row and column position corresponding to the logic interval information storage array based on the logic tag, deletes the information at the corresponding position, and then checks the pending input information in the spin queue. If the spin queue is empty, the deletion result is returned to the spinlock control module. The input information is distributed to the return message queue via a message identifier. If the spin queue is not empty, the input information is retrieved sequentially from the spin queue. Then, all columns of the starting row in the logical interval information storage array are checked for intervals to determine whether the logical interval of the input information overlaps with the stored logical intervals. If the result of the judgment in the spin queue is that there is an overlap, the message is resent to the spin queue. If the result of the judgment is that there is no overlap, the logical interval information in the input information is added to the logical interval information storage array, and the row and column positions of the newly added logical interval information are added as logical labels to the return message.

[0034] In this embodiment, the positions in the logical interval information storage array that do not store logical interval information are written with 0. During row-based parallel search, the minimum distance in the logical interval information storage array that can store logical interval information is found by checking the 0 values ​​in the array.

[0035] The above description is merely the basic principle and preferred embodiment of the present invention. Improvements and substitutions made by those skilled in the art based on the present invention are within the scope of protection of the present invention.

Claims

1. A hardware spinlock logic interval checking device supporting multiprocessor programming, characterized in that: It includes an interface control module and a logic control module. The interface control module includes a bus interface, n input message queues, n return message queues, and a register control module. The logic control module includes a spinlock control module, a logic interval check control module, a logic interval information storage array, and a spin queue. n input message queues are connected to n external microprocessors to receive and store input messages from the microprocessors. A spinlock control module is connected to the n input message queues, a register control module, a logical interval check control module, a spin queue, and n return message queues. The register control module is connected to the bus interface and enables or disables the spinlock function of the spinlock control module according to bus commands. The spinlock control module receives input messages from the input message queues and determines whether to process the input message or pass it to the spin queue based on whether the spinlock function is enabled. When processing messages, the spinlock control module determines the operating mode based on the command operator in the input message, and then inputs the logical interval descriptor in the input message to the logical interval check control module. The logical interval check control module is connected to the logical interval information storage array, which stores logical intervals. The logical interval check control module compares the logical interval in the input message with the logical intervals stored in the logical interval information storage array, completes the corresponding operating mode, and then returns the execution result to the return message queue through the logical interval check module and the spinlock control module. n is a positive integer.

2. The hardware spinlock logic interval checking device supporting multiprocessor programming according to claim 1, characterized in that: The input message includes command operators, logical interval descriptors, and message identifiers. The command operators include four working modes: logical interval check, logical tag request, logical tag request with spin, and logical tag deletion. The logical interval descriptor includes the logical interval start value and logical interval offset value. The message identifier is the message code to be processed, which is used for the generation and recycling of message commands managed by the on-chip software.

3. The hardware spinlock logic interval checking device supporting multiprocessor programming according to claim 2, characterized in that: After the register control module enables the spinlock function of the spinlock control module, the spinlock control module first checks the lock flag bit in the input message. If the lock flag bit in an input message in a certain input message queue is set, messages from other input message queues will enter the spin queue, waiting for the unlock flag bit in the input message queue where the lock flag bit is set. The input message queue where the lock flag bit is set is called the locked input message queue. After the spinlock control module retrieves the input message from the locked input message queue, it adds queue information and continues to pass it to the logical interval check control module. The logical interval check control module controls the logical interval comparison, and after completing the corresponding working mode, it returns information to the spinlock control module. The spinlock control module parses the queue information and distributes it to the corresponding return message queue.

4. The hardware spinlock logic interval checking device supporting multiprocessor programming according to claim 2 or 3, characterized in that: The logical interval check is used to check whether the logical interval information in the input message overlaps with the logical interval information in the logical interval storage array. The operation process is as follows: the logical interval is placed in the input message and added to the input message queue through the bus interface to wait for execution. The spinlock control module obtains the logical interval descriptor from the input message queue, and then performs an interval check on all columns of the starting row in the logical interval information storage array to determine whether the logical interval of the input information overlaps with the stored logical interval. The judgment result is then returned to the spinlock control module, which distributes it to the return message queue through the message identifier. Finally, the microprocessor obtains the return message and gets the logical interval check result.

5. The hardware spinlock logic interval checking device supporting multiprocessor programming according to claim 2 or 3, characterized in that: The logical tag application is used to add logical interval information from the input message to the logical interval information storage array. The operation process is as follows: the logical interval is placed in the input message and added to the input message queue through the bus interface to wait for execution. The spinlock control module obtains the logical interval descriptor from the input message queue, and then performs an interval check on all columns of the starting row in the logical interval information storage array to determine whether the logical interval of the input message overlaps with the stored logical interval. If the result is no overlap, the logical interval information is added to the logical interval information storage array, and the row and column positions of the newly added logical interval information are added as logical tags to the return message. Otherwise, the result is directly returned to the spinlock control module and distributed to the return message queue through the message identifier.

6. The hardware spinlock logic interval checking device supporting multiprocessor programming according to claim 2 or 3, characterized in that: The application of a spin-based logical tag is used to add logical interval information from the input message to the logical interval information storage array. If the interval judgment result is overlapping, the input message is distributed to the spin queue for waiting. The operation process is as follows: the logical interval is placed in the input message and added to the input message queue through the bus interface for execution. The spin lock control module obtains the logical interval descriptor from the input message queue, and then checks the interval from all columns of the starting row in the logical interval information storage array to determine whether the logical interval of the input information overlaps with the stored logical intervals. If the judgment result is no overlap, the logical interval information is added to the logical interval information storage array, and the row and column positions of the newly added logical interval information are added as logical tags to the return message. If the judgment result is overlapping, the input information is distributed to the spin queue for subsequent operations. Then the judgment result is returned to the spin lock control module and distributed to the return message queue through the message identifier.

7. The hardware spinlock logic interval checking device supporting multiprocessor programming according to claim 2 or 3, characterized in that: The logic tag deletion function is used to reclaim logic tags and clear the information at the corresponding position in the logic interval information storage array. Its operation process is as follows: A logic tag is placed in the input message, and the logic tag is bound to the row and column information of the logic interval information storage array. It is added to the input message queue via the bus interface to await execution. The spinlock control module retrieves the logic tag from the input message queue, then parses the row and column position corresponding to the logic interval information storage array based on the logic tag, deletes the information at the corresponding position, and then checks the pending input information in the spin queue. If the spin queue is empty, the deletion result is returned to the spinlock control module. The input information is distributed to the return message queue via a message identifier. If the spin queue is not empty, the input information is retrieved sequentially from the spin queue. Then, all columns of the starting row in the logical interval information storage array are checked for intervals to determine whether the logical interval of the input information overlaps with the stored logical intervals. If the result of the judgment in the spin queue is that there is an overlap, the message is resent to the spin queue. If the result of the judgment is that there is no overlap, the logical interval information in the input information is added to the logical interval information storage array, and the row and column positions of the newly added logical interval information are added as logical labels to the return message.

8. The hardware spinlock logic interval checking device supporting multiprocessor programming according to claim 2 or 3, characterized in that: The logical interval information storage array writes 0 at positions where logical interval information is not stored. During row-based parallel search, the minimum distance where logical interval information can be stored in the logical interval information storage array is found by checking the 0 values ​​in the array.

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