Gate drive circuit and display panel

Abstract

The present invention discloses a gate drive circuit and a display panel. The gate drive circuit includes a node potential control module, a first output module, a pulse width modulation module and a second output module. The first output module includes a first control terminal and a second control terminal, and the second output module includes a third control terminal and a fourth control terminal; the node potential control module controls the potential of the first control terminal and the second control terminal according to an input signal to control the output of the first output module; the pulse width modulation module is used to control the potential of the fourth control terminal according to the potential of the second control terminal and the light control signal output by the light control driving circuit; the third control terminal is electrically connected to the first control terminal, and the second output module outputs a second scanning signal according to the potential of the third control terminal and the fourth control terminal; the pulse width of the second scanning signal is determined based on the input signal and the light control signal. The present invention can simplify the structure of the gate drive circuit, which is conducive to realizing the narrow frame design of the display panel.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a gate driving circuit and a display panel. Background Art

[0002] With the continuous development of display technology, the application scope of display panels is becoming more and more extensive, and people's requirements for display panels are also becoming higher and higher. In the prior art, with the increase of pixel circuit functions and the increase of scanning signals required, the types and number of scanning signals required to be provided by the gate drive circuit increase, making the structure of the gate drive circuit more and more complex, which in turn makes the border width of the display panel larger, which is not conducive to the narrow border design. Summary of the invention

[0003] The present invention provides a gate driving circuit and a display panel to simplify the structure of the gate driving circuit, which is beneficial to realizing a narrow frame design of the display panel.

[0004] To achieve the above technical objectives, the embodiments of the present invention provide the following technical solutions:

[0005] A gate drive circuit, comprising:

[0006] A node potential control module and a first output module, wherein the first output module includes a first control terminal and a second control terminal; the node potential control module is electrically connected to the first control terminal and the second control terminal respectively, and receives an input signal; the node potential control module is used to control the potentials of the first control terminal and the second control terminal according to the input signal, and the first output module is used to output a first scanning signal according to the potentials of the first control terminal and the second control terminal;

[0007] A pulse width modulation module and a second output module, the pulse width modulation module is electrically connected to the second control terminal and is connected to the light control signal output by the light control driving circuit; the second output module includes a third control terminal and a fourth control terminal, the third control terminal is electrically connected to the first control terminal, and the fourth control terminal is electrically connected to the output terminal of the pulse width modulation module; the pulse width modulation module is used to control the potential of the fourth control terminal according to the potential of the second control terminal and the light control signal, and the second output module is used to output a second scanning signal according to the potential of the third control terminal and the fourth control terminal; wherein the pulse width of the second scanning signal is determined based on the input signal and the light control signal.

[0008] Optionally, the node potential control module controls the potentials of the first control terminal and the second control terminal in response to the first clock signal, the second clock signal, the input signal, the first potential signal and the second potential signal;

[0009] The first output module responds to the potentials of the first control terminal and the second control terminal to determine whether to output the second potential signal as the first scanning signal and whether to output the second clock signal as the first scanning signal;

[0010] The pulse width modulation module responds to the second clock signal and the light emitting control signal to determine whether to transmit the potential of the second control terminal to the fourth control terminal;

[0011] The second output module responds to the first clock signal, the potential of the third control terminal and the potential of the fourth control terminal to determine whether to output the first potential signal as the second scanning signal and whether to output the second potential signal as the second scanning signal.

[0012] Optionally, the node potential control module includes:

[0013] A first input unit, electrically connected to the first control terminal, and used to control whether the input signal is transmitted to the first control terminal according to the first clock signal;

[0014] A potential control unit, electrically connected to the second control terminal, and configured to control whether the first potential signal is transmitted to the second control terminal according to the first clock signal;

[0015] A first node mutual control unit, electrically connected to the first control terminal and the second control terminal respectively, and used to control whether the first clock signal is transmitted to the second control terminal according to the potential of the first control terminal;

[0016] The second node mutual control unit is electrically connected to the first control terminal and the second control terminal respectively, and is used to control whether the second potential signal is transmitted to the first control terminal according to the second clock signal and the potential of the second control terminal.

[0017] Optionally, the first input unit includes: a first transistor; a gate of the first transistor is connected to the first clock signal, a first electrode of the first transistor is connected to the input signal, and a second electrode of the first transistor is electrically connected to the first control terminal;

[0018] And / or, the potential control unit comprises: a second transistor; a gate of the second transistor is connected to the first clock signal, a first electrode of the second transistor is connected to the first potential signal, and a second electrode of the second transistor is electrically connected to the second control terminal;

[0019] And / or, the first node mutual control unit includes: a third transistor; the gate of the third transistor is electrically connected to the first control terminal, the first electrode of the third transistor is connected to the first clock signal, and the second electrode of the third transistor is electrically connected to the second control terminal;

[0020] And / or, the second node mutual control unit includes: a fourth transistor and a fifth transistor; the gate of the fourth transistor is electrically connected to the second control terminal, the first electrode of the fourth transistor is connected to the second potential signal, and the second electrode of the fourth transistor is electrically connected to the first electrode of the fifth transistor; the gate of the fifth transistor is connected to the second clock signal, and the second electrode of the fifth transistor is electrically connected to the first control terminal.

[0021] Optionally, the first output module includes:

[0022] A first output unit, wherein the control end of the first output unit serves as a first control end, and the input end of the first output unit is connected to a second clock signal;

[0023] A second output unit, wherein the control end of the second output unit serves as a second control end, the input end of the second output unit is connected to a second potential signal, the output end of the second output unit is electrically connected to the output end of the first output unit and serves as the output end of the first output module;

[0024] Optionally, the first output unit includes: a sixth transistor and a first capacitor; the gate of the sixth transistor serves as a first control terminal and is electrically connected to a first terminal of the first capacitor; the first electrode of the sixth transistor serves as an input terminal of the first output unit; the second electrode of the sixth transistor serves as an output terminal of the first output unit and is electrically connected to a second terminal of the first capacitor;

[0025] The second output unit includes: a seventh transistor and a second capacitor; the gate of the seventh transistor serves as a second control terminal and is electrically connected to the first terminal of the second capacitor; the first electrode of the seventh transistor serves as an input terminal of the second output unit and is electrically connected to the second terminal of the second capacitor; the second electrode of the seventh transistor serves as an output terminal of the second output unit;

[0026] Optionally, the first output unit further includes: an eighth transistor; the gate of the eighth transistor is connected to the first potential signal, the first electrode of the eighth transistor serves as the first control terminal, and the second electrode of the eighth transistor is electrically connected to the gate of the sixth transistor.

[0027] Optionally, the pulse width modulation module includes:

[0028] A first transmission unit, wherein an input end of the first transmission unit is electrically connected to the second control end;

[0029] a second transmission unit, wherein an input end of the second transmission unit is electrically connected to an output end of the first transmission unit, and an output end of the second transmission unit is electrically connected to a fourth control end;

[0030] The control end of the first transmission unit is connected to the second clock signal, and the control end of the second transmission unit is connected to the light control signal; or the control end of the first transmission unit is connected to the light control signal, and the control end of the second transmission unit is connected to the second clock signal;

[0031] Optionally, the first transmission unit includes a ninth transistor; the gate of the ninth transistor serves as a control terminal of the first transmission unit, the first electrode of the ninth transistor serves as an input terminal of the first transmission unit, and the second electrode of the ninth transistor serves as an output terminal of the first transmission unit;

[0032] The second transmission unit includes a tenth transistor; the gate of the tenth transistor serves as the control end of the second transmission unit, the first electrode of the tenth transistor serves as the input end of the second transmission unit, and the second electrode of the tenth transistor serves as the output end of the second transmission unit.

[0033] Optionally, the second output module includes:

[0034] a coupling unit, electrically connected to the fourth control terminal, and configured to respond to the potential of the fourth control terminal and perform coupling control on the potential of the fourth control terminal according to the first clock signal;

[0035] A third node mutual control unit, electrically connected to the third control terminal and the fourth control terminal respectively, and used for controlling whether the second potential signal is transmitted to the fourth control terminal according to the potential of the third control terminal;

[0036] a third output unit, electrically connected to the third control terminal, and used for controlling whether the second potential signal is output as the second scanning signal according to the potential of the third control terminal;

[0037] The fourth output unit is electrically connected to the fourth control terminal and is used to control whether the first potential signal is output as the second scanning signal according to the potential of the fourth control terminal.

[0038] Optionally, the coupling unit includes: a coupling subunit and a switch subunit;

[0039] The control end of the switch subunit is electrically connected to the fourth control end, the input end of the switch subunit is connected to the first clock signal, the output end of the switch subunit is electrically connected to the first end of the coupling subunit, and the second end of the coupling subunit is electrically connected to the fourth control end;

[0040] Optionally, the coupling subunit includes: a third capacitor; a first end of the third capacitor serves as a first end of the coupling subunit, and a second end of the third capacitor serves as a second end of the coupling subunit;

[0041] The switch subunit includes: an eleventh transistor; the gate of the eleventh transistor serves as a control terminal of the switch subunit, the first electrode of the eleventh transistor serves as an input terminal of the switch subunit, and the second electrode of the eleventh transistor serves as an output terminal of the switch subunit.

[0042] Optionally, the third node mutual control unit includes: a twelfth transistor; the gate of the twelfth transistor is electrically connected to the third control terminal, the first electrode of the twelfth transistor is connected to the second potential signal, and the second electrode of the twelfth transistor is electrically connected to the fourth control terminal;

[0043] The third output unit includes: a thirteenth transistor and a fourth capacitor; the gate of the thirteenth transistor is electrically connected to the third control terminal and the first terminal of the fourth capacitor respectively; the first electrode of the thirteenth transistor serves as the input terminal of the third output unit and is electrically connected to the second terminal of the fourth capacitor; the second electrode of the thirteenth transistor serves as the output terminal of the third output unit;

[0044] The fourth output unit includes: a fourteenth transistor; the gate of the fourteenth transistor is electrically connected to the fourth control terminal, the first electrode of the fourteenth transistor serves as the input terminal of the fourth output unit, and the second electrode of the fourteenth transistor serves as the output terminal of the fourth output unit.

[0045] Correspondingly, an embodiment of the present invention further provides a display panel, comprising: a light emitting control driving circuit and a gate driving circuit provided by any embodiment of the present invention.

[0046] Optionally, the display panel includes a plurality of gate driving circuits, and the plurality of gate driving circuits are cascade-connected, and the first scanning signal output by the gate driving circuit of this stage is used as an input signal of the gate driving circuit of the next stage;

[0047] Optionally, the display panel further comprises a plurality of rows of pixel circuits;

[0048] The second scanning signal output by the gate driving circuit of the same level and the light emitting control signal connected to the gate driving circuit of the same level are transmitted to the pixel circuits of the same row or different rows;

[0049] The first scanning signal and the second scanning signal output by the gate driving circuit of the same level are transmitted to the pixel circuits of the same row or different rows.

[0050] The gate drive circuit provided by the embodiment of the present invention provides a new drive architecture. Through the setting of the node potential control module, the first output module, the pulse width adjustment module and the second output module, one gate drive circuit can output two scan signals. Among them, the pulse width of the second scan signal is adjustable, and its actual pulse width is determined based on the corresponding relationship between the input signal and the light-emitting control signal, so that the gate drive circuit can provide two types of scan signals with different pulse widths, which is conducive to the realization of a narrow frame on the basis of meeting the driving requirements of the pixel circuit. Specifically, the node potential control module is used for controlling the first output module, and is also used together with the pulse width adjustment module to control the second output module, so that the node potential control module realizes multiplexing in the output control process of the two types of scan signals (or the potentials of the two nodes of the first control terminal and the second control terminal are multiplexed). Compared with the need to provide two groups of gate drive circuits in the prior art, the embodiment of the present invention simplifies the structure of the gate drive circuit as a whole, which is conducive to reducing the frame of the display panel. In addition, the light-emitting control signal is provided by the original light-emitting control drive circuit in the display panel, and there is no need to provide an additional pulse width control signal, which is conducive to further simplifying the circuit structure. Therefore, compared with the prior art, the embodiment of the present invention can simplify the structure of the gate drive circuit, which is conducive to realizing the narrow frame design of the display panel. The pulse width of the second scanning signal is controlled by the light control signal, which is conducive to the subsequent screen debugging and ensures the lighting effect. When the screen is debugged, the second scanning signal can be debugged at the same time by debugging the light control signal, without the need to debug the second scanning signal separately, thereby improving the debugging efficiency.

[0051] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0053] Figure 1 is a structural schematic diagram of a pixel circuit provided by an embodiment of the present invention;

[0054] Figure 2 is a driving timing diagram of a pixel circuit provided by an embodiment of the present invention;

[0055] Figure 3 is a driving timing diagram of another pixel circuit provided by an embodiment of the present invention;

[0056] Figure 4 is a schematic structural diagram of a gate driving circuit provided by an embodiment of the present invention;

[0057] Figure 5 is a schematic structural diagram of another gate driving circuit provided by an embodiment of the present invention;

[0058] Figure 6 is a structural schematic diagram of another gate driving circuit provided by an embodiment of the present invention;

[0059] Figure 7 It is a driving timing diagram of a gate driving circuit provided by an embodiment of the present invention;

[0060] Figure 8 is a driving timing diagram of another gate driving circuit provided by an embodiment of the present invention;

[0061] Fig. 9 It is a driving timing diagram of another gate driving circuit provided by an embodiment of the present invention;

[0062] Fig.10 It is a driving timing diagram of another gate driving circuit provided by an embodiment of the present invention;

[0063] Fig.11 It is a driving timing diagram of another gate driving circuit provided by an embodiment of the present invention;

[0064] Fig.12 is a structural schematic diagram of another gate driving circuit provided by an embodiment of the present invention;

[0065] Fig.13 is a structural schematic diagram of another gate driving circuit provided by an embodiment of the present invention;

[0066] Fig.14 It is a driving timing diagram of another gate driving circuit provided by an embodiment of the present invention;

[0067] Fig.15 It is a schematic diagram of the structure of a display panel provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0068] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0069] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0070] As described in the background technology, with the increase of pixel circuit functions and the increase of required scanning signals, the structure of the gate drive circuit is becoming more and more complex. For example, due to the demand for broadband drive, LTPO pixel circuits have received more and more attention. Since the LTPO pixel circuit contains two types of transistors, LTPS and IGZO, its driving process requires a variety of scanning signals with different pulse potentials and pulse widths, so multiple sets of gate drive circuits need to be provided in its driving circuit. Figure 1 , taking a 7T1C structure LTPO pixel circuit as an example, the causes of the above problems are explained. Figure 1 The pixel circuit includes: a driving transistor DTFT, a first initialization module 110 composed of a transistor M22, a second initialization module 120 composed of a transistor M23, a data writing module 130 composed of a transistor M24, a threshold compensation module 140 composed of a transistor M25, a light emitting control module 150 composed of a transistor M26 and a transistor M27, and a storage capacitor Cst.

[0071] It is defined that among the control signals (including various scanning signals and light-emitting control signals) connected to the gate of the transistor, the pulse used to control the conduction of the transistor is called the on-pulse, and the pulse used to control the turn-off of the transistor is called the off-pulse; accordingly, the on-pulse width is the duration during which the control signal remains at a potential that can control the conduction of the transistor, and the off-pulse width is the duration during which the control signal remains at a potential that can control the turn-off of the transistor.

[0072] For example, Figure 1In the pixel circuit shown, at least the threshold compensation module 140 is composed of an N-type IGZO transistor (transistor M25), and the high-potential on-pulse of the scan signal S3 can control the transistor M25 to be turned on. In addition, the first initialization module 110 is also composed of an N-type IGZO transistor (transistor M22), and the high-potential on-pulse of the scan signal S1 can control the transistor M22 to be turned on. The second initialization module 120 and the data writing module 130 are both composed of P-type transistors (transistor M23 and transistor M24), and the low-potential on-pulse of the scan signal S2 can control the transistor M23 and the transistor M24 to be turned on. The light-emitting control module 150 is composed of P-type transistors (transistor M26 and transistor M27), and the high-potential off-pulse of the light-emitting control signal EM can control the transistor M26 and the transistor M27 to be turned off. The pulse potentials and pulse action times of the above-mentioned control signals are different, and the pulse frequencies of the control signals are also different in different scenarios such as high-frequency and low-frequency driving. Therefore, in the prior art, for example Figure 1 The LTPO pixel circuit shown in the figure needs to be provided with four sets of driving circuits (including three sets of gate driving circuits and one set of light-emitting control driving circuit) to provide scanning signals S1, S2, S3 and light-emitting control signals EM. The overall driving circuit structure formed by each driving circuit is complex and occupies a large frame width, which is not conducive to the design of a narrow frame of the display panel.

[0073] To solve the above problems, the embodiment of the present invention provides a new gate driving circuit, which can effectively simplify the structure of the gate driving circuit. In order to better explain the working mode of the scanning signal output by the gate driving circuit provided by the embodiment of the present invention, the driving process of the pixel circuit is first described below.

[0074] Figure 2 1 is a driving timing diagram of a pixel circuit provided by an embodiment of the present invention. Figure 1 and Figure 2 Exemplarily, the LTPO pixel circuit has the ability of broadband display. When displaying at a low frequency, a display frame of the pixel circuit may include a refresh frame A1 and at least one hold frame A2. When displaying at a high frequency, a display frame of the pixel circuit may only include a refresh frame A1. Among them, the refresh frame A1 includes an initialization phase T211, a data writing phase T212, and a first light-emitting phase T22. The hold frame A2 includes a black insertion phase T23 and a second light-emitting phase T24, and no data is written in the black insertion phase T23.

[0075] Specifically, taking the low-frequency refresh scenario as an example, the driving process of the LTPO pixel circuit includes:

[0076] In the initialization stage T211, the scanning signals S1, S2 and the light emitting control signal EM are all at high potential, and the scanning signal S3 is at low potential. The transistor M22 is turned on, and the first initialization signal Vref1 is transmitted through the transistor M22 to initialize the gate of the driving transistor DTFT.

[0077] In the data writing stage T212, the scanning signal S1 and the scanning signal S2 are both at low potential, and the scanning signal S3 and the light emitting control signal EM are both at high potential. The transistor M22 is turned off, and the transistor M23, the transistor M24 and the transistor M25 are all turned on. The data signal Vdata is transmitted to the gate of the driving transistor DTFT through the transistor M24, the first and second electrodes of the driving transistor DTFT, and the transistor M25 to complete the data writing. At the same time, the second initialization signal Vref2 is used to initialize the anode of the light emitting device OLED through the transistor M23.

[0078] In the first light-emitting stage T22, the scanning signal S1, the scanning signal S3 and the light-emitting control signal EM are all at low potentials, and the scanning signal S2 is at high potential. The transistor M25 is turned off, and the transistor M26 and the transistor M27 are both turned on, so that the driving current generated by the driving transistor DTFT is transmitted to the light-emitting device OLED, driving the light-emitting device OLED to emit light.

[0079] In the black insertion stage T23, the scanning signals S1 and S3 maintain low potentials, the scanning signal S2 maintains high potential, the light emitting control signal EM becomes high potential, the transistors M26 and M27 are both turned off, and the light emitting device OLED stops emitting light.

[0080] In the second light-emitting stage T24, the scanning signals S1 and S3 maintain low potentials, the scanning signal S2 maintains high potential, the light-emitting control signal EM becomes low potential again, and the transistors M26 and M27 are turned on again, so that the driving current generated by the driving transistor DTFT drives the light-emitting device OLED to emit light.

[0081] The subsequent stages repeat the driving process of the frame A2 until the next refresh frame A1 arrives.

[0082] The above driving process does not serve as Figure 1 Definition of the pixel circuit driving scheme. Figure 3 is a driving timing diagram of another pixel circuit provided by an embodiment of the present invention, see Figure 3 ,and Figure 2 The difference in the driving process is that Figure 3 In the initialization stage T211, the scanning signal S3 is at a high potential, the transistor M25 is turned on, so that the first initialization signal Vref1 passes through the transistor M22 and then continues to be transmitted through the transistor M25, thereby initializing the second electrode of the driving transistor DTFT.

[0083] in addition, Figure 1 The pixel circuit shown in the figure is not intended to limit the structure of the LTPO pixel circuit. In other embodiments, the first initialization module 110 can be directly connected to the second electrode of the driving transistor DTFT. Figure 3 if on this basis the transistor M22 is replaced by a P-type transistor, the scan signal S1 can be replaced by a corresponding low-potential on-pulse scan signal, ie, in the initialization stage T211, the scan signal S1 is low potential, and the remaining stages can be high potential.

[0084] From the above analysis, it can be seen that in the driving process of the LTPO pixel circuit, four types of control signals with different pulse potentials, pulse widths and action frequencies are required. Figure 1 Taking the pixel structure in FIG. 1 as an example, the potentials of the on pulse of the scanning signal S1, the on pulse of the scanning signal S3 and the off pulse of the light emitting control signal EM are all high potentials, and the potential of the on pulse of the scanning signal S2 is low potential. The on pulse width of the scanning signal S1 is smaller than the off pulse width of the light emitting control signal EM. The on pulse width of the scanning signal S3 is larger than the on pulse width of the scanning signal S2, and the on pulse width of the scanning signal S3 in the writing frame A1 can be smaller than the off pulse width of the light emitting control signal EM, or can be the same as the off pulse width of the light emitting control signal EM.

[0085] The gate driving circuit provided by the embodiment of the present invention is described below. Figure 4 is a schematic diagram of the structure of a gate drive circuit provided by an embodiment of the present invention. Figure 4 The gate drive circuit includes: a node potential control module 10, a first output module 20, a pulse width adjustment module 30 and a second output module 40. The first output module 20 includes a first control terminal N1 and a second control terminal N2, and the second output module 40 includes a third control terminal N3 and a fourth control terminal N4.

[0086] The node potential control module 10 is electrically connected to the first control terminal N1 and the second control terminal N2 respectively, and is connected to the input signal SIN; the node potential control module 10 is used to control the potentials of the first control terminal N1 and the second control terminal N2 based on the input signal SIN, and the first output module 10 is used to output the first scanning signal Vout1 according to the potentials of the first control terminal N1 and the second control terminal N2. The pulse width adjustment module 30 is electrically connected to the second control terminal N2, and is connected to the light control signal EM output by the light control driving circuit. The third control terminal N3 is electrically connected to the first control terminal N1, and the fourth control terminal N4 is electrically connected to the output end of the pulse width adjustment module 30. The pulse width adjustment module 30 is used to control the potential of the fourth control terminal N4 according to the potential of the first control terminal N1 and the light control signal EM, and the second output module 40 is used to output the second scanning signal Vout2 according to the potentials of the third control terminal N3 and the fourth control terminal N4. Among them, the pulse width of the second scanning signal Vout2 is determined based on the input signal SIN and the light control signal EM.

[0087] The on-pulse of the first scanning signal Vout1 may be a high-potential on-pulse or a low-potential on-pulse. The on-pulse of the second scanning signal Vout2 may be a high-potential on-pulse or a low-potential on-pulse. The on-pulse of one of the first scanning signal Vout1 and the second scanning signal Vout2 may be a high-potential on-pulse, and the on-pulse of the other may be a low-potential on-pulse. The on-pulses of the first scanning signal Vout1 and the second scanning signal Vout2 may both be high-potential on-pulses, or both be low-potential on-pulses. The pulse types of the first scanning signal Vout1 and the second scanning signal Vout2 may be set as needed, and the embodiment of the present invention is not limited to this.

[0088] The process of the input signal SIN and the light emitting control signal EM controlling the pulse width of the second scanning signal Vout2 may be: the input signal SIN controls the pulse start time of the second scanning signal Vout2, and the light emitting control signal EM controls the pulse end time of the second scanning signal Vout2.

[0089] The control process of the gate drive circuit is briefly described below in conjunction with a possible implementation manner. Figure 5 is a schematic diagram of the structure of another gate drive circuit provided by an embodiment of the present invention. Figure 5, exemplarily, the node potential control module 10 controls the potentials of the first control terminal N1 and the second control terminal N2 in response to the first clock signal SCK1, the second clock signal SCK2, the input signal SIN, the first potential signal VGL and the second potential signal VGH. The first output module 20 determines whether to output the second clock signal SCK2 as the first scanning signal Vout1 in response to the potential of the first control terminal N1, and determines whether to output the second potential signal VGH as the first scanning signal Vout1 in response to the potential of the second control terminal N2. The pulse width modulation module 30 determines whether to transmit the potential of the second control terminal N2 to the fourth control terminal N4 in response to the second clock signal SCK2 and the light emitting control signal EM. The second output module 40 determines whether to output the second potential signal VGH as the second scanning signal Vout2 in response to the potential of the third control terminal N3, and determines whether to output the first potential signal VGL as the second scanning signal Vout2 in response to the first clock signal SCK1 and the potential of the fourth control terminal N4.

[0090] Wherein, the first potential signal VGL and the second potential signal VGH can both be direct current voltage signals, and the logic of the first potential signal VGL and the second potential signal VGH is opposite, for example, the first potential signal VGL is a low potential signal, and the second potential signal VGH is a high potential signal. The first clock signal SCK1 and the second clock signal SCK2 are both clock signals that alternate between high potential and low potential. The frequencies of the first clock signal SCK1 and the second clock signal SCK2 can be the same, and the phases can be opposite. The input signal SIN can be a pulse signal whose effective potential is a first potential (for example, a low potential). The light-emitting control signal EM can be a pulse signal whose off pulse is a high potential. The off pulse width of the light-emitting control signal EM can be greater than the effective potential pulse width of the input signal SIN, and the pulse effective time of the input signal SIN is within the off pulse effective time of the light-emitting control signal EM. Based on the above control process, the first scanning signal Vout1 output by the gate drive circuit can be a scanning signal whose on pulse is a first potential (for example, a low potential) obtained after the input signal SIN is shifted, and the second scanning signal Vout2 can be a scanning signal whose on pulse is a second potential (for example, a high potential). For example, the first scanning signal Vout1 can be used as Figure 1 The scanning signal S2 required by the pixel circuit, the second scanning signal Vout2 can be used as Figure 1 The scanning signal S1 or the scanning signal S3 required by the pixel circuit.

[0091] The process of the input signal SIN and the light-emitting control signal EM controlling the pulse width of the second scanning signal Vout2 may be: the effective potential pulse start time of the input signal SIN controls the on-pulse start time of the second scanning signal Vout2, and the off-pulse end time of the light-emitting control signal EM controls the on-pulse end time of the second scanning signal Vout2. For example, during the time when the effective potential (for example, it may be a low potential) of the input signal SIN is maintained, in conjunction with the control of the first clock signal SCK1 and the second clock signal SCK2, the node potential control module 10 controls the potential of the third control terminal N3 by controlling the potential jump of the first control terminal N1, thereby controlling the time when the second output module 40 outputs the second potential (for example, it may be a high potential) of the second potential signal VGH, so as to realize the control of the pulse start time of the second scanning signal Vout2. During the period when the effective potential pulse of the input signal SIN ends and the off-pulse of the light-emitting control signal EM still continues, the node potential control module 10 maintains the potential of the first control terminal N1 to maintain the output state of the second scanning signal Vout2 unchanged. And, after the off pulse of the light-emitting control signal EM ends, in conjunction with the control of the second clock signal SCK2, the pulse width modulation module 30 controls the time when the second output module 40 outputs the first potential (for example, it can be a low potential) of the first potential signal VGL by controlling the potential jump of the fourth control terminal N4, so as to realize the control of the end time of the pulse of the second scanning signal Vout2. In other words, the length of time between the start time of the effective potential pulse of the input signal SIN and the end time of the off pulse of the light-emitting control signal EM determines the pulse width of the second scanning signal Vout2. It should be noted that the pulse width of the second scanning signal Vout2 can refer to the on-pulse width of the second scanning signal Vout2, the pulse start time of the second scanning signal Vout2 is its on-pulse start time, and the pulse end time of the second scanning signal Vout2 is its on-pulse end time.

[0092] Then, by adjusting the corresponding relationship between the effective potential pulse of the input signal SIN and the off pulse of the light-emitting control signal EM, the on pulse width of the second scanning signal Vout2 can be adjusted. Alternatively, by adjusting the off pulse width of the light-emitting control signal EM itself, the on pulse width of the second scanning signal Vout2 can also be adjusted; wherein, the off pulse width of the light-emitting control signal EM can be adjusted by the light-emitting control driving circuit; illustratively, the light-emitting control driving circuit can adopt the 10T3C or 13T3C architecture commonly used in the industry, and its specific structure is not limited here.

[0093] The gate drive circuit provided by the embodiment of the present invention provides a new drive architecture. Through the setting of the node potential control module 10, the first output module 20, the pulse width adjustment module 30 and the second output module 40, a gate drive circuit can output two scan signals. Among them, the pulse width of the second scan signal Vout2 is adjustable, and its actual pulse width is determined based on the corresponding relationship between the input signal SIN and the light-emitting control signal EM, so that the gate drive circuit can provide two types of scan signals with different pulse widths, which is conducive to the realization of a narrow frame on the basis of meeting the driving requirements of the pixel circuit. Specifically, the node potential control module 10 is used for controlling the first output module 20, and is also used together with the pulse width adjustment module 30 to control the second output module 40, so that the node potential control module 10 realizes multiplexing in the output control process of the two types of scan signals (or the potentials of the two nodes of the first control terminal N1 and the second control terminal N2 are multiplexed). Compared with the need to provide two groups of gate drive circuits in the prior art, the embodiment of the present invention simplifies the structure of the gate drive circuit as a whole, which is conducive to reducing the frame of the display panel. Furthermore, the light emitting control signal EM is provided by the original light emitting control driving circuit in the display panel, and no additional pulse width control signal is required, which is conducive to further simplifying the circuit structure. Therefore, compared with the prior art, the embodiment of the present invention can simplify the structure of the gate driving circuit, which is conducive to realizing the narrow frame design of the display panel.

[0094] The following describes the possible structures of each functional module in the gate drive circuit. Figure 6 is a schematic diagram of the structure of another gate drive circuit provided by an embodiment of the present invention. Figure 6 In one implementation, optionally, the node potential control module 10 includes: a first input unit 11. The first input unit 11 is electrically connected to the first control terminal N1, and receives an input signal SIN and a first clock signal SCK1.

[0095] Optionally, the node potential control module 10 further includes: a potential control unit 12. The potential control unit 12 is electrically connected to the second control terminal N2, and receives the first clock signal SCK1 and the first potential signal VGL.

[0096] Optionally, the node potential control module 10 further includes: a first node mutual control unit 13. The first node mutual control unit 13 is electrically connected to the first control terminal N1 and the second control terminal N2 respectively, and receives the first clock signal SCK1.

[0097] Optionally, the node potential control module 10 further includes: a second node mutual control unit 14. The second node mutual control unit 14 is electrically connected to the first control terminal N1 and the second control terminal N2 respectively, and receives the second clock signal SCK2 and the second potential signal VGH.

[0098] The first input unit 11 is used to respond to the first clock signal SCK1 being turned on and transmit the input signal SIN to the first control terminal N1. The potential control unit 12 is used to respond to the first clock signal SCK1 being turned on and transmit the first potential signal VGL to the second control terminal N2. The first node mutual control unit 13 is used to control the potential of the second control terminal N2 according to the potential of the first control terminal N1, and the second node mutual control unit is used to control the potential of the first control terminal N1 according to the potential of the second control terminal N2. The node potential mutual control of the first control terminal N1 and the second control terminal N2 can be achieved through the two node mutual control units, reducing the possibility of the potential of the first control terminal N1 and the potential of the second control terminal N2 appearing in the middle between the high and low potentials, ensuring that the potentials of the two control terminals are clear, so that the first output module 20 can accurately identify the potentials of the two control terminals, thereby ensuring that the output state of the first output module 20 is accurate, so as to improve the accuracy and stability of the first scan signal Vout1. Specifically, the first node mutual control unit 13 is used to respond to the potential of the first control terminal N1 being turned on and transmit the first clock signal SCK1 to the second control terminal N2. The second node mutual control unit 14 is used for transmitting the second potential signal VGH to the first control terminal N1 in response to the second clock signal SCK2 and the potential conduction of the second control terminal N2.

[0099] Continue to see Figure 6 In one embodiment, optionally, the first output module 20 includes: a first output unit 21 and a second output unit 22. The control end of the first output unit 21 serves as the first control end N1, and the input end is connected to the second clock signal SCK2. The control end of the second output unit 22 serves as the second control end N2, and the input end is connected to the second potential signal VGH. The output end of the second output unit 22 is electrically connected to the output end of the first output unit 21 and serves as the output end of the first output module 20.

[0100] The first output unit 21 is used to control whether the input terminal and the output terminal are connected according to the potential of the first control terminal N1, thereby controlling whether the second clock signal SCK2 is output as the first scanning signal Vout1. The second output unit 22 is used to control whether the input terminal and the output terminal are connected according to the potential of the second control terminal N2, thereby controlling whether the second potential signal VGH is output as the first scanning signal Vout1.

[0101] Continue to see Figure 6 In one embodiment, optionally, the pulse width modulation module 30 includes: a first transmission unit 31 and a second transmission unit 32. The control end of the first transmission unit 31 is connected to the second clock signal SCK2, and the input end of the first transmission unit 31 is electrically connected to the second control end N2.

[0102] The control end of the second transmission unit 32 receives the light emitting control signal EM, the input end of the second transmission unit 32 is electrically connected to the output end of the first transmission unit 31 , and the output end of the second transmission unit 32 is electrically connected to the fourth control end N4 .

[0103] When the first transmission unit 31 is turned on in response to the second clock signal SCK2 and the second transmission unit 32 is turned on in response to the light emitting control signal EM, the potential of the second control terminal N2 is transmitted to the fourth control terminal N4 through the first transmission unit 31 and the second transmission unit 32 .

[0104] Continue to see Figure 6 In one embodiment, optionally, the second output module 40 includes: a coupling unit 41, a third node mutual control unit 42, a third output unit 43 and a fourth output unit 44. The coupling unit 41 is electrically connected to the fourth control terminal N4 and connected to the first clock signal SCK1. The third node mutual control unit 42 is electrically connected to the third control terminal N3 and the fourth control terminal N4 respectively, and connected to the second potential signal VGH. The control end of the third output unit 43 is electrically connected to the third control terminal N3, the input end is connected to the second potential signal VGH, and the output end is electrically connected to the output end of the fourth output unit 44. The control end of the fourth output unit 44 is electrically connected to the fourth control terminal N4, the input end is connected to the first potential signal VGL, and the output end serves as the output end of the second output module 40.

[0105] The coupling unit 41 is used to respond to the potential of the fourth control terminal N4 and couple the potential of the fourth control terminal N4 according to the first clock signal SCK1. The third node mutual control unit 42 is used to respond to the potential of the third control terminal N3 to control whether the second potential signal VGH is transmitted to the fourth control terminal N4. The third output unit 43 is used to control whether the input terminal and the output terminal are connected according to the potential of the third control terminal N3, thereby controlling whether the second potential signal VGH is output as the second scanning signal Vout2. The fourth output unit 44 is used to control whether the input terminal and the output terminal are connected according to the potential of the fourth control terminal N4, thereby controlling whether the first potential signal VGL is output as the second scanning signal Vout2.

[0106] In the prior art, the gate driving circuit, which is used to output the first scanning signal, requires the control of two clock signals and one input signal, and the driving circuit, which is used to output the second scanning signal, requires another two clock signals and one input signal. The signal lines in the display panel are crisscrossed and will affect each other, causing signal delay. The two driving circuits are separately provided with clock signal lines and input signal lines, which will result in a large number of signal lines and serious signal delay. In the embodiment of the present invention, the pulse width modulation module 30 uses the light-emitting control signal EM output by the existing light-emitting control driving circuit in the display panel, and the clock signal connected to the common node potential control module 10. There is no need to provide input signals and clock signals separately for the output control process of the second scanning signal. Compared with the prior art, the number of signal lines can be reduced and the signal delay can be reduced.

[0107] The working process of the gate driving circuit provided by the embodiment of the present invention is described below in conjunction with the driving timing. Figure 7 1 is a driving timing diagram of a gate driving circuit provided by an embodiment of the present invention. Figure 6 and Figure 7 , the driving process of the gate drive circuit includes:

[0108] In the first stage T11, the first clock signal SCK1 and the input signal SIN are at low potential, and the second clock signal SCK2 and the light-emitting control signal EM are at high potential. The first input unit 11 is turned on, and the low potential of the input signal SIN is transmitted to the first control terminal N1, so that the first output unit 21 is turned on, and the high potential of the second clock signal SCK2 is output. The potential control unit 12 is turned on, and the low potential of the first potential signal VGL is transmitted to the second control terminal N2, and the first node mutual control unit 13 is turned on, and the low potential of the first clock signal SCK1 is transmitted to the second control terminal N2, so that the second output unit 22 is turned on, and the high potential of the second potential signal VGH is output. Therefore, the first scanning signal Vout1 is at a high potential. The second node mutual control unit 14 is turned off under the action of the high potential of the second clock signal SCK2. The first transmission unit 31 and the second transmission unit 32 are both turned off, and the low potential of the second control terminal N2 cannot be transmitted to the fourth control terminal N4. The third control terminal N3 is at the same low potential as the first control terminal N1, the third node inter-control unit 42 and the third output unit 43 are both turned on, and the high potential of the second potential signal VGH is transmitted to the fourth control terminal N4 through the third node inter-control unit 42; the third output unit 43 outputs the second potential signal VGH, that is, the second scan signal Vout2 is at a high potential.

[0109] In the second stage T12, the second clock signal SCK2 is at a low potential, and the first clock signal SCK1, the input signal SIN and the light-emitting control signal EM are at a high potential. The first input unit 11 and the potential control unit 12 are turned off under the high potential of the first clock signal SCK1. The first control terminal N1 maintains the low potential of the previous stage, so that the first output unit 21 outputs the low potential of the second clock signal SCK2; the first node mutual control unit 13 is turned on, and the high potential of the first clock signal SCK1 is transmitted to the second control terminal N2, and the second output unit 22 is controlled to be turned off and has no output. Therefore, the first scan signal Vout1 is at a low potential. The second node mutual control unit 14 is turned off under the high potential of the second control terminal N2. The second transmission unit 32 is turned off, and the high potential of the second control terminal N2 cannot be transmitted to the fourth control terminal N4. The third control terminal N3 is at the same low potential as the first control terminal N1, the third node inter-control unit 42 and the third output unit 43 are both turned on, and the high potential of the second potential signal VGH is transmitted to the fourth control terminal N4 through the third node inter-control unit 42; the third output unit 43 outputs the second potential signal VGH, that is, the second scan signal Vout2 is at a high potential.

[0110] In the third stage T13, the first clock signal SCK1 is at a low potential, and the second clock signal SCK2, the input signal SIN and the light-emitting control signal EM are at a high potential. The first input unit 11 is turned on, and the high potential of the input signal SIN is transmitted to the first control terminal N1, so that the first output unit 21 is turned off and has no output. The potential control unit 12 is turned on, and the low potential of the first potential signal VGL is transmitted to the second control terminal N2, so that the second output unit 22 is turned on, and the high potential of the second potential signal VGH is output. Therefore, the first scanning signal Vout1 is at a high potential. The first node mutual control unit 13 is turned off under the high potential of the first control terminal N1. The second node mutual control unit 14 is turned off under the high potential of the second clock signal SCK2. The first transmission unit 31 and the second transmission unit 32 are both turned off, and the low potential of the second control terminal N2 cannot be transmitted to the fourth control terminal N4. The fourth control terminal N4 maintains the high potential of the previous stage, and the fourth output unit 44 is turned off. The third control terminal N3 is at the same high potential as the first control terminal N1, the third node mutual control unit 42 is turned off, and the third output unit 43 is turned off. The second scan signal Vout2 maintains the high potential of the previous stage.

[0111] In the fourth stage T14, the second clock signal SCK2 is at a low potential, and the first clock signal SCK1, the input signal SIN and the light-emitting control signal EM are at a high potential. The second control terminal N2 maintains the low potential of the previous stage, controls the second output unit 22 to be turned on, and outputs the high potential of the second potential signal VGH. The low potential of the second control terminal N2 and the second clock signal SCK2 jointly control the second node mutual control unit 14 to be turned on, transmit the high potential of the second potential signal VGH to the first control terminal N1, and control the first output unit 21 to be turned off and have no output. Therefore, the first scanning signal Vout1 is at a high potential. The second transmission unit 32 is turned off, and the low potential of the second control terminal N2 cannot be transmitted to the fourth control terminal N4. The fourth control terminal N4 maintains the high potential of the previous stage, and the fourth output unit 44 is turned off. The third control terminal N3 is the same high potential as the first control terminal N1, the third node mutual control unit 42 is turned off, and the third output unit 43 is turned off. The second scanning signal Vout2 maintains the high potential of the previous stage.

[0112] During the subsequent period when the light-emitting control signal EM still maintains a high potential (i.e., before the end of the first off-pulse stage T31 of the light-emitting control signal EM), the driving process of the gate drive circuit repeats the third stage T13 and the fourth stage T14, and the first scanning signal Vout1 and the second scanning signal Vout2 both maintain a high potential until the light-emitting control signal EM becomes a low potential and enters the fifth stage T15 (and simultaneously enters the first on-pulse stage T32 of the light-emitting control signal EM).

[0113] In the fifth stage T15, the second clock signal SCK2 and the light-emitting control signal EM are at a low potential, and the first clock signal SCK1 and the input signal SIN are at a high potential. Since the input signal SIN still maintains a high potential without change, the control process of the node potential control module 10 is still the same as that in the fourth stage T14, the second control terminal N2 is still at a low potential, the second output unit 22 is controlled to be turned on, and the high potential of the second potential signal VGH is output. The first control terminal N1 is still at a high potential, and the first output unit 21 is controlled to be turned off without output. Therefore, the first scan signal Vout1 is still at a high potential. The third control terminal N3 is the same high potential as the first control terminal N1, the third node mutual control unit 42 is turned off, and the third output unit 43 is turned off without output. The first transmission unit 31 and the second transmission unit 32 are both turned on, the low potential of the second control terminal N2 is transmitted to the fourth control terminal N4, the fourth output unit 44 starts to turn on, the first potential signal VGL starts to be output through the fourth output unit 44, and the potential of the second scan signal Vout2 decreases. At this time, the coupling unit 41 stores the high potential of the first clock signal SCK1 and the potential of the fourth control terminal N4.

[0114] In the sixth stage T16, the first clock signal SCK1 and the light-emitting control signal EM are at low potential, and the second clock signal SCK2 and the input signal SIN are at high potential. Since the input signal SIN still maintains a high potential without change, the control process of the node potential control module 10 is still the same as that in the third stage T13, the second control terminal N2 is still at a low potential, the first control terminal N1 is still at a high potential, and the first scanning signal Vout1 is still at a high potential. The third control terminal N3 is at the same high potential as the first control terminal N1, the third node mutual control unit 42 is turned off, and the third output unit 43 is turned off and has no output. The first transmission unit 31 is turned off, and the low potential of the second control terminal N2 does not affect the potential of the fourth control terminal N4. Since the first clock signal SCK1 changes from a high potential to a low potential, the coupling unit 41 couples the potential change to the fourth control terminal N4, so that the potential of the fourth control terminal N4 further decreases, and the fourth output unit 44 is fully turned on, and the first potential signal VGL is output as the second scanning signal Vout2.

[0115] During the subsequent period when the light-emitting control signal EM still maintains a low potential (i.e., before the end of the first on-pulse stage T32 of the light-emitting control signal EM), since the input signal SIN and the light-emitting control signal EM no longer change, the potential changes of each control terminal in the gate drive circuit repeat the fifth stage T15 and the sixth stage T16, the first scanning signal Vout1 maintains a high potential, and the second scanning signal Vout2 maintains a low potential, until the light-emitting control signal EM becomes a high potential again, that is, entering the second off-pulse stage T33 of the light-emitting control signal EM.

[0116] In the second off pulse stage T33 of the light emitting control signal EM, since the input signal SIN still maintains a high potential without change, the control process of the node potential control module 10 still repeats the control process of the third stage T13 and the fourth stage T14, the second control terminal N2 still maintains a low potential, the first control terminal N1 still maintains a high potential, and the first scanning signal Vout1 still maintains a high potential. The third control terminal N3 is the same high potential as the first control terminal N1, the third node mutual control unit 42 is turned off, and the third output unit 43 is turned off without output. Since the light emitting control signal EM is a high potential, the second transmission unit 32 is turned off, the potential of the second control terminal N2 does not affect the potential of the fourth control terminal N4, and the second scanning signal Vout2 continues to be a low potential.

[0117] In the second on-pulse stage T34 of the light-emitting control signal EM, since the input signal SIN still maintains a high potential without change, the second control terminal N2 still maintains a low potential, the first control terminal N1 still maintains a high potential, and the first scanning signal Vout1 still maintains a high potential. The third control terminal N3 is at the same high potential as the first control terminal N1, the third node mutual control unit 42 is turned off, and the third output unit 43 is turned off and has no output. Although the low potential of the light-emitting control signal EM controls the second transmission unit 32 to be turned on, since the potential of the second control terminal N2 always maintains a low potential, the control process of the second output module 40 in this stage is still the same as the control process after the sixth stage T16 in the first on-pulse stage T32, and the second scanning signal Vout2 still maintains a low potential.

[0118] In summary, as long as the input signal SIN does not jump back to a low potential, the potential change of the light-emitting control signal EM will no longer affect the output state of the second scanning signal Vout2. In other words, no matter how many pulses the light-emitting control signal EM continues to have, as long as the input signal SIN does not jump, the first scanning signal Vout1 will maintain a high potential and the second scanning signal Vout2 will maintain a low potential.

[0119] It can be seen that the gate drive circuit realizes the shift output of the input signal SIN, and obtains the second scanning signal Vout2 whose on-pulse width is the same as the off-pulse width of the light-emitting control signal EM. Moreover, when the input signal SIN is a low-frequency signal, even if the light-emitting control signal EM is a high-frequency signal, the first scanning signal Vout1 and the second scanning signal Vout2 are both low-frequency signals, which meets the requirements of low-frequency driving of the LTPO pixel circuit. For example, for Figure 7 The pixel circuit connected to the light emitting control signal EM, Figure 7 The first off pulse phase T31 and the first on pulse phase T32 in the embodiment may correspond to a refresh frame, Figure 7 The second off-pulse phase T33 and the second on-pulse phase T34 in the embodiment may correspond to the holding frame.

[0120] When the input signal SIN is the same high-frequency signal as the light-emitting control signal, Figure 6 The driving timing of the gate drive circuit shown can be found in Figure 8 ,according to Figure 8 It can be seen that if the effective potential pulse of the input signal SIN comes again at the same time as the second off pulse stage T33 of the light emitting control signal EM, the driving process T41-T46 of the gate driving circuit repeats the driving process of stage T11-T16. That is, when the input signal SIN and the light emitting control signal EM are both high-frequency signals, the first scanning signal Vout1 and the second scanning signal Vout2 are also high-frequency signals, which meets the requirements of high-frequency driving of the LTPO pixel circuit. Then, Figure 8 The first off pulse phase T31 and the first on pulse phase T32 in the embodiment may correspond to a refresh frame. Figure 8 The second off-pulse phase T33 and the second on-pulse phase T34 in the embodiment may correspond to the next refresh frame.

[0121] like Figure 8 As shown in FIG. 1 , when the effective potential pulse of the input signal SIN starts at the same time as the off pulse of the light emitting control signal EM, so that the on pulse width of the second scanning signal Vout2 is the same as the off pulse width of the light emitting control signal EM, a pixel circuit in the display panel can be provided with Figure 3 The driving timing in. Specifically, the second scanning signal Vout2 output by a certain gate driving circuit and the light emitting control signal EM connected to the gate driving circuit are connected to the same row of pixel circuits, and the second scanning signal Vout2 is used as the scanning signal S3 of the pixel circuit in the row; and the first scanning signal Vout1 and the second scanning signal Vout2 output by the same gate driving circuit are connected to different rows of pixel circuits, for example, the second scanning signal Vout2 output by the gate driving circuit of this level is used as the scanning signal S3 of the pixel circuit in this row, and the first scanning signal Vout1 output by the gate driving circuit of this level is used as the scanning signal S2 of the pixel circuit in the previous row. Then, another set of gate driving circuits needs to be provided in the display panel to provide the scanning signal S1. That is to say, a total of three sets of driving circuits need to be set up in the display panel, which can reduce one set of driving circuits compared with the prior art.

[0122] On the basis of the above-mentioned embodiments, if the transistor M22 in the pixel circuit is connected to the second electrode of the driving transistor DTFT and replaced by a P-type transistor, the scanning signal S1 is correspondingly replaced by a scanning signal with a low potential in the conduction pulse. Since multiple gate driving circuits are cascaded in the display panel (the first scanning signal Vout1 output by the gate driving circuit of this stage can be used as the input signal SIN of the gate driving circuit of the next stage), illustratively, different levels of first scanning signals Vout1 can be used as the scanning signal S1 and the scanning signal S2 of the same row of pixel circuits, respectively, without providing an additional set of gate driving circuits for generating the scanning signal S1, so as to further reduce the number of driving circuit groups.

[0123] The above-mentioned embodiments exemplify the case where the on-pulse width of the second scanning signal is the same as the off-pulse width of the light-emitting control signal, but this is not intended to limit the present invention. In other embodiments, the on-pulse width of the second scanning signal can be controlled to be smaller than the off-pulse width of the light-emitting control signal. Fig. 9 FIG. 1 is a driving timing diagram of another gate driving circuit provided by an embodiment of the present invention. Fig. 9 ,and Figure 7 and Figure 8The difference in the drive timing is that Fig. 9 The effective potential pulse of the input signal SIN and the off pulse of the light-emitting control signal EM do not start at the same time, but the effective potential pulse of the input signal SIN appears later than the off pulse of the light-emitting control signal EM. Then, the start time of the on pulse of the second scanning signal Vout2 generated under the timing control is later than the start time of the off pulse of the light-emitting control signal EM, but the end time of the on pulse of the second scanning signal Vout2 is still the same as the end time of the off pulse of the light-emitting control signal EM, so that the on pulse width of the second scanning signal Vout2 is smaller than the off pulse width of the light-emitting control signal EM.

[0124] Specifically, when the input signal SIN and the first clock signal SCK1 are both at a low potential, the on-pulse of the second scanning signal Vout2 begins, and when the light-emitting control signal EM and the second clock signal SCK2 are both at a low potential, the on-pulse of the second scanning signal Vout2 ends. By reasonably setting the start time of the effective potential pulse of the input signal SIN, and the coordination of the first scanning signal, the second scanning signal and the light-emitting control signal at each level, the output signal of the gate drive circuit can meet Figure 2 Control requirements for the pixel circuit driving process shown.

[0125] Several ways of providing the driving control signal in the pixel circuit are described below, but are not intended to limit the present invention.

[0126] Fig.10 is a driving timing diagram of another gate driving circuit provided by an embodiment of the present invention. For example, Fig.10 The input and output signals of the gate drive circuits from the nth stage to the n+2th stage are given in FIG. Fig.10 By way of example, taking the pixel circuit (for example, the pixel circuit of the n+2th row) connected to the light emitting control signal EM(n+2) connected to the n+2th level gate driving circuit as an example, the connection relationship between the relevant signals of the gate driving circuit and the pixel circuit is explained.

[0127] See also Fig.10In one embodiment, optionally, the first scanning signal and the second scanning signal output by the same gate driving circuit, and the light-emitting control signal connected to the gate driving circuit can be transmitted to the same row of pixel circuits. Exemplarily, the n+2-th level light-emitting control signal EM(n+2) is used as the light-emitting control signal in the n+2-th row of pixel circuits, the n+2-th level first scanning signal Vout1(n+2) can be used as the scanning signal S2 of the n+2-th row of pixel circuits, and the n+2-th level second scanning signal Vout2(n+2) can be used as the scanning signal S3 of the n+2-th row of pixel circuits. In addition, the second scanning signal Vout2 output by the previous-stage gate driving circuit can also be connected to the row of pixel circuits and used as the scanning signal S1 of the row of pixel circuits, for example, the n-th level second scanning signal Vout2(n) is used as the scanning signal S1 of the n+2-th row of pixel circuits. In this way, the on-pulse time of the second scanning signal Vout2(n) of the nth level serves as the initialization phase T211(n+2) of the pixel circuit of the n+2th row, the on-pulse time of the first scanning signal Vout1(n+2) of the n+2th level serves as the data writing phase T212(n+2) of the pixel circuit of the n+2th row, and when the off-pulse of the n+2th level light-emitting control signal EM(n+2) ends, the light-emitting phase T22(n+2) of the pixel circuit of the n+2th row begins. It can be seen that in order to drive the LTPO pixel circuit, only two groups of driving circuits, namely the light-emitting control driving current and the gate driving circuit, need to be set in the display panel, which is conducive to the realization of a narrow frame.

[0128] In another embodiment, optionally, at least one of the first scanning signal Vout1 and the second scanning signal Vout2 output by the same gate driving circuit, and the light emitting control signal EM connected to the gate driving circuit can be connected to different rows of pixel circuits with other signals; in other words, the scanning signal S2, the scanning signal S3 and the light emitting control signal required by the same row of pixel circuits can be provided by related signals of at least two stages of gate driving circuits. The following is a detailed description.

[0129] Fig.11 This is a driving timing diagram of another gate driving circuit provided in an embodiment of the present invention. Taking the light-emitting control signal EM(n+2) connected to the n+2-th row of pixel circuits connected to the n+2-th level gate driving circuit as an example, at this time, any one of the n-th level second scanning signal Vout2(n), the n+1-th level second scanning signal Vout2(n+1) and the n+2-th level second scanning signal Vout2(n+2) can be used as the scanning signal S3 in the n+2-th row of pixel circuits.

[0130] See also Fig.11, when the n+1th level second scanning signal Vout2(n+1) is used as the scanning signal S3 in the n+2th row pixel circuit, the nth level first scanning signal Vout1(n) can be used as the scanning signal S2 in the n+2th row pixel circuit, that is, the on-pulse time of the nth level first scanning signal Vout1(n) is used as the data writing stage T212(n+2) in the driving process of the n+2th row pixel circuit. The scanning signal S1 in the n+2th row pixel circuit can be provided in the time period between the start of the off-pulse of the n+2th level light emitting control signal EM(n+2) and the start of the on-pulse of the nth level first scanning signal Vout1(n); when the on-pulse of the scanning signal S1 is at a low potential, the n-1th level first scanning signal Vout1(n-1) can be used as the scanning signal S1 in the n+2th row pixel circuit.

[0131] Alternatively, when the n+1-th level second scanning signal Vout2(n+1) is used as the scanning signal S3 in the n+2-th row pixel circuit, the n+1-th level first scanning signal Vout1(n+1) or the n+2-th level first scanning signal Vout1(n+2) can also be used as the scanning signal S2 in the n+2-th row pixel circuit. In short, the conduction pulses of the scanning signal S1 and the scanning signal S3 in the pixel circuit are controlled to be within the turn-off pulse of the light-emitting control signal EM in the pixel circuit, the conduction pulse of the scanning signal S2 in the pixel circuit is controlled not to overlap with the conduction pulse of the scanning signal S1, and the conduction pulse of the scanning signal S2 is controlled to overlap with the conduction pulse of the scanning signal S3, so that the pixel circuit can be driven correctly, and the specific connection relationship between the gate driving circuits of each level and the pixel circuits of each row can be matched according to actual needs. Among them, the conduction pulses of the scanning signal S1 and the scanning signal S3 of the pixel circuit in the same row can overlap or not overlap.

[0132] The above-mentioned embodiments exemplarily illustrate the constituent units of the gate driving circuit and their functioning processes. Next, the specific structure that each functional unit may have will be described.

[0133] Fig.12 is a schematic diagram of the structure of another gate drive circuit provided by an embodiment of the present invention. Fig.12In one embodiment, optionally, the first input unit 11 includes: a first transistor M1; the gate of the first transistor M1 is connected to the first clock signal SCK1, the first electrode is connected to the input signal SIN, and the second electrode is electrically connected to the first control terminal N1. The potential control unit 12 includes: a second transistor M2; the gate of the second transistor M2 is connected to the first clock signal SCK1, the first electrode is connected to the first potential signal VGL, and the second electrode is electrically connected to the second control terminal N2. The first node mutual control unit 13 includes: a third transistor M3; the gate of the third transistor M3 is electrically connected to the first control terminal N1, the first electrode is connected to the first clock signal SCK1, and the second electrode is electrically connected to the second control terminal N2. The second node mutual control unit 14 includes: a fourth transistor M4 and a fifth transistor M5; the gate of the fourth transistor M4 is electrically connected to the second control terminal N2, the first electrode is connected to the second potential signal VGH, and the second electrode is electrically connected to the first electrode of the fifth transistor M5; the gate of the fifth transistor M5 is connected to the second clock signal SCK2, and the second electrode is electrically connected to the first control terminal N1.

[0134] Continue to see Fig.12 In one embodiment, optionally, the first output unit 21 includes: a sixth transistor M6 and a first capacitor C1. The gate of the sixth transistor M6 serves as the first control terminal N1 and is electrically connected to the first terminal of the first capacitor C1; the first electrode of the sixth transistor M6 is connected to the second clock signal SCK2; the second electrode of the sixth transistor M6 is electrically connected to the second terminal of the first capacitor C1 and serves as the output terminal of the first output unit 21. The first capacitor C1 is used to stabilize the gate potential of the sixth transistor M6 and couple the potential of the second electrode of the sixth transistor M6.

[0135] Further, the first output unit 21 may also include: an eighth transistor M8; the gate of the eighth transistor M8 is connected to the first potential signal VGL, the first electrode of the eighth transistor M8 serves as the first control terminal N1, and the second electrode (node ​​N7) of the eighth transistor M8 is electrically connected to the gate of the sixth transistor M6. In this embodiment, the first electrode and the second electrode of the eighth transistor M8 are respectively connected to the first control terminal N1 and the gate of the sixth transistor M6, so that when the potential of the first control terminal N1 jumps, the large cross-voltage between the node N7 and the first control terminal N1 can be reduced, thereby increasing circuit reliability.

[0136] The second output unit 22 includes: a seventh transistor M7 and a second capacitor C2. The gate of the seventh transistor M7 serves as the second control terminal N2 and is electrically connected to the first terminal of the second capacitor C2; the first electrode of the seventh transistor M7 is connected to the second potential signal VGH and is electrically connected to the second terminal of the second capacitor C2; the second electrode of the seventh transistor M7 serves as the output terminal of the second output unit 22. The second capacitor C2 is used to stabilize the gate potential of the seventh transistor M7.

[0137] In summary, the embodiment of the present invention provides a specific structure of the node potential control module 10 and the first output module 20, which can realize the shift output of the input signal SIN.

[0138] Continue to see Fig.12 In one implementation, optionally, the first transmission unit 31 includes a ninth transistor M9; the gate of the ninth transistor M9 is connected to the second clock signal SCK2, the first electrode is electrically connected to the second control terminal N2, and the second electrode (node ​​N6) serves as the output terminal of the first transmission unit 31. The second transmission unit 32 includes a tenth transistor M10; the gate of the tenth transistor M10 is connected to the light emitting control signal EM, the first electrode is electrically connected to the second electrode of the ninth transistor M9, and the second electrode serves as the output terminal of the second transmission unit 32. In this embodiment, both transmission units are configured to be composed of one transistor, so that the circuit structure is simple.

[0139] Continue to see Fig.12 In one implementation, optionally, the coupling unit 41 includes: a coupling subunit 411 and a switch subunit 412. The control end of the switch subunit 412 is electrically connected to the fourth control end N4, the input end of the switch subunit 412 is connected to the first clock signal SCK1, the output end of the switch subunit 412 is electrically connected to the first end (node ​​N5) of the coupling subunit 411, and the second end of the coupling subunit 411 is electrically connected to the fourth control end N4.

[0140] The coupling subunit 411 is used to couple and control the potential of the fourth control terminal N4 according to the potential of the node N5. For example, when the fourth control terminal N4 and the node N5 are both written with voltage, the coupling subunit 411 stores the potential difference between the two ends (the potential difference can be 0 or not 0); when the potential of the fourth control terminal N4 is vacant, the coupling subunit 411 couples the potential change of the node N5 to the fourth control terminal N4. The switch subunit 411 is used to transmit the first clock signal SCK1 to the node N5 in response to the potential conduction of the fourth control terminal N4. By setting the switch subunit 411, when the fourth output unit 44 is turned off, the switch subunit 411 is turned off, so as to avoid the voltage jump of the first clock signal SCK1 affecting the voltage of the fourth control terminal N4, thereby improving the stability of the voltage of the fourth control terminal N4.

[0141] Further, the coupling subunit 411 includes: a third capacitor C3; a first end of the third capacitor C3 is used as a first end of the coupling subunit 411, and a second end is used as a second end of the coupling subunit 411. The switch subunit 412 includes: an eleventh transistor M11; a gate of the eleventh transistor M11 is used as a control end of the switch subunit 411, a first electrode is used as an input end of the switch subunit 411, and a second electrode is used as an output end of the switch subunit 411.

[0142] Continue to see Fig.12 In one implementation, optionally, the third node mutual control unit 42 includes: a twelfth transistor M12; a gate of the twelfth transistor M12 is electrically connected to the third control terminal N3, a first electrode is connected to the second potential signal VGH, and a second electrode is electrically connected to the fourth control terminal N4.

[0143] The third output unit 43 includes: a thirteenth transistor M13 and a fourth capacitor C4. The gate of the thirteenth transistor M13 serves as a third control terminal N3 and is electrically connected to a first terminal of the fourth capacitor C4; the first electrode of the thirteenth transistor M13 is connected to the second potential signal VGH and is electrically connected to a second terminal of the fourth capacitor C4; the second electrode of the thirteenth transistor M13 serves as an output terminal of the third output unit 41.

[0144] The fourth output unit 44 includes a fourteenth transistor M14 . The gate of the fourteenth transistor M14 serves as a fourth control terminal N4 , a first electrode is connected to the first potential signal VGL, and a second electrode serves as an output terminal of the fourth output unit 42 .

[0145] In summary, the embodiment of the present invention provides a specific structure of the pulse width modulation module 30 and the second output module 40, which achieves the effect of outputting the second scanning signal Vout2 based on the potential of the first control terminal N1, the potential of the second control terminal N2 and the light emitting control signal EM.

[0146] The gate drive circuit provided in the embodiment of the present invention adopts a 14T4C architecture, and requires four control signals, namely, an input signal SIN, a light-emitting control signal EM, a first clock signal SCK1, and a second clock signal SCK2. By means of sharing voltage nodes in the circuit, the simultaneous output of high and low potentials with different pulse widths can be achieved, meeting the driving requirements of the LTPO pixel circuit, and the time for the second scanning signal Vout2 to output a high potential is adjustable, and the wiring method of the display panel and the driving timing of the pixel circuit can be adjusted without changing the structure of the gate driving circuit, so as to facilitate the debugging of the display effect of the screen. When debugging the screen, by debugging the light-emitting control signal EM, the debugging of the second scanning signal Vout2 can be achieved at the same time, without the need to debug the second scanning signal Vout2 separately, thereby improving the debugging efficiency. And by continuously coupling the potential of the fourth control terminal N4 through the coupling unit 41, it can be ensured that the fourth control terminal N4 maintains a low potential, thereby ensuring that the second scanning signal Vout2 outputs the first potential signal VGL for a long time. Compared with existing combination structures such as 20T3C in the industry and the six control signals required, the embodiments of the present invention require less layout space and signals, which can ensure the reliability of the two output scanning signals, and at the same time is conducive to achieving narrow screen borders and low power consumption requirements.

[0147] The above embodiments exemplarily provide a specific structure of a gate drive circuit, but are not intended to limit the present invention. In other embodiments, optionally, Fig.13 As shown, the control signals of the first transmission unit 31 and the second transmission unit 32 can also be swapped, that is, the control end of the first transmission unit 31 is connected to the light-emitting control signal EM, and the control end of the second transmission unit 32 is connected to the second clock signal SCK2. In this way, when both the light-emitting control signal EM and the second clock signal SCK2 are on pulses, the function of transmitting the potential of the second control end N2 to the fourth control end N4 via the pulse width modulation module 30 can also be achieved.

[0148] In order to verify the output effect of the gate drive circuit provided by the embodiment of the present invention, the inventors Fig.12 The specific structure of the gate drive circuit shown in the figure is simulated, and the simulation results are shown in Fig.14 shown. Fig.14 In addition to the input signal SIN, the first clock signal SCK1, the second clock signal SCK2, the light-emitting control signal EM, the first scanning signal Vout1 and the second scanning signal Vout2, the potential changes of each key node in the circuit are also given, that is, the potential VN1 of the first control terminal N1, the potential VN2 of the second control terminal N2, the potential VN3 of the third control terminal N3, the potential VN4 of the fourth control terminal N4, the potential VN5 of the node N5, the potential VN6 of the node N6, and the potential VN7 of the node N7. See Fig.14 It can be seen that the gate driving circuit realizes that in the working state, the first scanning signal Vout1 outputs a low voltage and the second scanning signal Vout2 outputs a high voltage, which can ensure that the pixel circuit is driven normally.

[0149] It should be noted that, for each transistor involved in the above-mentioned embodiments, its first electrode can be called one of the source or the drain, and correspondingly, its second electrode can be called the other of the drain or the source. Since the structure of the transistors in the display panel is symmetrical, no distinction is made between the source and the drain of each transistor.

[0150] It should also be noted that in the above embodiments, each transistor in the gate drive circuit is exemplarily shown as a P-type transistor, which is not a limitation of the present invention. In other embodiments, some or all transistors can be set as N-type transistors as needed.

[0151] An embodiment of the present invention further provides a display panel, comprising a cascade-connected multi-stage light-emitting control driving circuit and a cascade-connected multi-stage gate driving circuit as provided in any embodiment of the present invention, which has corresponding beneficial effects. Fig.15 is a schematic diagram of the structure of a display panel provided by an embodiment of the present invention. Fig.15 The gate driving circuit 100 is used to provide the pixel circuit in the display panel with the gate driving signal (scanning signal) required by it; the light-emitting control driving circuit 200 is used to provide the pixel circuit with the light-emitting control signal EM; the gate driving circuit 100 and the light-emitting control driving circuit 200 can be connected at the same level or across levels. The cascade connection of the gate driving circuits 100 at each level means that the first scanning signal Vout1 output by the gate driving circuit 100 at this level is used as the input signal of the gate driving circuit at the next level. The cascade connection of the light-emitting control driving circuits 200 at each level means that the light-emitting control signal EM at this level is used as the input signal of the light-emitting control driving circuit 200 at the next level.

[0152] Continue to see Fig.15 On the basis of the above embodiments, optionally, the display panel further includes: a first potential signal line 71, a second potential signal line 72, a first input signal line 73, a first clock signal line 74, a second clock signal line 75, a second input signal line 76, a scanning signal line 50, a scanning signal line 60 and a light-emitting control signal line 90. The first potential signal line 21 is used to provide a first potential signal, the second potential signal line 22 is used to provide a second potential signal, the first input signal line 73 is used to provide an input signal required by the first-stage gate driving circuit 100, the first clock signal line 74 is used to provide a first clock signal, the second clock signal line 75 is used to provide a second clock signal, the second input signal line 76 is used to provide an input signal required by the first-stage light-emitting control driving circuit 200, the scanning signal line 50 is used to transmit a first scanning signal Vout1 to the pixel circuit, the scanning signal line 60 is used to transmit a second scanning signal Vout2 to the pixel circuit, and the light-emitting control signal line 90 is used to transmit a light-emitting control signal EM to the pixel circuit.

[0153] Each stage of the gate driving circuit 100 is electrically connected to the first potential signal line 71 and the second potential signal line 72. Each stage of the gate driving circuit 100 is alternately connected to the first clock signal line 74 and the second clock signal line 75. Each stage of the light emitting control driving circuit 200 can also be electrically connected to the first potential signal line 71 and the second potential signal line 72, and each stage of the light emitting control driving circuit 200 is alternately connected to two clock signal lines (not shown here) required by it.

[0154] Optionally, the scanning signal line 60 is used to transmit the second scanning signal Vout2 to the threshold compensation module 140 of the pixel circuit.

[0155] Exemplarily, the second scanning signal output by the gate driving circuit of the same level and the light emitting control signal connected to the gate driving circuit of the same level are transmitted to the pixel circuits of the same row or different rows.

[0156] Optionally, the first scanning signal output by the gate driving circuit of the same level and the light emitting control signal connected to the gate driving circuit of the same level are transmitted to the pixel circuits of the same row or different rows.

[0157] Optionally, the first scanning signal and the second scanning signal output by the gate driving circuit at the same level are transmitted to the pixel circuits in the same row or to the pixel circuits in different rows.

[0158] The specific connection method can be found in the description of the above embodiments and will not be described in detail.

[0159] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A gate drive circuit, characterized in that: include: A node potential control module and a first output module, wherein the first output module includes a first control terminal and a second control terminal; the node potential control module is electrically connected to the first control terminal and the second control terminal respectively, and receives an input signal; the node potential control module is used to control the potentials of the first control terminal and the second control terminal according to the input signal, and the first output module is used to output a first scanning signal according to the potentials of the first control terminal and the second control terminal; a pulse width modulation module and a second output module, the pulse width modulation module is electrically connected to the second control terminal and is connected to the light control signal output by the light control driving circuit; the second output module includes a third control terminal and a fourth control terminal, the third control terminal is electrically connected to the first control terminal, and the fourth control terminal is electrically connected to the output terminal of the pulse width modulation module; the pulse width modulation module is used to control the potential of the fourth control terminal according to the potential of the second control terminal and the light control signal, and the second output module is used to output a second scanning signal according to the potentials of the third control terminal and the fourth control terminal; wherein the pulse width of the second scanning signal is determined based on the input signal and the light control signal; The pulse width modulation module determines whether to transmit the potential of the second control terminal to the fourth control terminal in response to the second clock signal and the light emitting control signal; The pulse width modulation module comprises: A first transmission unit, wherein an input end of the first transmission unit is electrically connected to the second control end; a second transmission unit, wherein an input end of the second transmission unit is electrically connected to an output end of the first transmission unit, and an output end of the second transmission unit is electrically connected to the fourth control end; The control end of the first transmission unit is connected to the second clock signal, and the control end of the second transmission unit is connected to the light-emitting control signal; or the control end of the first transmission unit is connected to the light-emitting control signal, and the control end of the second transmission unit is connected to the second clock signal; The node potential control module controls the potentials of the first control terminal and the second control terminal in response to the first clock signal, the second clock signal, the input signal, the first potential signal and the second potential signal; The first output module responds to the potentials of the first control terminal and the second control terminal to determine whether to output the second potential signal as the first scanning signal and whether to output the second clock signal as the first scanning signal; The second output module responds to the first clock signal, the potential of the third control terminal, and the potential of the fourth control terminal to determine whether to output the first potential signal as the second scanning signal and whether to output the second potential signal as the second scanning signal.

2. The gate driving circuit according to claim 1, characterized in that: The node potential control module comprises: a first input unit, electrically connected to the first control end, and configured to control whether the input signal is transmitted to the first control end according to the first clock signal; a potential control unit, electrically connected to the second control end, and configured to control whether the first potential signal is transmitted to the second control end according to the first clock signal; A first node mutual control unit, electrically connected to the first control end and the second control end respectively, and configured to control whether the first clock signal is transmitted to the second control end according to the potential of the first control end; The second node mutual control unit is electrically connected to the first control end and the second control end respectively, and is used to control whether the second potential signal is transmitted to the first control end according to the second clock signal and the potential of the second control end.

3. The gate driving circuit according to claim 2, characterized in that: The first input unit comprises: a first transistor; a gate of the first transistor is connected to the first clock signal, a first electrode of the first transistor is connected to the input signal, and a second electrode of the first transistor is electrically connected to the first control terminal; And / or, the potential control unit comprises: a second transistor; a gate of the second transistor is connected to the first clock signal, a first electrode of the second transistor is connected to the first potential signal, and a second electrode of the second transistor is electrically connected to the second control terminal; And / or, the first node mutual control unit includes: a third transistor; the gate of the third transistor is electrically connected to the first control terminal, the first electrode of the third transistor is connected to the first clock signal, and the second electrode of the third transistor is electrically connected to the second control terminal; And / or, the second node mutual control unit includes: a fourth transistor and a fifth transistor; the gate of the fourth transistor is electrically connected to the second control terminal, the first electrode of the fourth transistor is connected to the second potential signal, and the second electrode of the fourth transistor is electrically connected to the first electrode of the fifth transistor; the gate of the fifth transistor is connected to the second clock signal, and the second electrode of the fifth transistor is electrically connected to the first control terminal.

4. The gate driving circuit according to claim 1, characterized in that: The first output module comprises: a first output unit, wherein a control end of the first output unit serves as the first control end, and an input end of the first output unit is connected to the second clock signal; A second output unit, wherein the control end of the second output unit serves as the second control end, the input end of the second output unit is connected to a second potential signal, the output end of the second output unit is electrically connected to the output end of the first output unit and serves as the output end of the first output module.

5. The gate driving circuit according to claim 4, characterized in that: The first output unit includes: a sixth transistor and a first capacitor; the gate of the sixth transistor serves as the first control terminal and is electrically connected to the first terminal of the first capacitor; the first electrode of the sixth transistor serves as the input terminal of the first output unit; the second electrode of the sixth transistor serves as the output terminal of the first output unit and is electrically connected to the second terminal of the first capacitor; The second output unit includes: a seventh transistor and a second capacitor; the gate of the seventh transistor serves as the second control terminal and is electrically connected to the first terminal of the second capacitor; the first electrode of the seventh transistor serves as the input terminal of the second output unit and is electrically connected to the second terminal of the second capacitor; the second electrode of the seventh transistor serves as the output terminal of the second output unit.

6. The gate driving circuit according to claim 5, characterized in that: The first output unit further includes: an eighth transistor; the gate of the eighth transistor is connected to the first potential signal, the first electrode of the eighth transistor serves as the first control terminal, and the second electrode of the eighth transistor is electrically connected to the gate of the sixth transistor.

7. The gate driving circuit according to claim 1, characterized in that: The first transmission unit includes a ninth transistor; the gate of the ninth transistor serves as a control terminal of the first transmission unit, the first electrode of the ninth transistor serves as an input terminal of the first transmission unit, and the second electrode of the ninth transistor serves as an output terminal of the first transmission unit; The second transmission unit includes a tenth transistor; the gate of the tenth transistor serves as a control end of the second transmission unit, the first electrode of the tenth transistor serves as an input end of the second transmission unit, and the second electrode of the tenth transistor serves as an output end of the second transmission unit.

8. The gate driving circuit according to claim 1, characterized in that: The second output module comprises: a coupling unit, electrically connected to the fourth control terminal, and configured to respond to the potential of the fourth control terminal and perform coupling control on the potential of the fourth control terminal according to the first clock signal; A third node mutual control unit, electrically connected to the third control terminal and the fourth control terminal respectively, and used for controlling whether the second potential signal is transmitted to the fourth control terminal according to the potential of the third control terminal; a third output unit, electrically connected to the third control terminal, and configured to control whether the second potential signal is output as the second scanning signal according to the potential of the third control terminal; A fourth output unit is electrically connected to the fourth control terminal, and is used to control whether the first potential signal is output as the second scanning signal according to the potential of the fourth control terminal.

9. The gate driving circuit according to claim 8, characterized in that: The coupling unit comprises: a coupling subunit and a switch subunit; The control end of the switch subunit is electrically connected to the fourth control end, the input end of the switch subunit is connected to the first clock signal, the output end of the switch subunit is electrically connected to the first end of the coupling subunit, and the second end of the coupling subunit is electrically connected to the fourth control end.

10. The gate driving circuit according to claim 9, characterized in that: The coupling subunit includes: a third capacitor; the first end of the third capacitor serves as the first end of the coupling subunit, and the second end of the third capacitor serves as the second end of the coupling subunit; The switch subunit includes: an eleventh transistor; the gate of the eleventh transistor serves as the control end of the switch subunit, the first electrode of the eleventh transistor serves as the input end of the switch subunit, and the second electrode of the eleventh transistor serves as the output end of the switch subunit.

11. The gate driving circuit according to claim 8, characterized in that: The third node mutual control unit includes: a twelfth transistor; the gate of the twelfth transistor is electrically connected to the third control terminal, the first electrode of the twelfth transistor is connected to the second potential signal, and the second electrode of the twelfth transistor is electrically connected to the fourth control terminal; The third output unit includes: a thirteenth transistor and a fourth capacitor; the gate of the thirteenth transistor is electrically connected to the third control terminal and the first end of the fourth capacitor respectively; the first electrode of the thirteenth transistor serves as the input end of the third output unit and is electrically connected to the second end of the fourth capacitor; the second electrode of the thirteenth transistor serves as the output end of the third output unit; The fourth output unit includes: a fourteenth transistor; the gate of the fourteenth transistor is electrically connected to the fourth control terminal, the first electrode of the fourteenth transistor serves as the input terminal of the fourth output unit, and the second electrode of the fourteenth transistor serves as the output terminal of the fourth output unit.

12. A display panel, characterized in that: include: A light emitting control driving circuit and a gate driving circuit as described in any one of claims 1 to 11.

13. The display panel according to claim 12, characterized in that: The display panel includes a plurality of the gate driving circuits, and the plurality of the gate driving circuits are cascade-connected, and the first scanning signal output by the gate driving circuit of this stage serves as an input signal of the gate driving circuit of the next stage.

14. The display panel according to claim 13, characterized in that: The display panel also includes a plurality of rows of pixel circuits; The second scanning signal output by the gate driving circuit of the same level and the light emitting control signal connected to the gate driving circuit of the same level are transmitted to the pixel circuits of the same row or different rows; The first scanning signal and the second scanning signal output by the gate driving circuit at the same level are transmitted to the pixel circuits in the same row or to the pixel circuits in different rows.

Images