Electronic device for performing data alignment operations

Abstract

An electronic device includes: a clock divider circuit configured to generate a sampling clock, an alignment clock, and an output clock by dividing the frequency of a write clock; and a data alignment circuit configured to receive input data having any one of a first level to a fourth level in a first operating mode and generate aligned data by aligning the input data in sync with the sampling clock, the alignment clock, and the output clock; and to receive input data having any one of the first level and the fourth level in a second operating mode and generate aligned data by aligning the input data in sync with the sampling clock, the alignment clock, and the sampling clock.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Application No. 10-2021-0082613, filed with the Korean Intellectual Property Office on June 24, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of this disclosure generally relate to an electronic device, and more specifically, an electronic device configured to perform data alignment operations according to operating speed. Background Technology

[0004] Recently, in order to improve the operating speed of semiconductor devices, various schemes have been used for inputting / outputting data consisting of multiple bits per clock cycle. For example, Return-to-Zero (RZ) format, Non-Return-to-Zero (NRZ) format, and Four-Level Pulse Amplitude Modulation (PAM4) format are used.

[0005] In return-to-zero (RZZ) format, when the input / output includes a logic high bit in a multi-bit data set, that bit remains logic high and then immediately returns to logic low. In non-return-to-zero (NRZ) format, both logic high and logic low bits in a multi-bit data set maintain their respective logic levels until the next bit is input. In four-level pulse amplitude modulation (PAM4) format, the data is input / output by modulating the pulse amplitude of the data to four levels, with each pulse inputting / outputting 2 bits of data. In four-level pulse amplitude modulation (PAM4) format, three comparators are used to identify 2-bit data, and this identification is achieved by encoding the output signals of each comparator. Summary of the Invention

[0006] In one embodiment, an electronic device may include: a comparison circuit configured to generate first to third comparison signals by receiving input data having any one of a first to a fourth level in a first operating mode, and to generate a second comparison signal by receiving input data having any one of a first level and a fourth level in a second operating mode; a sampling circuit configured to generate first to third sampled data from the first to third comparison signals in synchronization with a sampling clock in the first operating mode, and to generate second sampled data from the second comparison signal in the second operating mode; and an alignment circuit configured to align the first to third sampled data in synchronization with an alignment clock and an output clock and generate aligned data based on the aligned first to third sampled data, or to align the second sampled data in synchronization with an alignment clock and an output clock and generate aligned data based on the aligned second sampled data.

[0007] In one embodiment, an electronic device may include: a clock divider circuit configured to generate first to fourth sampling clocks, first to fourth alignment clocks, and first and second output clocks by dividing the frequency of a write clock; and a data alignment circuit configured to receive input data having any one of the first to fourth levels in a first operating mode and generate aligned data by aligning the input data synchronously with the first to fourth sampling clocks, the first to fourth alignment clocks, and the first and second output clocks; and to receive input data having any one of the first and fourth levels in a second operating mode and generate aligned data by aligning the input data synchronously with the first to fourth sampling clocks, the first to fourth alignment clocks, and the first and second output clocks. Attached Figure Description

[0008] Figure 1 This is a block diagram illustrating the configuration of an electronic device according to an embodiment of the present disclosure.

[0009] Figure 2 It is a diagram. Figure 1 The diagram shows a block diagram of the configuration of a clock divider circuit included in the electronic device.

[0010] Figure 3 It is a diagram. Figure 2 The circuit diagram shown illustrates the configuration of the clock selection circuit included in the clock divider circuit.

[0011] Figure 4 and Figure 5 It is to help explain Figure 2 The diagram shows the operation of the clock divider circuit.

[0012] Figure 6 It is a diagram. Figure 1 A diagram showing the configuration of the comparator circuit included in the electronic device.

[0013] Figure 7 It is a graph that helps to illustrate the levels of input data and reference voltage in the first operating mode according to an embodiment of the present disclosure.

[0014] Figure 8 It is a graph that helps to illustrate the levels of input data and reference voltage in the second operating mode according to the embodiments of this disclosure.

[0015] Figure 9 It is a diagram. Figure 1 A diagram showing the configuration of the sampling circuit included in the electronic device.

[0016] Figure 10 It is a diagram. Figure 1 A block diagram showing the configuration of alignment circuitry included in the electronic device.

[0017] Figure 11 It is to help explain Figure 10 The table shown illustrates the operation of the encoder.

[0018] Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16 and Figure 17 This is a timing diagram that helps to illustrate the operation of an electronic device according to embodiments of the present disclosure.

[0019] Figure 18 The illustration shows the application according to the implementation method. Figures 1 to 17 A diagram illustrating the configuration of the electronic system of the electronic device shown. Detailed Implementation

[0020] The term "preset" refers to the fact that the value of a parameter is predetermined when it is used in a process or algorithm. Depending on the implementation, the value of the parameter may be set at the start of the process or algorithm or during the execution of the process or algorithm.

[0021] Terms such as "first" and "second" used to distinguish various parts are not limited to parts. For example, the first part can be called the second part, and vice versa.

[0022] When a component is referred to as "coupled" or "connected" to another component, it should be understood that these components may be directly coupled or connected to each other, or coupled or connected to each other through other components placed between them. On the other hand, when a component is referred to as "directly coupled" or "directly connected" to another component, it should be understood that these components are directly coupled or connected to each other without any other components placed between them.

[0023] "Logic high level" and "logic low level" are used to describe the logic level of a signal. A signal having a "logic high level" is different from a signal having a "logic low level". For example, when a signal having a first voltage corresponds to a "logic high level", a signal having a second voltage can correspond to a "logic low level". According to an embodiment, a "logic high level" can be set to a voltage higher than a "logic low level". According to an embodiment, the logic level of a signal can be set to different logic levels or opposite logic levels. For example, a signal having a logic high level can be set to a logic low level according to an embodiment, and a signal having a logic low level can be set to a logic high level according to an embodiment.

[0024] The teachings of this disclosure will be described in more detail below by way of embodiments. These embodiments are merely examples to provide examples of the teachings of this disclosure, and the scope of this disclosure is not limited by these embodiments.

[0025] Some embodiments of this disclosure may relate to an electronic device capable of supporting a first operating mode and a second operating mode, wherein in the first operating mode, during a data alignment operation, the pulse amplitude of the data is adjusted to four levels and each pulse inputs / outputs 2 bits of data, while in the second operating mode, during a data alignment operation, both logic high-level bits and logic low-level bits in the data maintain their logic levels until the time point when the next bit is input.

[0026] According to embodiments of this disclosure, a first operating mode and a second operating mode can be supported. In the first operating mode, during the data alignment operation, the pulse amplitude of the data is adjusted to four levels and each pulse inputs / outputs 2 bits of data. In the second operating mode, during the data alignment operation, both logic high-level bits and logic low-level bits in the data maintain their logic levels until the time point when the next bit is input.

[0027] Furthermore, according to embodiments of this disclosure, the reliability of the data alignment operation can be ensured by selectively executing a first operation mode and a second operation mode based on high-speed operation and low-speed operation during the data alignment operation.

[0028] like Figure 1 As shown, the electronic device 10 according to an embodiment of the present disclosure may include a control circuit 110, a write clock generation circuit 120, a clock divider circuit 130, and a data alignment circuit 140.

[0029] Control circuit 110 can generate a selection signal SEL in both mode register setting operation and test mode. In mode register setting operation, control circuit 110 can generate an enabled selection signal SEL to enter the first operating mode via the mode register setting signal MRS. In mode register setting operation, control circuit 110 can also generate a disabled selection signal SEL to enter the second operating mode via the mode register setting signal MRS. In test mode, control circuit 110 can generate an enabled selection signal SEL to enter the first operating mode via the test mode signal TM. In test mode, control circuit 110 can also generate a disabled selection signal SEL to enter the second operating mode via the test mode signal TM.

[0030] The mode register setting operation can be configured to store and output information used to control the operation of electronic device 10. The test mode can be configured for external devices to test the operation of electronic device 10. The first operating mode can be configured in four-level pulse amplitude modulation (PAM4) format, where each pulse inputs / outputs 2 bits of data by adjusting the pulse amplitude of the data to four levels. The first operating mode can be executed when electronic device 10 is operating at high speed to input / output data. The second operating mode can be configured in a non-return-to-zero format, where both logic high and logic low bits in a multi-bit data sequence maintain their logic levels until the next bit is input. The second operating mode can be executed when electronic device 10 is operating at low speed to input / output data.

[0031] The write clock generation circuit 120 can generate a write clock WCLK and an inverted write clock WCLKB by receiving a clock CLK from an external device of the electronic device 10. The write clock generation circuit 120 can generate a write clock WCLK with the same phase as the clock CLK input from the external device. The write clock generation circuit 120 can also generate an inverted write clock WCLKB with a phase opposite to the clock CLK input from the external device. The clock CLK can be set to periodically change to synchronize the operation of the electronic device 10 with the external device.

[0032] Clock divider circuit 130 can receive selection signal SEL from control circuit 110. Clock divider circuit 130 can receive write clock WCLK and inverted write clock WCLKB from write clock generation circuit 120. Clock divider circuit 130 can generate first to fourth sampling clocks SCLK<1:4>, first to fourth alignment clocks ACLK<1:4>, and first and second output clocks OCLK<1:2> by dividing the frequencies of write clock WCLK and inverted write clock WCLKB according to selection signal SEL. When selection signal SEL is enabled and therefore the first operating mode is executed, clock divider circuit 130 can generate first to fourth sampling clocks SCLK<1:4> by dividing the frequencies of write clock WCLK and inverted write clock WCLKB by 2. When selection signal SEL is enabled and therefore the first operating mode is executed, clock divider circuit 130 can generate first to fourth alignment clocks ACLK<1:4> by dividing the frequencies of write clock WCLK and inverted write clock WCLKB by 2. When the selection signal SEL is enabled and thus the first operating mode is executed, the clock divider circuit 130 can generate the first and second output clocks OCLK<1:2> by dividing the frequencies of the write clock WCLK and the inverted write clock WCLKB by four. When the selection signal SEL is disabled and thus the second operating mode is executed, the clock divider circuit 130 can generate the first to fourth sampling clocks SCLK<1:4> by dividing the frequencies of the write clock WCLK and the inverted write clock WCLKB by two. When the selection signal SEL is disabled and thus the second operating mode is executed, the clock divider circuit 130 can generate the first to fourth aligned clocks ACLK<1:4> by dividing the frequencies of the write clock WCLK and the inverted write clock WCLKB by four. When the selection signal SEL is disabled and thus the second operating mode is executed, the clock divider circuit 130 can generate the first and second output clocks OCLK<1:2> by dividing the frequencies of the write clock WCLK and the inverted write clock WCLKB by eight.

[0033] The data alignment circuit 140 may include a comparison circuit 210, a sampling circuit 220, and an alignment circuit 230.

[0034] In the first operating mode, the comparator circuit 210 can receive input data DIN having any one of the first to fourth levels. In the second operating mode, the comparator circuit 210 can receive input data DIN having any one of the first and fourth levels. The comparator circuit 210 can receive a selection signal SEL from the control circuit 110. In the first operating mode, the comparator circuit 210 can generate a first comparison signal CD1, a second comparison signal CD2, and a third comparison signal CD3 based on the input data DIN having any one of the first to fourth levels. In the second operating mode, the comparator circuit 210 can generate a second comparison signal CD2 based on the input data DIN having any one of the first and fourth levels.

[0035] The sampling circuit 220 can receive a first comparison signal CD1, a second comparison signal CD2, and a third comparison signal CD3 from the comparison circuit 210. The sampling circuit 220 can receive first to fourth sampling clocks SCLK<1:4> from the clock divider circuit 130. In a first operating mode, the sampling circuit 220 can generate first sampled data CSI1<1:4>, second sampled data CSI2<1:4>, and third sampled data CSI3<1:4> synchronously with the first to fourth sampling clocks SCLK<1:4>. In a second operating mode, the sampling circuit 220 can generate second sampled data CSI2<1:4> synchronously with the first to fourth sampling clocks SCLK<1:4> from the second comparison signal CD2.

[0036] Alignment circuit 230 can receive first sampled data CSI1<1:4>, second sampled data CSI2<1:4>, and third sampled data CSI3<1:4> from sampling circuit 220. Alignment circuit 230 can receive first to fourth alignment clocks ACLK<1:4> and first and second output clocks OCLK<1:2> from clock divider circuit 130. In a first operating mode, alignment circuit 230 can synchronize the first sampled data CSI1<1:4>, second sampled data CSI2<1:4>, and third sampled data CSI3<1:4> with the first to fourth alignment clocks ACLK<1:4> and the first and second output clocks OCLK<1:2>. Alignment circuit 230 can generate alignment data AD based on the first sampled data CSI1<1:4>, second sampled data CSI2<1:4>, and third sampled data CSI3<1:4> aligned in the first operating mode. In the second operating mode, the alignment circuit 230 can synchronize the second sampled data CSI2<1:4> with the first to fourth alignment clocks ACLK<1:4> and the first and second output clocks OCLK<1:2>. The alignment circuit 230 can generate alignment data AD based on the second sampled data CSI2<1:4> aligned in the second operating mode.

[0037] In the first operating mode, the data alignment circuit 140 can receive input data DIN having any one of the first to fourth levels from an external device. In the first operating mode, the data alignment circuit 140 can generate aligned data AD by aligning the input data DIN synchronously with the first to fourth sampling clocks SCLK<1:4>, the first to fourth alignment clocks ACLK<1:4>, and the first and second output clocks OCLK<1:2>. In the second operating mode, the data alignment circuit 140 can receive input data DIN having any one of the first and fourth levels from an external device. In the second operating mode, the data alignment circuit 140 can generate aligned data AD by aligning the input data DIN synchronously with the first to fourth sampling clocks SCLK<1:4>, the first to fourth alignment clocks ACLK<1:4>, and the first and second output clocks OCLK<1:2>. Input data DIN, comprising multiple bits input sequentially, can be input serially. Aligned data AD, comprising multiple bits generated simultaneously, can be generated in parallel. The input data DIN having any one of the first to fourth levels in both the first and second operating modes will be referred to later. Figure 7 and Figure 8 Describe it. In Figure 1 The operation of generating alignment data AD from input data DIN in the data alignment circuit 140 shown will be referred to later. Figures 12 to 17 Describe it.

[0038] Figure 2 This is a block diagram illustrating an implementation of the clock divider circuit 130. (As shown...) Figure 2 As shown, the clock divider circuit 130 may include a first divider 131, a second divider 132, a third divider 133, and a clock selection circuit 134.

[0039] The first frequency divider 131 can generate the first to fourth internal clocks ICLK<1:4> by dividing the frequencies of the write clock WCLK and the inverted write clock WCLKB by two. In one embodiment, the first frequency divider 131 can generate the first to fourth internal clocks ICLK<1:4> by dividing the frequency of the write clock WCLK by two. The corresponding first to fourth internal clocks ICLK<1:4> can be generated with a phase difference of 90° (i.e., 90 degrees). The first to fourth internal clocks ICLK<1:4> can be generated with a frequency that is half the frequency of the write clock WCLK.

[0040] The second frequency divider 132 can generate the first to fourth divided clocks DCLK<1:4> by dividing the frequencies of the first to fourth internal clocks ICLK<1:4> by two. The corresponding first to fourth divided clocks DCLK<1:4> can be generated with a 90° phase difference. The first to fourth divided clocks DCLK<1:4> can also be generated with a frequency that is 1 / 4 times the frequency of the write clock WCLK.

[0041] The third frequency divider 133 can divide the third frequency clock DCLK. <3> The frequency is divided by two to generate the first and second pre-output clocks POCLK<1:2>. The corresponding first and second pre-output clocks POCLK<1:2> can be generated with a phase difference of 180°. The first and second pre-output clocks POCLK<1:2> can be generated with a frequency that is 1 / 8 times the frequency of the write clock WCLK.

[0042] Clock selection circuit 134 can generate first to fourth sampling clocks SCLK<1:4> from the first to fourth internal clocks ICLK<1:4>. Clock selection circuit 134 can output the first to fourth internal clocks ICLK<1:4> as the first to fourth sampling clocks SCLK<1:4> in both first and second operating modes. Clock selection circuit 134 can generate first to fourth aligned clocks ACLK<1:4> and first and second output clocks OCLK<1:2> from the first to fourth internal clocks ICLK<1:4>, the first to fourth divided clocks DCLK<1:4>, and the first and second pre-output clocks POCLK<1:2> according to the logic level of the selection signal SEL. The operation of clock selection circuit 134 in generating first to fourth aligned clocks ACLK<1:4> and first and second output clocks OCLK<1:2> from the first to fourth internal clocks ICLK<1:4>, the first to fourth divided clocks DCLK<1:4>, and the first and second pre-output clocks POCLK<1:2> will be described below. Figure 3 Describe it.

[0043] Figure 3 This is a circuit diagram illustrating an implementation of the clock selection circuit 134. (See diagram for example.) Figure 3 As shown, the clock selection circuit 134 may include a sampling clock generation circuit 134_1, an alignment clock generation circuit 134_2, and an output clock generation circuit 134_3.

[0044] The sampling clock generation circuit 134_1 may include a first buffer 150. <1> Second buffer 150 <2> Third buffer 150 <3> and the fourth buffer 150 <4> .

[0045] First buffer 150 <1> The first internal clock ICLK can be buffered. <1> To generate the first sampling clock SCLK <1> .

[0046] Second buffer 150 <2> The second internal clock ICLK can be buffered. <2> To generate the second sampling clock SCLK <2> .

[0047] Third buffer 150 <3> The third internal clock ICLK can be buffered. <3> To generate the third sampling clock SCLK <3> .

[0048] Fourth buffer 150 <4> The fourth internal clock ICLK can be buffered. <4> To generate the fourth sampling clock SCLK <4> .

[0049] The aligned clock generation circuit 134_2 may include a first multiplexer 160 <1> Second multiplexer 160 <2> Third multiplexer 160 <3> and the fourth multiplexer 160 <4> .

[0050] First Multiplexer 160 <1> The second internal clock ICLK can be output based on the logic level of the selection signal SEL. <2> Second frequency divider clock DCLK <2> Any one of them as the first alignment clock ACLK <1> When the selection signal SEL is logic high, the first multiplexer 160... <1> It can output a second internal clock ICLK <2> As the first alignment clock ACLK <1> When the selection signal SEL is logic low, the first multiplexer 160... <1> It can output the second divided clock DCLK <2> As the first alignment clock ACLK <1> .

[0051] Second Multiplexer 160 <2> The third internal clock ICLK can be output based on the logic level of the selection signal SEL. <3> and the third frequency divider clock DCLK <3> Any one of them as the second alignment clock ACLK <2> When the selection signal SEL is logic high, the second multiplexer 160... <2> It can output a third internal clock ICLK <3> As the second alignment clock ACLK <2> When the selection signal SEL is logic low, the second multiplexer 160... <2> It can output the third divided clock DCLK <3> As the second alignment clock ACLK <2> .

[0052] Third Multiplexer 160 <3> The fourth internal clock ICLK can be output based on the logic level of the selection signal SEL. <4> and the fourth frequency divider clock DCLK <4> Any one of them as the third aligned clock ACLK <3> When the selection signal SEL is logic high, the third multiplexer 160... <3> It can output a fourth internal clock ICLK <4> As the third alignment clock ACLK <3> When the selection signal SEL is logic low, the third multiplexer 160... <3> It can output the fourth frequency divider clock DCLK <4> As the third alignment clock ACLK <3> .

[0053] Fourth Multiplexer 160 <4> The first internal clock ICLK can be output based on the logic level of the selection signal SEL. <1> and the first divided clock DCLK <1> Any one of them as the fourth aligned clock ACLK <4> When the selection signal SEL is logic high, the fourth multiplexer 160... <4> It can output the first internal clock ICLK <1> As the fourth alignment clock ACLK <4> When the selection signal SEL is logic low, the fourth multiplexer 160... <4> It can output the first divided clock DCLK <1> As the fourth alignment clock ACLK <4> .

[0054] The output clock generation circuit 134_3 may include a fifth multiplexer 170. <1> and the sixth multiplexer 170 <2> .

[0055] Fifth Multiplexer 170 <1> The second divided clock DCLK can be output based on the logic level of the selection signal SEL. <2> and the first pre-output clock POCLK <1> Any one of them as the first output clock OCLK <1> When the selection signal SEL is logic high, the fifth multiplexer 170... <1> It can output the second divided clock DCLK <2> OCLK as the first output clock <1> When the selection signal SEL is logic low, the fifth multiplexer 170... <1> It can output the first pre-output clock POCLK <1> OCLK as the first output clock <1> .

[0056] Sixth Multiplexer 170 <2> The fourth frequency divider clock DCLK can be output based on the logic level of the selection signal SEL. <4> Second pre-output clock POCLK <2> Any one of the outputs can be used as the second output clock OCLK <2> When the selection signal SEL is logic high, the sixth multiplexer 170... <2> It can output the fourth frequency divider clock DCLK <4> OCLK as the second output clock <2> When the selection signal SEL is logic low, the sixth multiplexer 170... <2> It can output a second pre-output clock POCLK <2> OCLK as the second output clock <2> .

[0057] Figure 4 This is a diagram illustrating the operation of the clock divider circuit 130 in the first operating mode.

[0058] The control circuit 110 generates a selection signal SEL that is enabled to a logic high level to enter the first operating mode.

[0059] Clock divider circuit 130 generates first to fourth internal clocks ICLK<1:4> by dividing the frequencies of the write clock WCLK and the inverted write clock WCLKB by two. The corresponding first to fourth internal clocks ICLK<1:4> are generated with a 90° phase difference. Clock divider circuit 130 generates first to fourth divided clocks DCLK<1:4> by dividing the frequencies of the write clock WCLK and the inverted write clock WCLKB by four. The corresponding first to fourth divided clocks DCLK<1:4> are generated with a 90° phase difference. Clock divider circuit 130 generates first and second pre-output clocks POCLK<1:2> by dividing the frequencies of the write clock WCLK and the inverted write clock WCLKB by eight. The corresponding first and second pre-output clocks POCLK<1:2> are generated with a 180° phase difference.

[0060] The clock divider circuit 130 generates the first to fourth sampling clocks SCLK<1:4> from the first to fourth internal clocks ICLK<1:4>. Since the first to fourth sampling clocks SCLK<1:4> are generated to have the same frequency and phase as the first to fourth internal clocks ICLK<1:4>, their description will be omitted here.

[0061] The clock divider circuit 130 generates the first to fourth aligned clocks ACLK<1:4> from the first to fourth internal clocks ICLK<1:4> by receiving the logic high-level selection signal SEL. The first to fourth aligned clocks ACLK<1:4> are generated as a frequency that is half the frequency of the write clock WCLK. The clock divider circuit 130 also generates the first to fourth aligned clocks ACLK<1:4> from the second internal clock ICLK. <2> Generate the first aligned clock ACLK <1> The clock divider circuit 130 receives the third internal clock ICLK. <3> Generate a second aligned clock ACLK <2> The clock divider circuit 130 receives the fourth internal clock ICLK. <4> Generate a third aligned clock ACLK <3> The clock divider circuit 130 receives the first internal clock ICLK. <1> Generate the fourth aligned clock ACLK <4> .

[0062] The clock divider circuit 130 receives the second divided clock DCLK from the selection signal SEL, which is a logic high level. <2> and the fourth frequency divider clock DCLK <4> First and second output clocks OCLK<1:2> are generated. The first and second output clocks OCLK<1:2> are generated at a frequency that is 1 / 4 times the frequency of the write clock WCLK. Clock divider circuit 130 divides the second clock DCLK... <2> Generate the first output clock OCLK <1> The clock divider circuit 130 divides the clock frequency from the fourth divided clock, DCLK. <4> Generate the second output clock OCLK <2> .

[0063] Figure 5 This is a diagram to help illustrate the operation of the clock divider circuit 130 in the second operating mode.

[0064] The control circuit 110 generates a selection signal SEL that is disabled to a logic low level to enter the second operating mode.

[0065] Clock divider circuit 130 generates first to fourth internal clocks ICLK<1:4> by dividing the frequencies of the write clock WCLK and the inverted write clock WCLKB by two. The corresponding first to fourth internal clocks ICLK<1:4> are generated with a phase difference of 90°. Clock divider circuit 130 generates first to fourth divided clocks DCLK<1:4> by dividing the frequencies of the write clock WCLK and the inverted write clock WCLKB by four. The corresponding first to fourth divided clocks DCLK<1:4> are generated with a phase difference of 90°. Clock divider circuit 130 generates first and second pre-output clocks POCLK<1:2> by dividing the frequencies of the write clock WCLK and the inverted write clock WCLKB by eight. The corresponding first and second pre-output clocks POCLK<1:2> are generated with a phase difference of 180°.

[0066] The clock divider circuit 130 generates the first to fourth sampling clocks SCLK<1:4> from the first to fourth internal clocks ICLK<1:4>. The first to fourth sampling clocks SCLK<1:4> are generated at a frequency that is half the frequency of the write clock WCLK. Since the first to fourth sampling clocks SCLK<1:4> are generated with the same frequency and phase as the first to fourth internal clocks ICLK<1:4>, a description of them will be omitted here.

[0067] Clock divider circuit 130 generates first to fourth aligned clocks ACLK<1:4> from the first to fourth divided clocks DCLK<1:4> by receiving a logic low-level selection signal SEL. The first to fourth aligned clocks ACLK<1:4> are generated as a frequency that is 1 / 4 times the frequency of the write clock WCLK. <2> Generate the first aligned clock ACLK <1> The clock divider circuit 130 divides the clock frequency from the third divided clock, DCLK. <3> Generate a second aligned clock ACLK <2> The clock divider circuit 130 divides the clock frequency from the fourth divided clock, DCLK. <4> Generate a third aligned clock ACLK <3> The clock divider circuit 130 divides the clock frequency from the first divided clock, DCLK. <1> Generate the fourth aligned clock ACLK <4> .

[0068] Clock divider circuit 130 generates first and second output clocks OCLK<1:2> from first and second pre-output clocks POCLK<1:2> by receiving a logic low-level selection signal SEL. The first and second output clocks OCLK<1:2> are generated at a frequency that is 1 / 8 times the frequency of the write clock WCLK. Clock divider circuit 130 generates the first pre-output clock POCLK from... <1> Generate the first output clock OCLK <1> The clock divider circuit 130 takes the second pre-output clock POCLK as input. <2> Generate the second output clock OCLK <2> .

[0069] Figure 6 This is a block diagram illustrating an implementation of the comparator circuit 210. (Example) Figure 6 As shown, the comparison circuit 210 may include a first comparator 211, a second comparator 212, and a third comparator 213.

[0070] The first comparator 211 can operate when the selection signal SEL is enabled to a logic high level. When the selection signal SEL is input to a logic high level in the first operating mode, the first comparator 211 can generate a first comparison signal CD1 by comparing the first reference voltage VREFH and the input data DIN.

[0071] The second comparator 212 can generate a second comparison signal CD2 by comparing the second reference voltage VREFM and the input data DIN in the first operating mode and the second operating mode.

[0072] The third comparator 213 can operate when the selection signal SEL is enabled at a logic high level. When the selection signal SEL is input at a logic high level in the first operating mode, the third comparator 213 can generate the third comparison signal CD3 by comparing the third reference voltage VREFL and the input data DIN.

[0073] The levels of input data DIN, first reference voltage VREFH, second reference voltage VREFM, and third reference voltage VREFL in the first operating mode will be referenced below. Figure 7 Describe it.

[0074] In the first operating mode, the fourth level of the input data DIN represents a voltage level higher than the level of the first reference voltage VREFH.

[0075] In the first operating mode, the third level of the input data DIN, 3rd LEVEL, represents a voltage level that is lower than the first reference voltage VREFH and higher than the second reference voltage VREFM.

[0076] In the first operating mode, the second level 2nd LEVEL of the input data DIN represents a voltage level that is lower than the second reference voltage VREFM and higher than the third reference voltage VREFL.

[0077] In the first operating mode, the first level of the input data DIN, 1st LEVEL, represents a voltage level lower than the level of the third reference voltage, VREFL.

[0078] The first reference voltage VREFH is a voltage with a level between the fourth level (4th LEVEL) of the input data DIN and the third level (3rd LEVEL) of the input data DIN.

[0079] The second reference voltage VREFM is a voltage with a level between the third level (3rd LEVEL) of the input data DIN and the second level (2nd LEVEL) of the input data DIN.

[0080] The third reference voltage VREFL is a voltage with a level between the second level 2nd LEVEL of the input data DIN and the first level 1st LEVEL of the input data DIN.

[0081] The levels of input data DIN and the second reference voltage VREFM in the second operating mode will be referenced below. Figure 8 Describe it.

[0082] In the second operating mode, the fourth level of input data DIN represents a voltage level higher than the second reference voltage VREFM. The fourth level of input data DIN also indicates that input data DIN is at a logic high. The fourth level of input data DIN also indicates a voltage level higher than the aforementioned reference voltage VREFM. Figure 7 The input data described is the same voltage level as the fourth level (4th LEVEL) of DIN.

[0083] In the second operating mode, the first level (1st LEVEL) of the input data DIN represents a voltage level lower than the second reference voltage VREFM. The first level (1st LEVEL) of the input data DIN indicates that the input data DIN is at a logic low level. The first level (1st LEVEL) of the input data DIN also indicates a voltage level lower than the second reference voltage VREFM. Figure 7 The input data described is the same voltage level as the first level (1st LEVEL) of DIN.

[0084] The second reference voltage VREFM is a voltage with a level between the fourth level (4th LEVEL) of input data DIN and the first level (1st LEVEL) of input data DIN.

[0085] Figure 9 This is a diagram illustrating an implementation of the sampling circuit 220. (See diagram for details.) Figure 9 The sampling circuit 220 may include a first driver 221, a second driver 222, and a third driver 223.

[0086] The first driver 221 can operate when the selection signal SEL is enabled to a logic high level. When the selection signal SEL is input at a logic high level in the first operating mode, the first driver 221 can generate first sampled data CSI1<1:4> from the first comparison signal CD1 in synchronization with the first to fourth sampling clocks SCLK<1:4>. The first bit of the first sampled data CSI1<1:4> is CSI1. <1> With the first sampling clock SCLK <1> Synchronously generated from the first comparison signal CD1, the second bit CSI1 of the first sampled data CSI1<1:4> <2> With the second sampling clock SCLK <2> Synchronously generated from the first comparison signal CD1, the third bit CSI1 of the first sampled data CSI1<1:4> <3> With the third sampling clock SCLK <3> Synchronously generated from the first comparison generation signal CD1, and the fourth bit CSI1 of the first sampled data CSI1<1:4>. <4> With the fourth sampling clock SCLK <4> It is generated synchronously from the first comparison signal CD1. Although the first driver 221 is shown as a single circuit, the number of bits of the first to fourth sampling clock SCLK<1:4> corresponding to the first driver 221 can be implemented by four circuits.

[0087] The second driver 222 can generate second sampled data CSI2<1:4> from the second comparison signal CD2 synchronously with the first to fourth sampling clocks SCLK<1:4> in both the first and second operating modes. The first bit of the second sampled data CSI2<1:4> is CSI2. <1> With the first sampling clock SCLK <1> Synchronously generated from the second comparison signal CD2, the second bit of the second sampled data CSI2<1:4>, CSI2 <2> With the second sampling clock SCLK <2> The third bit CSI2 of the second sampled data CSI2<1:4> is generated synchronously from the second comparison signal CD2. <3> With the third sampling clock SCLK <3> Synchronously generated from the second comparison signal CD2, and the fourth bit of the second sampled data CSI2<1:4>, CSI2 <4> With the fourth sampling clock SCLK <4> It is generated synchronously from the second comparison signal CD2. Although the second driver 222 is shown as a single circuit, the number of bits of the second driver 222 corresponding to the first to fourth sampling clock SCLK<1:4> can be implemented by four circuits.

[0088] The third driver 223 can operate when the selection signal SEL is enabled at a logic high level. When the selection signal SEL is input at a logic high level in the first operating mode, the third driver 223 can generate third sampled data CSI3<1:4> from the third comparison signal CD3 in synchronization with the first to fourth sampling clocks SCLK<1:4>. The first bit of the third sampled data CSI3<1:4> is CSI3. <1> With the first sampling clock SCLK <1> Synchronously generated from the third comparison signal CD3, the second bit of the third sampled data CSI3<1:4>, CSI3 <2> With the second sampling clock SCLK <2> Synchronously generated from the third comparison signal CD3, the third bit CSI3 of the third sampled data CSI3<1:4>. <3> With the third sampling clock SCLK <3> Synchronously generated from the third comparison signal CD3, and the fourth bit CSI3 of the third sampled data CSI3<1:4>. <4> With the fourth sampling clock SCLK <4> It is generated synchronously from the third comparison signal CD3. Although the third driver 223 is shown as a single circuit, the number of bits of the third driver 223 corresponding to the first to fourth sampling clock SCLK<1:4> can be implemented by four circuits.

[0089] Figure 10 This is a block diagram illustrating an embodiment of the alignment circuit 230. (As shown) Figure 10 The alignment circuit 230 may include an encoder 231, a first alignment circuit 232, and a second alignment circuit 233.

[0090] Encoder 231 can generate first to eighth encoded data ED<1:8> by encoding first sampled data CSI1<1:4>, second sampled data CSI2<1:4>, and third sampled data CSI3<1:4> in the first operating mode. When a logic high-level selection signal SEL is input in the first operating mode, encoder 231 can generate first to eighth encoded data ED<1:8> by encoding the first bit CSI1 of the first sampled data CSI1<1:4>. <1> The first bit of the second sampled data CSI2<1:4>, CSI2 <1> The first bit of the third sampled data CSI3<1:4>, CSI3 <1> Encoding is used to generate first and second encoded data ED<1:2>. When a logic high-level selection signal SEL is input in the first operating mode, encoder 231 can generate the second bit CSI1 of the first sampled data CSI1<1:4>. <2> The second bit of the second sampled data CSI2<1:4>, CSI2 <2> The second bit of the third sampled data CSI3<1:4>, CSI3 <2> Encoding is used to generate the third and fourth encoded data ED<3:4>. When the logic high-level selection signal SEL is input in the first operating mode, the encoder 231 can generate the third bit CSI1 of the first sampled data CSI1<1:4>. <3> The third bit of the second sampled data CSI2<1:4>, CSI2 <3> The third bit of the third sampled data CSI3<1:4> <3> Encoding is used to generate the fifth and sixth encoded data ED<5:6>. When the logic high-level selection signal SEL is input in the first operating mode, the encoder 231 can generate the fourth bit CSI1 of the first sampled data CSI1<1:4>. <4> The fourth bit of the second sampled data CSI2<1:4>, CSI2 <4> The fourth bit of the third sampled data CSI3<1:4>, CSI3 <4> The encoding process generates the seventh and eighth encoded data ED<7:8>. The operation of encoder 231 in generating the first to eighth encoded data ED<1:8> by encoding the first sampled data CSI1<1:4>, the second sampled data CSI2<1:4>, and the third sampled data CSI3<1:4> will be referred to later. Figure 11 Describe it.

[0091] In a first operating mode, the first alignment circuit 232 can generate the first to eighth pre-aligned data PAD<1:8> by aligning the first to eighth encoded data ED<1:8>. When the selection signal SEL is input at a logic high level in the first operating mode, the first alignment circuit 232 can generate the first to eighth pre-aligned data PAD<1:8> by aligning the first to eighth encoded data ED<1:8> synchronously with the first to fourth alignment clocks ACLK<1:4>. In a second operating mode, the first alignment circuit 232 can generate the first to eighth pre-aligned data PAD<1:8> by aligning the second sampled data CSI2<1:4>. When the selection signal SEL is input at a logic low level in the second operating mode, the first alignment circuit 232 can generate the first to eighth pre-aligned data PAD<1:8> by aligning the second sampled data CSI2<1:4> synchronously with the first to fourth alignment clocks ACLK<1:4>. The first alignment circuit 232 may include multiple latching circuits and can perform operations of latching the first to eighth encoded data ED<1:8> and realigning the latched first to eighth encoded data ED<1:8>. The operation of the first alignment circuit 232 in the first and second operating modes to generate the first to eighth pre-aligned data PAD<1:8> will be described later. Figures 12 to 17 Describe it.

[0092] The second alignment circuit 233 can generate alignment data AD in both the first and second operating modes by aligning the first to eighth pre-aligned data PAD<1:8> synchronously with the first and second output clocks OCLK<1:2>. The second alignment circuit 233 may include multiple latching circuits and can perform operations of latching the first to eighth pre-aligned data PAD<1:8> and realigning the latched first to eighth pre-aligned data PAD<1:8>. The operation of the second alignment circuit 233 in generating alignment data AD in both the first and second operating modes will be described later. Figures 12 to 17 Describe it.

[0093] The following will use encoder 231 to determine the first bit CSI1 of the first sampled data CSI1<1:4>. <1> The first bit of the second sampled data CSI2<1:4>, CSI2 <1> The first bit of the third sampled data CSI3<1:4>, CSI3 <1> Taking the logic levels of the generated first and second encoded data ED<1:2> as an example, refer to... Figure 11 Describe the operation of encoder 231 in the first operating mode.

[0094] When the first bit of the first sampled data CSI1<1:4> is CSI1 <1> The first bit of the second sampled data CSI2<1:4> is a logic high level (i.e., H). <1> The first bit of the third sampled data CSI3<1:4> is at a logic high level. <1> When the logic level is high, encoder 231 can generate the first encoded data ED, which is logic high. <1> The second encoded data ED at a logic high level <2> .

[0095] When the first bit of the first sampled data CSI1<1:4> is CSI1 <1> The first bit of the second sampled data CSI2<1:4> is a logic low level (i.e., L). <1> The first bit of the third sampled data CSI3<1:4> is at a logic high level. <1> When the logic level is high, encoder 231 can generate the first encoded data ED, which is logic high. <1> The second encoded data ED at a logic low level <2> .

[0096] When the first bit of the first sampled data CSI1<1:4> is CSI1 <1> The first bit of the second sampled data CSI2<1:4> is at a logic low level. <1> The first bit of the third sampled data CSI3<1:4> is at a logic low level. <1> When the logic level is high, the encoder 231 can generate the first encoded data ED, which is at a logic low level. <1> The second encoded data ED with a logic high level <2> .

[0097] When the first bit of the first sampled data CSI1<1:4> is CSI1 <1> The first bit of the second sampled data CSI2<1:4> is at a logic low level. <1> The first bit of the third sampled data CSI3<1:4> is at a logic low level. <1> When the logic level is low, encoder 231 can generate first encoded data ED with a logic level of low. <1> The second encoded data ED at a logic low level <2> .

[0098] The operation of encoder 231 in generating the third to eighth encoded data ED<3:8> is the same as the operation of encoder 231 in generating the first and second encoded data ED<1:2>, so its description will be omitted.

[0099] The following will refer to Figure 12 The data alignment operation in a first operating mode of an electronic device 10 according to an embodiment of the present disclosure is described as the operation of generating first sampled data CSI1<1:4>, second sampled data CSI2<1:4> and third sampled data CSI3<1:4> from 32-bit input data DIN<1:32>.

[0100] In the first operating mode, the 32 bits of the input data DIN<1:32> are input sequentially, each having the following characteristics: Figure 7 Any of the first to fourth levels shown. The 32-bit input data DIN<1:32> is implemented as the first to sixteenth pulses input sequentially, and each pulse includes 2 bits of input data DIN.

[0101] The control circuit 110 generates a selection signal SEL that is enabled to a logic high level to enter the first operating mode.

[0102] The clock divider circuit 130 generates the first to fourth sampling clocks SCLK<1:4> by dividing the frequencies of the write clock WCLK and the inverted write clock WCLKB by two according to the logic high-level selection signal SEL.

[0103] At time T1, the first comparator 211 of the comparator circuit 210 operates by receiving a logic high-level selection signal SEL and generates a first comparison signal CD1 by comparing a first reference voltage VREFH with a first pulse of the input data DIN. The second comparator 212 of the comparator circuit 210 generates a second comparison signal CD2 by comparing a second reference voltage VREFM with a first pulse of the input data DIN. The third comparator 213 of the comparator circuit 210 operates by receiving a logic high-level selection signal SEL and generates a third comparison signal CD3 by comparing a third reference voltage VREFL with a first pulse of the input data DIN. The first pulse included in the input data DIN includes the first and second input data DIN<1:2>.

[0104] The first driver 221 of the sampling circuit 220 operates by receiving a logic high-level selection signal SEL and is synchronized with the first sampling clock SCLK. <1> The first bit CSI1 of the first sampled data CSI1<1:4> is generated synchronously from the first comparison signal CD1. <1> The second driver 222 of the sampling circuit 220 is connected to the first sampling clock SCLK. <1> The first bit CSI2 of the second sampled data CSI2<1:4> is generated synchronously from the second comparison signal CD2. <1> The third driver 223 of the sampling circuit 220 operates by receiving a logic high-level selection signal SEL and is synchronized with the first sampling clock SCLK. <1> The first bit of the third sampled data CSI3<1:4> is generated synchronously from the third comparison signal CD3. <1> The first bit of the first sampled data CSI1<1:4> <1> The first bit of the second sampled data CSI2<1:4>, CSI2 <1> The first bit of the third sampled data CSI3<1:4>, CSI3 <1> It is generated from the first pulse included in the input data DIN.

[0105] At time T2, the first comparator 211 of the comparator circuit 210 operates by receiving a logic high-level selection signal SEL and generates a first comparison signal CD1 by comparing a first reference voltage VREFH with a second pulse of the input data DIN. The second comparator 212 of the comparator circuit 210 generates a second comparison signal CD2 by comparing a second reference voltage VREFM with a second pulse of the input data DIN. The third comparator 213 of the comparator circuit 210 operates by receiving a logic high-level selection signal SEL and generates a third comparison signal CD3 by comparing a third reference voltage VREFL with a second pulse of the input data DIN. The second pulse included in the input data DIN includes the third and fourth input data DIN<3:4>.

[0106] The first driver 221 of the sampling circuit 220 operates by receiving a logic high-level selection signal SEL and is synchronized with the second sampling clock SCLK. <2> The second bit CSI1 of the first sampled data CSI1<1:4> is generated synchronously from the first comparison signal CD1. <2> The second driver 222 of the sampling circuit 220 is connected to the second sampling clock SCLK. <2> The second bit CSI2 of the second sampled data CSI2<1:4> is generated synchronously from the second comparison signal CD2. <2> The third driver 223 of the sampling circuit 220 operates by receiving a logic high-level selection signal SEL and is synchronized with the second sampling clock SCLK. <2> The second bit CSI3 of the third sampled data CSI3<1:4> is generated synchronously from the third comparison signal CD3. <2> The second bit of the first sampled data CSI1<1:4> is CSI1. <2> The second bit of the second sampled data CSI2<1:4>, CSI2 <2> The second bit of the third sampled data CSI3<1:4>, CSI3 <2> It is generated from the second pulse included in the input data DIN.

[0107] At time T3, the first comparator 211 of the comparator circuit 210 operates by receiving a logic high-level selection signal SEL and generates a first comparison signal CD1 by comparing the first reference voltage VREFH with the third pulse of the input data DIN. The second comparator 212 of the comparator circuit 210 generates a second comparison signal CD2 by comparing the second reference voltage VREFM with the third pulse of the input data DIN. The third comparator 213 of the comparator circuit 210 operates by receiving a logic high-level selection signal SEL and generates a third comparison signal CD3 by comparing the third reference voltage VREFL with the third pulse of the input data DIN. The third pulse included in the input data DIN includes the fifth and sixth input data DIN<5:6>.

[0108] The first driver 221 of the sampling circuit 220 operates by receiving a logic high-level selection signal SEL and is synchronized with the third sampling clock SCLK. <3> The third bit CSI1 of the first sampled data CSI1<1:4> is generated synchronously from the first comparison signal CD1. <3> The second driver 222 of the sampling circuit 220 is connected to the third sampling clock SCLK. <3> The third bit CSI2 of the second sampled data CSI2<1:4> is generated synchronously from the second comparison signal CD2. <3> The third driver 223 of the sampling circuit 220 operates by receiving a logic high-level selection signal SEL and is synchronized with the third sampling clock SCLK. <3> The third bit CSI3 of the third sampled data CSI3<1:4> is generated synchronously from the third comparison signal CD3. <3> The third bit of the first sampled data CSI1<1:4>, CSI1 <3> The third bit of the second sampled data CSI2<1:4>, CSI2 <3> The third bit of the third sampled data CSI3<1:4> <3> It is generated from the third pulse included in the input data DIN.

[0109] At time T4, the first comparator 211 of comparator circuit 210 operates by receiving a logic high-level selection signal SEL and generates a first comparison signal CD1 by comparing the first reference voltage VREFH with the fourth pulse of the input data DIN. The second comparator 212 of comparator circuit 210 generates a second comparison signal CD2 by comparing the second reference voltage VREFM with the fourth pulse of the input data DIN. The third comparator 213 of comparator circuit 210 operates by receiving a logic high-level selection signal SEL and generates a third comparison signal CD3 by comparing the third reference voltage VREFL with the fourth pulse of the input data DIN. The fourth pulse included in the input data DIN includes the seventh and eighth input data DIN<7:8>.

[0110] The first driver 221 of the sampling circuit 220 operates by receiving a logic high-level selection signal SEL and is synchronized with the fourth sampling clock SCLK. <4> The fourth bit CSI1 of the first sampled data CSI1<1:4> is generated synchronously from the first comparison signal CD1. <4> The second driver 222 of the sampling circuit 220 is connected to the fourth sampling clock SCLK. <4> The fourth bit CSI2 of the second sampled data CSI2<1:4> is generated synchronously from the second comparison signal CD2. <4> The third driver 223 of the sampling circuit 220 operates by receiving a logic high-level selection signal SEL and is synchronized with the fourth sampling clock SCLK. <4> The fourth bit CSI3 of the third sampled data CSI3<1:4> is generated synchronously from the third comparison signal CD3. <4> The fourth bit of the first sampled data CSI1<1:4>, CSI1 <4> The fourth bit of the second sampled data CSI2<1:4>, CSI2 <4> The fourth bit of the third sampled data CSI3<1:4>, CSI3 <4> It is generated from the fourth pulse included in the input data DIN.

[0111] The bits of the first sampled data CSI1<1:4>, the second sampled data CSI2<1:4>, and the third sampled data CSI3<1:4> generated from the fifth to sixteenth pulses of the input data DIN are generated in the same manner as the bits generated in the operation from time point T1 to time point T4, therefore a detailed description of them will be omitted.

[0112] The following will refer to Figure 13 The data alignment operation in a first operating mode of an electronic device 10 according to an embodiment of the present disclosure is described as an operation to generate first to eighth pre-aligned data PAD<1:8> from first sampled data CSI1<1:4>, second sampled data CSI2<1:4> and third sampled data CSI3<1:4>.

[0113] The clock divider circuit 130 generates the first to fourth aligned clocks ACLK<1:4> by dividing the frequencies of the write clock WCLK and the inverted write clock WCLKB by two according to the logic high-level selection signal SEL.

[0114] The encoder 231 generates the first to eighth encoded data ED<1:8> by encoding the first sampled data CSI1<1:4>, the second sampled data CSI2<1:4>, and the third sampled data CSI3<1:4> according to the logic high-level selection signal SEL.

[0115] At time T5, the first alignment circuit 232 and the second alignment clock ACLK are synchronized. <2> The first and second encoded data ED<1:2> are aligned synchronously. The aligned first and second encoded data ED<1:2> are generated from the first pulse of the input data DIN.

[0116] At time T6, the first alignment circuit 232 and the third alignment clock ACLK are synchronized. <3> The third and fourth encoded data ED<3:4> are aligned synchronously. The aligned third and fourth encoded data ED<3:4> are generated from the second pulse of the input data DIN.

[0117] At time T7, the first alignment circuit 232 and the fourth alignment clock ACLK are synchronized. <4> The fifth and sixth encoded data ED<5:6> are aligned synchronously, and first and second pre-aligned data PAD<1:2> are generated from the aligned fifth and sixth encoded data ED<5:6>. The aligned fifth and sixth encoded data ED<5:6> are generated from the third pulse of the input data DIN. The first and second pre-aligned data PAD<1:2> are generated from the third pulse of the input data DIN.

[0118] First alignment circuit 232 and fourth alignment clock ACLK <4> The fifth and sixth pre-aligned data PAD<5:6> are generated synchronously from the first and second coded data ED<1:2> aligned at time point T5. The fifth and sixth pre-aligned data PAD<5:6> are generated from the first pulse of the input data DIN. The first alignment circuit 232 is synchronized with the fourth alignment clock ACLK. <4> The seventh and eighth pre-aligned data PAD<7:8> are generated synchronously from the third and fourth encoded data ED<3:4> aligned at time point T6. The seventh and eighth pre-aligned data PAD<7:8> are generated from the second pulse of the input data DIN.

[0119] At time T8, the first alignment circuit 232 and the first alignment clock ACLK... <1> The seventh and eighth encoded data ED<7:8> are aligned synchronously, and the third and fourth pre-aligned data PAD<3:4> are generated from the aligned seventh and eighth encoded data ED<7:8>. The aligned seventh and eighth encoded data ED<7:8> are generated from the fourth pulse of the input data DIN. The third and fourth pre-aligned data PAD<3:4> are generated from the fourth pulse of the input data DIN.

[0120] The first to eighth pre-aligned data PAD<1:8> generated from the fifth to sixteenth pulses of the input data DIN are generated in the same way as the pre-aligned data generated during the operation from time point T5 to time point T8, so their detailed description will be omitted.

[0121] The first alignment circuit 232 has been described in synchronizing with the first to fourth alignment clocks ACLK<1:4> to align the first to eighth encoded data ED<1:8> encoded from the first sampled data CSI1<1:4>, the second sampled data CSI2<1:4>, and the third sampled data CSI3<1:4>, but this is only an example. In another embodiment, the first alignment circuit 232 can be implemented by first synchronizing the first sampled data CSI1<1:4>, the second sampled data CSI2<1:4>, and the third sampled data CSI3<1:4> with the first to fourth alignment clocks ACLK<1:4> to generate the first to eighth pre-aligned data PAD<1:8>, and generating the first to eighth encoded data ED<1:8> from the generated first to eighth pre-aligned data PAD<1:8>.

[0122] The following will refer to Figure 14 The data alignment operation in a first operating mode of an electronic device 10 according to an embodiment of the present disclosure is described as an operation of generating 32-bit aligned data AD<1:32> from the first to the eighth pre-aligned data PAD<1:8>.

[0123] The clock divider circuit 130 generates the first and second output clocks OCLK<1:2> by dividing the frequencies of the write clock WCLK and the inverted write clock WCLKB by four according to the logic high-level selection signal SEL.

[0124] At time T9, the second alignment circuit 233 and the second output clock OCLK are synchronized. <2> Synchronously align the first to eighth pre-aligned data PAD<1:8>. The first to eighth pre-aligned data PAD<1:8> are generated from the first to fourth pulses of the input data DIN.

[0125] At time T10, the second alignment circuit 233 is synchronized with the first output clock OCLK. <1> Synchronously align the first to eighth pre-aligned data PAD<1:8>. The first to eighth pre-aligned data PAD<1:8> are generated from the fifth to eighth pulses of the input data DIN.

[0126] The second alignment circuit 233 and the first output clock OCLK <1> Synchronously realign the first to eighth pre-aligned data PAD<1:8> aligned at time point T9. The first to eighth pre-aligned data PAD<1:8> are generated from the first to fourth pulses of the input data DIN.

[0127] At time T11, the second alignment circuit 233 and the second output clock OCLK are synchronized. <2> Synchronously align the first to eighth pre-aligned data PAD<1:8>. The first to eighth pre-aligned data PAD<1:8> are generated from the ninth to twelfth pulses of the input data DIN.

[0128] At time T12, the second alignment circuit 233 is synchronized with the first output clock OCLK. <1> Synchronously align the first to eighth pre-aligned data PAD<1:8>. The first to eighth pre-aligned data PAD<1:8> are generated from the thirteenth to sixteenth pulses of the input data DIN.

[0129] The second alignment circuit 233 and the first output clock OCLK <1> Synchronously realign the first to eighth pre-aligned data PAD<1:8> aligned at time point T11. The first to eighth pre-aligned data PAD<1:8> are generated from the ninth to twelfth pulses of the input data DIN.

[0130] The second alignment circuit 233 and the first output clock OCLK <1> The two first to eighth pre-aligned data PAD<1:8> that were aligned at time point T10 are synchronously realigned. The two first to eighth pre-aligned data PAD<1:8> are generated from the first to eighth pulses of the input data DIN.

[0131] At time T13, the second alignment circuit 233 is synchronized with the first output clock OCLK. <1> The two first to eighth pre-aligned data PAD<1:8> that were aligned at time point T12 are synchronously realigned. The two first to eighth pre-aligned data PAD<1:8> are generated from the ninth to sixteenth pulses of the input data DIN.

[0132] The second alignment circuit 233 is synchronized with the first output clock OCLK. <1> Synchronously realign the two pre-aligned data PAD<1:8> from the first to the eighth alignment at time point T12 to generate the first to the sixteenth alignment data AD<1:16>. The first to the sixteenth alignment data AD<1:16> are generated from the first to the eighth pulses of the input data DIN.

[0133] The second alignment circuit 233 is synchronized with the first output clock OCLK. <1> Synchronously realign the two first to eighth pre-aligned data PAD<1:8> aligned at time point T13 to generate the seventeenth to thirty-second aligned data AD<17:32>. The seventeenth to thirty-second aligned data AD<17:32> are generated from the ninth to sixteenth pulses of the input data DIN.

[0134] The following will refer to Figure 15 The data alignment operation in a second operating mode of an electronic device 10 according to an embodiment of the present disclosure is described as the operation of generating second sampled data CSI2<1:4> from 32-bit input data DIN<1:32>.

[0135] In the second operating mode, the 32 bits of the input data DIN<1:32> can be entered sequentially, each having the following characteristics: Figure 8 Either the first level or the fourth level shown. The 32-bit input data DIN<1:32> can be implemented as the first to the thirty-second pulses input sequentially, and can be implemented as 1 bit of input data DIN for each pulse.

[0136] The control circuit 110 generates a selection signal SEL that is disabled to a logic low level to enter the second operating mode.

[0137] The clock divider circuit 130 generates the first to fourth sampling clocks SCLK<1:4> by dividing the frequencies of the write clock WCLK and the inverted write clock WCLKB by two according to the low-level selection signal SEL.

[0138] The second comparator 212 of the comparator circuit 210 generates a second comparison signal CD2 by comparing the second reference voltage VREFM with the first to thirty-second input data DIN<1:32>.

[0139] At time T31, the second driver 222 of the sampling circuit 220 is synchronized with the first sampling clock SCLK. <1> The first bit CSI2 of the second sampled data CSI2<1:4> is generated synchronously from the second comparison signal CD2. <1> The first bit of the second sampled data CSI2<1:4> is CSI2. <1> It is generated from the first pulse of the input data DIN.

[0140] At time T32, the second driver 222 of the sampling circuit 220 is synchronized with the second sampling clock SCLK. <2> The second bit CSI2 of the second sampled data CSI2<1:4> is generated synchronously from the second comparison signal CD2. <2> The second bit of the second sampled data CSI2<1:4> is CSI2. <2> It is generated from the second pulse of the input data DIN.

[0141] At time T33, the second driver 222 of the sampling circuit 220 is synchronized with the third sampling clock SCLK. <3> The third bit CSI2 of the second sampled data CSI2<1:4> is generated synchronously from the second comparison signal CD2. <3> The third bit of the second sampled data CSI2<1:4>, CSI2 <3> It is generated from the third pulse of the input data DIN.

[0142] At time T34, the second driver 222 of the sampling circuit 220 is synchronized with the fourth sampling clock SCLK. <4> The fourth bit CSI2 of the second sampled data CSI2<1:4> is generated synchronously from the second comparison signal CD2. <4> The fourth bit of the second sampled data CSI2<1:4>, CSI2 <4> It is generated based on the fourth pulse of the input data DIN.

[0143] The bits of the second sampled data CSI2<1:4> generated from the fifth to the thirty-second pulses of the input data DIN are generated in the same manner as the bits generated in the operation from time point T31 to time point T34, so its detailed description will be omitted.

[0144] The following will refer to Figure 16 The data alignment operation in a second operating mode of an electronic device 10 according to an embodiment of the present disclosure is described as an operation of generating first to eighth pre-aligned data PAD<1:8> from second sampled data CSI2<1:4>.

[0145] The clock divider circuit 130 generates the first to fourth aligned clocks ACLK<1:4> by dividing the frequencies of the write clock WCLK and the inverted write clock WCLKB by four according to the low-level selection signal SEL.

[0146] At time T35, the first alignment circuit 232 and the second alignment clock ACLK are synchronized. <2> The first and second bits of the second sampled data CSI2<1:4>, CSI2<1:2>, are synchronously aligned. The first and second bits of the second sampled data CSI2<1:4>, CSI2<1:2>, are generated from the first and second pulses of the input data DIN.

[0147] At time T36, the first alignment circuit 232 and the third alignment clock ACLK are synchronized. <3> The third and fourth bits of the second sampled data CSI2<1:4>, CSI2<3:4>, are synchronously aligned. The aligned third and fourth bits of the second sampled data CSI2<1:4>, CSI2<3:4>, are generated from the third and fourth pulses of the input data DIN.

[0148] At time T37, the first alignment circuit 232 and the fourth alignment clock ACLK are synchronized. <4> The first and second bits (CSI2<1:2>) of the second sampled data CSI2<1:4> are synchronously aligned, and first and second pre-aligned data PAD<1:2> are generated from the aligned first and second bits (CSI2<1:2>) of the second sampled data CSI2<1:4>. The aligned first and second bits (CSI2<1:2>) of the second sampled data CSI2<1:4> are generated from the fifth and sixth pulses of the input data DIN. The first and second pre-aligned data PAD<1:2> are generated from the fifth and sixth pulses of the input data DIN.

[0149] First alignment circuit 232 and fourth alignment clock ACLK <4> The fifth and sixth pre-aligned data PAD<5:6> are generated synchronously from the first and second bits CSI2<1:2> of the second sampled data CSI2<1:4> aligned at time point T35. The fifth and sixth pre-aligned data PAD<5:6> are generated from the first and second pulses of the input data DIN. The first alignment circuit 232 is synchronized with the fourth alignment clock ACLK. <4> The seventh and eighth pre-aligned data PAD<7:8> are generated synchronously from the third and fourth bits CSI2<3:4> of the second sampled data CSI2<1:4> aligned at time point T36. The seventh and eighth pre-aligned data PAD<7:8> are generated from the third and fourth pulses of the input data DIN.

[0150] At time T38, the first alignment circuit 232 and the first alignment clock ACLK... <1> The third and fourth bits (CSI2<3:4>) of the second sampled data CSI2<1:4> are synchronously aligned, and the third and fourth pre-aligned data PAD<3:4> are generated from the aligned third and fourth bits (CSI2<3:4>) of the second sampled data CSI2<1:4>. The aligned third and fourth bits (CSI2<3:4>) of the second sampled data CSI2<1:4> are generated from the seventh and eighth pulses of the input data DIN. The third and fourth pre-aligned data PAD<3:4> are generated from the seventh and eighth pulses of the input data DIN.

[0151] The first to eighth pre-aligned data PAD<1:8> generated from the ninth to thirty-second pulses of the input data DIN are generated in the same way as the pre-aligned data generated during the operation from time point T35 to time point T38, so their detailed description will be omitted.

[0152] The following will refer to Figure 17 The data alignment operation in a second operating mode of an electronic device 10 according to an embodiment of the present disclosure is described as an operation of generating 32-bit aligned data AD<1:32> from the first to the eighth pre-aligned data PAD<1:8>.

[0153] The clock divider circuit 130 generates the first and second output clocks OCLK<1:2> by dividing the frequencies of the write clock WCLK and the inverted write clock WCLKB by eight according to the logic low-level selection signal SEL.

[0154] At time T39, the second alignment circuit 233 and the second output clock OCLK are synchronized. <2> Synchronously align the first to eighth pre-aligned data PAD<1:8>. The first to eighth pre-aligned data PAD<1:8> are generated from the first to eighth pulses of the input data DIN.

[0155] At time T40, the second alignment circuit 233 is synchronized with the first output clock OCLK. <1> Synchronously align the first to eighth pre-aligned data PAD<1:8>. The first to eighth pre-aligned data PAD<1:8> are generated from the ninth to sixteenth pulses of the input data DIN.

[0156] The second alignment circuit 233 and the first output clock OCLK <1> Synchronously realign the first to eighth pre-aligned data PAD<1:8> aligned at time point T39. The first to eighth pre-aligned data PAD<1:8> are generated from the first to eighth pulses of the input data DIN.

[0157] At time T41, the second alignment circuit 233 and the second output clock OCLK are synchronized. <2> Synchronously align the first to eighth pre-aligned data PAD<1:8>. The first to eighth pre-aligned data PAD<1:8> are generated from the seventeenth to twenty-fourth pulses of the input data DIN.

[0158] At time T42, the second alignment circuit 233 is synchronized with the first output clock OCLK. <1> Synchronously align the first to eighth pre-aligned data PAD<1:8>. The first to eighth pre-aligned data PAD<1:8> are generated from the twenty-fifth to thirty-second pulses of the input data DIN.

[0159] The second alignment circuit 233 and the first output clock OCLK <1> Synchronously realign the first to eighth pre-aligned data PAD<1:8> aligned at time point T41. The first to eighth pre-aligned data PAD<1:8> are generated from the seventeenth to twenty-fourth pulses of the input data DIN.

[0160] The second alignment circuit 233 and the first output clock OCLK <1> The two first to eighth pre-aligned data PAD<1:8> are synchronously realigned at time point T40. The two first to eighth pre-aligned data PAD<1:8> are generated from the first to sixteenth pulses of the input data DIN.

[0161] At time T43, the second alignment circuit 233 is synchronized with the first output clock OCLK. <1> The two first to eighth pre-aligned data PAD<1:8> aligned at time point T42 are synchronously realigned. The two first to eighth pre-aligned data PAD<1:8> are generated from the seventeenth to thirty-second pulses of the input data DIN.

[0162] The second alignment circuit 233 and the first output clock OCLK <1> The first to sixteenth aligned data AD<1:16> are generated synchronously by realigning the two first to eighth pre-aligned data PAD<1:8> aligned at time point T42. The first to sixteenth aligned data AD<1:16> are generated from the first to sixteenth pulses of the input data DIN.

[0163] The second alignment circuit 233 and the first output clock OCLK <1> The seventeenth to thirty-second alignment data AD<17:32> is generated synchronously by realigning the two first to eighth pre-aligned data PAD<1:8> aligned at time point T43. The seventeenth to thirty-second alignment data AD<17:32> is generated from the seventeenth to thirty-second pulses of the input data DIN.

[0164] As is apparent from the above description, the electronic device 10 according to embodiments of the present disclosure can support a first operating mode and a second operating mode. In the first operating mode, during data alignment operation, the pulse amplitude of the data is adjusted to four levels, and each pulse inputs / outputs 2 bits of data. In the second operating mode, during data alignment operation, both logic high-level bits and logic low-level bits in the data maintain their logic levels until the input of the next bit. The electronic device 10 can ensure the reliability of the data alignment operation by selectively executing the first and second operating modes according to high-speed and low-speed operation during data alignment operation.

[0165] Figure 18 This is a block diagram illustrating the configuration of an electronic system 1000 according to an embodiment of the present disclosure. (See diagram for example.) Figure 18 As shown, the electronic system 1000 may include a host 1100 and a semiconductor system 1200.

[0166] The host 1100 and the semiconductor system 1200 can transmit signals to each other using an interface protocol. Examples of interface protocols used between the host 1100 and the semiconductor system 1200 may include MMC (Multimedia Card), ESDI (Enhanced Small Disk Interface), IDE (Integrated Drive Electronics), PCI-E (Peripheral Component Interconnect), ATA (Advanced Technology Accessories), SATA (Serial ATA), PATA (Parallel ATA), SAS (Serial Attached SCSI), and USB (Universal Serial Bus).

[0167] Semiconductor system 1200 may include controller 1300 and electronic device 1400 (K:1). Controller 1300 may control electronic device 1400 (K:1) such that electronic device 1400 (K:1) executes a first operating mode and a second operating mode according to the operating speed during data alignment operation. Each electronic device 1400 (K:1) may execute the first operating mode and the second operating mode. In the first operating mode, during data alignment operation, the pulse amplitude of the data is adjusted to four levels and 2 bits of data are input / output per pulse. In the second operating mode, during data alignment operation, both logic high-level bits and logic low-level bits in the data maintain their logic levels until the time point when the next bit is input. Each electronic device 1400 (K:1) may ensure the reliability of data alignment operation by selectively executing the first operating mode and the second operating mode according to high-speed operation and low-speed operation during data alignment operation.

[0168] Each electronic device 1400 (K:1) can be made from Figure 1 The illustrated electronic device 10 is used to implement this. According to an embodiment, each electronic device 1400(K:1) can be implemented by one of DRAM (Dynamic Random Access Memory), PRAM (Phase Change Random Access Memory), RRAM (Resistive Random Access Memory), MRAM (Magnetic Random Access Memory), and FRAM (Ferroelectric Random Access Memory).

[0169] While some embodiments of this teaching have been disclosed for illustrative purposes, those skilled in the art will understand that various modifications, additions, and substitutions are possible without departing from the scope and spirit of this teaching as defined in the appended claims.

Claims

1. An electronic device, comprising: Comparator circuit, Specifically: Based on the selection signal for selecting a first operating mode or a second operating mode, in the first operating mode, a first comparison signal to a third comparison signal is generated by receiving input data having any one of a first level to a fourth level, and in the second operating mode, a second comparison signal is generated by receiving input data having any one of the first level and the fourth level. A sampling circuit, wherein: in a first operating mode, it generates first sampled data to third sampled data from a first comparison signal to a third comparison signal in synchronization with a sampling clock; and in a second operating mode, it generates second sampled data from a second comparison signal; and An alignment circuit that: aligns the first sampled data to the third sampled data in sync with an alignment clock and an output clock, and generates aligned data based on the aligned first sampled data to the aligned third sampled data; or aligns the second sampled data in sync with the alignment clock and the output clock, and generates the aligned data based on the aligned second sampled data.

2. The electronic device according to claim 1, further comprising: The control circuit generates the selection signal when a mode register setting signal or a test mode signal is input.

3. The electronic device according to claim 1, wherein, In the first operating mode, the pulse included in the input data includes 2 bits of information and is input from an external device; and in the second operating mode, the pulse included in the input data includes 1 bit of information and is input from the external device.

4. The electronic device according to claim 1, wherein... In the first operating mode, the comparator circuit generates the first comparison signal to the third comparison signal by comparing the input data with a first reference voltage to a third reference voltage. In the second operating mode, the comparison circuit generates the second comparison signal by comparing the input data with a second reference voltage.

5. The electronic device according to claim 1, wherein In both the first and second operating modes, the sampling clock is generated at a frequency that is half the frequency of the write clock. In the first operating mode, the alignment clock is generated with a frequency that is 1 / 2 times the frequency of the write clock, and the output clock is generated with a frequency that is 1 / 4 times the frequency of the write clock. In the second operating mode, the alignment clock is generated at a frequency that is 1 / 4 times the frequency of the write clock, and the output clock is generated at a frequency that is 1 / 8 times the frequency of the write clock.

6. The electronic device according to claim 4, wherein, The comparison circuit includes: A first comparator operates when the selection signal is enabled and generates the first comparison signal by comparing the first reference voltage and the input data. A second comparator generates the second comparison signal by comparing the second reference voltage and the input data; and A third comparator operates when the selection signal is enabled and generates the third comparison signal by comparing the third reference voltage with the input data.

7. The electronic device according to claim 4, wherein The first reference voltage is a voltage having a level between the fourth level and the third level of the input data. The second reference voltage is a voltage having a level between the third level of the input data and the second level of the input data, and The third reference voltage is a voltage with a level between the second level of the input data and the first level of the input data.

8. The electronic device according to claim 1, wherein, The alignment circuit includes: An encoder that generates encoded data in the first operating mode by encoding the first sampled data to the third sampled data based on the selection signal; A first alignment circuit, comprising: generating pre-aligned data in a first operating mode by aligning the encoded data in synchronization with the alignment clock based on the selection signal; and generating the pre-aligned data in a second operating mode by aligning the second sampled data in synchronization with the alignment clock based on the selection signal; and The second alignment circuit generates the alignment data by aligning the pre-aligned data in sync with the output clock.

9. An electronic device, comprising: A clock divider circuit generates a first sampling clock to a fourth sampling clock, a first alignment clock to a fourth alignment clock, a first output clock, and a second output clock by dividing the frequency of the written clock. A data alignment circuit, wherein, according to a selection signal for selecting a first operating mode or a second operating mode, in the first operating mode, receives input data having any one of a first level to a fourth level and generates aligned data by aligning the input data synchronously with the first sampling clock to the fourth sampling clock, the first alignment clock to the fourth alignment clock, and the first output clock and the second output clock; and in the second operating mode, receives input data having any one of the first level and the fourth level and generates the aligned data by aligning the input data synchronously with the first sampling clock to the fourth sampling clock, the first alignment clock to the fourth alignment clock, and the first output clock and the second output clock.

10. The electronic device according to claim 9, further comprising: The control circuit generates the selection signal when a mode register setting signal or a test mode signal is input.

11. The electronic device according to claim 9, wherein, In the first operating mode, the pulse of the input data includes 2 bits of information and is input from an external device; and in the second operating mode, the pulse of the input data includes 1 bit of information and is input from the external device.

12. The electronic device according to claim 9, wherein, The input data is a serially input signal comprising multiple bits that are input sequentially, and the alignment data is a parallelly generated signal comprising multiple bits that are generated simultaneously.

13. The electronic device according to claim 9, wherein, The first sampling clock to the fourth sampling clock are signals with a 90° phase difference, the first alignment clock to the fourth alignment clock are signals with a 90° phase difference, and the first output clock and the second output clock are signals with a 180° phase difference.

14. The electronic device according to claim 9, wherein, The clock divider circuit includes: The first frequency divider generates the first internal clock to the fourth internal clock by dividing the frequency of the written clock by two. The second frequency divider generates the first frequency divided clock to the fourth frequency divided clock by dividing the frequency of the first internal clock to the frequency of the fourth internal clock by two. The third frequency divider generates the first and second pre-output clocks by dividing the frequency of the third frequency divider clock by two; and A clock selection circuit that: generates a first sampling clock to a fourth sampling clock from a first internal clock to a fourth internal clock, and generates a first aligned clock to a fourth aligned clock, a first output clock, and a second output clock from the first internal clock to the fourth internal clock, a first divided clock to a fourth divided clock, a first pre-output clock, and a second pre-output clock according to the logic level of the selection signal.

15. The electronic device according to claim 9, wherein, The data alignment circuit includes: A comparison circuit, wherein, based on the selection signal, in a first operating mode, it generates a first comparison signal to a third comparison signal by receiving input data having any one of the first to the fourth levels, and in a second operating mode, it generates a second comparison signal by receiving input data having any one of the first and the fourth levels. A sampling circuit, wherein: in a first operating mode, it generates first sampled data to third sampled data from a first comparison signal to a third comparison signal in synchronization with a sampling clock; and in a second operating mode, it generates second sampled data from a second comparison signal; and An alignment circuit that: aligns the first sampled data to the third sampled data synchronously with the first alignment clock to the fourth alignment clock, the first output clock, and the second output clock, and generates the aligned data based on the aligned first sampled data to the aligned third sampled data; or aligns the second sampled data synchronously with the first alignment clock to the fourth alignment clock, the first output clock, and the second output clock, and generates the aligned data based on the aligned second sampled data.

16. The electronic device of claim 15, wherein... In the first operating mode, the comparator circuit generates the first comparison signal to the third comparison signal by comparing the input data with a first reference voltage to a third reference voltage. In the second operating mode, the comparison circuit generates the second comparison signal by comparing the input data with the second reference voltage.

17. The electronic device according to claim 16, wherein, The comparison circuit includes: A first comparator operates when the selection signal is enabled and generates the first comparison signal by comparing the first reference voltage and the input data. A second comparator generates the second comparison signal by comparing the second reference voltage and the input data; and A third comparator operates when the selection signal is enabled and generates the third comparison signal by comparing the third reference voltage with the input data.

18. The electronic device according to claim 17, wherein, The selection signal is a signal that is enabled to execute the first operation mode.

19. The electronic device according to claim 17, wherein, When the input data has the fourth level, the first comparator generates the first comparator signal that is enabled; when the input data has a level equal to or higher than the third level, the second comparator generates the second comparator signal that is enabled; and when the input data has a level equal to or higher than the second level, the third comparator generates the third comparator signal that is enabled.

20. The electronic device according to claim 15, wherein, The alignment circuit includes: An encoder that generates encoded data in the first operating mode by encoding the first sampled data to the third sampled data based on the selection signal; A first alignment circuit, comprising: generating pre-aligned data in a first operating mode by aligning the encoded data synchronously with the first alignment clock to the fourth alignment clock based on the selection signal; and generating the pre-aligned data in a second operating mode by aligning the second sampled data synchronously with the first alignment clock to the fourth alignment clock based on the selection signal; and The second alignment circuit generates the alignment data by aligning the pre-aligned data in sync with the first output clock and the second output clock.

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