Fan-in package structure and method for manufacturing a fan-in package structure

Abstract

Embodiments of the present application provide a fan-in packaging structure and a preparation method thereof, and relate to the technical field of semiconductor packaging. The fan-in packaging structure comprises a base chip, a combined wiring layer, a plastic package body and a connecting wire. The combined wiring layer is arranged on one side of the base chip, the plastic package body covers the combined wiring layer and the base chip, and the connecting wire is arranged in the plastic package body in a bent manner. The side of the base chip away from the combined wiring layer is exposed to the plastic package body, and the combined wiring layer is electrically connected to the base chip. By arranging the bent connecting wire, the wire on the conventional die can be changed to the wire on the surrounding back surface, the distribution range of the I / O pad is expanded, the number and distribution area are less limited, and the integration degree can be greatly improved. At the same time, water vapor can be prevented from entering the combined wiring layer through the wire, and the waterproof effect is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and more specifically, to a fan-in package structure and a method for preparing the fan-in package structure. Background Technology

[0002] With the rapid development of the semiconductor industry, wafer-level packaging is divided into fan-out and fan-in types. Fan-in packaging involves routing the entire wafer individually to each die, with the I / O pads for each die confined to the area directly above the die surface. Given the limited area of ​​the die, the number of I / O pads is limited by the spacing between them, which in turn limits the number of I / O solder balls that can be packaged on the die surface. Furthermore, during wafer fabrication, a dielectric layer is typically used to cover the wiring layer to achieve the process. However, since the dielectric layer material is usually polyimide, which is extremely hygroscopic, moisture can affect the product, impacting the electrical properties of the internal circuitry and causing delamination between the dielectric layer and the chip surface. Ultimately, this affects the product's reliability and lifespan. Summary of the Invention

[0003] The objectives of this invention include, for example, providing a fan-in package structure and a method for preparing the fan-in package structure, which can increase the number and distribution area of ​​I / O pads, improve integration, and at the same time avoid the product being affected by moisture, thereby improving product reliability and service life.

[0004] The embodiments of the present invention can be implemented as follows:

[0005] In a first aspect, the present invention provides a fan-in package structure, comprising:

[0006] Substrate chip;

[0007] A combined circuit layer disposed on one side of the substrate chip;

[0008] A plastic encapsulation covering the combined circuit layer and the substrate chip;

[0009] And, a connecting wire bent and disposed in the encapsulation body;

[0010] The substrate chip is exposed on the side away from the combined circuit layer in the molding compound. The combined circuit layer is electrically connected to the substrate chip. One end of the connecting wire is connected to the combined circuit layer, and the other end is bent and extends to the side surface of the molding compound that exposes the substrate chip.

[0011] In an optional embodiment, one end of the connecting wire away from the combined circuit layer extends out of the molding compound and is bent to form an external pin. The external pin is attached to one side of the molding compound that exposes the substrate chip and is protruding relative to the substrate chip.

[0012] In an optional embodiment, the connecting wire includes an integrally formed first connecting segment, a second connecting segment, and a third connecting segment. One end of the first connecting segment is connected to the combined circuit layer. The second connecting segment is connected to the end of the first connecting segment away from the combined circuit layer and extends outward relative to the first connecting segment. The third connecting segment is connected to the end of the second connecting segment away from the first connecting segment and is bent relative to the second connecting segment, extending towards the surface of the molding compound that exposes the substrate chip.

[0013] In an optional implementation, the bonding height H1 of the connecting wire relative to the combined circuit layer is the same as the sinking height H2 of the external pin relative to the combined circuit layer.

[0014] In an optional embodiment, wiring pads are provided on both sides of the combined circuit layer, and the connecting wires are disposed on the wiring pads and bent and distributed on both sides of the substrate chip.

[0015] In an optional embodiment, the combined circuit layer includes a first dielectric layer, a wiring layer, and a second dielectric layer. Chip pads are provided on the substrate chip. The first dielectric layer is disposed on the substrate chip. The wiring layer is embedded in the first dielectric layer and connected to the chip pads. The second dielectric layer is disposed on the first dielectric layer. The wiring pads are disposed on the second dielectric layer and connected to the wiring layer.

[0016] In an optional embodiment, a protective adhesive film layer is attached to the surface of the substrate chip away from the combined circuit layer, and a clearance opening is provided on the protective adhesive film, with the external pin disposed in the clearance opening.

[0017] In an optional embodiment, the surface of the external pin away from the molding compound is further provided with an anti-oxidation layer.

[0018] Secondly, the present invention provides a method for preparing a fan-in package structure, used to prepare the fan-in package structure as described in the foregoing embodiments, the method comprising:

[0019] Provide a vehicle;

[0020] The wafer is mounted onto the carrier;

[0021] A combined circuit layer is formed on the wafer;

[0022] The wafer and the combined circuit layer are cut along the first dicing path to form a plurality of substrate chips with the combined circuit layer;

[0023] Connecting conductors are formed by bonding wires on adjacent combined circuit layers;

[0024] Bending the connecting wire;

[0025] A molding compound is formed on the carrier, the molding compound covering the combined circuit layer and the substrate chip;

[0026] Remove the carrier so that the side of the substrate chip away from the combined circuit layer is exposed in the molding compound;

[0027] The encapsulated body is cut along the second cutting path;

[0028] The combined circuit layer is electrically connected to the substrate chip, one end of the connecting wire is connected to the combined circuit layer, and the other end is bent and extended to the molded body to expose one side surface of the substrate chip.

[0029] In an optional embodiment, the carrier is pre-prepared with a groove corresponding to the first cutting path, and the step of bending the connecting wire includes:

[0030] The middle portion of the connecting wire is bent to the bottom of the groove;

[0031] The portion of the connecting wire bent into the groove extends out of the encapsulation body and is bent to form an external pin.

[0032] In an optional embodiment, prior to the step of bending the middle portion of the connecting wire to the bottom of the groove, the preparation method further includes:

[0033] An anti-oxidation layer is formed within the groove;

[0034] The anti-oxidation layer is used for grinding and soldering onto the external pins.

[0035] In an optional embodiment, after the step of removing the carrier, the preparation method further includes:

[0036] A protective adhesive film layer is attached to the surface of the substrate chip on the side away from the combined circuit layer.

[0037] The beneficial effects of the embodiments of the present invention include, for example:

[0038] This invention provides a fan-in package structure and its fabrication method. By setting a molding compound outside the combined circuit layer and the substrate chip, the influence of external moisture on the chip can be effectively blocked. Simultaneously, the side of the substrate chip furthest from the combined circuit layer is exposed within the molding compound. Connecting wires are bent and disposed within the molding compound, extending downwards to the surface of the molding compound where they expose the substrate chip. On one hand, by setting the bent connecting wires, the conventional top-of-die wiring can be changed to peripheral back-side wiring, expanding the distribution range of I / O pads with fewer restrictions on their number and distribution area, significantly improving integration density. On the other hand, it prevents moisture from entering the combined circuit layer through the wiring outlets, improving waterproofing. Compared to existing technologies, this invention can increase the number and distribution area of ​​I / O pads, improve integration density, and simultaneously prevent the product from being affected by moisture, improving product reliability and lifespan. Attached Figure Description

[0039] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 This is a schematic diagram of the fan-in package structure provided in the first embodiment of the present invention;

[0041] Figure 2 This is a partial structural diagram of the fan-in package structure provided in the first embodiment of the present invention;

[0042] Figure 3 This is a schematic diagram of the upper board of the fan-in package structure provided in the first embodiment of the present invention;

[0043] Figure 4 This is a schematic diagram of the fan-in package structure provided in the second embodiment of the present invention;

[0044] Figure 5 This is a schematic diagram of the fan-in package structure provided in the third embodiment of the present invention;

[0045] Figures 6 to 13 The process flow diagram is shown for the fabrication method of the fan-in package structure provided in the fourth embodiment of the present invention.

[0046] Icons: 100 - Fan-in package structure; 110 - Substrate chip; 130 - Combined circuit layer; 131 - First dielectric layer; 133 - Wiring layer; 135 - Second dielectric layer; 137 - Wiring pad; 150 - Molded package; 170 - Connecting wire; 171 - External pin; 173 - First connection segment; 175 - Second connection segment; 177 - Third connection segment; 180 - Protective adhesive layer; 190 - Anti-oxidation layer; 200 - Substrate; 300 - Carrier; 310 - Groove; 400 - Wafer. Detailed Implementation

[0047] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0048] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0049] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0050] In the description of this invention, it should be noted that if terms such as "upper," "lower," "inner," or "outer" are used to indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of this invention is usually placed, they are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention.

[0051] Furthermore, the terms "first" and "second" are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.

[0052] As disclosed in the background section, in existing technologies, fan-in packaging involves individual wiring on a single die within a wafer, with each die's I / O pads confined to the area directly above the die's surface. Given the limited area of ​​the die, the number of I / O pads is limited by the spacing between them, which in turn limits the number of I / O solder balls that can be packaged on the die's surface. In other words, the distribution number and area of ​​I / O pads serving as electrical signal input / output ports are restricted by the limited space above the die, resulting in lower integration density. For example, a larger I / O pad spacing and size may lead to a smaller number of I / O pads, affecting input / output performance. Furthermore, in conventional processes, the upper dielectric layer is typically made of polyimide, a material highly hygroscopic. This moisture can affect the product's electrical properties, causing delamination between the dielectric layer and the chip surface, ultimately impacting product reliability and lifespan.

[0053] Furthermore, conventional fan-in package structures use surface-mount pads / pins on the top to be soldered to surface-mount pads on the substrate. This soldering performance is relatively poor, easily leading to issues such as solder voids. Additionally, conventional fan-in package structures are prone to excessive warping of the molded body during molding, which can cause excessive stress on the chip, resulting in microcracks and delamination.

[0054] To address the aforementioned issues, this invention provides a novel fan-in package structure and its fabrication method, which can increase the number and distribution area of ​​I / O pads, improve integration density, and simultaneously prevent the product from being affected by moisture, thereby improving product reliability and lifespan. It should be noted that, unless otherwise specified, features in the embodiments of this invention can be combined with each other.

[0055] First Embodiment

[0056] See Figures 1 to 3 This embodiment provides a fan-in package structure 100, which can increase the number and distribution area of ​​I / O pads, improve integration, and prevent the product from being affected by moisture, thereby improving product reliability and service life. Furthermore, the fan-in package structure 100 provided in this embodiment can effectively solve the warpage problem during the molding process and results in better soldering performance when mounted on the board.

[0057] The fan-in package structure 100 provided in this embodiment includes a substrate chip 110, a combined circuit layer 130, a molding compound 150, and connecting wires 170. The combined circuit layer 130 is disposed on one side of the substrate chip 110, and the molding compound 150 covers the combined circuit layer 130 and the substrate chip 110. The connecting wires 170 are bent and disposed within the molding compound 150. The side of the substrate chip 110 away from the combined circuit layer 130 is exposed in the molding compound 150. The combined circuit layer 130 is electrically connected to the substrate chip 110. One end of the connecting wire 170 is connected to the combined circuit layer 130, and the other end is bent and extends onto the molding compound 150, exposing one side surface of the substrate chip 110.

[0058] In this embodiment, the front side of the substrate chip 110 faces upward, and chip pads are provided on the front side of the substrate chip 110. The chip pads are in electrical contact with the combined circuit layer 130, thereby realizing the electrical connection between the combined circuit layer 130 and the substrate chip 110. The back side of the substrate chip 110 is exposed on the bottom side of the molding compound 150, which facilitates the use of the carrier 300 to mold the molding compound 150 and also improves the heat dissipation performance of the substrate chip 110. This embodiment effectively blocks external moisture from affecting the chip by providing a molding compound 150 outside the combined circuit layer 130 and the substrate chip 110. Simultaneously, the side of the substrate chip 110 furthest from the combined circuit layer 130 is exposed within the molding compound 150. Connecting wires 170 are bent and disposed within the molding compound 150, extending downwards to expose one side of the substrate chip 110 on the surface of the molding compound 150. On one hand, by providing bent connecting wires 170, the conventional top-of-die wiring can be changed to peripheral back-side wiring, expanding the distribution range of I / O terminals with fewer restrictions on their number and distribution area, significantly improving integration density. On the other hand, it prevents moisture from entering the combined circuit layer 130 through the wiring outlets, improving waterproofing.

[0059] It should be noted that there may be multiple connecting wires 170 in this embodiment. Only two are shown in this embodiment for illustration. In this embodiment, the connecting wires 170 are bent and disposed in the molding compound 150. They are bent in the opposite direction from the side of the combined circuit layer 130 away from the substrate chip 110 and extend out of the molding compound 150 near the back of the substrate chip 110. This allows the I / O terminals to extend from the surface of the combined circuit layer 130 to the surface of the molding compound 150, with a wider range and less mutual interference between the I / O terminals. This is beneficial for improving the integration of the I / O terminals and thus improving the input / output performance of the product.

[0060] It should also be noted that in this embodiment, the molding compound 150 can be made of epoxy-based resin or silicone-based resin. The moisture absorption rate of the hygroscopic material in the molding compound 150 (e.g., 0.19%) is lower than that of the dielectric material in the combined circuit layer 130 (e.g., 5%). Simultaneously, alumina thermal conductive powder or nano-alumina can be filled into the molding compound 150 to achieve high heat dissipation. In traditional circuit layers, the dielectric material easily absorbs moisture or chemical agents, which not only leads to a decrease in the volume resistivity of the material but also causes the chemical agents to contaminate the wiring layer 133 and the chip surface and form oxides during the baking and degassing process, thus affecting the chip's performance and reliability. In this embodiment, by covering the molding compound 150, moisture or chemical agents can be effectively isolated.

[0061] In this embodiment, one end of the connecting wire 170, away from the combined circuit layer 130, extends out of the molding compound 150 and is bent to form an external pin 171. The external pin 171 is attached to the molding compound 150, exposing one side surface of the substrate chip 110, and protrudes relative to the substrate chip 110. Specifically, in this embodiment, the external pin 171 formed on the outside of the connecting wire 170 can serve as an I / O terminal of the package structure. Furthermore, during board mounting, the back side of the substrate chip 110 can be faced with the substrate 200, so that the external pin 171 is soldered and fixed to the surface pads on the substrate 200, achieving fixed soldering. The setting of the external pin 171 can improve the sidewall wettability of the solder, allowing the solder to climb along the external pin 171 during soldering, thereby improving the overall soldering strength and resulting in better soldering effect. The exposed back side of the substrate chip 110 can face the substrate / pad. After filling the bottom adhesive layer, the back side of the substrate chip 110 can be filled, thereby achieving the protection of the back side of the substrate chip 110 and more effectively preventing external moisture from corroding the substrate chip 110.

[0062] It should be noted that in this embodiment, the height of the external pin 171 protruding relative to the base chip 110 can be the same as the wire diameter of the connecting wire 170. By setting the external pin 171 to protrude, a certain gap can be maintained between the base chip 110 and the substrate 200 after soldering on the upper board, allowing the area below the base chip 110 to be hollowed out, further improving the heat dissipation effect. At the same time, the protrusion of the external pin 171 can also increase the soldering area during soldering and allow the solder to climb up the sidewall of the external pin 171, thereby improving the overall soldering strength.

[0063] In this embodiment, the connecting wire 170 includes an integrally formed first connecting segment 173, a second connecting segment 175, and a third connecting segment 177. One end of the first connecting segment 173 is connected to the combined circuit layer 130. The second connecting segment 175 is connected to the end of the first connecting segment 173 away from the combined circuit layer 130 and extends outward relative to the first connecting segment 173 by bending. The third connecting segment 177 is connected to the end of the second connecting segment 175 away from the first connecting segment 173, and the third connecting segment 177 is bent relative to the second connecting segment 175 and extends towards the surface of the molding compound 150 that exposes the substrate chip 110. Specifically, the first connecting segment 173, the second connecting segment 175, and the third connecting segment 177 are all straight segments. The first connecting segment 173 and the third connecting segment 177 extend vertically, while the second connecting segment 175 extends horizontally, so that the connecting wire 170 extends in opposite directions after being bent at two points. Of course, the first connecting segment 173, the second connecting segment 175, and the third connecting segment 177 here can also have a slight curvature to reduce the difficulty of pressing the line.

[0064] It is worth noting that the connecting wire 170 here can be formed by wire pressing and cutting, and the connecting wire 170 can be a metal wire, such as copper wire / gold wire. Specifically, a wafer 400 with multiple dies can be placed on a carrier 300. A groove 310 is set at a preset position on the carrier 300. After the combined circuit layer 130 is prepared, it is cut once to form multiple substrate chips 110. Then, wires are bonded between the combined circuit layers 130 of two adjacent substrate chips 110 to form connecting wires 170. Then, the connecting wires 170 are pressed so that the middle part of the connecting wires 170 is bent and pressed into the groove 310. The groove 310 is used to flatten it, and after molding, a second cut is made along the middle position of the groove 310 to form external pins 171.

[0065] It should be noted that in this embodiment, the connecting wire 170 adopts a two-bend structure, and is bent again at the external pin 171. Utilizing multiple bends effectively reduces the warpage of the encapsulation body 150 during the molding process, acting as a balancing spring and providing a certain degree of buffering capacity. Simultaneously, using a metal wire as the connecting wire 170 also improves the heat dissipation performance inside the package structure.

[0066] In this embodiment, the bonding height H1 of the connecting wire 170 relative to the combined circuit layer 130 is the same as the recess height H2 of the external pin 171 relative to the combined circuit layer 130. Specifically, the bonding height H1 of the connecting wire 170 relative to the combined circuit layer 130 refers to the vertical distance between the second connecting segment 175 and the surface of the combined circuit layer 130 away from the substrate chip 110, and the recess height H2 of the external pin 171 relative to the combined circuit layer 130 refers to the vertical distance between the external pin 171 and the surface of the combined circuit layer 130 away from the substrate chip 110. By setting H1 and H2 to be the same, it can be ensured that the bent part can be pressed into the groove 310 on the carrier 300 when the connecting wire 170 is bent, which utilizes the ductility of the metal wire.

[0067] In this embodiment, wiring pads 137 are provided on both sides of the combined circuit layer 130, and connecting wires 170 are disposed on the wiring pads 137 and bent and distributed on both sides of the substrate chip 110. Specifically, there can be multiple wiring pads 137, and each wiring pad 137 is provided with connecting wires 170, thereby forming multiple I / O terminals. By bending and distributing the connecting wires 170 on both sides of the substrate chip 110, it is possible to achieve wire output on both sides of the substrate chip 110, thereby making the I / O terminals on both sides farther apart and further avoiding mutual interference between the I / O terminals on both sides. In other preferred embodiments of the present invention, wiring pads 137 may also be provided around the perimeter of the combined circuit layer 130, so that the connecting wires are bent and distributed around the perimeter of the substrate chip 110, further increasing the number of I / O terminals.

[0068] The combined circuit layer 130 includes a first dielectric layer 131, a wiring layer 133, and a second dielectric layer 135. Chip pads are provided on the substrate chip 110. The first dielectric layer 131 is disposed on the substrate chip 110. The wiring layer 133 is embedded in the first dielectric layer 131 and connected to the chip pads. The second dielectric layer 135 is disposed on the first dielectric layer 131, and wiring pads 137 are disposed on the second dielectric layer 135 and connected to the wiring layer 133. Specifically, both the first dielectric layer 131 and the second dielectric layer 135 are made of dielectric materials, such as silicon nitride, silicon oxynitride, polyimide, benzocyclobutene, etc. The wiring layer 133 can be a copper layer, serving an electrical connection function.

[0069] It should be noted that the width of the combined circuit layer 130 is the same as the width of the substrate chip 110, which facilitates a single cut.

[0070] In summary, this embodiment provides a fan-in package structure 100. By providing a molding compound 150 outside the combined circuit layer 130 and the substrate chip 110, it can effectively block the influence of external moisture on the chip. Simultaneously, the side of the substrate chip 110 furthest from the combined circuit layer 130 is exposed outside the molding compound 150. Connecting wires 170 are bent and disposed within the molding compound 150, extending downwards to expose one side of the substrate chip 110 on the surface of the molding compound 150. On one hand, by providing bent connecting wires 170, the conventional top-of-die wiring can be changed to peripheral back-side wiring, expanding the distribution range of I / O pads with fewer restrictions on their number and distribution area, significantly improving integration density. On the other hand, it prevents moisture from entering the combined circuit layer 130 through the wiring outlets, improving waterproofing. Furthermore, by providing an external pin structure 171, the soldering effect during board mounting can be improved, preventing desoldering. Furthermore, the use of multiple bent connecting wires 170 can effectively reduce the warping of the encapsulated body 150 during the molding process, acting as a balancing spring and providing a certain buffering capacity to prevent the substrate chip 110 from being subjected to excessive stress, which could lead to problems such as microcracks and delamination.

[0071] Second Embodiment

[0072] See Figure 4 This embodiment provides a fan-in package structure 100, whose basic structure, principle and technical effects are the same as those of the first embodiment. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content in the first embodiment.

[0073] In this embodiment, the fan-in package structure 100 includes a substrate chip 110, a combined circuit layer 130, a molding compound 150, and connecting wires 170. The combined circuit layer 130 is disposed on one side of the substrate chip 110, and the molding compound 150 covers the combined circuit layer 130 and the substrate chip 110. The connecting wires 170 are bent and disposed within the molding compound 150. The side of the substrate chip 110 away from the combined circuit layer 130 is exposed in the molding compound 150. The combined circuit layer 130 is electrically connected to the substrate chip 110. One end of the connecting wire 170 is connected to the combined circuit layer 130, and the other end is bent and extends onto the molding compound 150, exposing one side surface of the substrate chip 110. The portion of the connecting wire 170 away from the combined circuit layer 130 extends out of the molding compound 150 and is bent to form an external pin 171. The external pin 171 is attached to the side surface of the molding compound 150 exposed from the substrate chip 110 and protrudes relative to the substrate chip 110.

[0074] In this embodiment, a protective adhesive film layer 180 is attached to the surface of the substrate chip 110 away from the combined circuit layer 130, and a clearance opening is provided on the protective adhesive film layer 180, in which the external pin 171 is disposed. Specifically, the protective adhesive film layer 180 may only cover the back side of the substrate chip 110, thereby forming a clearance opening around it, preventing the protective adhesive film layer 180 from covering the external pin 171 and causing electrical connection failure. At the same time, by providing the protective adhesive film layer 180, the back side of the substrate chip 110 can be protected.

[0075] In this embodiment, a clearance opening is provided on the protective film layer 180, which allows the protective film layer 180 to be spaced apart from the external pin 171, so that the solder side can crawl into the gap during soldering to enhance the soldering effect.

[0076] In other preferred embodiments of the present invention, the protective film layer 180 may also extend toward the surface of the molding compound 150 and be bonded to the external pin 171, so that there is no gap between the protective film layer 180 and the external pin 171, thereby enhancing the protective effect of the protective film layer 180.

[0077] In other preferred embodiments of the present invention, the height of the external pin 171 relative to the molding compound 150 may be greater than the height of the protective film layer 180 relative to the molding compound 150, so that the external pin 171 is bonded to the pads on the substrate during soldering, and the protective film layer 180 is kept at a distance from the substrate to enhance the bottom heat dissipation function.

[0078] Third Embodiment

[0079] See Figure 5 This embodiment provides a fan-in package structure 100, whose basic structure, principle and technical effects are the same as those of the first embodiment. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content in the first embodiment.

[0080] The fan-in package structure 100 provided in this embodiment includes a substrate chip 110, a combined circuit layer 130, a molding compound 150, and connecting wires 170. The combined circuit layer 130 is disposed on one side of the substrate chip 110, and the molding compound 150 covers the combined circuit layer 130 and the substrate chip 110. The connecting wires 170 are bent and disposed within the molding compound 150. The side of the substrate chip 110 away from the combined circuit layer 130 is exposed in the molding compound 150. The combined circuit layer 130 is electrically connected to the substrate chip 110. One end of the connecting wire 170 is connected to the combined circuit layer 130, and the other end is bent and extends onto the molding compound 150, exposing one side surface of the substrate chip 110. The portion of the connecting wire 170 away from the combined circuit layer 130 extends out of the molding compound 150 and is bent to form an external pin 171. The external pin 171 is attached to the side surface of the molding compound 150 exposed from the substrate chip 110 and protrudes relative to the substrate chip 110.

[0081] In this embodiment, an anti-oxidation layer 190 is also provided on the surface of the external pin 171 away from the molding compound 150. Specifically, an anti-oxidation metal material can be coated in the groove 310 of the carrier 300, and then the external pin 171 is ground and welded to the anti-oxidation layer 190 during the bending process of the connecting wire 170. This results in an anti-oxidation layer 190 forming on the surface of the external pin 171 after the carrier 300 is removed, which can improve the anti-oxidation function of the external pin 171 and avoid the need for a separate anti-oxidation process in the traditional process, thus improving manufacturing efficiency.

[0082] Fourth embodiment

[0083] This embodiment provides a method for preparing a fan-in package structure 100, which is used to prepare the fan-in package structure 100 as provided in the first embodiment, the second embodiment, or the third embodiment. The basic structure and principle of the fan-in package structure 100 and the resulting technical effects are the same as those in the first embodiment, the second embodiment, or the third embodiment. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding contents in the first embodiment, the second embodiment, or the third embodiment.

[0084] This embodiment provides a method for fabricating a fan-in package structure 100, which is used to fabricate the fan-in package structure 100 as described in the foregoing embodiments. The fabrication method includes the following steps:

[0085] S1: Provide one vehicle (300).

[0086] See also Figure 6 Specifically, the carrier 300 is pre-set with a groove 310, which is the placement area for the subsequent external pin 171 after bending.

[0087] S2: Mount wafer 400 onto carrier 300.

[0088] See also Figure 7 Specifically, an adhesive layer is coated on the carrier 300, and then the wafer 400 is mounted on the carrier 300. The adhesive layer serves as the bonding agent, and after curing, the wafer 400 is fixed. The carrier 300 can be made of materials such as glass, silicon oxide, or metal. The wafer 400 is a single-piece structure without cutting, achieving fan-in packaging. The material of the wafer 400 can be silicon nitride, gallium nitride, etc., and its adhesive layer can be a thermoplastic adhesive layer. Since the carrier 300 needs to be removed in subsequent processes, the adhesive layer here can be thermoplastic. Its material can be separated by irradiating with UV light, which exposes the back of the substrate chip 110 for heat dissipation.

[0089] S3: A combined circuit layer 130 is formed on wafer 400.

[0090] See also Figure 8 Specifically, after the wafer 400 is mounted, a combined circuit layer 130 can be formed on the wafer 400, which is electrically connected to the substrate chip 110. Specifically, firstly, a dielectric material is uniformly coated onto the wafer 400 using a spin coater, and then soft-baking is performed on a hot plate to form a first dielectric layer 131. Then, an oven is used to accelerate the curing of the first dielectric layer 131 to a fully cured and stable state. Next, patterning is performed on the first dielectric layer 131, followed by exposure and development to form patterned openings. A metal layer is then electroplated into the openings to form the circuit layer. This circuit layer can also be formed using physical vapor deposition (PVD), chemical vapor deposition (CVD), sputtering, or electroless plating processes. The circuit layer is connected to the chip pads on the front side of the substrate chip 110 to achieve electrical conduction. Then, dielectric material is spin-coated onto the first dielectric layer 131 again, and after curing, a second dielectric layer 135 is formed. Finally, laser grooving or etching grooving is performed on the second dielectric layer 135, and metal is electroplated to form the wiring pad 137 structure. The wiring pad 137 contacts the circuit layer, thereby realizing the conduction of electrical functions. The formed wiring pad 137 serves as the base pad for subsequent wire bonding structures.

[0091] In this embodiment, the dielectric material can be silicon nitride, silicon oxynitride, polyimide, benzocyclobutene, or other materials.

[0092] S4: Cut wafer 400 and combined circuit layer 130 along the first dicing path.

[0093] See also Figure 9Specifically, along a predetermined first dicing path, the wafer 400 and the combined circuit layer 130 are separated using laser cutting or mechanical cutting processes to form multiple individual substrate chips 110 with the combined circuit layer 130. The depth of the first dicing path extends to the surface of the carrier 300 and corresponds to the position of the groove 310. After cutting, the surface of the wafer 400 can be cleaned to remove silicon residue from the dicing path.

[0094] S5: Drill wires on the adjacent combined circuit layer 130 to form a connecting conductor 170.

[0095] See also Figure 10 Specifically, after forming a single base chip 110, the adjacent wiring pads 137 can be connected by vertical wire bonding using a wire bonding process, at which time the connecting wire 170 is suspended above the groove 310.

[0096] S6: 170° bendable connecting wire.

[0097] See also Figure 11 After wire bonding is completed, the middle portion of the connecting wire 170 can be bent to the bottom of the groove 310. The portion of the connecting wire 170 bent into the groove 310 extends out of the molding compound 150 and is bent to form an external pin 171. Specifically, using a bending process, the connecting wire 170 on the first cutting track is bent and pressed into the bottom of the groove 310 on the carrier 300. The bottom of the groove 310 flattens the wire arc, forming a bending angle, and the bending point of the groove 310 is lower than the back side of the substrate chip 110.

[0098] It should be noted that when fabricating the fan-in package structure 100 as provided in the third embodiment, before bending the connecting wire 170, an anti-oxidation layer 190 needs to be formed in the groove 310. The anti-oxidation layer 190 is used for grinding and soldering onto the external pin 171. Specifically, a seed layer can be formed in the groove 310 after a single cut using metal sputtering or dispensing. The seed layer is a metal layer, which can be the anti-oxidation layer 190, such as a nickel-tungsten-copper alloy layer. During the bending step of the connecting wire 170, the connecting wire 170 is ground and soldered onto the seed layer on the surface of the groove 310, thereby depositing the anti-oxidation layer 190 onto the surface of the external pin 171. This achieves an anti-oxidation process on the surface of the external pin 171, thus avoiding the need for a separate anti-oxidation layer 190 process on the external pin 171 in traditional processes, greatly improving manufacturing efficiency.

[0099] S7: A molding compound 150 is formed on a carrier 300, which covers the combined circuit layer 130 and the substrate chip 110.

[0100] See also Figure 12Specifically, a molding compound 150 is formed on the carrier 300 using a molding process. This molding can be achieved using liquid spraying or traditional pressure injection molding. The molding mold needs to be designed with arc-shaped grooves 310 to protect the connecting wires 170. The molding compound 150 protects the connecting wires 170 and fills the first dicing area, i.e., the location of the groove 310, thus protecting the sidewalls of the substrate chip 110 and the combined circuit layer 130. This improves the chip structure's resistance to moisture and avoids the problem of the dielectric layer being exposed and easily corroded by moisture in traditional structures, thereby improving product reliability and lifespan.

[0101] S8: Remove the carrier 300 so that the side of the substrate chip 110 away from the combined circuit layer 130 is exposed in the molding compound 150.

[0102] See also Figure 13 Specifically, UV light is irradiated on the bottom of the vehicle 300, and the vehicle 300 is removed by separating the adhesive layer.

[0103] It should be noted that when preparing the fan-in package structure 100 provided in the second embodiment, after removing the carrier 300, a protective adhesive film layer 180 can be attached to the surface of the substrate chip 110 away from the combined circuit layer 130 to protect the back side of the substrate chip 110.

[0104] S9: Cut the encapsulated body 150 along the second cutting track.

[0105] Please continue reading Figure 1 Specifically, the second cutting channel cuts the molded package 150 along the central area of ​​the first cutting channel using laser cutting or mechanical cutting, separating the package structure into individual products, thereby completing the process. After cutting, one end of the connecting wire 170 is connected to the combined circuit layer 130, and the other end is bent and extended to the molded package 150, exposing one side of the substrate chip 110.

[0106] In summary, this embodiment provides a method for fabricating a fan-in package structure 100. By providing a molding compound 150 outside the combined circuit layer 130 and the substrate chip 110, the influence of external moisture on the chip can be effectively blocked. Simultaneously, the side of the substrate chip 110 furthest from the combined circuit layer 130 is exposed within the molding compound 150. Connecting wires 170 are bent and disposed within the molding compound 150, extending downwards to expose one side of the substrate chip 110 on the surface of the molding compound 150. On one hand, by providing bent connecting wires 170, the conventional top-of-die wiring can be changed to peripheral back-side wiring, expanding the distribution range of I / O pads with fewer restrictions on their number and distribution area, significantly improving integration density. On the other hand, it prevents moisture from entering the combined circuit layer 130 through the wiring exits, improving waterproofing.

[0107] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for fabricating a fan-in package structure, characterized in that, The preparation method includes: Provide a vehicle; The wafer is mounted onto the carrier; A combined circuit layer is formed on the wafer; The wafer and the combined circuit layer are cut along the first dicing path to form a plurality of substrate chips with the combined circuit layer; Connecting conductors are formed by bonding wires on adjacent combined circuit layers; Bending the connecting wire; A molding compound is formed on the carrier, the molding compound covering the combined circuit layer and the substrate chip; Remove the carrier so that the side of the substrate chip away from the combined circuit layer is exposed in the molding compound; The encapsulated body is cut along the second cutting path; The combined circuit layer is electrically connected to the substrate chip, one end of the connecting wire is connected to the combined circuit layer, and the other end is bent and extended to the molded body to expose one side surface of the substrate chip.

2. The method for preparing the fan-in package structure according to claim 1, characterized in that, The carrier is pre-prepared with a groove corresponding to the first cutting path, and the step of bending the connecting wire includes: The middle portion of the connecting wire is bent to the bottom of the groove; The portion of the connecting wire bent into the groove extends out of the encapsulation body and is bent to form an external pin.

3. The method for preparing the fan-in package structure according to claim 2, characterized in that, Prior to the step of bending the middle portion of the connecting wire to the bottom of the groove, the preparation method further includes: An anti-oxidation layer is formed within the groove; The anti-oxidation layer is used for grinding and soldering onto the external pin.

4. The method for preparing the fan-in package structure according to claim 1, characterized in that, After the step of removing the carrier, the preparation method further includes: A protective adhesive film layer is attached to the surface of the substrate chip on the side away from the combined circuit layer.

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