Clock boost circuit, on-chip high voltage generation circuit and electronic devices

Abstract

A clock boost circuit, an on-chip high-voltage generation circuit, and electronic devices are disclosed. The clock boost circuit includes an output terminal, a capacitor, a first switch connected between the output terminal and ground, a second switch connected between the second terminal of the capacitor and the output terminal, and a third switch connected between a power supply terminal and the output terminal. The output terminal receives a clock signal, and the first terminal of the capacitor receives a clock signal with a delayed rising edge. By controlling the switch, preferably implemented by a MOSFET, via the clock signal, the clock signal with a delayed rising edge, and combinations thereof, and by combining the boost effect of the capacitor, the output swing of the clock signal used by the charge pump can be effectively increased, for example, from 0 to 2 × V. DD This allows for the development of more efficient on-chip high-voltage generation circuits and electronic devices.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuits, and more particularly to a clock boost circuit, an on-chip high voltage generation circuit, and an electronic device. Background Technology

[0002] Common integrated circuit chips typically operate at power supply voltages of 3V, 1.8V, and 1.2V. However, some specialized chips, such as flash memory chips, require a voltage higher than the power supply voltage for internal operation. In such cases, a voltage conversion circuit must be incorporated within the chip to generate the higher voltage. Similarly, display panels require a voltage higher than the power supply voltage to drive their pixel array.

[0003] Since inductors are not easy to implement and integrate on chips, DC-DC conversion circuits are usually implemented using components that can be easily integrated onto chips, such as MOS capacitors and MOS switches, for example, charge pumps. Figure 1 An example of a charge pump used in an integrated circuit chip is shown. In the illustrated four-stage Dickson charge pump, MOSFETs (MD1-MD5) are connected in series between the input and output terminals and are connected via diodes. Capacitors C1-C4 are connected to the clock (φ1) and the inverting clock (φ2), respectively. Cf acts as a current limiter.

[0004] In practical applications, the input terminal is connected to a power supply voltage V. DD The odd-numbered capacitors and even-numbered capacitors perform pumping operations at different half-clock cycles to achieve a high-level output V at the output terminal. HH .

[0005] As semiconductor process nodes continue to advance, the operating voltage of integrated circuit chips gradually decreases, while the high voltages used internally for tasks such as writing and erasing flash memory remain essentially unchanged. This results in lower efficiency for charge pump circuits at lower supply voltages.

[0006] Therefore, a solution is needed to improve the efficiency of the charge pump inside the chip. Summary of the Invention

[0007] One technical problem this disclosure aims to solve is to provide a clock boost circuit capable of providing an increased swing range, particularly a swing of 0 to 2 × V, via a capacitor combined with a charging branch. DD The clock signal. This enables a more efficient on-chip high-voltage generation circuit.

[0008] According to a first aspect of this disclosure, a clock boost circuit is provided, comprising: an input terminal for receiving a first clock signal; an output terminal; a capacitor, a first end of which receives a second clock signal, the second clock signal and the first clock signal having the same falling edge, the rising edge of the second clock signal being delayed compared to the rising edge of the first clock signal; a first switch connected between the output terminal and ground; a second switch connected between a second end of the capacitor and the output terminal; and a charging branch connected between a power supply terminal and the output terminal; wherein, when both the first clock signal and the second clock signal are low, the first switch is turned on, and the second switch and the charging branch are turned off; when the first clock signal is high and the second clock signal is low, the first switch is turned off, and the second switch and the charging branch are turned on; when both the first clock signal and the second clock signal are high, the first switch and the charging branch are turned off, and the second switch is turned on.

[0009] According to a second aspect of this disclosure, an on-chip high voltage generation circuit is provided, comprising: a clock boost circuit as described in the first aspect, the clock boost circuit outputting a high-value boosted clock signal; and a charge pump circuit acquiring the high-value boosted clock signal as a clock signal for the charge pump circuit.

[0010] According to a third aspect of this disclosure, an electronic device is provided, including an on-chip high-voltage generation circuit as described in the second aspect. Optionally, the electronic device is a memory or a display device.

[0011] Therefore, the clock boost circuit controls the charging of capacitors by multiple switches, preferably implemented by MOSFETs, via the clock signal, the clock signal with rising edge delay, and the signal that changes only during the delay period, thereby providing a clock with a higher swing. This enables a more efficient on-chip high-value boost circuit and improves the performance of electronic devices. Attached Figure Description

[0012] The above and other objects, features and advantages of this disclosure will become more apparent from the more detailed description of exemplary embodiments thereof taken in conjunction with the accompanying drawings, wherein like reference numerals generally denote like parts.

[0013] Figure 1 An example of a charge pump used in an integrated circuit chip is shown.

[0014] Figure 2 A circuit diagram of a clock boost circuit according to an embodiment of the present invention is shown.

[0015] Figure 3 It shows Figure 2The timing diagram shown is of the clock boost circuit during operation.

[0016] Figure 4 A circuit diagram of a clock boost circuit according to an embodiment of the present invention is shown.

[0017] Figure 5 An example of a rising edge delay circuit is shown.

[0018] Figure 6 It shows Figure 4 The timing diagram shown is of the clock boost circuit during operation.

[0019] Figure 7 A circuit diagram of a clock boost circuit according to an embodiment of the present invention is shown.

[0020] Figure 8 It shows Figure 7 The timing diagram shown is of the clock boost circuit during operation.

[0021] Figure 9 An example of the composition of an on-chip high voltage generation circuit according to an embodiment of the present invention is shown. Detailed Implementation

[0022] Preferred embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While preferred embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0023] The terms "first" and "second" used herein are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0024] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0025] The following disclosure provides many different implementations or examples for carrying out different structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or reference letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various implementations and / or arrangements discussed.

[0026] As mentioned earlier, certain types of integrated circuit chips require high-level voltages for internal operation. For example, flash memory chips still require essentially unchanged high voltages for programming and erasing even when the power supply voltage is reduced. The generation of these high voltages depends on on-chip high-voltage circuitry.

[0027] As the chip's power supply voltage gradually decreases, while the chip's internal high-voltage requirements remain essentially unchanged (i.e., V...), DD Decrease, V HH (With the same demand), existing high-voltage generation circuits require more levels of charge pumps and are inefficient.

[0028] To improve the swing amplitude of the high-voltage charge pump in special integrated circuit chips (e.g., flash memory chips), the present invention proposes a driving circuit that can be used as a clock boost circuit, connected after an oscillator circuit for providing a clock signal, and improves the efficiency of the charge pump by providing a clock signal with a multiplied amplitude, thereby reducing power consumption.

[0029] Figure 2 A circuit diagram of a clock signal boost circuit according to an embodiment of the present invention is shown.

[0030] The input terminal of clock boost circuit 1 receives the clock signal CLK. Here, the clock signal CLK can be a rectangular wave signal generated by an oscillator; for example, the high level is equal to the power supply voltage V. DD A rectangular wave signal with a low level equal to 0 and high and low levels of equal duration (i.e., a duty cycle of 50%), which may also be referred to as the "first clock signal" below. In this document, the inverted signal of the clock signal CLK may also be used, which can be represented as the inverted clock signal CLK. B Furthermore, this can be obtained by connecting an inverter to the clock signal CLK. It should be understood that the inverted clock signal CLK... B Switching under control can also be seen as switching under the control of the clock signal CLK, except that the high and low levels of control are in the opposite direction.

[0031] Figure 2 The clock boost circuit 1 shown also uses a rising edge delayed clock signal CLK.D Here, the clock signal CLK with a rising edge delay. D The clock signal CLK has the same low-level start position as the clock signal CLK, but with a rising edge delay. D The high level of the clock signal CLK starts slightly later than the high level of the clock signal CLK. D It has the same falling edge as the clock signal CLK, but a rising edge that is delayed compared to the clock signal CLK. Therefore, when the clock signal CLK is low, the rising edge of the clock signal CLK is delayed. D It is also a low level; when the clock signal CLK is high, the rising edge of the clock signal CLK is delayed. D First a low level, then a high level. In the clock signal CLK, a low level is 0V and a high level is V. DD When dealing with a rectangular wave signal, the clock signal CLK with a rising edge delay... D Similarly, a low level can be 0V and a high level can be V. DD A rectangular wave signal. Clock signal CLK and rising edge delayed clock signal CLK. D Clock signals CLK have the same period, but are delayed due to the rising edge. D The rising edge of the clock signal CLK is delayed, therefore the rising edge of the clock signal is delayed. D The high-level duration of the clock signal CLK must be shorter than the high-level duration of the clock signal CLK. For example, if the duty cycle of the clock signal CLK is 50%, meaning the high-level duration of the clock signal CLK is equal to the low-level duration, then the rising edge delayed clock signal CLK... D The duty cycle is less than 50%, that is, the clock signal CLK with a rising edge delay. D The high-level duration must be shorter than the low-level duration. In the following text, the rising edge delayed clock signal CLK may also be referred to as such. D This is referred to as the "second clock signal". In this article, a clock signal CLK with a rising edge delay can also be used. D The inverted signal, which can be represented as a clock signal CLK with its rising edge delayed by the inverted phase. DB And it can be controlled by the clock signal CLK D This is obtained after connecting an inverter. It should be understood that the clock signal CLK is delayed on the rising edge of the inverted phase. DB Switching under control can also be viewed as a clock signal CLK delayed on the rising edge. D The switch is operated under the control of [the system], but the high and low levels of the control are in the opposite direction.

[0032] like Figure 2As shown, the clock boost circuit 1 includes: an input terminal, an output terminal OUT, a capacitor C, a first switch S1, a second switch S2, and a charging branch Br. The input terminal receives a first clock signal CLK. The first terminal of capacitor C (i.e., the first node N1) receives a second clock signal CLK. D The second clock signal CLK D The second clock signal CLK has the same falling edge as the first clock signal CLK. D The rising edge of the first clock signal CLK is delayed compared to the rising edge of the second clock signal CLK. The first switch S1 is connected between the output terminal OUT and ground GND. The second switch S2 is connected between the second terminal (i.e., the second node N2) of the capacitor C and the output terminal OUT. The charging branch Br is connected between the power supply terminal and the output terminal OUT. The rising edge of the first clock signal CLK and the second clock signal CLK are delayed. D When both are at low levels, the first switch S1 is turned on, and the second switch S2 and the charging branch Br are disconnected. When the first clock signal CLK is high, the second clock signal CLK... D When the signal is low, the first switch S1 is open, and the second switch S2 and the charging branch Br are open. This is achieved when the first clock signal CLK and the second clock signal CLK are low. D When both are at high level, the first switch S1 and the charging branch Br are disconnected, and the second switch S2 is turned on.

[0033] In some embodiments, the charging branch Br (such as...) Figure 2 (As shown in the dashed box) includes a third switch S3, one end of which is connected to the power supply terminal, and the other end is connected to the output terminal OUT. This is in response to the first clock signal CLK and the second clock signal CLK. D When both are low or both are high, the third switch S3 is open, and the first clock signal CLK is high and the second clock signal CLK is high. D When the voltage level is low, the third switch S3 is turned on.

[0034] Figure 3 It shows Figure 2 The timing diagram shown is of the clock boost circuit during operation. Figure 3 The timing diagram shown is after the clock boost circuit has stabilized (e.g., after several clock cycles). Once the clock boost circuit has stabilized, the voltage difference across capacitor C is V. DD . Figure 3 Two complete clock cycles are shown. For ease of explanation, stages I, II, and III are marked in the latter clock cycle. It should be understood that stages I, II, and III can be included within each clock cycle.

[0035] The following will combine Figure 3 The components and working principle of the clock boost circuit 1 are further described.

[0036] Specifically, the input terminal of the clock boost circuit 1 receives the first clock signal CLK, and the first terminal of the capacitor C of the clock boost circuit 1 receives the second clock signal CLK. D Among them, the second clock signal CLK D The second clock signal CLK has the same falling edge as the first clock signal CLK. D The rising edge of the clock signal is delayed compared to the rising edge of the first clock signal CLK, specifically as follows: Figure 3 As shown, the first clock signal CLK and the second clock signal CLK D They have the same period. The second clock signal CLK D The rising edge of the first clock signal CLK is delayed by a certain time compared to the rising edge of the second clock signal CLK (as shown by the duration Tdelay of stage II in the figure). Within each cycle, the low level of the first clock signal CLK and the second clock signal CLK... D The low-level start position is the same as that of the second clock signal CLK. D The high-level start position is later than the high-level start position of the first clock signal CLK. The low level of the first clock signal CLK and the second clock signal CLK D The low levels of the two clock signals CLK and CLK have the same magnitude, for example, both are 0V. The high level of the first clock signal CLK and the second clock signal CLK... D The high levels of both have the same amplitude, for example, both are power supply voltage V. DD For example, a first clock signal CLK is generated by an oscillator, and a second clock signal CLK is generated based on the first clock signal CLK by a rising edge delay circuit. D .

[0037] like Figure 3 As shown, the first clock signal CLK and the second clock signal CLK D The cycle can be divided into three phases. In phase I, the first clock signal CLK and the second clock signal CLK... D Both are low level. In Phase II, the first clock signal CLK is high level, and the second clock signal CLK... D The level is low. In Phase III, the first clock signal CLK is high, and the second clock signal CLK is low. D It is a high level.

[0038] In phase I, the first switch S1 is on, while the second switch S2 and the third switch S3 are both off. Since the output terminal OUT of the clock boost circuit 1 is grounded when the first switch S1 is on, the voltage at the output terminal OUT of the clock boost circuit 1 is 0V, meaning the clock signal CLK output from the output terminal OUT of the clock boost circuit 1 is zero. OUT The voltage is 0V. In phase I, the voltage at the first node N1 is 0V, and the voltage at the second node N2 is the supply voltage V. DD .

[0039] In stage II, the first switch S1 is open, while the second switch S2 and the third switch S3 are both closed. Since the output terminal OUT of the clock boost circuit 1 is connected to the power supply terminal when the third switch S3 is closed, the voltage at the output terminal OUT of the clock boost circuit 1 is equal to the power supply voltage V. DD That is, the clock signal CLK output by the output terminal OUT of clock boost circuit 1. OUT The voltage is the power supply voltage V. DD Since both the second switch S2 and the third switch S3 are on, the second terminal of capacitor C is connected to the power supply terminal and maintains the power supply voltage V. DD The first terminal of capacitor C receives the second clock signal CLK. D At this time, the second clock signal CLK D The voltage level remains low; therefore, the voltage difference across capacitor C remains at V. DD .

[0040] In phase III, the first switch S1 and the third switch S3 are open, and the second switch S2 is on. This is because the first terminal of capacitor C receives the second clock signal CLK. D When the voltage level is high, the voltage across capacitor C will not change abruptly (i.e., the voltage difference across capacitor C remains constant at V). DD Therefore, the voltage across the second terminal of capacitor C is twice the supply voltage (i.e., 2 × V). DD The clock signal CLK is output from the output terminal OUT of clock boost circuit 1. OUT The voltage is 2×V DD .

[0041] exist Figure 2 In the clock boost circuit shown, the charging branch Br is turned on in stage II, providing the power supply voltage V to the output terminal. DD At the same time, the second terminal of capacitor C is maintained at the power supply voltage V. DD The charging branch Br is cut off in stages I and II. Specifically, the first switch S1 and the second switch S2 can be implemented to be controlled by the clock signal CLK (or the inverted clock signal CLK). BThe switches controlled by the circuit, for example, the first switch S1 and the second switch S2, can each be implemented as a single MOS transistor or a combination of multiple MOS transistors. Since the charging branch Br (e.g., the third switch S3) is only activated in stage II, the control signal for the charging branch Br (e.g., the third switch S3) needs to be based on the first clock signal CLK and the second clock signal CLK. D The charging branch Br (e.g., the third switch S3) can be implemented as a single MOS transistor or a combination of multiple MOS transistors, for example, multiple MOS transistors connected in series. Specifically, the present invention can generate the charging circuit from V in the third stage III via the output terminal OUT. DD To 2×V DD The transition causes the charging branch Br to shut down in the third stage.

[0042] Figure 4 A circuit diagram of a clock boost circuit according to an embodiment of the present invention is shown. Figure 4 The clock boost circuit 10 shown implements switches S1-S3 through MOS transistors.

[0043] Specifically, in the clock boost circuit 10, the first switch S1 and the third switch S3 are implemented as the first NMOS transistor M1 and the second NMOS transistor M3, and the second switch S2 is implemented as the first PMOS transistor M2. Additionally, the clock boost circuit 10 may also include a capacitor C, a rise delay circuit 11, and a first inverter 12.

[0044] Specifically, the input of the rise delay circuit 11 receives the first clock signal CLK, and the output of the rise delay circuit 11 provides the second clock signal CLK. D To the first terminal (first node N1) of capacitor C.

[0045] Figure 5 An exemplary rising edge delay circuit 11 is shown. The rising edge delay circuit 11 may include: an inverter 111, an inverter 112, capacitors C11 and C12, a NAND gate circuit 114, and an inverter 113. The input of inverter 111 receives a first clock signal CLK. The output of inverter 111 is connected to the first terminal of capacitor C11 and the input of inverter 112. The second terminal of capacitor C11 is grounded. The output of inverter 112 is connected to the first terminal of capacitor C12 and the first input of NAND gate circuit 114. The second terminal of capacitor C12 is grounded. The second input of NAND gate circuit 114 receives the first clock signal CLK. The output of NAND gate circuit 114 is connected to the input of inverter 113. The output of inverter 113 outputs a second clock signal CLK. D It is understandable that the implementation of the rising edge delay circuit 11 is not limited to... Figure 5The circuit shown.

[0046] In some embodiments, the rise delay circuit 11 may further include a buffer (not shown). The input terminal of the buffer is connected to the output terminal of the rise delay circuit 11, and the output terminal of the buffer is connected to the first terminal of the capacitor C.

[0047] In this embodiment, the input terminal of the inverter 12 in the clock boost circuit 10 is connected to the input terminal of the clock boost circuit 10, and the inverter 12 is used to provide a clock signal CLK that is inverted with the first clock signal. B .

[0048] like Figure 4 As shown, the output terminal of inverter 12 is connected to the gate of the first NMOS transistor M1 and the gate of the first PMOS transistor M2, respectively. That is, the gates of the first NMOS transistor M1 and the first PMOS transistor M2 receive the clock signal CLK, which is inverted from the first clock signal CLK. B The gate of the second NMOS transistor M3 is connected to the input terminal of the clock boost circuit 10, and receives the first clock signal CLK.

[0049] Furthermore, the first clock signal CLK and the second clock signal CLK D The high level is the power supply voltage V. DD In other embodiments, the first clock signal CLK and the second clock signal CLK D The high level is not limited to the power supply voltage; it can also be a preset high voltage. The first clock signal CLK and the second clock signal CLK D The low level can be 0V.

[0050] Figure 6 It shows Figure 4 The timing diagram shown is of the clock boost circuit during operation. Figure 6 The timing diagram shown is after the clock boost circuit has stabilized (e.g., after several clock cycles). After the clock boost circuit stabilizes, the capacitor C has a voltage of V across it. DD -V T The voltage difference. The following will combine... Figure 6 ,describe Figure 4 The circuit shown operates.

[0051] In phase I, the first clock signal CLK and the second clock signal CLK DBoth are at low level. At this time, the first NMOS transistor M1 is turned on, and the first PMOS transistor M2 and the second NMOS transistor M3 are turned off. Because the first NMOS transistor M1 is turned on, the output terminal OUT is grounded to GND, that is, the voltage of the output terminal OUT is 0V. That is, the clock signal CLK output by the output terminal OUT of the clock boost circuit 10 is... OUT The voltage is 0V. This is due to the second clock signal CLK. D The voltage is low, therefore, the voltage across the first terminal of capacitor C is 0V. After the clock boost circuit stabilizes, the voltage across the second terminal of capacitor C is V. DD -V T Because the first PMOS transistor M2 is off, the second terminal of capacitor C can maintain V. DD -V T It will not be pulled down to 0.

[0052] In phase II, the first clock signal CLK is high, and the second clock signal CLK... D The voltage level is low, at which point the first NMOS transistor M1 is off. The gate voltage of the second NMOS transistor M3 is the high level of the first clock signal CLK (i.e., V). DD The drain voltage of the second NMOS transistor M3 is the power supply voltage V. DD Therefore, the source voltage of the second NMOS transistor M3 is V. DD -V T V T This is the threshold voltage of the second NMOS transistor M3. The voltage at the output terminal OUT is V. DD -V T The gate of the first PMOS transistor M2 receives a clock signal CLK that is inverted by the first clock signal. B Therefore, the gate voltage of the first PMOS transistor M2 is low. The first PMOS transistor M2 is turned on, and its drain voltage is V. DD -V T The source voltage (voltage at the second terminal of capacitor C) of the first PMOS transistor M2 is also V. DD -V T At this time, the second clock signal CLK D The voltage level remains low, therefore, the voltage difference across capacitor C is V. DD -V T .

[0053] In phase I of the first clock cycle after the clock boost circuit 10 starts operating, the voltage at both the first and second terminals of capacitor C is 0. In phase II of the first clock cycle, the power supply terminals charge capacitor C via the second NMOS transistor M3 and the first PMOS transistor M2. After several clock cycles, capacitor C has a voltage difference V. DD -V T .

[0054] In Phase III, the first clock signal CLK is high, and the second clock signal CLK... D The voltage is high. At this time, the first NMOS transistor M1 remains off. The voltage across the first terminal of capacitor C changes from 0 to V. DD The voltage across the second terminal of capacitor C is from V DD -V T It becomes 2×V DD -V T The gate voltage of the first PMOS transistor M2 is low, and the source voltage of the first PMOS transistor M2 is 2 × V. DD -V T Therefore, the first PMOS transistor M2 remains in the on state, and the drain voltage of the first PMOS transistor M2 is 2 × V. DD -V T The voltage at the output terminal OUT is also 2×V. DD -V T At this time, the gate voltage of the second NMOS transistor M3 is the high level V of the first clock signal CLK. DD The source voltage of the second NMOS transistor M3 is 2 × V. DD -V T Therefore, the first NMOS transistor M3 is in the off state, and the voltage at the output terminal OUT will not be pulled down to the power supply voltage V. DD That is, in stage III, the clock signal CLK output by the output terminal OUT of the clock boost circuit 10. OUT The voltage is 2×V DD -V T .

[0055] Phase III is followed by Phase I of the next clock cycle, with the first clock signal CLK and the second clock signal CLK. D All are at low level. At this time, the first NMOS transistor M1 is turned on, the first PMOS transistor M2 and the second NMOS transistor M3 are turned off, and the voltage at the output terminal OUT becomes 0. Due to the second clock signal CLK... D When the voltage is low, the voltage at the first terminal of capacitor C changes from V. DD When the voltage drops to 0, the voltage across the second terminal of capacitor C changes from 2 × V. DD -VT Change to V DD -V T .

[0056] As can be seen from the above, although the charging branch formed by a single NMOS transistor M3 can provide conduction to the output terminal OUT only in stage II, because NMOS transistor M3 is connected as a diode in stage II, the high level of the final clock signal is 2×V. DD -V T .

[0057] Figure 7 A circuit diagram of a clock boost circuit according to an embodiment of the present invention is shown. Figure 7 As shown, the clock boost circuit 20 includes NMOS transistor M1, PMOS transistor M2, PMOS transistor M3, PMOS transistor M4, NMOS transistor M5, PMOS transistor M6, and capacitor C. NMOS transistor M1 is implemented as a first switch S1, and PMOS transistor M2 is implemented as a second switch S2. PMOS transistors M3 and M4 together form a charging branch Br, where PMOS transistor M3 is implemented as a third switch and PMOS transistor M4 is implemented as a fourth switch. Therefore, the charging branch Br includes a third switch and a fourth switch connected in series between the power supply terminal and the output terminal. The third switch and the fourth switch operate when the first clock signal CLK is high and the second clock signal CLK is high. D The fourth switch is turned on when the signal is low, and is activated by the second clock signal CLK. D The high-level period is interrupted. The third switch is a second PMOS transistor, the fourth switch is a third PMOS transistor, and the gate of the second PMOS transistor is connected to the third clock signal CLK. A The third clock signal CLK A In the first clock signal CLK and the second clock signal CLK D The signal is high during the same period of time, during the first clock signal CLK and the second clock signal CLK. D The voltage level is low during different periods. Furthermore, NMOS transistor M5 and PMOS transistor M6 are used to control the on / off state of PMOS transistor M4. NMOS transistor M5 is implemented as the fifth switch, and PMOS transistor M6 is implemented as the sixth switch. Thus, the fifth switch is connected between the gate of the third PMOS transistor and ground; the sixth switch is connected between the gate of the third PMOS transistor and the output terminal; the fifth switch operates on the second clock signal CLK. D Disconnect during the high level period of the second clock signal CLK. DThe sixth switch is turned on during the low level period of the second clock signal CLK. D During the high level period, the fourth switch is turned on, controlling the second clock signal CLK to be activated. D The circuit is disconnected during the high-level period. The fifth switch is a second NMOS transistor, and the sixth switch is a fourth PMOS transistor. The gate of the second NMOS transistor is connected to an inverted second clock signal, and the gate of the fourth PMOS transistor is connected to a power supply terminal.

[0058] In addition to using the first clock signal CLK and the second clock signal CLK D In addition to control, in this embodiment, it can also be based on the first clock signal CLK and the second clock signal CLK. D The generated signal is used for switch control. Specifically, the clock signal CLK A It can be in CLK and CLK D The same level is low during the period of CLK and CLK. D Signals that are high during different periods, such as CLK. A Low level is 0V, high level is V DD A rectangular wave signal. In some embodiments, the clock signal CLK A Through the first clock signal CLK and the second clock signal CLK D The clock signal CLK is obtained through an AND operation. In some embodiments, the clock signal CLK is... A It can also be achieved through, for example, clock signal CLK and clock signal CLK DB The clock signal CLK is obtained through NAND operations. DB The second clock signal CLK D The inverted clock signal. In some embodiments, the clock signal CLK A It can also be achieved through the clock signal CLK B Second clock signal CLK D The "AND" operation is used to obtain the clock signal CLK. The clock signal CLK can also be used in the following text. A It is called the "third clock signal".

[0059] The gate of NMOS transistor M1 is connected to the clock signal CLK. B The drain is connected to the output terminal OUT, and the source is connected to the GND terminal. NMOS transistor M1 can also be referred to as the "first NMOS transistor".

[0060] The gate of PMOS transistor M2 is also connected to an inverted clock signal CLK. B The source is connected to the second node N2, and the drain is connected to the output terminal OUT. PMOS transistor M2 can also be called the "first PMOS transistor".

[0061] The gate of PMOS transistor M3 is connected to the third clock signal CLK. A The source is connected to the power supply terminal, and the drain is connected to the third node N3. PMOS transistor M3 can also be called "second PMOS transistor".

[0062] The gate of PMOS transistor M4 is connected to the fourth node N4, the source is connected to the third node N3, and the drain is connected to the output terminal OUT. PMOS transistor M4 can also be referred to as the "third PMOS transistor". The path from the power supply terminal to the output terminal via PMOS transistors M3 and M4 is the charging branch Br.

[0063] The gate connection clock signal CLK of NMOS transistor M5 is also connected. DB The drain is connected to the fourth node N4, and the source is connected to the GND terminal. NMOS transistor M5 can also be called the "second NMOS transistor".

[0064] The gate of PMOS transistor M6 is connected to the power supply terminal, the source is connected to the fourth node N4, and the drain is connected to the output terminal OUT. PMOS transistor M6 can also be referred to as the "fourth PMOS transistor".

[0065] The first terminal of capacitor C is connected to the first node N1 to receive the clock signal CLK with a rising edge delay. D The second end is connected to the second node N2.

[0066] The power terminals provide the power supply voltage V. DD The GND terminal is grounded, for example. The circuit may include input terminals for receiving the clock signal CLK generated by the oscillator. The received clock signal CLK can be processed in various ways to obtain the various clock signals mentioned above, such as an inverted clock signal CLK. B The rising edge delayed clock signal CLK D The inverted rising edge delayed clock signal CLK DB and clock signal CLK A .

[0067] Specifically, the clock signal CLK can be connected to an inverter, such as... Figure 7 The inverter 22 shown directly produces a clock signal CLK that is inverted from the clock signal. B The input of inverter 22 is connected to the input terminal of the clock boost circuit, and the output is connected to the gates of NMOS transistor M1 and PMOS transistor M2, thereby providing a clock signal CLK, which is inverted from the clock signal, to the gates of NMOS transistor M1 and PMOS transistor M2. B .

[0068] In one embodiment, the second clock signal CLK can be obtained by connecting the first clock signal CLK to the rising edge delay circuit 21. D The rising edge delay circuit 21 can have the following characteristics: Figure 5 The configuration shown allows the input signal to be transformed by the rising edge delay circuit into a rising edge delayed output signal, namely, the second clock signal CLK. D .

[0069] Furthermore, a second clock signal CLK is generated from the first clock signal CLK. D Afterwards, the first clock signal CLK and the second clock signal CLK can also be used. D Process to obtain the third clock signal CLK A .exist Figure 7 In the illustrated embodiment, the output of the rising edge delay circuit 21 is connected to the inverter 23 to obtain the clock signal CLK. D The inverted signal CLK DB The output of inverter 23 is connected to the first input of NAND gate 24, and the clock signal CLK is connected to the second input of NAND gate 24. That is, the clock signal CLK is generated by the first clock signal CLK and the second clock signal CLK. DB The NAND operation obtains the third clock signal CLK. A .

[0070] The output of NAND gate 24 is connected to the gate of PMOS transistor M3. The output of NAND gate 24 is also connected to the first input of NAND gate 26. The second output of NAND gate 26 receives the first clock signal CLK. The output of NAND gate 26 is connected to the input of inverter 27. The third clock signal CLK... A The result of passing the first clock signal CLK through NAND gate 26 and inverter 27 is the clock signal CLK. D The output of inverter 27 is connected to the first node N1. It should be understood that the first node N1 can also be directly connected to the output of rising edge delay circuit 21 to obtain CLK. D In other words, this invention addresses how to obtain the second clock signal CLK from the first clock signal CLK. D and the third clock signal CLK A The approach is not limited. However, in a preferred embodiment, the second clock signal CLK of the first node N1... D It is the third clock signal CLK based on the gate of PMOS transistor M3. A This allows the third clock signal CLK of the gate of PMOS transistor M3 to be obtained at the beginning of phase III. AThe voltage level transition (from low to high) occurs earlier than the voltage transition (from low to high) at the first terminal (first node N1) of capacitor C. This ensures that the charging branch Br is already disconnected when the first node N1 goes high, and the output terminal OUT is at a high level of 2V. DD There will be no leakage or loss.

[0071] Although the figure shows the inverted clock signal CLK obtained using inverter 22. B The second clock signal CLK is obtained using the rising edge delay circuit 21. D And the third clock signal CLK obtained using inverter 23 and NAND gate 24. A However, it should be understood that in other implementations, the clock boost circuit 20 of the present invention can directly obtain the first clock signal CLK and the inverted clock signal CLK from an external source. B and / or the second clock signal CLK D and / or the third clock signal CLK A In other words, the inverter 22, the rising edge delay circuit 21, and the logic gates 23-27 in the clock boost circuit 20 are not essential. The clock boost circuit 20 can also directly obtain the required first clock signal CLK and the inverted clock signal CLK from external circuits. B Second clock signal CLK D Or the third clock signal CLK A For example, a non-overlapping signal generation circuit generates a clock signal CLK and an inverted clock signal CLK based on a clock signal provided by an oscillator. B .

[0072] The following will combine Figure 8 The timing diagram illustrates the circuit's operation. In this example and the following description of the invention, the clock signal CLK is 0V low and V high. DD A rectangular wave signal with the same duration for both high and low levels (i.e., a duty cycle of 50%).

[0073] Figure 8 It shows Figure 7 The timing diagram shown is of the clock boost circuit during operation. Figure 8 The timing diagram shown is after the clock boost circuit 20 has stabilized (e.g., after several clock cycles). Once the clock boost circuit has stabilized, the voltage difference across capacitor C is V. DD . Figure 8 Two complete cycles are shown. For ease of explanation, stages I, II, and III are labeled within the latter clock cycle. In stage I, the first clock signal CLK and the second clock signal CLK... DBoth are low level. In Phase II, the first clock signal CLK is high, and the second clock signal CLK... D It remains low. In Phase III, the first clock signal CLK and the second clock signal CLK... D Both are high. In contrast, the third clock signal CLK... A It is low only in phase II, and high in phases I and III.

[0074] In phase I, the inverted clock signal CLK B When the signal is high, NMOS transistor M1 is turned on and PMOS transistor M2 is turned off, so the output of the output terminal OUT is 0.

[0075] Due to the third clock signal CLK A When the voltage is high, the gate and source voltages of PMOS transistor M3 are the same, both being V. DD Therefore, PMOS transistor M3 (charging branch Br) is turned off. This is due to the inverted rising edge delay of the clock signal CLK. DB During stage I, the voltage level is high, so NMOS transistor M5 is turned on, and the voltage at node N4 is 0. PMOS transistor M6 is turned off because its gate is connected to the power supply voltage, and both its gate and drain are at low levels.

[0076] In phase II, the first clock signal CLK transitions to V. DD But the second clock signal CLK D It has not yet jumped to V DD Due to the inverted clock signal CLK B The value jumps to 0, so NMOS transistor M1 is turned off and PMOS transistor M2 is turned on.

[0077] On the charging branch Br, due to the third clock signal CLK A The timer jumps to 0, therefore PMOS transistor M3 turns on. Simultaneously, due to the clock signal CLK... DB With the voltage at node OUT remaining high, the voltage at node 4 (N4) is 0. Therefore, PMOS transistor M4 is turned on, causing the voltage at output terminal OUT to become V. DD PMOS transistor M6 remains off because its gate is connected to the power supply voltage.

[0078] At this time, because PMOS transistor M2 is turned on, the second terminal of capacitor C (second node N2) is maintained at V. DD Because the second clock signal CLK is connected to the first node N1. D The voltage is still 0, therefore the capacitor C has a voltage across its sides of V. DD The voltage difference.

[0079] In Phase III, the first clock signal CLK and the second clock signal CLK D All are V DD Inverting clock signal CLK B The value is 0, therefore NMOS transistor M1 remains off, and PMOS transistor M2 remains on. At this time, due to the second clock signal CLK... D Jump from 0 to V DD The capacitor C is used to maintain V DD The voltage difference causes the voltage at the second node N2 to jump to 2V. DD This causes the output terminal OUT to become 2V. DD .

[0080] Clock signal CLK DB When the voltage is 0, NMOS transistor M5 is off. The gate of PMOS transistor M6 is at a high level V. DD The drain voltage is 2V. DD Therefore, PMOS transistor M6 is turned on, and the source voltage of PMOS transistor M6 is 2V. DD The gate and drain voltages of PMOS transistor M4 are both 2V. DD Therefore, PMOS transistor M4 is turned off, and the third clock signal CLK... A The voltage transitions to a high level, therefore the gate and source voltages of PMOS transistor M3 are the same, both being V. DD PMOS transistor M3 is also turned off. Therefore, the charging branch Br is disconnected.

[0081] Thus, through stages I, II, and III, the output terminal OUT was able to switch from 0 to V. DD It then became 2×V DD This increases the output swing of the drive circuit, thereby achieving the effect of increasing the output swing of the drive circuit.

[0082] In phase I of the next clock cycle, the first clock signal CLK and the second clock signal CLK D All values ​​become 0, and the voltage at the second node N2 changes from 2V. DD Coupled as V DD The output terminal OUT is pulled low to 0 by the NMOS transistor M1, which is turned on, while the PMOS transistor M2 is pulled low by the inverted clock signal CLK. B Change to V DD Since the capacitor is disconnected, capacitor C essentially retains its value of V. DD The potential difference.

[0083] Phase II is between the rising edge of clock signal CLK and the rising edge delay of clock signal CLK. D Between the rising edges, the duration of stage II is equal to the rising edge delay of the clock signal CLK. DThe shorter the time difference between the rising edge of the clock signal CLK and the rising edge of the clock signal CLK, the closer the final output clock waveform will be to a low level of 0 and a high level of 2V. DD A rectangular wave. However, since the PMOS transistor M2 needs sufficient time to conduct, the time difference cannot be too small, that is, stage II cannot be too short. Therefore, it is necessary to reasonably select the rise time delay, for example, by reasonably setting the rise time delay circuit 21.

[0084] Thus, the clock boost circuit 20 of the present invention provides a swing from 0 to 2×V. DD The clock signal.

[0085] The output OUT of the clock boost circuit can then be used as the clock input of the charge pump. Since the charge pump requires a pair of clocks with opposite phases, a non-overlapping clock generator circuit can also be used to generate a clock input based on the output of the clock boost circuit 20. Figure 1 φ1 and φ2 are shown.

[0086] The charge pump is only one part of the on-chip high-voltage generation circuit. Therefore, the present invention can also be implemented as an on-chip high-voltage generation circuit, including the clock boost circuit as described above, and a charge pump that acquires the output of the clock boost circuit as a clock input.

[0087] Figure 9 An example of the composition of an on-chip high voltage generation circuit according to an embodiment of the present invention is shown.

[0088] like Figure 9 As shown, in addition to the charge pump, the high voltage generation circuit also includes a reference voltage generation circuit, a regulator, an oscillator, a level shifter, and the clock boost circuit of the present invention.

[0089] Reference voltage generation circuits typically use a bandgap reference to provide a reference voltage V that is independent of supply voltage and temperature. REF .

[0090] The regulator includes, for example, a voltage divider resistor and a comparator. The voltage divider resistor includes a first resistor disposed between the output of the charge pump and the feedback node, and a second resistor disposed between the feedback node and ground. The feedback node is connected to the first input of the comparator to provide the voltage V corresponding to the output voltage V of the charge pump. PP Proportional feedback voltage V MON The second input of the comparator receives the reference voltage V. REF The comparator responds to the feedback voltage V. MON With reference voltage V REFCompare, if V MON Greater than V REF (V PP If the voltage is greater than the target voltage value, turn off the charge pump. MON Less than V REF (V PP The charge pump operates when the voltage is less than the target voltage value. An oscillator provides the clock signal to the charge pump. The oscillator receives the power supply voltage V. DD This generates a clock signal, the highest amplitude of which is the power supply voltage V. DD .

[0091] The charge pump is the main component of the high-voltage generation circuit and can be implemented using various circuit structures. Figure 1 The Dickson charge pump shown is a commonly used type. The Dickson charge pump uses a pair of non-overlapping clock signals. In other embodiments, the charge pump can use two pairs of non-overlapping clock signals. A voltage level shifter is a switch used to connect the charge pump to a load. The load can be a capacitor or a resistor, or both.

[0092] Unlike existing technologies that directly utilize oscillators to generate high values ​​up to the power supply voltage V, DD The clock voltage is used as the input clock for the charge pump. The on-chip high-voltage generation circuit of this invention can be connected after the oscillator and combined with the front. Figure 2 , Figure 4 and Figure 7 The described clock boost circuit is used to obtain a swing increase, for example, from 0 to 2×V. DD The clock signal.

[0093] Furthermore, the present invention can also be implemented as an electronic device, including the on-chip high-voltage generation circuit described above. The electronic device may, in particular, be a memory or a display device. The memory may be a non-volatile memory, such as flash memory. Flash memory includes NOR Flash and NAND Flash. The on-chip high-voltage generation circuit is used to provide various operating voltages for the flash memory, such as the voltages required for read operations, erase operations, and programming operations. The memory may also be a volatile memory, such as DRAM. The display device is, for example, a liquid crystal display, an organic light-emitting diode display, etc.

[0094] The clock boost circuit according to the present invention, along with the corresponding on-chip high-voltage generation circuit and electronic device, has been described in detail above with reference to the accompanying drawings. The clock boost circuit of the present invention controls a switch, preferably implemented by a MOSFET, via a clock signal and a clock signal with a delayed rising edge. Combined with the boost effect of a capacitor, it can effectively increase the output swing of the clock signal used by the charge pump from 0 to 2 × V. DD This allows for the development of more efficient on-chip high-voltage generation circuits and electronic devices.

[0095] The various embodiments of the present invention have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A clock boost circuit, characterized in that, include: The input terminal receives the first clock signal; Output terminals; A capacitor, wherein a first terminal of the capacitor receives a second clock signal, the second clock signal and the first clock signal having the same falling edge, and the rising edge of the second clock signal being delayed compared to the rising edge of the first clock signal; The first switch is connected between the output terminal and ground; A second switch is connected between the second end of the capacitor and the output terminal; The charging branch is connected between the power supply terminal and the output terminal; Specifically, when both the first clock signal and the second clock signal are low, the first switch is turned on, and the second switch and the charging branch are disconnected; when the first clock signal is high and the second clock signal is low, the first switch is disconnected, and the second switch and the charging branch are turned on; when both the first clock signal and the second clock signal are high, the first switch and the charging branch are disconnected, and the second switch is turned on.

2. The clock boost circuit according to claim 1, characterized in that, include: A rising edge delay circuit is provided, wherein the input terminal of the rising edge delay circuit receives the first clock signal, and the output terminal of the rising edge delay circuit provides the second clock signal.

3. The clock boost circuit according to claim 1, characterized in that, The first switch is a first NMOS transistor, the second switch is a first PMOS transistor, and the clock boost circuit further includes an inverter connected between the input terminal and the gate of the first switch.

4. The clock boost circuit according to claim 1, characterized in that, The high level of both the first clock signal and the second clock signal is the power supply voltage.

5. The clock boost circuit as described in claim 1, characterized in that, The charging branch includes a second NMOS transistor, the drain of which is connected to the power supply terminal, the gate of which receives the first clock signal, and the source of which is connected to the output terminal.

6. The clock boost circuit as described in claim 1, characterized in that, The charging branch includes a third switch and a fourth switch connected in series between the power supply terminal and the output terminal. The third switch and the fourth switch are turned on when the first clock signal is high and the second clock signal is low, and the fourth switch is turned off during the high level of the second clock signal.

7. The clock boost circuit as described in claim 6, characterized in that, The third switch is a second PMOS transistor, the fourth switch is a third PMOS transistor, and the gate of the second PMOS transistor is connected to a third clock signal. The third clock signal is high when the first clock signal and the second clock signal are at the same level, and low when the first clock signal and the second clock signal are at different levels.

8. The clock boost circuit as described in claim 7, characterized in that, Also includes: The fifth switch is connected between the gate of the third PMOS transistor and ground; The sixth switch is connected between the gate and the output terminal of the third PMOS transistor; The fifth switch is open during the high level of the second clock signal and open during the low level of the second clock signal; the sixth switch is open during the high level of the second clock signal; and the fourth switch is open during the high level of the second clock signal.

9. The clock boost circuit as described in claim 8, characterized in that, The fifth switch is a second NMOS transistor, and the sixth switch is a fourth PMOS transistor. The gate of the second NMOS transistor is connected to an inverted second clock signal, and the gate of the four PMOS transistors is connected to a power supply terminal.

10. An on-chip high-voltage generation circuit, characterized in that, include: The clock boost circuit as described in any one of claims 1-9; as well as Charge pump circuit.

11. An electronic device, characterized in that, Includes the on-chip high voltage generation circuit as described in claim 10.

12. The electronic device as claimed in claim 11, characterized in that, The electronic device is a memory or a display device.

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