Chip testing method and related apparatus

Abstract

Embodiments of the present application disclose a chip testing method and related device, the method comprising: obtaining to-be-verified information of a chip when the chip is powered on for the first time, the to-be-verified information comprising P backup trim information; obtaining standard information of the chip, the standard information comprising P standard trim information; comparing the P backup trim information with the P standard trim information to obtain Q backup trim information that passes the comparison; verifying the verification information corresponding to the Q backup trim information to obtain K backup trim information that passes the verification; performing a loading operation according to the K backup trim information that passes the verification to obtain a loading result flag; starting a processor and reading the loading result flag; and confirming that the chip is normal when the loading result flag meets a preset condition. The embodiments of the present application can improve the chip testing efficiency.

Description

Technical Field

[0001] This application relates to the field of chip technology, specifically to a chip testing method and related apparatus. Background Technology

[0002] With the rapid development of electronic technology, new energy vehicles are gradually being accepted by the public and are becoming a future development trend. New energy vehicles can integrate various chips to enhance their intelligence. Among these, TRIM information is crucial for the chip's power supply, clock, and functional specifications. Errors in TRIM information can cause the chip to malfunction or affect its performance. Inconsistencies between the chip specifications and the delivered chip will also affect its functional specifications. Therefore, improving chip testing efficiency is an urgent issue that needs to be addressed. Summary of the Invention

[0003] This application provides a chip testing method and related apparatus, which can improve chip testing efficiency.

[0004] In a first aspect, embodiments of this application provide a chip testing method, wherein when the chip is not being used for the first time, the data in the chip is empty, the method comprising:

[0005] When the chip is powered on for the first time, the chip's verification information is obtained. The verification information includes P backup trim information, each backup trim information corresponds to a verification information, and P is an integer greater than 1.

[0006] Obtain the standard information of the chip, which includes P standard trim information, and the standard trim information corresponds one-to-one with the backup trim information;

[0007] The P backup trim information is compared with the P standard trim information to obtain Q backup trim information that are successfully matched, where Q is a positive integer less than or equal to P;

[0008] The verification information corresponding to the Q backup trim information is verified to obtain K backup trim information that have been successfully verified, where K is a positive integer less than or equal to Q;

[0009] A loading operation is performed based on the K successfully verified backup trim information to obtain a loading result flag;

[0010] Start the processor and read the loading result flag;

[0011] Check whether the loading result flag meets the preset conditions;

[0012] When the loading result flag meets the preset conditions, the chip is confirmed to be normal.

[0013] Secondly, embodiments of this application provide a chip testing apparatus applied to a chip. When the chip is not being used for the first time, the data in the chip is empty. The apparatus includes: an acquisition unit, a comparison unit, a verification unit, a loading unit, a startup unit, a detection unit, and a determination unit.

[0014] The acquisition unit is used to acquire the chip's verification information when the chip is powered on for the first time. The verification information includes P backup trim information, each backup trim information corresponds to a verification information, where P is an integer greater than 1; and to acquire the chip's standard information, which includes P standard trim information, each standard trim information corresponding to a backup trim information.

[0015] The comparison unit is used to compare the P backup trim information with the P standard trim information to obtain Q backup trim information that are successfully matched, where Q is a positive integer less than or equal to P.

[0016] The verification unit is used to verify the verification information corresponding to the Q backup trim information to obtain K backup trim information that have been successfully verified, where K is a positive integer less than or equal to Q.

[0017] The loading unit is used to perform a loading operation based on the K successfully verified backup trim information to obtain a loading result flag.

[0018] The startup unit is used to start the processor and read the loading result flag;

[0019] The detection unit is used to detect whether the loading result flag meets the preset conditions;

[0020] The determining unit is used to confirm that the chip is normal when the loading result flag meets the preset condition.

[0021] Thirdly, embodiments of this application provide a chip including a processor, a memory, a communication interface, and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the processor, and the programs include instructions for performing the steps in the first aspect of embodiments of this application.

[0022] Fourthly, embodiments of this application provide a computer-readable storage medium storing a computer program for electronic data interchange, wherein the computer program causes a computer to perform some or all of the steps described in the first aspect of embodiments of this application.

[0023] Fifthly, embodiments of this application provide a computer program product, wherein the computer program product includes a non-transitory computer-readable storage medium storing a computer program operable to cause a computer to perform some or all of the steps described in the first aspect of embodiments of this application. The computer program product may be a software installation package.

[0024] Implementing the embodiments of this application has the following beneficial effects:

[0025] As can be seen, the chip testing method and related apparatus described in the embodiments of this application are applied to chips. When the chip is not used for the first time, the data in the chip is empty. When the chip is powered on for the first time, the chip's verification information is obtained. The verification information includes P backup trim information, each backup trim information corresponding to one verification information, where P is an integer greater than 1. The chip's standard information is obtained, which includes P standard trim information. The standard trim information corresponds one-to-one with the backup trim information. The P backup trim information is compared with the P standard trim information to obtain Q backup trim information that successfully match, where Q is a positive integer less than or equal to P. The Q backup trim information corresponds to... The verification information is verified to obtain K successfully verified backup trim information, where K is a positive integer less than or equal to Q. A loading operation is then performed based on the K successfully verified backup trim information to obtain a loading result flag. The processor is then started, the loading result flag is read, and it is checked whether the loading result flag meets preset conditions. If the loading result flag meets the preset conditions, the chip is confirmed to be normal. In this way, multiple backup trim information can be compared and verified based on the successfully compared backup trim information when the chip is first powered on. The processor is then started based on the verification result to test whether the chip has a fault. This is equivalent to achieving the effect of multiple chip tests in one chip test process, which can improve chip testing efficiency. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a schematic flowchart of a chip testing method provided in an embodiment of this application;

[0028] Figure 2 This is a schematic flowchart of another chip testing method provided in an embodiment of this application;

[0029] Figure 3 This is a schematic diagram of the structure of a chip provided in an embodiment of this application;

[0030] Figure 4 This is a functional unit block diagram of a chip testing device provided in an embodiment of this application. Detailed Implementation

[0031] The terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that comprises a series of steps or units is not limited to the listed steps or units, but in one possible example includes steps or units not listed, or in one possible example includes other steps or units inherent to these processes, methods, products, or apparatuses.

[0032] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0033] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present application.

[0034] Please see Figure 1 , Figure 1 This is a schematic flowchart of a chip testing method provided in an embodiment of this application. As shown in the figure, it is applied to a chip. When the chip is not being used for the first time, the data in the chip is empty. The method includes:

[0035] 101. When the chip is powered on for the first time, the chip's verification information is obtained. The verification information includes P backup trim information, each backup trim information corresponds to a verification information, and P is an integer greater than 1.

[0036] In this embodiment, the chip is empty when it is not being used for the first time. The chip can be an automotive chip or an in-vehicle chip.

[0037] In practice, when the chip is powered on for the first time, the chip's verification information can be obtained. This verification information can include P backup trim messages, each backup trim message corresponding to a verification message, where P is an integer greater than 1. The verification information can be stored in memory or a register.

[0038] In this embodiment of the application, when the chip is powered on, it can first check whether the trim area is empty. After the comparison is passed according to the agreed sequence, the loading process of trim information will be started.

[0039] Optionally, step 101 above, obtaining the verification information of the chip, may include the following steps:

[0040] 11. Obtain a test instruction, wherein the test instruction carries test content parameters;

[0041] 12. Obtain the chip's verification information based on the test content parameters.

[0042] In this embodiment of the application, the test instruction may carry corresponding test content parameters. The test content parameters may include at least one of the following: test purpose, test function type, test environment, etc., which are not limited here.

[0043] In practice, test instructions can be obtained, which carry test content parameters. The mapping relationship between preset test content parameters and information to be verified can be stored in advance. Based on this mapping relationship, the information to be verified of the chip can be determined. In this way, targeted testing can be achieved, and the reliability of the chip can be improved.

[0044] 102. Obtain the standard information of the chip, the standard information including P standard trim information, and the standard trim information and the backup trim information correspond one-to-one.

[0045] In this embodiment, the standard information may include P standard trim information entries, with each standard trim information entry corresponding one-to-one with a backup trim information entry. The standard information may be stored in a memory or a register.

[0046] In this embodiment of the application, the information to be verified and the standard information can be stored in the same storage area or in different storage areas.

[0047] 103. Compare the P backup trim information with the P standard trim information to obtain Q backup trim information that are successfully matched, where Q is a positive integer less than or equal to P.

[0048] In this embodiment of the application, P backup trim information can be compared one by one with P standard trim information, that is, the P backup trim values ​​are compared with the corresponding standard trim values ​​to obtain Q backup trim information that are successfully matched, where Q is a positive integer less than or equal to P.

[0049] Optionally, each of the P backup trim messages corresponds to a weight value, which represents the importance of the backup trim value; between steps 103 and 104, the following steps may also be included:

[0050] A1. Obtain the weight value of each backup trim information in the Q backup trim information to obtain Q weight values;

[0051] A2. Determine the first sum of the Q weight values ​​and the mean of the Q weight values;

[0052] A3. Obtain the sum of the weight values ​​of each backup trim information in the P backup trim information to get the second sum;

[0053] A4. Determine the ratio between the first sum and the second sum;

[0054] A5. Detect whether the ratio is greater than a first preset threshold and whether the mean is greater than a second preset threshold;

[0055] A6. When the ratio is greater than the first preset threshold and the mean is greater than the second preset threshold, perform the step of verifying the verification information corresponding to the Q backup trim information.

[0056] In this embodiment of the application, both the first preset threshold and the second preset threshold can be preset or set by system default.

[0057] In the specific implementation, each of the P backup trim messages corresponds to a weight value, which is used to represent the importance of the backup trim value. Of course, different trim messages can correspond to different category labels, and each category label corresponds to a weight value.

[0058] Specifically, the weight value of each of the Q backup trim information can be obtained to get Q weight values. Then, the first sum and the mean of the Q weight values ​​are determined. Then, the sum of the weight values ​​of each of the P backup trim information is obtained to get the second sum. The ratio between the first sum and the second sum is determined. It is checked whether the ratio is greater than a first preset threshold and whether the mean is greater than a second preset threshold. If the ratio is greater than the first preset threshold and the mean is greater than the second preset threshold, the step of verifying the verification information corresponding to the Q backup trim information is executed. Otherwise, it indicates that there is a fault in the trim information or the chip.

[0059] For example, in this embodiment of the application, during the verification process, the backed-up trim information can also be classified according to its importance, into two categories: particularly important and generally important. Firstly, for particularly important trim information, multiple backups can be loaded, and the verified trim information is voted on. The trim information that wins the vote is considered reliable (for example, out of 5 trims, at least 3 must be identical to be considered a reliable trim). For generally important trim information, the backup trim information is loaded sequentially. As soon as a verified trim information is identified, it is loaded into the designated location and becomes effective.

[0060] Optionally, the following steps may also be included:

[0061] A5. Obtain test condition parameters;

[0062] A6. Determine the first preset threshold and the second preset threshold based on the test condition parameters.

[0063] In this embodiment, the test condition parameters may include at least one of the following: internal test condition parameters, external test environment conditions, etc., which are not limited herein. Internal test condition parameters may include at least one of the following: application type, memory size, number of CPU cores, CPU model, GPU model, etc., which are not limited herein. External test environment conditions may include at least one of the following: temperature, humidity, magnetic field interference intensity, weather, etc., which are not limited herein. A pre-stored mapping relationship between preset test condition parameters and a first preset threshold, and a pre-stored mapping relationship between preset test condition parameters and a second preset threshold, can be used. Based on these two mapping relationships, dynamic testing under different environments can be achieved, which helps improve the reliability of the chip.

[0064] 104. Verify the verification information corresponding to the Q backup trim information to obtain K backup trim information that have been successfully verified, where K is a positive integer less than or equal to Q.

[0065] In this embodiment of the application, the verification information corresponding to the Q backup trim information can be verified one by one. That is, the preset verification information can be stored in advance, and the verification information can be compared with the preset verification information to obtain the K backup trim information that have been successfully verified, where K is a positive integer less than or equal to Q.

[0066] 105. Perform a loading operation based on the K successfully verified backup trim information to obtain a loading result flag.

[0067] In this embodiment of the application, the loading operation is performed based on the K successfully verified backup trim information. That is, only the successfully verified backup trim information can be loaded, and after loading, the corresponding loading result flag can be obtained.

[0068] 106. Start the processor and read the loading result flag.

[0069] In this embodiment of the application, the processor, i.e. the CPU, can be started, and the loading result flag can be read by the processor and stored in a register.

[0070] In this embodiment, the CPU can only be started after the backed-up trim information has been successfully verified and loaded. After the CPU starts, it can query the read-only register to check whether the backed-up trim information has been loaded correctly.

[0071] 107. Check whether the loading result flag meets the preset conditions.

[0072] The preset conditions can be set in advance or be the system default. For example, the preset condition can be that the loading result flag is consistent with the preset loading result flag.

[0073] 108. When the loading result flag meets the preset conditions, confirm that the chip is normal.

[0074] In this embodiment of the application, if the loading result flag meets the preset conditions, it indicates that the chip is normal.

[0075] In the specific implementation, when a new chip is received, the chip contains no information or data. During the storage of trim information, multiple backups are stored. These backups are loaded sequentially and compared with the standard trim information until the correct trim information is found. Each backup trim information includes valid trim information and corresponding verification information. During the loading process, the backup trim information is verified; only backups that pass verification are considered reliable, and the loading result is then marked.

[0076] In the actual implementation, if the multiple backups of the trim information are correctly loaded by querying the read-only register, the CPU instruction is obtained and executed.

[0077] Optionally, the following steps may also be included:

[0078] B1. If the loading result flag does not meet the preset conditions, it is confirmed that the chip is faulty;

[0079] B2. Determine the target fault repair strategy corresponding to the loading result flag;

[0080] B3. Push the target fault repair strategy to the user.

[0081] In this embodiment, when the loading result flag does not meet the preset conditions, it can be confirmed that the chip is faulty. The loading result flag can determine some relevant information about the fault. For example, the loading result flag may include multiple loading result flags, each of which corresponds to a component, a region, or a module. The position of the erroneous loading result flag among the multiple loading result flags can be determined. According to the preset mapping relationship between the position and the fault repair strategy, the target fault repair strategy corresponding to the loading result flag is determined, and then the target fault repair strategy is pushed to the user. In this way, the corresponding fault repair strategy can be determined through the loading result flag, thereby improving the chip repair efficiency.

[0082] Optionally, when Q=0, the following steps may also be included:

[0083] C1. Load error flags;

[0084] C2. After the processor starts up, read the error flag bit;

[0085] C3. Decide whether to continue executing the program via software, or report a failure during startup.

[0086] In this embodiment of the application, when Q=0, it means that all P backup trim information have failed to match. Then, an error flag can be loaded. After the processor starts, the error flag is read, and the software determines whether to continue executing the program or to report a failure in the startup. In this way, the testers can be alerted in time.

[0087] In this embodiment, if all the backed-up TRIM information is corrupted, a loading error flag is set. After the CPU starts up and reads the error flag, the software program decides whether to continue executing the program or to report a failure to the host during the startup process.

[0088] Optionally, the following steps may also be included:

[0089] D1. Receive target instructions;

[0090] D2. Obtain the reference instruction set corresponding to the K backup trim information;

[0091] D3. Detect whether the target instruction exists in the reference instruction set;

[0092] D4. When the target instruction exists in the reference instruction set, execute the target instruction.

[0093] In this embodiment of the application, different backup trim information can correspond to different instructions. Therefore, a preset mapping relationship between backup trim information and instructions can be stored in advance. Based on the mapping relationship, instructions corresponding to K backup trim information are obtained, and these instructions are combined into a reference instruction set.

[0094] Furthermore, after obtaining the target instruction, it is possible to detect whether the target instruction exists in the reference instruction set. If the target instruction exists in the reference instruction set, the target instruction is executed. That is, different backup trim information can correspond to different functions. Only when the corresponding backup trim information is correct can the chip be guaranteed to perform the corresponding function. In this way, partial functional testing of the chip can be achieved, thereby improving the reliability of the chip.

[0095] As can be seen, the chip testing method described in this application embodiment is applied to a chip. When the chip is not used for the first time, the data in the chip is empty. When the chip is powered on for the first time, the chip's verification information is obtained. The verification information includes P backup trim information, each backup trim information corresponding to a verification information, where P is an integer greater than 1. The chip's standard information is obtained, which includes P standard trim information. The standard trim information corresponds one-to-one with the backup trim information. The P backup trim information is compared with the P standard trim information to obtain Q backup trim information that successfully match, where Q is a positive integer less than or equal to P. The verification information corresponding to the Q backup trim information is then processed. The verification information is used to obtain K successfully verified backup trim information, where K is a positive integer less than or equal to Q. A loading operation is then performed based on these K successfully verified backup trim information to obtain a loading result flag. The processor is then started, the loading result flag is read, and it is checked whether the loading result flag meets preset conditions. If the loading result flag meets the preset conditions, the chip is confirmed to be normal. In this way, multiple backup trim information can be compared and verified based on the successfully compared backup trim information when the chip is first powered on. The processor is then started based on the verification result to test whether the chip has a fault. This is equivalent to achieving the effect of multiple chip tests in one chip test process, which can improve chip testing efficiency.

[0096] Through the above embodiments of this application, the accuracy and reliability of the trim information can be guaranteed, and the process of verifying the trim information avoids inconsistencies between the chip clock and power supply and the calibration values, thereby solving the problem of the chip failing to work properly or affecting performance. Furthermore, it ensures that the chip specifications are consistent with the delivered specs without affecting the chip's functional specifications.

[0097] With the above Figure 1 The illustrated embodiments are consistent with those shown in the example. Please refer to [link / reference]. Figure 2 , Figure 2 This is a flowchart illustrating a chip testing method provided in an embodiment of this application. Applied to a chip, when the chip is not being used for the first time, the data in the chip is empty. This chip testing method includes:

[0098] 201. When the chip is powered on for the first time, the chip's verification information is obtained. The verification information includes P backup trim information, each backup trim information corresponds to a verification information, and P is an integer greater than 1.

[0099] 202. Obtain the standard information of the chip, the standard information including P standard trim information, and the standard trim information and the backup trim information correspond one-to-one.

[0100] 203. Compare the P backup trim information with the P standard trim information to obtain Q backup trim information that are successfully matched, where Q is a positive integer less than or equal to P.

[0101] 204. Verify the verification information corresponding to the Q backup trim information to obtain K backup trim information that have been successfully verified, where K is a positive integer less than or equal to Q.

[0102] 205. Perform a loading operation based on the K successfully verified backup trim information to obtain a loading result flag.

[0103] 206. Start the processor and read the loading result flag.

[0104] 207. Check whether the loading result flag meets the preset conditions.

[0105] 208. When the loading result flag meets the preset conditions, confirm that the chip is normal.

[0106] 209. If the loading result flag does not meet the preset conditions, it is confirmed that the chip is faulty.

[0107] The specific descriptions of steps 201-209 above can be found in the above descriptions. Figure 1 The corresponding steps of the described chip testing method will not be repeated here.

[0108] As can be seen, the chip testing method described in the embodiments of this application is applied to a chip. When the chip is not used for the first time, the data in the chip is empty. When the chip is powered on for the first time, multiple backup trim information can be compared, and the backup trim information that is successfully compared can be verified. The processor is started based on the verification result to test whether the chip has a fault. This is equivalent to achieving the effect of multiple chip tests in one chip test process, which can improve the chip testing efficiency.

[0109] Consistent with the above embodiments, please refer to Figure 3 , Figure 3 This is a schematic diagram of a chip structure provided in an embodiment of this application. As shown in the figure, when the chip is not being used for the first time, the data in the chip is empty. One or more programs are stored in the memory and configured to be executed by the processor. In this embodiment, the programs include instructions for performing the following steps:

[0110] When the chip is powered on for the first time, the chip's verification information is obtained. The verification information includes P backup trim information, each backup trim information corresponds to a verification information, and P is an integer greater than 1.

[0111] Obtain the standard information of the chip, which includes P standard trim information, and the standard trim information corresponds one-to-one with the backup trim information;

[0112] The P backup trim information is compared with the P standard trim information to obtain Q backup trim information that are successfully matched, where Q is a positive integer less than or equal to P;

[0113] The verification information corresponding to the Q backup trim information is verified to obtain K backup trim information that have been successfully verified, where K is a positive integer less than or equal to Q;

[0114] A loading operation is performed based on the K successfully verified backup trim information to obtain a loading result flag;

[0115] Start the processor and read the loading result flag;

[0116] Check whether the loading result flag meets the preset conditions;

[0117] When the loading result flag meets the preset conditions, the chip is confirmed to be normal.

[0118] Optionally, the above procedure may also include instructions for performing the following steps.

[0119] If the loading result flag does not meet the preset conditions, it is confirmed that the chip is faulty;

[0120] Determine the target fault repair strategy corresponding to the loading result flag;

[0121] The target fault repair strategy is pushed to the user.

[0122] Optionally, when Q=0, the above procedure also includes instructions for performing the following steps:

[0123] Load error flag;

[0124] After the processor starts up, the error flag bit is read;

[0125] The decision to continue the program can be made via software, or a report can be sent indicating a failure during the startup process.

[0126] Optionally, the above procedure may also include instructions for performing the following steps.

[0127] Receive target instructions;

[0128] Obtain the reference instruction set corresponding to the K backup trim information;

[0129] Detect whether the target instruction exists in the reference instruction set;

[0130] When the target instruction exists in the reference instruction set, the target instruction is executed.

[0131] Optionally, each of the P backup trim messages corresponds to a weight value, which is used to represent the importance of the backup trim value;

[0132] The above procedure also includes instructions for performing the following steps:

[0133] Obtain the weight value of each of the Q backup trim information to get Q weight values;

[0134] Determine the first sum of the Q weight values ​​and the mean of the Q weight values;

[0135] The sum of the weight values ​​of each backup trim information in the P backup trim information is obtained to obtain the second sum;

[0136] Determine the ratio between the first sum and the second sum;

[0137] Detect whether the ratio is greater than a first preset threshold and whether the mean is greater than a second preset threshold;

[0138] When the ratio is greater than a first preset threshold and the mean is greater than a second preset threshold, the step of verifying the verification information corresponding to the Q backup trim information is executed.

[0139] Optionally, the above procedure may also include instructions for performing the following steps:

[0140] Obtain test condition parameters;

[0141] The first preset threshold and the second preset threshold are determined based on the test condition parameters.

[0142] Optionally, in obtaining the verification information of the chip, the above program includes instructions for performing the following steps:

[0143] Obtain a test instruction, which carries test content parameters;

[0144] The chip's verification information is obtained based on the test parameters.

[0145] As can be seen, in the chip described in this application embodiment, the data in the chip is empty when the chip is not used for the first time. When the chip is powered on for the first time, the chip's verification information is obtained. The verification information includes P backup trim information, each backup trim information corresponding to a verification information, where P is an integer greater than 1. The chip's standard information is obtained, which includes P standard trim information. The standard trim information corresponds one-to-one with the backup trim information. The P backup trim information is compared with the P standard trim information to obtain Q backup trim information that successfully match, where Q is a positive integer less than or equal to P. The verification information corresponding to the Q backup trim information is then processed. The verification process involves obtaining K successfully verified backup trim information, where K is a positive integer less than or equal to Q. A loading operation is then performed based on these K successfully verified backup trim information to obtain a loading result flag. The processor is then started, the loading result flag is read, and it is checked whether the loading result flag meets preset conditions. If the loading result flag meets the preset conditions, the chip is confirmed to be normal. In this way, multiple backup trim information can be compared and verified based on the successfully compared backup trim information during the chip's first power-on. The processor is then started based on the verification result to test whether the chip has a fault. This is equivalent to achieving the effect of multiple chip tests in a single chip test process, thus improving chip testing efficiency.

[0146] Figure 4 This is a functional block diagram of the chip testing device 400 involved in the embodiments of this application. The device 400 is applied to a chip. When the chip is not being used for the first time, the data in the chip is empty. The device includes: an acquisition unit 401, a comparison unit 402, a verification unit 403, a loading unit 404, a startup unit 405, a detection unit 406, and a determination unit 407.

[0147] The acquisition unit 401 is used to acquire the chip's verification information when the chip is powered on for the first time. The verification information includes P backup trim information, each backup trim information corresponds to a verification information, and P is an integer greater than 1; and to acquire the chip's standard information, the standard information including P standard trim information, each standard trim information corresponding to a backup trim information.

[0148] The comparison unit 402 is used to compare the P backup trim information with the P standard trim information to obtain Q backup trim information that are successfully matched, where Q is a positive integer less than or equal to P.

[0149] The verification unit 403 is used to verify the verification information corresponding to the Q backup trim information to obtain K backup trim information that have been successfully verified, where K is a positive integer less than or equal to Q.

[0150] The loading unit 404 is used to perform a loading operation based on the K successfully verified backup trim information to obtain a loading result flag.

[0151] The startup unit 405 is used to start the processor and read the loading result flag;

[0152] The detection unit 406 is used to detect whether the loading result flag meets the preset conditions;

[0153] The determining unit 407 is used to confirm that the chip is normal when the loading result flag meets the preset condition.

[0154] Optionally, the device 400 is further specifically used for:

[0155] If the loading result flag does not meet the preset conditions, it is confirmed that the chip is faulty;

[0156] Determine the target fault repair strategy corresponding to the loading result flag;

[0157] The target fault repair strategy is pushed to the user.

[0158] Optionally, when Q=0, the device 400 is further specifically used for:

[0159] Load error flag;

[0160] After the processor starts up, the error flag bit is read;

[0161] The decision to continue the program can be made via software, or a report can be sent indicating a failure during the startup process.

[0162] Optionally, the device 400 is further specifically used for:

[0163] Receive target instructions;

[0164] Obtain the reference instruction set corresponding to the K backup trim information;

[0165] Detect whether the target instruction exists in the reference instruction set;

[0166] When the target instruction exists in the reference instruction set, the target instruction is executed.

[0167] Optionally, each of the P backup trim messages corresponds to a weight value, which is used to represent the importance of the backup trim value;

[0168] The device 400 is also specifically used for:

[0169] Obtain the weight value of each of the Q backup trim information to get Q weight values;

[0170] Determine the first sum of the Q weight values ​​and the mean of the Q weight values;

[0171] The sum of the weight values ​​of each backup trim information in the P backup trim information is obtained to obtain the second sum;

[0172] Determine the ratio between the first sum and the second sum;

[0173] Detect whether the ratio is greater than a first preset threshold and whether the mean is greater than a second preset threshold;

[0174] When the ratio is greater than a first preset threshold and the mean is greater than a second preset threshold, the step of verifying the verification information corresponding to the Q backup trim information is executed.

[0175] Optionally, the device 400 is further specifically used for:

[0176] Obtain test condition parameters;

[0177] The first preset threshold and the second preset threshold are determined based on the test condition parameters.

[0178] Optionally, in acquiring the verification information of the chip, the device 400 is specifically used for:

[0179] Obtain a test instruction, which carries test content parameters;

[0180] The chip's verification information is obtained based on the test parameters.

[0181] As can be seen, the chip testing device described in this application embodiment is applied to a chip. When the chip is not used for the first time, the data in the chip is empty. When the chip is powered on for the first time, the chip's verification information is obtained. The verification information includes P backup trim information, each backup trim information corresponding to a verification information, where P is an integer greater than 1. The chip's standard information is obtained, which includes P standard trim information. The standard trim information corresponds one-to-one with the backup trim information. The P backup trim information is compared with the P standard trim information to obtain Q backup trim information that successfully match, where Q is a positive integer less than or equal to P. The verification information corresponding to the Q backup trim information is then processed. The verification information is used to obtain K successfully verified backup trim information, where K is a positive integer less than or equal to Q. A loading operation is then performed based on these K successfully verified backup trim information to obtain a loading result flag. The processor is then started, the loading result flag is read, and it is checked whether the loading result flag meets preset conditions. If the loading result flag meets the preset conditions, the chip is confirmed to be normal. In this way, multiple backup trim information can be compared and verified based on the successfully compared backup trim information when the chip is first powered on. The processor is then started based on the verification result to test whether the chip has a fault. This is equivalent to achieving the effect of multiple chip tests in one chip test process, which can improve chip testing efficiency.

[0182] It is understood that the functions of each program module of the chip testing device in this embodiment can be specifically implemented according to the methods in the above method embodiments. The specific implementation process can be referred to the relevant descriptions in the above method embodiments, and will not be repeated here.

[0183] This application also provides a computer storage medium storing a computer program for electronic data interchange, which causes a computer to perform some or all of the steps of any of the methods described in the above method embodiments, wherein the computer includes a domain chip.

[0184] This application also provides a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program operable to cause a computer to perform some or all of the steps of any of the methods described in the above method embodiments. The computer program product may be a software installation package, and the computer includes a chip.

[0185] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

[0186] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0187] In the several embodiments provided in this application, it should be understood that the disclosed apparatus can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of the units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical or other forms.

[0188] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0189] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0190] If the integrated units described above are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage device (CMD). Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a memory and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned memory includes various media capable of storing program code, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0191] Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, which may include: flash drive, read-only memory (ROM), random access memory (RAM), disk or optical disk, etc.

[0192] The embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A method of testing a chip, characterized by, Applied to a chip, when the chip is not used for the first time, data in the chip is empty, the method comprises: When the chip is powered on for the first time, obtaining to-be-verified information of the chip, the to-be-verified information comprising P backup trim information, each backup trim information corresponding to a verification information, P being an integer greater than 1; Obtaining standard information of the chip, the standard information comprising P standard trim information, the standard trim information corresponding to the backup trim information one by one; Comparing the P backup trim information with the P standard trim information to obtain Q backup trim information with successful comparison, Q being a positive integer less than or equal to P; Verifying the verification information corresponding to the Q backup trim information to obtain K backup trim information with successful verification, K being a positive integer less than or equal to Q; According to the K backup trim information with successful verification, performing a loading operation to obtain a loading result flag; Starting a processor and reading the loading result flag; Detecting whether the loading result flag meets a preset condition; When the loading result flag meets the preset condition, confirming that the chip is normal.

2. The method of claim 1, wherein, The method further comprises: When the loading result flag does not meet the preset condition, confirming that the chip has a fault; Determining a target fault repair strategy corresponding to the loading result flag; Pushing the target fault repair strategy to a user.

3. The method of claim 1, wherein, When Q=0, the method further comprises: Loading an error flag bit; After the processor is started, reading the error flag bit; Deciding by software whether to continue executing a program subsequently, or feeding back that this time of starting has a fault.

4. The method according to any one of claims 1 to 3, characterized in that, The method further comprises: Receiving a target instruction; Obtaining a reference instruction set corresponding to the K backup trim information; Detecting whether the target instruction exists in the reference instruction set; When the target instruction exists in the reference instruction set, executing the target instruction.

5. The method according to any one of claims 1 to 3, characterized in that, Each backup trim information in the P backup trim information corresponds to a weight value, the weight value being used to represent the importance of the backup trim value; The method further comprises: Obtaining the weight value in each backup trim information in the Q backup trim information to obtain Q weight values; Determining a first sum of the Q weight values and a mean value of the Q weight values; Obtaining a second sum of the weight values of each backup trim information in the P backup trim information; Determining a ratio between the first sum and the second sum; Detecting whether the ratio is greater than a first preset threshold value and whether the mean value is greater than a second preset threshold value; When the ratio is greater than the first preset threshold value and the mean value is greater than the second preset threshold value, performing the step of verifying the verification information corresponding to the Q backup trim information.

6. The method of claim 5, wherein, The method further comprises: Obtaining a test condition parameter; According to the test condition parameter, determining the first preset threshold value and the second preset threshold value.

7. The method according to any one of claims 1 to 3, characterized in that, The obtaining to-be-verified information of the chip comprises: Obtaining a test instruction, the test instruction carrying a test content parameter; According to the test content parameters, the to-be-verified information of the chip is obtained.

8. A chip testing apparatus characterized by comprising: The application is applied to a chip, when the chip is not used for the first time, the data in the chip is empty, and the device comprises an acquisition unit, a comparison unit, a verification unit, a loading unit, a starting unit, a detection unit and a determination unit, wherein, The acquisition unit is configured to acquire to-be-verified information of the chip when the chip is powered on for the first time, the to-be-verified information comprising P backup trim information, each backup trim information corresponding to one verification information, P being an integer greater than 1, and acquire standard information of the chip, the standard information comprising P standard trim information, the standard trim information corresponding to the backup trim information one by one. The comparison unit is configured to compare the P backup trim information with the P standard trim information to obtain Q backup trim information with successful comparison, Q being a positive integer less than or equal to P. The verification unit is configured to verify the verification information corresponding to the Q backup trim information to obtain K backup trim information with successful verification, K being a positive integer less than or equal to Q. The loading unit is configured to perform a loading operation according to the K backup trim information with successful verification to obtain a loading result flag. The starting unit is configured to start a processor and read the loading result flag. The detection unit is configured to detect whether the loading result flag meets a preset condition. The determination unit is configured to confirm that the chip is normal when the loading result flag meets the preset condition.

9. A chip, characterized by The device comprises a processor and a memory, the memory is used to store one or more programs and is configured to be executed by the processor, and the program comprises instructions for performing steps in the method of any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, A computer program for electronic data exchange is stored, wherein the computer program enables a computer to perform the method of any one of claims 1-7.

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