A method, system and terminal for updating mainboard firmware of a multi-node chassis

Abstract

The application discloses a method, system and terminal for updating mainboard firmware of a multi-node chassis, the method comprising: building a hardware environment for multi-node communication in the chassis; determining the position of each node in the chassis; assigning an I2C address and an internal network static IP address to the BMC of each node according to the position of each node in the chassis; triggering the BMC of a first node by using an external network IP address according to a first trigger command; the BMC of the first node being converted into a main updater mode and sequentially uploading firmware images to the BMCs of other nodes in the chassis; and updating the chassis firmware after the BMCs of all nodes in the chassis acquire the firmware images. The system comprises the BMC of any node in the chassis, a switch chip, a node position determination module, an address assignment module, a trigger module, a firmware image transmission module and a firmware update module. The application can effectively improve the efficiency of server mainboard firmware update.

Description

Technical Field

[0001] This application relates to the field of server motherboard firmware update technology, and in particular to a method, system and terminal for updating motherboard firmware in a multi-node chassis. Background Technology

[0002] With the development of server technology, server architecture has evolved from the original 1U / 2U standard servers to multi-node chassis servers, such as 2U 4- or 4U 8-node products, and even rack-mount 48-node products. These node products basically use the same motherboard and run the same BMC, BIOS, and CPLD firmware. To ensure the normal operation of the server, how to update the server motherboard firmware is an important technical issue.

[0003] Currently, the method for updating server motherboard firmware typically involves ensuring that the node's BMC firmware supports firmware upgrades for the BMC (Baseboard Management Controller), BIOS (Basic Input Output System), and CPLD (Complex Programmable Logic Device). Then, the node firmware is updated via remote management software or scripts. If multiple nodes need to be updated remotely in batches, the BMC IPs of the nodes requiring updates must be collected beforehand, and then each node is updated remotely one by one.

[0004] However, current methods for updating server motherboard firmware are inefficient because they require updating each server individually. Summary of the Invention

[0005] This application provides a method, system, and terminal for updating motherboard firmware in a multi-node chassis, in order to solve the problem that the existing motherboard firmware update methods have low update efficiency.

[0006] To address the aforementioned technical problems, the embodiments of this application disclose the following technical solutions: A method for updating motherboard firmware in a multi-node chassis, the method comprising: Set up the hardware environment for multi-node communication within the chassis; Determine the location of each node within the chassis; Based on the location of each node in the chassis, assign an I2C address and an internal network static IP address to the BMC of each node; Based on the first trigger command obtained, the BMC of the first node is triggered using the external network IP address. The first node is the primary updater node. The first node's BMC is converted to primary updater mode and then uploads the firmware image to the other node BMCs in the chassis in sequence. After all BMC nodes within the chassis have obtained the firmware image, the firmware of the entire chassis is updated.

[0007] Optionally, the BMC of the first node is converted to primary updater mode, and the firmware image is sequentially uploaded to the BMCs of other nodes in the chassis, including: Based on the obtained second trigger command, the BMC of the second node is triggered, and the second node is the secondary updater node; The second node's BMC switches to secondary updater mode and obtains the firmware image from the first node via the network; Based on the obtained third trigger command, the BMCs of all nodes except the first and second nodes in the chassis are triggered sequentially. The BMCs of nodes other than the first and second nodes inside the chassis enter update mode in sequence and obtain firmware images from the first or second node.

[0008] Optionally, the construction of the hardware environment for multi-node communication within the chassis includes: Connect the BMCs of all nodes within the chassis via the I2C bus; Connect one internal network channel from all nodes' BMCs within the chassis to a single switch chip.

[0009] Optionally, the method for determining the location of each node within the chassis is as follows: The location of each node in the chassis is determined based on the GPIO signals of each node.

[0010] Optionally, after all BMC nodes within the chassis have obtained the firmware image, the method for updating the firmware of the entire chassis includes: Determine whether all BMC nodes within the chassis have obtained the firmware image; If so, trigger the BMC updates of all nodes except the first node in the chassis in sequence; If not, the BMC of the first node continues to upload the firmware image to the BMCs of other nodes in the chassis until all BMCs in the chassis have obtained the firmware image. After all BMCs except the first node in the chassis have been updated, the first node's BMC will start its own update. Output the update results of BMC for all nodes in the output chassis.

[0011] A system for updating motherboard firmware in a multi-node chassis, the system comprising: a BMC of any node in the chassis, a switch chip, a node location determination module, an address allocation module, a trigger module, a firmware image transmission module, and a firmware update module, wherein the BMCs of all nodes in the chassis are connected via an I2C bus, and one internal network of all node BMCs in the chassis is connected in series with the switch chip. The node location determination module is used to determine the location of each node in the chassis; The address allocation module is used to allocate an I2C (Inter-Integrated Circuit) address and an internal network static IP address to each node's BMC based on the node's location in the chassis. The triggering module is used to trigger the BMC of the first node using an external network IP (Internet Protocol) address based on the obtained first triggering command. The first node is the primary updater node. The firmware image transmission module is used to control the BMC of the first node to switch to the primary updater mode, and to sequentially upload the firmware image to the BMCs of other nodes in the chassis through the BMC of the first node. The firmware update module is used to update the firmware of the entire chassis after all BMC nodes in the chassis have obtained the firmware image.

[0012] Optionally, the firmware image transmission module includes: The second node triggering unit is used to trigger the BMC of the second node according to the acquired second triggering command, wherein the second node is a secondary updater node; The secondary updater mode conversion unit is used to control the BMC of the second node to switch to secondary updater mode and obtain the firmware image from the first node via the network; Other node triggering units are used to trigger the BMCs of nodes other than the first and second nodes in the chassis in sequence according to the acquired third triggering command; The update mode startup unit is used to control the BMCs of nodes other than the first and second nodes in the chassis to enter update mode sequentially and obtain firmware images from the first or second node.

[0013] Optionally, the firmware update module includes: The judgment unit is used to determine whether all BMC nodes in the chassis have obtained the firmware image. If yes, the first firmware update unit is started; if no, the firmware image transmission module is started, and the BMC of the first node is controlled to continue uploading the firmware image to other BMC nodes in the chassis until all BMC nodes in the chassis have obtained the firmware image. The first firmware update unit is used to trigger all BMCs except the first BMC in the chassis to start updating when all BMCs in the chassis have obtained the firmware image. The second firmware update unit is used to control the BMC of the first node to start its own update after all the BMCs of nodes other than the BMC of the first node in the chassis have been updated. The output unit is used to output the update results of all BMC nodes within the chassis.

[0014] Optionally, the node position determination module is used to determine the position of each node in the chassis based on the GPIO signal of each node.

[0015] A terminal, the terminal comprising: a processor and a memory communicatively connected to the processor, wherein, The memory stores instructions that can be executed by the processor, which, when executed by the processor, enables the processor to perform the aforementioned method for updating motherboard firmware in a multi-node chassis.

[0016] The technical solutions provided by the embodiments of this application may include the following beneficial effects: This application provides a method for updating motherboard firmware in a multi-node chassis. The method first establishes a hardware environment for multi-node communication within the chassis and determines the location of each node within the chassis. Next, based on this location, an I2C address and an internal network static IP address are assigned to the BMC of each node. Then, the external network IP address is used to trigger the BMC of the first node, which switches to primary updater mode and sequentially uploads the firmware image to the BMCs of other nodes within the chassis. Finally, after all BMCs within the chassis obtain the firmware image, they update the firmware of the entire chassis. In this embodiment, by assigning an I2C address and an internal network static IP address to each node's BMC, a basis is provided for subsequent chassis firmware updates, which helps improve the accuracy and efficiency of motherboard updates. This embodiment designates the first node as the primary updater node, using its BMC to upload firmware images and update firmware to other BMCs. This makes each node's BMC act as a client for remote firmware flashing, triggering another node's BMC to perform firmware updates. This enables one-to-one, two-to-two, and four-to-four tree-structured update methods, significantly improving the efficiency of server motherboard firmware updates.

[0017] This application also provides a system for updating motherboard firmware in a multi-node chassis. The system mainly includes: a BMC (Browser Control Center) for any node within the chassis, a switch chip, a node location determination module, an address allocation module, a trigger module, a firmware image transmission module, and a firmware update module. All BMCs within the chassis are connected via an I2C bus, and one internal network of each BMC is connected in series with the switch chip, thus establishing the hardware environment for multi-node BMC communication within the chassis. The address allocation module provides a basis for determining the BMC of any firmware to be updated during subsequent firmware updates, improving the efficiency and accuracy of firmware updates. The trigger module and firmware image transmission module utilize a first node to build a one-to-one, two-to-two, or four-to-four tree-structured update architecture, enabling rapid firmware updates for the entire chassis through one of the chassis node BMCs, significantly improving the efficiency of firmware updates.

[0018] This application also provides a terminal that has the same technical effects as the above-mentioned method and system for updating motherboard firmware in a multi-node chassis, which will not be repeated here.

[0019] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0020] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0021] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a flowchart illustrating a method for updating motherboard firmware in a multi-node chassis, as provided in an embodiment of this application. Figure 2 This is a schematic diagram of the BMC I2C bus topology in a 2U4 chassis node; Figure 3 This is a schematic diagram illustrating the principle of a user triggering a firmware update at the first node (BMC) in this embodiment of the application. Figure 4 A schematic diagram illustrating the principle of updating the firmware of the entire chassis node in a 2U4 chassis node; Figure 5 This is a schematic diagram of a system for updating motherboard firmware in a multi-node chassis, provided as an embodiment of this application. Detailed Implementation

[0023] To enable those skilled in the art to better understand the technical solutions in this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of this application.

[0024] To better understand this application, the embodiments of this application will be explained in detail below with reference to the accompanying drawings.

[0025] Example 1 See Figure 1 , Figure 1 This is a flowchart illustrating a method for updating motherboard firmware in a multi-node chassis, as provided in an embodiment of this application. Figure 1 As can be seen, the method for updating motherboard firmware in a multi-node chassis in this embodiment mainly includes the following processes: S1: Set up the hardware environment for multi-node communication within the chassis.

[0026] Specifically, step S1 includes: S11: Connect the BMCs of all nodes in the chassis via the I2C bus.

[0027] This means connecting one I2C channel of the BMC of each node in the chassis together, so that the BMCs of all nodes in the entire chassis can achieve I2C bus communication.

[0028] S12: Connect one internal network of all nodes in the BMC within the chassis to a single switch chip.

[0029] Taking a 2U4 chassis node as an example, the schematic diagram of the node BMC I2C bus topology in this embodiment is as follows: Figure 2 As shown.

[0030] See also Figure 1 As can be seen, after setting up the hardware environment for multi-node communication within the chassis, step S2 is executed: determine the location of each node within the chassis.

[0031] The location of any node within the chassis can be determined using hardware mechanisms. For example, the location of each node within the chassis can be determined based on its GPIO signals.

[0032] S3: Assign an I2C address and an internal network static IP address to each node's BMC based on the node's location in the chassis.

[0033] Taking the 2U4 node as an example, the address allocation table for the chassis location of the 2U4 node in this embodiment can be found in Table 1 below.

[0034]

[0035] Table 1: Address Allocation Table for Chassis Location of 2U4 Nodes S4: Based on the obtained first trigger command, trigger the BMC of the first node using the external network IP address. The first node is the primary updater node.

[0036] The schematic diagram illustrating the principle of the user triggering the firmware update at the first node (BMC) in this embodiment can be found in [reference needed]. Figure 3 As shown.

[0037] S5: The first node's BMC is converted to primary updater mode and uploads the firmware image to the other node BMCs in the chassis in sequence.

[0038] Specifically, step S5 includes the following process: S51: Based on the obtained second trigger command, trigger the BMC of the second node, which is a secondary updater node.

[0039] S52: The BMC of the second node switches to secondary updater mode and obtains the firmware image from the first node via the network.

[0040] S53: Based on the obtained third trigger command, trigger the BMCs of nodes other than the first and second nodes in the chassis in sequence.

[0041] S54: The BMCs of nodes other than the first and second nodes in the chassis enter update mode in sequence and obtain firmware images from the first or second node.

[0042] As shown in steps S51-S54 above, after the BMC of the first node switches to primary updater mode, it first calculates the number of nodes that need to be updated, sends the firmware information to be updated to the BMCs of other nodes in the chassis, and the BMCs of other nodes in the chassis start themselves in pre-update mode, waiting to be triggered. First, the BMC of the second node is triggered, switching it to secondary updater mode. Then, the BMCs of other nodes in the chassis are triggered to enter update mode, and finally, all nodes in the chassis enter update mode. Figure 2 For example, in this embodiment, Node1 is the first node, and its BMC is in primary updater mode; Node2 is the second node, and its BMC is in secondary updater mode; Node3 and Node4 are the other nodes, and their BMCs are in update mode. The method for updating the firmware of the entire chassis nodes in this embodiment can be found in [link to documentation]. Figure 4 As shown, Figure 4Taking the 2U4 chassis node as an example, a detailed schematic diagram of the principle of updating the firmware of the entire chassis node is shown.

[0043] See also Figure 1 It can be seen that after the first node's BMC switches to the primary updater mode and uploads the firmware image to the other node BMCs in the chassis in sequence, step S6 is executed: after all node BMCs in the chassis have obtained the firmware image, the firmware of the entire chassis is updated.

[0044] Specifically, step S6 includes the following process: S61: Determine whether all BMC nodes in the chassis have obtained the firmware image.

[0045] If all node BMCs in the chassis have obtained the firmware image, proceed to step S62: sequentially trigger all node BMCs except the first node's BMC to start updating.

[0046] If any node BMC within the chassis fails to obtain the firmware image, first execute step S63: the first node's BMC continues to upload the firmware image to the other node BMCs within the chassis, until all node BMCs within the chassis have obtained the firmware image. Then, execute step S62 to sequentially trigger all node BMCs within the chassis except the first node's BMC to begin updating.

[0047] S64: After all BMCs of nodes other than the first node in the chassis have been updated, the BMC of the first node starts its own update.

[0048] S65: Outputs the update results of all BMC nodes within the chassis.

[0049] After all nodes in the chassis have completed the BMC update, the first node outputs the update results so that users can obtain them.

[0050] Example 2 exist Figures 1-4 Based on the illustrated embodiment, see also Figure 5 , Figure 5 This is a schematic diagram of a system for updating motherboard firmware in a multi-node chassis, provided as an embodiment of this application. Figure 5 As can be seen, the system for updating motherboard firmware in a multi-node chassis in this embodiment mainly includes: BMC of any node in the chassis, switch chip, node location determination module, address allocation module, triggering module, firmware image transmission module and firmware update module.

[0051] In this system, the BMCs of all nodes within the chassis are connected via an I2C bus, and one internal network of each node's BMC is connected in series with the switch chip. A node location determination module is used to determine the position of each node within the chassis.

[0052] The address allocation module assigns an I2C address and an internal network static IP address to each node's BMC based on its location within the chassis. The triggering module, based on a first trigger command, uses the external network IP address to trigger the BMC of the first node, which acts as the primary updater node. The firmware image transfer module controls the first node's BMC to switch to primary updater mode and sequentially uploads the firmware image to the BMCs of other nodes within the chassis. The firmware update module updates the firmware of the entire chassis after all node BMCs have received the firmware image.

[0053] Furthermore, the firmware image transmission module includes: a second node triggering unit, a secondary updater mode conversion unit, other node triggering units, and an update mode initiation unit. Specifically, the second node triggering unit is used to trigger the BMC of the second node (a secondary updater node) according to a acquired second triggering command; the secondary updater mode conversion unit is used to control the BMC of the second node to switch to secondary updater mode and obtain the firmware image from the first node via the network; the other node triggering unit is used to sequentially trigger the BMCs of nodes other than the first and second nodes within the chassis according to a acquired third triggering command; and the update mode initiation unit is used to control the BMCs of nodes other than the first and second nodes within the chassis to sequentially enter update mode and obtain the firmware image from either the first or second node.

[0054] The firmware update module includes a judgment unit, a first firmware update unit, a second firmware update unit, and an output unit. The judgment unit determines whether all BMC nodes within the chassis have obtained the firmware image. If so, it initiates the first firmware update unit; otherwise, it initiates the firmware image transmission module, controlling the first node's BMC to continue uploading the firmware image to other BMC nodes within the chassis, until all BMC nodes within the chassis have obtained the firmware image. The first firmware update unit, when all BMC nodes within the chassis have obtained the firmware image, sequentially triggers all BMC nodes except the first node's BMC to begin updating. The second firmware update unit, after all BMC nodes except the first node's BMC have completed updating, controls the first node's BMC to initiate its own update. The output unit outputs the update results of all BMC nodes within the chassis.

[0055] Furthermore, in this embodiment, the node position determination module is also used to determine the position of each node in the chassis based on the GPIO signal of each node.

[0056] The working principle and method of the system for updating motherboard firmware in a multi-node chassis in this embodiment are explained. Figures 1-4The embodiments shown have been described in detail and will not be repeated here.

[0057] Example 3 This application also provides a terminal, which includes a processor and a memory communicatively connected to the processor, wherein the memory stores instructions executable by the processor, and the instructions are executed by the processor to enable the processor to perform the above-described method for updating motherboard firmware for a multi-node chassis.

[0058] 1) The method for updating the motherboard firmware for multi-node chassis is as follows: 2) Set up the hardware environment for multi-node communication within the chassis; 3) Determine the location of each node within the chassis; 4) Assign an I2C address and an internal network static IP address to each node's BMC based on the node's location within the chassis; 5) Based on the first trigger command obtained, trigger the BMC of the first node using the external network IP address. The first node is the primary updater node. 6) The BMC of the first node is converted to the primary updater mode, and the firmware image is uploaded to the BMCs of other nodes in the chassis in sequence; 7) After all BMC nodes in the chassis have obtained the firmware image, update the firmware of the entire chassis.

[0059] For the specific execution steps and principles of the above methods, please refer to [link / reference]. Figure 1-4 Example 1 and Figure 5 The second embodiment shown will not be described in detail here.

[0060] The above description is merely a specific embodiment of this application, enabling those skilled in the art to understand or implement this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for updating motherboard firmware in a multi-node chassis, characterized in that, The method includes: The hardware environment for multi-node communication within the chassis is set up, including: connecting the BMCs of all nodes in the chassis via the I2C bus, and connecting one internal network of each node's BMC in the chassis to a single switch chip. The physical location of each node in the chassis is determined based on the GPIO signals of each node. Based on the physical location of each node in the chassis, assign a unique I2C address and a static IP address for internal network communication to each node's BMC. Based on the first trigger command obtained, the BMC on the first node is triggered using the external network IP address, and the first node is designated as the primary updater node; The first node's BMC switches from regular management mode to primary updater mode, and through the internal network, using the internal network's static IP address, uploads the firmware image sequentially to other node BMCs within the chassis. Determine whether all BMC nodes within the chassis have obtained the firmware image; Once all node BMCs have obtained the firmware image, the firmware update operation will be triggered on all node BMCs except the first node. After all nodes other than the first node have completed their BMC updates, the first node's BMC will then be triggered to perform its own firmware update operation.

2. The method for updating motherboard firmware in a multi-node chassis according to claim 1, characterized in that, The first node's BMC is converted to primary updater mode and sequentially uploads the firmware image to the other node BMCs within the chassis, including: Based on the obtained second trigger command, the BMC of the second node is triggered, and the second node is the secondary updater node; The second node's BMC switches to secondary updater mode and obtains the firmware image from the first node via the network; Based on the obtained third trigger command, the BMCs of all nodes except the first and second nodes in the chassis are triggered sequentially. The BMCs of nodes other than the first and second nodes inside the chassis enter update mode in sequence and obtain firmware images from the first or second node.

3. A system for updating motherboard firmware in a multi-node chassis, characterized in that, The system is used to implement the method of claim 1. The system includes: BMC of any node in the chassis, switch chip, node location determination module, address allocation module, trigger module, firmware image transmission module and firmware update module, wherein the BMCs of all nodes in the chassis are connected through I2C bus, and one internal network of all node BMCs in the chassis is connected in series on the switch chip. The node location determination module is used to determine the location of each node in the chassis; The address allocation module is used to allocate an I2C address and an internal network static IP address to each node's BMC based on the node's location in the chassis. The triggering module is used to trigger the BMC of the first node using an external network IP address based on the obtained first triggering command, wherein the first node is the primary updater node; The firmware image transmission module is used to control the BMC of the first node to switch to the primary updater mode, and to sequentially upload the firmware image to the BMCs of other nodes in the chassis through the BMC of the first node. The firmware update module is used to update the firmware of the entire chassis after all BMC nodes in the chassis have obtained the firmware image.

4. A system for updating motherboard firmware in a multi-node chassis according to claim 3, characterized in that, The firmware image transmission module includes: The second node triggering unit is used to trigger the BMC of the second node according to the acquired second triggering command, wherein the second node is a secondary updater node; The secondary updater mode conversion unit is used to control the BMC of the second node to switch to secondary updater mode and obtain the firmware image from the first node via the network; Other node triggering units are used to trigger the BMCs of nodes other than the first and second nodes in the chassis in sequence according to the acquired third triggering command; The update mode startup unit is used to control the BMCs of nodes other than the first and second nodes in the chassis to enter update mode sequentially and obtain firmware images from the first or second node.

5. A system for updating motherboard firmware in a multi-node chassis according to claim 3, characterized in that, The firmware update module includes: The judgment unit is used to determine whether all BMC nodes in the chassis have obtained the firmware image. If yes, the first firmware update unit is started; if no, the firmware image transmission module is started, and the BMC of the first node is controlled to continue uploading the firmware image to other BMC nodes in the chassis until all BMC nodes in the chassis have obtained the firmware image. The first firmware update unit is used to trigger all BMCs except the first BMC in the chassis to start updating when all BMCs in the chassis have obtained the firmware image. The second firmware update unit is used to control the BMC of the first node to start its own update after all the BMCs of nodes other than the BMC of the first node in the chassis have been updated. The output unit is used to output the update results of all BMC nodes within the chassis.

6. A system for updating motherboard firmware in a multi-node chassis according to claim 3, characterized in that, The node location determination module is used to determine the location of each node in the chassis based on the GPIO signals of each node.

7. A terminal, characterized in that, The terminal includes: a processor and a memory communicatively connected to the processor, wherein... The memory stores instructions that can be executed by the processor, which, when executed by the processor, enables the processor to perform the method for updating motherboard firmware for a multi-node chassis as described in any one of claims 1 to 2.

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