Vector instruction processing method, microprocessor, computer device and storage medium

Abstract

The application discloses a vector instruction execution method, a processor, a computer device and a storage medium. Through a vector instruction locking mechanism, a vector instruction is set to a locked state after being received by a second pipeline. The vector instruction identification releases the locked state of the vector instruction when flowing to a write-back stage along a first pipeline; the order of the vector instruction is maintained within the second pipeline; during the execution of the vector instruction, if the vector instruction in the locked state is not unlocked, the execution result cannot be written into a vector register, and the write operation of the vector register is performed after the lock is released; thus, it is ensured that the write-back operation of the vector instruction is later than the write-back operation of a non-vector instruction in front of the vector instruction, so that the program consistency problem caused by the leading update of the vector register by the vector instruction when the main pipeline is interrupted by a trap event during the efficient execution of the vector instruction in a vector extension instruction set V is prevented.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a vector instruction execution method, apparatus, processor, computer device, and storage medium. Background Technology

[0002] With the trend of the Internet of Things, RISC-V, as an open-source instruction set, is attracting increasing attention and use from enterprises. Recently, the Vector Extensions instruction set V (VALV) has been released. Compared to the basic RISC-V instruction set, the vector instructions in VALV are more complex to execute, requiring more clock cycles to complete the execution of a single instruction.

[0003] Therefore, how to efficiently execute vector instructions in the Vector Extension Instruction Set V has become a technical problem that needs to be solved. Summary of the Invention

[0004] This specification provides a vector instruction execution method, processor, computer device, and storage medium to efficiently execute vector instructions in the Vector Extended Instruction Set V.

[0005] This specification provides a microprocessor whose pipeline includes a first pipeline and a second pipeline. The first pipeline has an instruction dispatch unit and a write-back unit; the second pipeline has a vector instruction receiving unit. The instruction dispatch unit sends a vector instruction to the vector instruction receiving unit. The vector instruction receiving unit sets the vector instruction to a locked state. The write-back unit, upon receiving a vector instruction identifier of the vector instruction transmitted through the first pipeline, sends an unlock signal to the instruction processing unit corresponding to a specified pipeline stage in the second pipeline. The unlock signal unlocks the vector instruction in the locked state on the second pipeline, allowing the execution result of the vector instruction to be written into a vector register.

[0006] This specification provides a vector instruction processing method applied to a microprocessor, wherein the microprocessor employs a pipeline including a first pipeline and a second pipeline. The method includes: an instruction dispatch unit on the first pipeline sending a vector instruction to a vector instruction receiving unit on the second pipeline; the vector instruction receiving unit setting the vector instruction to a locked state; when a vector instruction identifier of the vector instruction is transmitted through the first pipeline to a write-back unit of the first pipeline, the write-back unit sends an unlock signal to the second pipeline; and unlocking the vector instruction in the locked state on the second pipeline according to the unlock signal, so as to write the execution result of the vector instruction into a vector register.

[0007] This specification provides a computer device including a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the steps of the method described in any of the above embodiments.

[0008] This specification provides a computer-readable storage medium storing a computer program thereon, characterized in that the computer program, when executed by a processor, implements the steps of the method described in any of the above embodiments.

[0009] In this embodiment, a vector instruction locking mechanism is used. Vector instructions are locked after being received by the second pipeline. The locked state of the vector instruction is released when it flows with the first pipeline to the write-back stage. The order of vector instructions is maintained within the second pipeline. During the execution of a vector instruction, if the locked instruction is not unlocked, the execution result cannot be written to the vector register. The write operation to the vector register is performed only after the lock is released. This ensures that the write-back operation of the vector instruction is later than the write-back operation of the non-vector instructions preceding it. This allows for efficient execution of vector instructions in the vector extended instruction set V while preventing program consistency issues caused by the main pipeline being interrupted by trap events and vector instructions prematurely updating the vector register. Attached Figure Description

[0010] Figure 1 This specification provides a schematic diagram of the structure of a microprocessor for each embodiment.

[0011] Figure 2 This specification provides a schematic diagram of the structure of a microprocessor for each embodiment.

[0012] Figure 3 This specification provides a schematic diagram of the structure of an instruction cache area for implementation purposes.

[0013] Figure 4 This specification provides a schematic diagram of the structure of a microprocessor for each embodiment.

[0014] Figure 5 This specification provides a schematic diagram of the structure of a microprocessor for each embodiment.

[0015] Figure 6 This specification provides a flowchart illustrating a vector instruction processing method for embodiments thereof. Detailed Implementation

[0016] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present invention, and should not be construed as limiting the present invention.

[0017] The RISC-V instruction set architecture boasts advantages such as low power consumption, low cost, open source, modularity, simplicity, small size, and high speed. The Vector Extensions V instruction set extension riscv-v-spec-1.0 has been released, representing the first stable version of the RISC-V extension. All subsequent modifications will maintain compatibility, allowing for the development of toolchains, function simulators, and software using this instruction set. Currently, there are no RISC-V microprocessors on the market that support the Vector Extensions V instruction set extension.

[0018] The V-Extended Instruction Set (vector instructions) features a large data width, configurable bit width, and a rich set of instructions. Compared to the basic RISC-V instruction set, V-Extended vector instructions are more complex to execute, often requiring more clock cycles to complete a single instruction. Therefore, this specification provides a RISC-V microprocessor supporting V-Extended Instructions. This microprocessor employs a pipeline including a first pipeline and a second pipeline. The first pipeline includes an instruction dispatch unit and a write-back unit; the second pipeline includes a vector instruction receiving unit. The instruction dispatch unit sends vector instructions to the vector instruction receiving unit; the vector instruction receiving unit sets the vector instructions to a locked state; the write-back unit, upon receiving the vector instruction identifier of a vector instruction transmitted through the first pipeline, sends an unlock signal to the instruction processing unit corresponding to the specified pipeline stage in the second pipeline. The unlock signal unlocks the vector instructions locked in the second pipeline, allowing the execution result of the vector instructions to be written to a vector register. This achieves efficient execution of V-Extended Instructions and reduces the negative impact of vector instructions on the execution of non-vector instructions. Furthermore, in the high-performance design process of RISC-V microprocessors supporting V extensions, the out-of-order execution of V extension instructions and other RISC-V instruction set instructions involved in the design scheme leads to program consistency issues.

[0019] The RISC-V microprocessor design scheme supporting V-extensions in the embodiments of this specification can send vector instructions to vector units for processing immediately. The execution process of the vector units is independent of the microprocessor's main pipeline, reducing the impact of V-extension instruction execution and main pipeline coupling on the main pipeline's execution efficiency, thereby contributing to improved microprocessor performance. The vector instruction locking mechanism (write-back locking mechanism or execution locking mechanism) ensures the consistency of the RISC-V microprocessor's program flow execution, while enabling the microprocessor to respond promptly to trap events such as exceptions and interrupts, ensuring the consistency and correctness of the processor state before and after the trap event response. Furthermore, the V-extension instructions in this specification perform write-back locking and unlocking sequentially, resulting in concise and efficient logic, low hardware implementation overhead, and reduced chip costs.

[0020] Figure 1 This specification provides a microprocessor for embodiments thereof. The microprocessor employs a pipeline including a first pipeline 102 and a second pipeline 104. The first pipeline 102 includes an instruction dispatch unit 106 and a write-back unit 108, and the second pipeline includes a vector instruction receiving unit 110.

[0021] The instruction distribution unit 106 is used to send vector instructions to the vector instruction receiving unit 110.

[0022] The vector instruction receiving unit 110 is used to set the vector instruction to a locked state.

[0023] The write-back unit 108 is used to send an unlock signal to the instruction processing unit corresponding to the specified pipeline stage in the second pipeline 104 when it receives the vector instruction identifier of the vector instruction transmitted through the first pipeline 102. The unlock signal is used to unlock the vector instruction that is in a locked state on the second pipeline, so that the execution result of the vector instruction can be written to the vector register.

[0024] Specifically, the first pipeline and the second pipeline can be two independent and parallel pipelines. The first pipeline can be a main pipeline of the microprocessor used to process non-vector instructions. The first pipeline may include an instruction dispatch unit, a write-back unit, a decoding unit, and an execution unit. The second pipeline can be a pipeline used to process vector instructions; it can also be understood as a RISC-V vector unit for processing vector instructions. The second pipeline may include a vector instruction receiving unit. The instruction dispatch unit sends vector instructions to the vector instruction receiving unit; the vector instruction receiving unit receives the vector instructions and sets the vector instructions to a locked state.

[0025] The vector instruction is equipped with a vector instruction identifier. When the instruction dispatch unit sends a vector instruction to the vector instruction receiver unit, the vector instruction identifier is passed to the next stage through the first pipeline. When the write-back unit receives the vector instruction identifier, i.e., when the vector instruction identifier reaches the write-back pipeline stage, the write-back unit on the first pipeline can send an unlock signal to the instruction processing unit corresponding to the specified pipeline stage in the second pipeline. The specified pipeline stage can be a write-back pipeline stage. The instruction processing unit corresponding to the specified pipeline stage can be a vector instruction write-back unit, a vector instruction execution unit, a vector instruction decoding unit, or a vector instruction receiver unit.

[0026] The second pipeline receives an unlock signal, and there are vector instructions in the locked state on the second pipeline. Therefore, the vector instructions in the locked state on the second pipeline are unlocked based on the unlock signal, so that the execution result of the vector instructions is written into the vector register.

[0027] For example, when the vector instruction write-back unit receives an unlock signal, a vector instruction in a locked state can be decoded and executed, but the execution result cannot be written back. Therefore, after unlocking a vector instruction in a locked state, the execution result of the vector instruction can be written back to the vector register.

[0028] For example, when the vector instruction execution unit receives an unlock signal, a vector instruction in a locked state can be decoded but cannot be executed or have its execution result written back. Therefore, after unlocking a vector instruction in a locked state, the vector instruction can be executed first, and then the execution result can be written back to the vector register.

[0029] In the above implementation, the vector instruction locking mechanism ensures that the write-back operation of a vector instruction is later than the write-back operation of a non-vector instruction preceding it. This prevents program consistency issues caused by vector instructions prematurely updating vector registers due to the main pipeline being interrupted by trap events. Vector instructions are set to a locked state after being received by the second pipeline. The vector instruction's locking state is released when it flows with the first pipeline to the write-back stage. The order of vector instructions is maintained within the second pipeline. During the execution of vector instructions, if a locked vector instruction is not unlocked, the execution result cannot be written to the vector register; the write operation to the vector register is performed only after the lock is released.

[0030] In some implementations, please refer to Figure 2 The first pipeline also includes a decoding unit 202. An instruction dispatch unit is used to send non-vector instructions to the decoding unit 202 via the first pipeline.

[0031] In the above embodiment, the first pipeline includes an instruction dispatch unit, a decoding unit, and a write-back unit. The instruction dispatch unit sends non-vector instructions to the decoding unit through the first pipeline. The first pipeline processes the non-vector instructions and then passes the vector instruction identifier of the vector instructions. This can minimize the blocking of the main pipeline caused by the execution of vector instructions and improve the performance of the microprocessor.

[0032] In some implementations, please refer to Figure 3 The vector instruction receiving unit includes an instruction buffer. The instruction buffer includes a lock marker area, which stores lock flags attached by the vector instruction receiving unit to the vector instruction.

[0033] Specifically, the vector instruction receiving unit receives vector instructions from the first pipeline and places them into the instruction buffer. The speed at which vector instructions enter the second pipeline is controlled by the fullness or emptiness of the instruction buffer. The vector instruction receiving unit receives refresh requests from the first pipeline and clears vector instructions from the instruction buffer that are no longer needed. The second pipeline can check the validity of the instructions and then transmit the check results to the first pipeline.

[0034] The instruction buffer contained in the vector instruction receiving unit is as follows: Figure 3 As shown, for each instruction received, the vector instruction receiving unit generates an accompanying instruction valid VALID signal and an instruction lock flag (i.e., the lock identifier for the vector instruction). The INST area contains the received vector instruction code and vector instruction pre-decoding information. For example, the instruction lock flag can be 0 or 1.

[0035] Vector instructions and instruction lock (LOCK) flags are passed through the second pipeline. Any locked vector instruction is passed up to the instruction write-back unit corresponding to the specified pipeline stage, awaiting unlocking. Upon receiving an UNLOCK signal from the first pipeline, the earliest locked vector instruction is released.

[0036] In the above implementation, by attaching a locking flag to the vector instructions, the consistency of program flow execution is ensured while allowing V extension instructions to be executed independently and out of order with other instruction set instructions.

[0037] In some implementations, the vector instruction receiving unit is further configured to set the vector instruction to a write-back locked state. Vector instructions in the write-back locked state are allowed to execute. The write-back unit is further configured to send a write-back unlock signal to the vector instruction write-back unit corresponding to the write-back pipeline stage in the second pipeline, wherein the lock flag in the lock flag area is updated to an unlock flag.

[0038] Specifically, the vector instruction receiving unit sets the vector instruction to a write-back locked state; wherein, the vector instruction in the write-back locked state is allowed to execute. When the vector instruction identifier of the vector instruction is transmitted to the write-back unit of the first pipeline via the first pipeline, the write-back unit of the first pipeline sends a write-back unlock signal to the vector instruction write-back unit corresponding to the write-back pipeline stage in the second pipeline. The vector instruction write-back unit receives the write-back unlock signal. Based on the write-back unlock signal, the locked identifier in the locked marker area is updated to the unlock identifier.

[0039] For example, please refer to Figure 4 Step 1: The instruction dispatch unit of the RISC-V microprocessor's mainline pipeline sends vector instructions to the RISC-V vector unit and non-vector instructions to the microprocessor's mainline pipeline. The vector unit and the mainline pipeline operate independently, and vector instructions and other RISC-V extension instructions are executed out of order. This minimizes the blocking of the mainline pipeline caused by the execution of vector instructions, thereby improving microprocessor performance.

[0040] Step 2: The vector instruction receiving unit receives the vector instruction and simultaneously adds a write-back lock flag to the vector instruction.

[0041] Step 3: The instruction distribution unit of the mainline simultaneously transmits the vector instruction identifier to the next stage through the mainline. When the vector instruction identifier reaches the write-back stage of the mainline, it sends the vector write-back unlock identifier to the RISC-V vector unit.

[0042] Step 4: Vector instructions with write-back lock flags in the RISC-V vector unit are sequentially sent from the vector instruction receiving unit to the vector instruction decoding unit and the vector instruction execution unit. The vector instruction receiving unit can receive the vector write-back unlock signal from the mainline to release the vector write-back lock flag.

[0043] Step 5: Vector instructions with a write-back lock flag can be decoded and executed, but the execution result cannot be written back to the vector register. After the write-back lock flag of a vector instruction is released by the vector write-back unlock signal sent from the mainline, the execution result of the vector instruction can be written back to the vector register. In the vector unit, the first instruction received is unlocked first; that is, the vector unlock signal sent after the vector flag transmitted by the mainline reaches the mainline write-back stage will unlock the vector instruction executed in the RISC-V vector unit corresponding to that vector flag.

[0044] When all vector instructions in the vector unit are in a write-back locked state, an interrupt can be handled without waiting for the vector instructions to finish executing, thus clearing the vector pipeline.

[0045] When all vector instructions in the vector unit are in the write-back unlock state, if the vector instruction writes to the fixed-point register or floating-point register, wait for the instruction to finish executing before processing the interrupt; if the vector instruction does not write back to the fixed-point register or floating-point register, you can process the interrupt directly without waiting, and the vector unit continues to execute the vector instruction.

[0046] When the instruction portion in the vector unit is in the write-back unlock state, the write-back locked instructions are cleared, the interrupt is handled, and the vector unlock instructions continue to execute.

[0047] In the above implementation, the vector instruction write-back locking mechanism ensures that the write-back operation of vector instructions is later than the write-back of non-vector instructions preceding them, thus preventing program consistency issues caused by vector instructions prematurely updating vector registers due to the main pipeline being interrupted by trap events. Vector instructions are set to a write-back locked state after being received by the second pipeline. The vector instruction is unlocked when it flows to the write-back stage with the first pipeline. The order of vector instructions is maintained within the second pipeline. During the execution of vector instructions, if the write-back lock flag is valid, the second pipeline cannot write the execution result to the vector register, waiting for the write-back lock to be released before performing the write operation to the vector register.

[0048] In some implementations, the vector instruction receiving unit is further configured to set the vector instruction to an execution locked state; wherein, a vector instruction in an execution locked state is not allowed to be executed. The write-back unit is further configured to send an execution unlock signal to the vector instruction execution unit in the second pipeline, wherein the lock flag in the lock flag area is updated to an unlock flag.

[0049] Specifically, the vector instruction receiving unit sets the vector instruction to an execution locked state; wherein, a vector instruction in an execution locked state is not allowed to be executed. When the vector instruction identifier of the vector instruction is transmitted to the write-back unit of the first pipeline, the write-back unit sends an execution unlock signal to the vector instruction execution unit in the second pipeline. Based on the write-back unlock signal, the locked identifier in the locked marker area is updated to an unlock identifier.

[0050] For example, please refer to Figure 5 Step 1: The instruction dispatch unit of the RISC-V microprocessor's mainline pipeline sends vector instructions to the RISC-V vector unit and non-vector instructions to the microprocessor's mainline pipeline. The vector unit and the mainline pipeline operate independently, and vector instructions and other RISC-V extension instructions are executed out of order. This minimizes the blocking of the mainline pipeline caused by the execution of vector instructions, thereby improving microprocessor performance.

[0051] Step 2: The vector instruction receiving unit receives the vector instruction and simultaneously attaches an execution lock flag to the vector instruction.

[0052] Step 3: The instruction distribution unit of the mainline simultaneously transmits the vector instruction identifier to the next stage through the mainline. When the vector instruction identifier reaches the write-back stage of the mainline, it sends a vector execution unlock identifier to the RISC-V vector unit.

[0053] Step 4: Vector instructions with execution lock flags in the RISC-V vector unit are sequentially sent from the vector instruction receiving unit to the vector instruction decoding unit. The vector instruction execution unit can receive the vector execution unlock signal from the mainline to release the vector execution lock flag.

[0054] Step 5: Vector instructions with an execution lock flag can be decoded, but cannot be executed, nor can the execution result be written back to the vector register. After the execution lock flag of a vector instruction is released by the vector execution unlock signal sent from the mainline, the vector instruction can be executed, and the execution result can be written back to the vector register. In the vector unit, the first instruction received is unlocked first; that is, the vector unlock signal sent after the vector flag transmitted by the mainline reaches the mainline write-back stage will unlock the vector instruction corresponding to that vector flag that is executed in the RISC-V vector unit.

[0055] In the above implementation, vector instructions in a locked state are not allowed to be executed. After the write-back unit sends an unlock signal, the vector instructions are sent to the vector instruction execution unit for execution, and then written back to the vector register after execution. In this implementation, the second pipeline depth required for vector unlocking can be significantly reduced, making the implementation of the vector lock unlocking logic simpler, significantly reducing the chip logic resource overhead occupied by the unlocking logic, and simplifying the design.

[0056] In some implementations, the second pipeline has a first pipeline stage and a second pipeline stage. The output of the first pipeline stage serves as the input of the second pipeline stage. The instruction processing unit corresponding to the second pipeline stage is configured to transmit an unlock signal to the instruction processing unit corresponding to the first pipeline stage when the vector instruction in the instruction processing unit corresponding to the second pipeline stage is in an unlocked state. The instruction processing unit corresponding to the first pipeline stage is configured to unlock the vector instruction in the instruction processing unit corresponding to the first pipeline stage that is in a locked state based on the unlock signal.

[0057] In some implementations, the second pipeline includes a vector instruction write-back unit; the vector instruction write-back unit is used to unlock the vector instructions that are in a locked state in the vector instruction write-back unit if there are vector instructions in the vector instruction write-back unit in a locked state when an unlock signal is received.

[0058] In the second pipeline, vector instructions in the write-back locked state can be decoded and executed, but the execution result is not allowed to be written back to the vector register; vector instructions in the write-back unlocked state can be decoded and executed, and the execution result is written back to the vector register.

[0059] Specifically, the first pipeline sends an unlock signal to the vector instruction write-back unit of the second pipeline, and the vector instruction write-back unit receives the unlock signal. It then checks whether there is a locked vector instruction in the vector instruction write-back unit. If so, the locked vector instruction in the vector instruction write-back unit is unlocked so that the execution result of the vector instruction can be written back to the vector register.

[0060] In this embodiment, since the vector instruction receiving unit, vector instruction decoding unit, and vector instruction execution unit may all contain vector instructions carrying the LOCK flag, the direction of the UNLOCK signal in the main pipeline is opposite to the pipeline direction in the second pipeline. If the instruction in the vector instruction execution unit is already UNLOCKed, the check continues to the next higher pipeline level, and so on, until it reaches the vector instruction receiving unit. The vector instructions in the vector instruction receiving unit are also checked sequentially according to their historical order. After finding the earliest locked vector instruction, its state is set to UNLOCK, and this process ends.

[0061] In some implementations, the second pipeline further includes a vector instruction execution unit. The vector instruction execution unit is configured to, upon receiving an unlock signal, unlock the locked vector instruction present in the vector instruction execution unit if the locked vector instruction does not exist in the vector instruction write-back unit but does exist in the vector instruction execution unit.

[0062] Specifically, the first pipeline sends an unlock signal to the vector instruction execution unit of the second pipeline. Upon receiving the unlock signal, the vector instruction execution unit checks whether there are any locked vector instructions in the vector instruction write-back unit and the vector instruction execution unit. If the vector instruction write-back unit does not contain any locked vector instructions, but the vector instruction execution unit does, the locked vector instructions in the vector instruction execution unit are unlocked to execute the vector instructions, and the execution result of the vector instructions is written back to the vector register.

[0063] In this embodiment, since the vector instructions in the vector execution unit are already in the UNLOCK state, the backtracking pipeline for vector unlocking is shortened, and the vector unlocking logic is simplified.

[0064] Please see Figure 6This specification provides a vector instruction processing method applied to a microprocessor, wherein the microprocessor employs a pipeline including a first pipeline and a second pipeline. The method includes:

[0065] S610, The instruction dispatch unit on the first pipeline sends a vector instruction to the vector instruction receiving unit on the second pipeline.

[0066] S620, The vector command receiving unit is set to a locked state for vector commands;

[0067] S630. When the vector instruction identifier of the vector instruction is transmitted through the first pipeline to the write-back unit of the first pipeline, the write-back unit sends an unlock signal to the second pipeline.

[0068] S640. Unlock the vector instruction that is in a locked state on the second pipeline according to the unlock signal, so as to write the execution result of the vector instruction into the vector register.

[0069] In some implementations, the first pipeline also includes a decoding unit; the method may further include: the instruction dispatch unit sending non-vector instructions to the decoding unit through the first pipeline.

[0070] In some implementations, the vector instruction receiving unit sets the vector instruction to a locked state, including: the vector instruction receiving unit attaches a lock flag to the vector instruction; wherein the lock flag is used to indicate that the vector instruction is in a locked state.

[0071] In some implementations, the vector instruction receiving unit sets the vector instruction to a locked state, including: the vector instruction receiving unit sets the vector instruction to a write-back locked state; wherein, the vector instruction in the write-back locked state is allowed to execute. The write-back unit sends an unlock signal to the second pipeline, including: the write-back unit sends a write-back unlock signal to the vector instruction write-back unit corresponding to the write-back pipeline stage in the second pipeline.

[0072] In some implementations, the vector instruction receiving unit sets the vector instruction to a locked state, including: the vector instruction receiving unit sets the vector instruction to an execution locked state; wherein, the vector instruction in the execution locked state is not allowed to be executed. The write-back unit sends an unlock signal to the second pipeline, including: the write-back unit sends an execution unlock signal to the vector instruction execution unit in the second pipeline.

[0073] In some implementations, the vector instructions in the locked state include a first locking instruction and a second locking instruction; the locking time of the first locking instruction is earlier than the locking time of the second locking instruction; unlocking the vector instructions in the locked state on the second pipeline according to the unlock signal, so as to write the execution result of the vector instructions into the vector register, includes: unlocking the earliest locked target vector instruction among the vector instructions in the locked state on the second pipeline according to the unlock signal, so as to write the execution result of the target vector instruction into the vector register.

[0074] In some embodiments, the second pipeline has a first pipeline stage and a second pipeline stage. The output of the first pipeline stage serves as the input of the second pipeline stage. Unlocking a vector instruction in a locked state on the second pipeline stage according to an unlock signal includes: if the vector instruction in the instruction processing unit corresponding to the second pipeline stage is in an unlocked state, transmitting the unlock signal to the instruction processing unit corresponding to the first pipeline stage; and unlocking the vector instruction in the instruction processing unit corresponding to the first pipeline stage that is in a locked state according to the unlock signal.

[0075] In some embodiments, the second pipeline includes a vector instruction execution unit and a vector instruction write-back unit. Unlocking vector instructions in a locked state on the second pipeline based on an unlock signal includes: upon receiving an unlock signal, if a locked vector instruction exists in the vector instruction write-back unit, then unlocking the locked vector instruction present in the vector instruction write-back unit. Conversely, upon receiving an unlock signal, if a locked vector instruction does not exist in the vector instruction write-back unit but exists in the vector instruction execution unit, then unlocking the locked vector instruction present in the vector instruction execution unit.

[0076] In some implementations, the method may further include: if the first pipeline is interrupted by a trap event, clearing the vector instructions in the second pipeline that are in a locked state, and continuing to execute the vector instructions in the second pipeline that are in an unlocked state.

[0077] For specific limitations on vector instruction processing methods, please refer to the limitations on microprocessors mentioned above, which will not be repeated here.

[0078] This specification provides a computer device including a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the steps of the method described in any of the above embodiments.

[0079] This specification provides a computer-readable storage medium storing a computer program thereon, characterized in that the computer program, when executed by a processor, implements the steps of the method described in any of the above embodiments.

[0080] It should be noted that the logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Alternatively, the computer-readable medium may be paper or other suitable media on which the program can be printed, since the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in a computer memory.

[0081] It should be understood that various parts of the present invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0082] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0083] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0084] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0085] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A microprocessor, characterized in that, The microprocessor employs a pipeline comprising a first pipeline and a second pipeline; wherein the first pipeline has an instruction dispatch unit and a write-back unit; and the second pipeline has a vector instruction receiving unit. The instruction distribution unit is used to send vector instructions to the vector instruction receiving unit; The vector instruction receiving unit is used to set the vector instruction to a locked state; The write-back unit is configured to send an unlock signal to the instruction processing unit corresponding to a specified pipeline stage in the second pipeline when it receives the vector instruction identifier of the vector instruction transmitted through the first pipeline; wherein the unlock signal is configured to unlock the vector instruction that is in a locked state on the second pipeline so as to write the execution result of the vector instruction into the vector register.

2. The microprocessor according to claim 1, characterized in that, The first pipeline also includes a decoding unit, and the instruction distribution unit is used to send non-vector instructions to the decoding unit through the first pipeline.

3. The microprocessor according to claim 1, characterized in that, The vector instruction receiving unit includes an instruction buffer area; the instruction buffer area includes a lock marker area, which is used to store lock identifiers attached by the vector instruction receiving unit to the vector instruction.

4. The microprocessor according to claim 3, characterized in that, The vector instruction receiving unit is further configured to set the vector instruction to a write-back locked state; wherein, the vector instruction in the write-back locked state is allowed to be executed; The write-back unit is further configured to send a write-back unlock signal to the vector instruction write-back unit corresponding to the write-back pipeline stage in the second pipeline, wherein the lock identifier in the lock marker area is updated to an unlock identifier.

5. The microprocessor according to claim 3, characterized in that, The vector instruction receiving unit is further configured to set the vector instruction to an execution locked state; wherein, the vector instruction in the execution locked state is not allowed to be executed; The write-back unit is further configured to send an execution unlock signal to the vector instruction execution unit in the second pipeline, wherein the lock identifier in the lock marker area is updated to an unlock identifier.

6. The microprocessor according to claim 1, characterized in that, The second production line has a first production stage and a second production stage; the output of the first production stage serves as the input of the second production stage. The instruction processing unit corresponding to the second pipeline stage is used to transmit the unlock signal to the instruction processing unit corresponding to the first pipeline stage when the vector instruction in the instruction processing unit corresponding to the second pipeline stage is in an unlocked state. The instruction processing unit corresponding to the first pipeline stage is used to unlock the vector instruction that is in a locked state in the instruction processing unit corresponding to the first pipeline stage according to the unlock signal.

7. The microprocessor according to claim 1, characterized in that, The second pipeline includes a vector instruction write-back unit; The vector instruction write-back unit is configured to, upon receiving the unlock signal, unlock the vector instruction that is in a locked state in the vector instruction write-back unit if there is such a vector instruction in the unit.

8. The microprocessor according to claim 7, characterized in that, The second pipeline also includes a vector instruction execution unit; The vector instruction execution unit is configured to, upon receiving the unlock signal, unlock the vector instruction that is locked in the vector instruction execution unit if the vector instruction does not exist in the vector instruction write-back unit but exists in the vector instruction execution unit.

9. A vector instruction processing method, characterized in that, Applied to a microprocessor, wherein the microprocessor employs a pipeline including a first pipeline and a second pipeline; the method includes: The instruction dispatch unit on the first pipeline sends a vector instruction to the vector instruction receiving unit on the second pipeline; The vector instruction receiving unit sets the vector instruction to a locked state; When the vector instruction identifier of the vector instruction is transmitted to the write-back unit of the first pipeline through the first pipeline, the write-back unit sends an unlock signal to the second pipeline; The vector instruction that is in a locked state on the second pipeline is unlocked according to the unlock signal, so as to write the execution result of the vector instruction into the vector register.

10. The method according to claim 9, characterized in that, The first production line also includes a decoding unit; the method further includes: The instruction dispatch unit sends non-vector instructions to the decoding unit through the first pipeline.

11. The method according to claim 9, characterized in that, The vector instruction receiving unit sets the vector instruction to a locked state, including: The vector instruction receiving unit attaches a lock flag to the vector instruction; wherein the lock flag is used to indicate that the vector instruction is in a locked state.

12. The method according to claim 9, characterized in that, The vector instruction receiving unit sets the vector instruction to a locked state, including: The vector instruction receiving unit sets the vector instruction to a write-back locked state; wherein, the vector instruction in the write-back locked state is allowed to be executed; The write-back unit sends an unlock signal to the second pipeline, including: The write-back unit sends a write-back unlock signal to the vector instruction write-back unit corresponding to the write-back pipeline stage in the second pipeline.

13. The method according to claim 9, characterized in that, The vector instruction receiving unit sets the vector instruction to a locked state, including: The vector instruction receiving unit sets the vector instruction to an execution locked state; wherein, the vector instruction in the execution locked state is not allowed to be executed; The write-back unit sends an unlock signal to the second pipeline, including: The write-back unit sends an execution unlock signal to the vector instruction execution unit in the second pipeline.

14. The method according to claim 9, characterized in that, The vector instructions in the locked state include a first locking instruction and a second locking instruction; the locking time of the first locking instruction is earlier than the locking time of the second locking instruction; the step of unlocking the vector instructions in the locked state on the second pipeline according to the unlock signal, so as to write the execution result of the vector instructions into the vector register, includes: According to the unlock signal, the earliest locked target vector instruction among the vector instructions in the locked state on the second pipeline is unlocked, so as to write the execution result of the target vector instruction into the vector register.

15. The method according to claim 9, characterized in that, The second pipeline has a first pipeline stage and a second pipeline stage; the output of the first pipeline stage serves as the input of the second pipeline stage; the step of unlocking the vector command that is in a locked state on the second pipeline stage according to the unlock signal includes: When the vector instruction in the instruction processing unit corresponding to the second pipeline stage is in an unlocked state, the unlock signal is transmitted to the instruction processing unit corresponding to the first pipeline stage. According to the unlock signal, the vector instruction that is in a locked state in the instruction processing unit corresponding to the first pipeline stage is unlocked.

16. The method according to claim 9, characterized in that, The second pipeline includes a vector instruction execution unit and a vector instruction write-back unit; the step of unlocking the vector instructions in the locked state on the second pipeline according to the unlock signal includes: Upon receiving the unlock signal, if there is a locked vector instruction in the vector instruction write-back unit, then the locked vector instruction in the vector instruction write-back unit is unlocked. Upon receiving the unlock signal, if the vector instruction is not present in the vector instruction write-back unit but exists in the vector instruction execution unit and is in a locked state, the locked vector instruction in the vector instruction execution unit is unlocked.

17. The method according to claim 9, characterized in that, The method further includes: If the first pipeline is interrupted by a trap event, the vector instructions in the second pipeline that are in a locked state are cleared, and the vector instructions in the second pipeline that are in an unlocked state are continued to be executed.

18. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 9 to 17.

19. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 9 to 17.

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