Gate driving circuit and display panel

Abstract

The application discloses a gate driving circuit and a display panel. The gate driving circuit comprises a gate driving unit, each gate driving unit comprises a first transistor and a second transistor, and the second size of the second transistor is greater than the first size of the first transistor. The working stability of the second transistor is improved, and the coupling of the output end potential of the first transistor to the output end potential of the second transistor is reduced or avoided.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a gate driving circuit and a display panel. BACKGROUND

[0002] In the gate driving circuit, the conduction or the cut-off of one transistor is usually driven by connecting the output end of the transistor with the control end of another transistor. However, since there is a parasitic capacitance between the gate of the another transistor and its output end, the output end potential of the another transistor will be coupled by the gate potential of the another transistor, which affects the stability of the output end potential of the another transistor, and further affects the working stability or reliability of the gate driving circuit. SUMMARY

[0003] The present application provides a gate driving circuit and a display panel to solve the technical problem of low working reliability of the gate driving circuit.

[0004] In a first aspect, the present application provides a gate driving circuit, which comprises a plurality of gate driving units. Each gate driving unit comprises a first transistor and a second transistor. One of the source / drain of the first transistor is connected with a first transmission line, and the gate of the first transistor is connected with a first control line. The gate of the second transistor is connected with the other of the source / drain of the first transistor, one of the source / drain of the second transistor is connected with a second transmission line, and the other of the source / drain of the second transistor is connected with an output line. The second size of the second transistor is greater than the first size of the first transistor.

[0005] In some embodiments, the second size is greater than or equal to 1.05 times of the first size, and less than or equal to 1.25 times of the first size.

[0006] In some embodiments, the second size is equal to 1.1 times of the first size.

[0007] In some embodiments, the output line is one of a cascade line or a scan line.

[0008] In some embodiments, each gate driving unit further comprises a third transistor. The gate of the third transistor is connected with the other of the source / drain of the first transistor, one of the source / drain of the third transistor is connected with the second transmission line, and the other of the source / drain of the third transistor is connected with the other of the cascade line or the scan line. The third size of the third transistor is greater than the first size of the first transistor.

[0009] In some embodiments, the third dimension is greater than or equal to 1.05 times the first dimension and less than or equal to 1.25 times the first dimension.

[0010] In some embodiments, the third dimension is 1.1 times the first dimension.

[0011] In some embodiments, the other one of the source / drain of the second transistor is connected with the cascade line, the other one of the source / drain of the third transistor is connected with the scan line, and the third dimension is greater than the second dimension.

[0012] In some embodiments, the output line is used to transmit an output signal, the output signal has a first potential and a second potential, the first potential is greater than the second potential, and the gate potential of the second transistor in the on state is greater than the first potential.

[0013] In a second aspect, the present application provides a display panel, which comprises the gate drive circuit in the at least one embodiment.

[0014] The gate drive circuit and the display panel provided by the present application increase the second dimension of the second transistor compared with the first dimension of the first transistor by setting the second dimension of the second transistor to be greater than the first dimension of the first transistor, thereby improving the working stability of the second transistor itself, limiting the transmission performance of the first transistor by the first dimension, reducing or avoiding the coupling of the output end potential of the first transistor to the output end potential of the second transistor, and stabilizing the output end potential of the second transistor, thereby improving the working stability or reliability of the gate drive circuit. BRIEF DESCRIPTION OF DRAWINGS

[0015] The technical solutions and other beneficial effects of the present application will become apparent through the following detailed description of the specific embodiments of the present application in conjunction with the accompanying drawings.

[0016] Figure 1 The structure schematic diagram of the gate drive circuit provided by the embodiments of the present application is shown.

[0017] Figure 2 The structure schematic diagram of the gate drive circuit provided by the embodiments of the present application is shown. Figure 1 The waveform schematic diagram of Q(N) and ST(N) before and after improvement is shown in FIG. 2.

[0018] Figure 3 The structure schematic diagram of the gate drive circuit provided by the embodiments of the present application is shown. Figure 1 The waveform schematic diagram of Q(N) and ST(N) before and after improvement is shown in FIG. 2. DETAILED DESCRIPTION

[0019] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0020] In view of the aforementioned technical problem of low reliability of the gate drive circuit, this embodiment provides a gate drive circuit, please refer to... Figures 1 to 3 ,like Figure 1 As shown, the gate driving circuit includes gate driving units, each of which includes a first transistor T11 and a second transistor T22. One of the source / drain terminals of the first transistor T11 is connected to the first transmission line 11, and the gate of the first transistor T11 is connected to the first control line 12. The gate of the second transistor T22 is connected to the other of the source / drain terminals of the first transistor T11, one of the source / drain terminals of the second transistor T22 is connected to the second transmission line 13, and the other of the source / drain terminal of the second transistor T22 is connected to the output line 14. The second dimension of the second transistor T22 is larger than the first dimension of the first transistor T11.

[0021] It is understood that the gate driving circuit provided in this embodiment, by setting the second size of the second transistor T22 to be larger than the first size of the first transistor T11, increases the second size of the second transistor T22 compared to the first size of the first transistor T11. This not only improves the working stability of the second transistor T22 itself, but also limits the transmission performance of the first transistor T11 by the first size, thereby reducing or avoiding the coupling of the output potential of the first transistor T11 to the output potential of the second transistor T22. This is beneficial to stabilizing the output potential of the second transistor T22, thereby improving the working stability or reliability of the gate driving circuit.

[0022] In one embodiment, the output line 14 is either a cascade line 141 or a scan line 142.

[0023] It should be noted that connecting the other of the source / drain terminals of the second transistor T22 to either cascade line 141 or scan line 142 can improve the operational stability of the gate drive circuit.

[0024] It should be noted that the output line 14 mentioned above can be either a cascade line 141 or a scan line 142. The cascade line 141 is used to transmit the Nth cascade signal ST(N). The scan line 142 is used to transmit the Nth scan signal G(N).

[0025] The first transmission line 11 can be used to transmit a first transmission signal, which can be a direct current signal or a square wave signal. The square wave signal can be another scanning signal earlier in phase than the Nth scanning signal G(N) in a frame, for example, the (N-1)th scanning signal, the (N-6)th scanning signal G(N-6), or the (N-9)th scanning signal, and so on. The scanning signals of different levels have the same waveform but different phases.

[0026] The first control line 12 can be used to transmit a first control signal, which can also be a square wave signal. The square wave signal can be another scanning signal earlier in phase than the Nth cascade signal ST(N) in a frame, for example, the (N-1)th cascade signal, the (N-6)th cascade signal ST(N-6), or the (N-9)th cascade signal, and so on. The cascade signals of different levels have the same waveform but different phases.

[0027] The second transmission line 13 can be used to transmit a second transmission signal, which can be a direct current signal or a clock signal, and specifically the Nth clock signal CK(N). The clock signals of different levels have the same waveform but different phases.

[0028] In one embodiment, the second dimension is greater than or equal to 1.05 times the first dimension and less than or equal to 1.25 times the first dimension.

[0029] It should be noted that the embodiment configures the proportional relationship between the first dimension and the second dimension, which can maximize the reduction of the adverse effects on the output potential of the second transistor T22 with appropriate dimensions, not only reducing the occupied space of the gate drive circuit, but also improving the stability of the gate drive circuit.

[0030] The second dimension of the second transistor T22 can be increased to more flexibly configure the positional relationship between the gate and the output end (i.e., the source or the drain) of the second transistor T22. For example, a smaller overlapping area between the gate and the source or the drain of the second transistor T22 can be configured in the thickness direction of the gate drive circuit, and even the overlapping area can be zero to reduce the parasitic capacitance between the gate and the source or the drain of the second transistor T22.

[0031] In one embodiment, the second dimension is 1.1 times the first dimension.

[0032] It should be noted that the embodiment configures the second dimension to be 1.1 times the first dimension, which can maximize the reduction of the adverse effects on the output potential of the second transistor T22 with the smallest dimensions, not only reducing the occupied space of the gate drive circuit, but also improving the stability of the gate drive circuit.

[0033] In one of the embodiments, each gate drive unit further comprises a third transistor T21, a gate of the third transistor T21 is connected with the other one of the source / drain of the first transistor T11, one of the source / drain of the third transistor T21 is connected with the second transmission line 13, the other one of the source / drain of the third transistor T21 is connected with the other one of the cascade line 141 or the scan line 142; wherein the third size of the third transistor T21 is greater than the first size of the first transistor T11.

[0034] It should be noted that, in the embodiment, the third size of the third transistor T21 is greater than the first size of the first transistor T11, which increases the third size of the third transistor T21 compared with the first size of the first transistor T11, not only improves the working stability of the third transistor T21 itself, but also limits the transmission performance of the first transistor T11 through the first size, so as to reduce or avoid the coupling of the output end potential of the first transistor T11 to the output end potential of the third transistor T21, which is conducive to stabilizing the output end potential of the third transistor T21, and further improves the working stability or reliability of the gate drive circuit.

[0035] In one of the embodiments, the third size is greater than or equal to 1.05 times of the first size, and less than or equal to 1.25 times of the first size.

[0036] It should be noted that, in the embodiment, the ratio between the first size and the third size is constructed, which can maximize the reduction of the adverse effects on the output end potential of the third transistor T21 with a suitable size, not only reduces the occupied space of the gate drive circuit, but also improves the stability of the gate drive circuit.

[0037] In one of the embodiments, the third size of the third transistor T21 can be more flexibly configured in the positional relationship between the gate and the output end, i.e. the source or the drain, of the third transistor T21, for example, a smaller overlapping area between the gate of the third transistor T21 and the source or the drain of the third transistor T21 can be constructed in the thickness direction of the gate drive circuit, and even the overlapping area can be zero, so as to reduce the parasitic capacitance between the gate of the third transistor T21 and the source or the drain of the third transistor T21.

[0038] In one of the embodiments, the third size is equal to 1.1 times of the first size.

[0039] It should be noted that, in the embodiment, the third size is equal to 1.1 times of the first size, which can maximize the reduction of the adverse effects on the output end potential of the third transistor T21 with the smallest size, not only reduces the occupied space of the gate drive circuit, but also improves the stability of the gate drive circuit.

[0040] In one of the embodiments, the other one of the source / drain of the second transistor T22 is connected with the cascade line 141, the other one of the source / drain of the third transistor T21 is connected with the scan line 142, and the third size is greater than the second size.

[0041] It needs to be explained that compared with the second transistor T22, the third transistor T21 connected with the scan line 142 needs to output the corresponding scan signal to the display panel through a longer path, and the third transistor T21 needs to drive more load, therefore, configuring the third transistor T21 with a size greater than that of the second transistor T22 is also beneficial to improve the load capacity of the output scan signal of the third transistor T21, and further stabilizes the working stability or reliability of the display panel.

[0042] In one of the embodiments, the gate driving unit further comprises a transistor T44, one of the source / drain of the transistor T44 is connected with the other one of the source / drain of the first transistor T11, the first node Q(N), the other one of the source / drain of the transistor T44 is connected with the first low potential line, and the gate of the transistor T32 is connected with the start line.

[0043] It needs to be explained that the first low potential line is used to transmit the first low potential signal VSSQ. The start line is used to transmit the start signal STV, which can be used to disable the gate driving circuit to provide the output signal with pulses in the blank phase of each frame.

[0044] In one of the embodiments, the gate driving unit further comprises a first inversion module, the first inversion module is connected with the first node Q(N) and the second node K.

[0045] It needs to be explained that in the embodiment, when the potential of the first node Q(N) is high, the potential of the second node K is low; when the potential of the first node Q(N) is low, the potential of the second node K is high.

[0046] In one of the embodiments, the first inverting module comprises a transistor T51, a transistor T52, a transistor T53 and a transistor T54. One of the source / drain of the transistor T51 is connected with one of the source / drain of the transistor T53, the second control line and the gate of the transistor T51, the other of the source / drain of the transistor T51 is connected with the gate of the transistor T53 and one of the source / drain of the transistor T52, the other of the source / drain of the transistor T53 is connected with the second node K, the gate of the transistor T32 and one of the source / drain of the transistor T54, the first low potential line is connected with the other of the source / drain of the transistor T52 and the other of the source / drain of the transistor T54, the first node Q(N) is connected with the gate of the transistor T52 and the gate of the transistor T54.

[0047] The second control line is used for transmitting a second control signal, and the second control signal is a low-frequency control signal LC1.

[0048] In one of the embodiments, the gate driving unit further comprises a transistor T42, one of the source / drain of the transistor T42 is connected with the first node Q(N), the other of the source / drain of the transistor T42 is connected with the first low potential line, and the gate of the transistor T42 is connected with the second node K.

[0049] In one of the embodiments, the gate driving unit further comprises a transistor T72, one of the source / drain of the transistor T72 is connected with the other of the source / drain of the second transistor T22 and the cascade line 141, the other of the source / drain of the transistor T72 is connected with the first low potential line, and the gate of the transistor T72 is connected with the second node K.

[0050] In one of the embodiments, the gate driving unit further comprises a transistor T32, one of the source / drain of the transistor T32 is connected with the other of the source / drain of the third transistor T21 and the scan line 142, the other of the source / drain of the transistor T32 is connected with the second low potential line, and the gate of the transistor T32 is connected with the second node K.

[0051] It is to be noted that the second low potential line is used for transmitting a second low potential signal VSSG.

[0052] In one of the embodiments, the gate driving unit further comprises a capacitor Cbt, one end of the capacitor Cbt is connected with the first node Q(N), and the other end of the capacitor Cbt is connected with the scan line 142.

[0053] In one of the embodiments, the gate driving unit further comprises a second inverting module, and the second inverting module is connected with the first node Q(N) and the third node P.

[0054] It needs to be explained that in the embodiment, the potential of the first node Q(N) is high potential, and the potential of the third node P is low potential; the potential of the first node Q(N) is low potential, and the potential of the third node P is high potential.

[0055] In one of the embodiments, the second inverting module comprises a transistor T61, a transistor T62, a transistor T63 and a transistor T64. One of the source / drain of the transistor T61 is connected with one of the source / drain of the transistor T63, the third control line and the gate of the transistor T61, the other of the source / drain of the transistor T61 is connected with the gate of the transistor T63 and one of the source / drain of the transistor T62, the other of the source / drain of the transistor T63 is connected with the third node P and one of the source / drain of the transistor T64, the first low potential line is connected with the other of the source / drain of the transistor T62 and the other of the source / drain of the transistor T64, the first node Q(N) is connected with the gate of the transistor T62 and the gate of the transistor T64.

[0056] The third control line is used for transmitting a third control signal, and the third control signal is a low-frequency control signal LC2. When the second control signal is low potential, the third control signal is high potential; when the second control signal is high potential, the third control signal is low potential.

[0057] In one of the embodiments, the gate driving unit further comprises a transistor T43, one of the source / drain of the transistor T43 is connected with the first node Q(N), the other of the source / drain of the transistor T43 is connected with the first low potential line, and the gate of the transistor T43 is connected with the third node P.

[0058] In one of the embodiments, the gate driving unit further comprises a transistor T73, one of the source / drain of the transistor T73 is connected with the cascade line 141, the other of the source / drain of the transistor T73 is connected with the first low potential line, and the gate of the transistor T73 is connected with the third node P.

[0059] In one of the embodiments, the gate driving unit further comprises a transistor T33, one of the source / drain of the transistor T33 is connected with the scanning line 142, the other of the source / drain of the transistor T33 is connected with the second low potential line, and the gate of the transistor T33 is connected with the third node P.

[0060] In one of the embodiments, the gate driving unit further comprises a transistor T41, one of the source / drain of the transistor T41 is connected with the first node Q(N), the other of the source / drain of the transistor T41 is connected with the first low potential line, and the gate of the transistor T41 is connected with the fourth control line.

[0061] It needs to be explained that, the fourth control line is used for transmitting the fourth control signal, which can be the N+8th cascade signal ST(N+8).

[0062] In one of the embodiments, the gate driving unit further comprises a transistor T31, one of the source / drain of the transistor T31 is connected with the scanning line 142, the other of the source / drain of the transistor T31 is connected with the second low potential line, and the gate of the transistor T31 is connected with the fourth control line.

[0063] In one of the embodiments, the above-mentioned transistors can be N-channel thin film transistors, specifically can be N-channel metal oxide thin film transistors, and preferably can be N-channel indium gallium zinc oxide thin film transistors.

[0064] In one of the embodiments, the above-mentioned transistors can be P-channel thin film transistors, specifically can be P-channel polysilicon thin film transistors, and preferably can be P-channel low temperature polysilicon thin film transistors.

[0065] Figure 2 For Figure 1 the waveform schematic diagram of Q(N) and ST(N) before improvement, Figure 3 for Figure 1 the waveform schematic diagram of Q(N) and ST(N) before and after improvement, please refer to Figure 2 , Figure 3 wherein, Q(N) is also the gate potential of the second transistor T22, and the curve S1 represents the potential variation trend of the Nth cascade signal ST(N), as shown in Figure 2 the dashed box in FIG. 2, when the gate potential of the second transistor T22 jumps to the highest potential, due to the existence of the capacitance between the gate of the second transistor T22 and the source or drain of the second transistor T22, the potential of the Nth cascade signal ST(N) will be coupled to rise. In addition, when the Nth cascade signal ST(N) is at a low potential, it will be coupled by the Nth clock signal CK(N) transmitted in the second transmission line 13 to produce changes such as glitches.

[0066] Please refer to Figure 3 , Figure 3 the curve S2 in FIG. 2 is the potential variation trend of the Nth cascade signal ST(N) after the size of the second transistor T22 is increased, compared with the curve S1, due to the increase of the size of the second transistor T22, the stability of its own work is improved, even if the gate potential of the second transistor T22 jumps to the highest potential, the potential of the Nth cascade signal ST(N) will not be coupled to rise. In addition, even if the Nth cascade signal ST(N) is at a low potential, the potential variation amplitude of the Nth cascade signal ST(N) is also reduced.

[0067] The output line 14 is configured to transmit an output signal, and the output signal has a first potential and a second potential, wherein the first potential is greater than the second potential.

[0068] It should be noted that, after increasing the size of the second transistor T22, even if the potential of the other one of the source / drain of the first transistor T11 is much higher than the potential of the Nth cascade signal ST(N), the second transistor T22 can still maintain stable output without being affected.

[0069] In one of the embodiments, the embodiment provides a display panel, which comprises the gate drive circuit in the at least one embodiment.

[0070] It can be understood that, the display panel provided by the embodiment increases the second size of the second transistor T22 compared with the first size of the first transistor T11, which not only improves the working stability of the second transistor T22 itself, but also limits the transmission performance of the first transistor T11 through the first size, so as to reduce or avoid the coupling of the output end potential of the first transistor T11 to the output end potential of the second transistor T22, which is conducive to stabilizing the output end potential of the second transistor T22, and further improves the working stability or reliability of the gate drive circuit.

[0071] It should be noted that, the display panel can be a liquid crystal display panel, or a self-luminous display panel, for example, an organic light-emitting diode display panel, a mini light-emitting diode display panel, a micro light-emitting diode display panel, or a quantum dot light-emitting diode display panel.

[0072] In the above embodiments, the description of each embodiment has its own focus, and the parts not described in detail in a certain embodiment can be referred to the relevant description of other embodiments.

[0073] The gate drive circuit and the display panel provided by the embodiments of the present application are described in detail above, and the principle and implementation manner of the present application are described by applying specific examples in this paper, and the above description of the embodiments is only used to help understand the technical solutions and core ideas of the present application; those skilled in the art should understand that: the technical solutions recorded in the above embodiments can be modified, or some technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A gate driving circuit, characterized in that, The gate driving circuit includes gate driving units, each of the gate driving units comprising: A first transistor, wherein one of its source / drain terminals is connected to a first transmission line for transmitting the (N-6)th level scan signal, and the gate of the first transistor is connected to a first control line for transmitting the (N-6)th level cascade signal; and The second transistor has its gate connected to the other of the source / drain of the first transistor, one of the source / drain of the second transistor is connected to the second transmission line, and the other of the source / drain of the second transistor is connected to the output line, which is a cascade line for transmitting the Nth stage transmission signal. The second dimension of the second transistor is larger than the first dimension of the first transistor.

2. The gate driving circuit according to claim 1, characterized in that, The second dimension is greater than or equal to 1.05 times the first dimension and less than or equal to 1.25 times the first dimension.

3. The gate driving circuit according to claim 2, characterized in that, The second dimension is equal to 1.1 times the first dimension.

4. The gate driving circuit according to claim 1, characterized in that, Each of the gate driving units further includes a third transistor, the gate of which is connected to the other of the source / drain of the first transistor, one of the source / drain of the third transistor is connected to the second transmission line, and the other of the source / drain of the third transistor is connected to the scan line; The third dimension of the third transistor is larger than the first dimension of the first transistor.

5. The gate driving circuit according to claim 4, characterized in that, The third dimension is greater than or equal to 1.05 times the first dimension and less than or equal to 1.25 times the first dimension.

6. The gate driving circuit according to claim 5, characterized in that, The third dimension is equal to 1.1 times the first dimension.

7. The gate driving circuit according to claim 4, characterized in that, The other of the source / drain of the second transistor is connected to the cascade line, and the other of the source / drain of the third transistor is connected to the scan line. The third dimension is larger than the second dimension.

8. The gate driving circuit according to claim 1, characterized in that, The output line is used to transmit an output signal, which has a first potential and a second potential, wherein the first potential is greater than the second potential. The gate potential of the second transistor in the on state is greater than the first potential.

9. A display panel, characterized in that, Includes the gate drive circuit as described in any one of claims 1-8.

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