Epitaxial structure and method of manufacturing the same, semiconductor device and method of manufacturing the same

Abstract

The embodiment of the present application discloses an epitaxial structure and a preparation method thereof, and a semiconductor device and a preparation method thereof. The epitaxial structure comprises: a substrate; a semiconductor layer located on one side of the substrate, and a surface of the semiconductor layer away from the substrate is a metal polarity surface; and a nitrogen polarity surface cap layer located on the side of the semiconductor layer away from the substrate. The semiconductor layer with the metal polarity surface and the nitrogen polarity surface cap layer form a composite polarity epitaxial structure. When the semiconductor device is formed, the nitrogen polarity surface cap layer with strong negative electricity can form a good ohmic contact with a source and a drain at normal temperature, without high-temperature treatment, so that the process difficulty can be reduced. The semiconductor layer can be used as a wet etching self-stopping layer of the nitrogen polarity surface cap layer, so that the threshold voltage is stable, the transconductance is improved, and the device performance is improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor technology, and in particular to an epitaxial structure and its preparation method, and a semiconductor device and its preparation method. Background Technology

[0002] Compound semiconductor materials, represented by gallium nitride, have the characteristics of large bandgap, high electron saturation drift velocity, high breakdown field strength, and good thermal conductivity, and are widely used in optoelectronic detection, communication, radar, power electronics and other fields.

[0003] Due to the strong polarization effect (spontaneous polarization and piezoelectric polarization) in the AlGaN / GaN heterostructure, a high-concentration two-dimensional electron gas (2DEG) can be formed at the interface of undoped heterojunctions fabricated using this polarization effect. This also avoids impurity scattering, significantly improving electron mobility. High electron mobility transistors (HEMTs) based on 2DEGs exhibit high power density, strong breakdown electric field, high cutoff frequency, and fast switching speed, making them ideal for operation under high voltage, high frequency, and high power conditions.

[0004] Currently, the fabrication of HEMT devices faces two main challenges: difficulty in achieving ohmic contacts and significant threshold voltage fluctuations. Regarding ohmic contacts, existing techniques struggle to achieve heavy doping in the cap layer due to thickness limitations. Therefore, methods such as high-temperature alloying and ion implantation are necessary. However, both high-temperature alloying and ion implantation require high-temperature processing. High-temperature alloy ohmic contacts suffer from alloy bursting issues and have limited process windows. Ion-implanted ohmic contacts require high-temperature activation (above 1000°C), which can damage the passivation medium, increasing leakage current and degrading device performance. As for a stable threshold voltage, existing techniques primarily avoid etching the epitaxial layer, using it as a self-stopping layer with the epitaxial layer as the overlying passivation medium. However, this method degrades the device's leakage current and transconductance characteristics.

[0005] Therefore, in order to improve the electrical characteristics of HEMT devices and the process window during fabrication, low-temperature ohmic contacts and low-damage, highly controllable semiconductor layer RECESS technology are urgent problems to be solved. Summary of the Invention

[0006] This invention provides an epitaxial structure and its fabrication method, as well as a semiconductor device and its fabrication method, to provide an epitaxial structure and semiconductor device that can achieve low-temperature ohmic contact, threshold stability, and good transconductance performance.

[0007] In a first aspect, embodiments of the present invention provide an epitaxial structure for a semiconductor device, the epitaxial structure comprising:

[0008] Substrate;

[0009] A semiconductor layer is located on one side of the substrate, and the surface of the semiconductor layer on the side away from the substrate is a metallic polar surface;

[0010] A nitrogen polar cap layer is located on the side of the semiconductor layer away from the substrate.

[0011] Optionally, the semiconductor layer includes: a metal polarity barrier layer and a channel layer located on the side of the metal polarity barrier layer near the substrate, wherein the metal polarity barrier layer and the channel layer form a heterojunction structure.

[0012] Optionally, the nitrogen polar cap layer further includes an n-type doped material;

[0013] The n-type doped material includes at least one of silicon, germanium, carbon, and oxygen;

[0014] The doping concentration of the n-type doped material is D, 10 17 / cm 3 ≤D≤10 20 / cm 3 .

[0015] In a second aspect, embodiments of the present invention provide a semiconductor device, the semiconductor device comprising: an epitaxial structure and an electrode structure;

[0016] The epitaxial structure includes:

[0017] Substrate;

[0018] A semiconductor layer is located on one side of the substrate, and the surface of the semiconductor layer on the side away from the substrate is a metallic polar surface;

[0019] A nitrogen-polar cap layer is located on the side of the semiconductor layer away from the substrate, and a first opening is provided in the nitrogen-polar cap layer, the first opening penetrating the nitrogen-polar cap layer;

[0020] The electrode structure includes a source, a gate, and a drain; the source and the drain are located on the side of the nitrogen polar cap layer away from the substrate, and both the source and the drain form an ohmic contact with the nitrogen polar cap layer; at least a portion of the gate is located within the first opening, and the gate is insulated from the nitrogen polar cap layer.

[0021] Optionally, the semiconductor device further includes a passivation layer, at least a portion of which is located within the first opening, and the gate is insulated from the nitrogen polar cap layer through the passivation layer.

[0022] Optionally, a second opening is provided in the passivation layer located within the first opening, and the second opening at least partially penetrates the passivation layer;

[0023] At least a portion of the gate is located within the second opening.

[0024] Optionally, the second opening extends through the passivation layer and stops at the surface of the semiconductor layer on the side away from the substrate;

[0025] The gate is in contact with the semiconductor layer.

[0026] Thirdly, embodiments of the present invention provide a method for fabricating an epitaxial structure of a semiconductor device, used to fabricate the epitaxial structure described in the first aspect, the method comprising:

[0027] Provide substrate;

[0028] A semiconductor layer is fabricated on one side of the substrate, and the surface of the semiconductor layer on the side away from the substrate is a metallic polar surface;

[0029] A nitrogen polar cap layer is prepared on the side of the semiconductor layer away from the substrate.

[0030] This invention provides a method for fabricating a semiconductor device, the method comprising:

[0031] Provide substrate;

[0032] A semiconductor layer is fabricated on one side of the substrate, and the surface of the semiconductor layer on the side away from the substrate is a metallic polar surface;

[0033] A nitrogen polar cap layer is prepared on the side of the semiconductor layer away from the substrate, and a first opening is formed in the nitrogen polar cap layer, the first opening penetrating the nitrogen polar cap layer;

[0034] A source and a drain are fabricated on the side of the nitrogen-polar cap layer away from the substrate, and both the source and the drain form an ohmic contact with the nitrogen-polar cap layer; a gate is fabricated at least within the first opening, and the gate is insulated from the nitrogen-polar cap layer; the source, the gate, and the drain constitute an electrode structure.

[0035] Optionally, the preparation method further includes:

[0036] A passivation layer is formed at least within the first opening, and the gate is insulated from the nitrogen polar cap layer through the passivation layer.

[0037] Optionally, the preparation method further includes:

[0038] A second opening is formed in a passivation layer located within the first opening, the second opening at least partially penetrating the passivation layer;

[0039] The gate is fabricated at least within the second opening.

[0040] Optionally, forming the first opening in the nitrogen polar cap layer includes:

[0041] The nitrogen polar cap layer is etched with an alkaline solution to form a first opening in the nitrogen polar cap layer, the first opening penetrating the nitrogen polar cap layer.

[0042] The epitaxial structure of the semiconductor device provided in this embodiment of the invention includes a substrate, a semiconductor layer, and a nitrogen-polarized cap layer stacked together. The surface of the semiconductor layer away from the substrate is a metallic polarized surface. The semiconductor layer with the metallic polarized surface and the nitrogen-polarized cap layer form a composite polarized epitaxial structure. During the subsequent formation of the semiconductor device, on the one hand, the nitrogen-polarized cap layer naturally exhibits strong negative charge, allowing it to form good ohmic contacts with the source and drain at room temperature, respectively, without the need for high-temperature processing, thus reducing process difficulty and increasing the process window. On the other hand, a through-hole first opening is formed in the nitrogen-polarized cap layer through wet etching, with at least a portion of the gate located within the first opening. The gate is insulated from the nitrogen-polarized cap layer, making the semiconductor layer act as a self-stopping layer for wet etching of the nitrogen-polarized cap layer. This stabilizes the threshold voltage while increasing transconductance and reducing leakage current, thereby improving device performance. Attached Figure Description

[0043] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, although the drawings described below are some specific embodiments of the present invention, those skilled in the art can extend and extend the basic concepts of the device structure, driving method and manufacturing method disclosed and indicated by various embodiments of the present invention to other structures and drawings. Undoubtedly, these should all be within the scope of the claims of the present invention.

[0044] Figure 1 This is a schematic diagram of the epitaxial structure of a semiconductor device provided in an embodiment of the present invention;

[0045] Figure 2 This is a schematic diagram of the epitaxial structure of another semiconductor device provided in an embodiment of the present invention;

[0046] Figure 3 This is a schematic diagram of the epitaxial structure of another semiconductor device provided in an embodiment of the present invention;

[0047] Figure 4This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention;

[0048] Figure 5 This is a schematic diagram of another semiconductor device provided in an embodiment of the present invention;

[0049] Figure 6 This is a schematic diagram of the structure of another semiconductor device provided in an embodiment of the present invention;

[0050] Figure 7 This is a schematic diagram of the structure of another semiconductor device provided in an embodiment of the present invention;

[0051] Figure 8 This is a flowchart illustrating a method for fabricating an epitaxial structure of a semiconductor device according to an embodiment of the present invention;

[0052] Figure 9 This is a flowchart of another method for fabricating the epitaxial structure of a semiconductor device provided in an embodiment of the present invention;

[0053] Figure 10 This is a flowchart of another method for fabricating the epitaxial structure of a semiconductor device provided in an embodiment of the present invention;

[0054] Figure 11 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention;

[0055] Figure 12 This is a flowchart of another method for fabricating a semiconductor device provided in an embodiment of the present invention;

[0056] Figure 13 This is a flowchart of another method for fabricating a semiconductor device provided in an embodiment of the present invention;

[0057] Figure 14 This is a flowchart of another method for fabricating a semiconductor device provided in an embodiment of the present invention. Detailed Implementation

[0058] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of this invention. Obviously, the described embodiments are only some embodiments of this invention, not all embodiments. Based on the basic concepts disclosed and indicated in the embodiments of this invention, all other embodiments obtained by those skilled in the art are within the scope of protection of this invention.

[0059] Figure 1 This is a schematic diagram of the epitaxial structure of a semiconductor device provided in an embodiment of the present invention, as shown below. Figure 1As shown, the epitaxial structure provided in this embodiment includes: a substrate 100; a semiconductor layer 200 located on one side of the substrate 100, the surface of the semiconductor layer 200 away from the substrate 100 being a metal polar surface; and a nitrogen polar surface cap layer 210 located on the side of the semiconductor layer 200 away from the substrate 100.

[0060] For example, refer to Figure 1 The epitaxial structure of the semiconductor device provided in this embodiment includes a substrate 100, a semiconductor layer 200, and a nitrogen polar cap layer 210 stacked sequentially. The substrate 100 may be one or more of gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, indium phosphide, gallium arsenide, silicon carbide, diamond, sapphire, germanium, and silicon, or any other material capable of growing group III nitrides.

[0061] The surface of the semiconductor layer 200 away from the substrate 100 is a metallic polar surface. The semiconductor layer 200 with the metallic polar surface and the nitrogen polar surface cap layer 210 form a composite polar epitaxial structure, that is, the semiconductor layer 200 and the nitrogen polar surface cap layer 210 have different polar surfaces. By adopting this composite polar epitaxial structure, room temperature ohmic contact can be achieved when forming semiconductor devices, reducing the difficulty of the process, increasing the process window, stabilizing the threshold voltage and increasing the transconductance, thereby improving the device performance.

[0062] Specifically, a source fabrication region 11 and a drain fabrication region 13 are provided on the side of the nitrogen polar cap layer 210 away from the substrate 100. When forming a semiconductor device, the source and drain can be fabricated in the source fabrication region 11 and the drain fabrication region 13 respectively, and the source and drain are in direct contact with the nitrogen polar cap layer 210. Due to the strong negative charge inherent in the nitrogen polar cap layer 210, good ohmic contact can be formed with the source and drain at room temperature, without the need for high-temperature treatment. This reduces the difficulty of the process, increases the process window, reduces the leakage current of the device, and thus improves the device performance.

[0063] Furthermore, when forming a semiconductor device, a first opening can be formed in the nitrogen polar cap layer 210 by wet etching. The first opening penetrates the nitrogen polar cap layer 210 and a gate fabrication region 12 is formed in the first opening. A gate can be formed in the gate fabrication region 12 so that at least part of the gate is located in the first opening, thereby stabilizing the threshold voltage while improving the transconductance. Specifically, a through-hole opening is formed in the nitrogen polar cap layer 210 by wet etching. On the one hand, wet etching causes less damage to the device compared to dry etching. On the other hand, if the first opening is formed by wet etching using an alkaline solution, the alkaline solution can easily etch nitrogen polar group III nitride materials, but cannot etch metal polar group III nitride materials. Therefore, by using a composite polar epitaxial structure formed by a semiconductor layer 200 with a metal polar surface and a nitrogen polar cap layer 210, the first opening can be stopped precisely on the surface of the semiconductor layer 200 away from the substrate, that is, at the interface between the semiconductor layer 200 and the nitrogen polar cap layer 210. This makes the semiconductor layer 200 a self-stopping layer for wet etching of the nitrogen polar cap layer 210, thereby achieving low-damage and highly controllable semiconductor layer RECESS capability and stabilizing the threshold voltage. At least part of the gate is located within the first opening. Compared with the prior art, which does not etch the epitaxial layer, the gate is closer to the 2DEG in the semiconductor device, which can effectively improve transconductance characteristics, reduce leakage current, and further improve device performance.

[0064] Therefore, by using a composite polar epitaxial structure formed by a semiconductor layer 200 with a metallic polar surface and a nitrogen polar cap 220, room-temperature ohmic contact can be achieved when forming semiconductor devices, reducing process difficulty and increasing the process window. The semiconductor layer 200 can serve as a wet etching self-stopping layer for the nitrogen polar cap layer 210, enabling low-damage and highly controllable semiconductor layer RECESS function. While stabilizing the threshold voltage, it can also increase transconductance and reduce leakage current, thereby improving device performance.

[0065] It should be noted that if the nitrogen polar cap layer 210, which has a strong negative charge, comes into direct contact with the gate during the formation of a semiconductor device, a short circuit will occur. Therefore, a passivation medium is required to separate the nitrogen polar cap layer 210 from the gate and to ensure that the nitrogen polar cap layer 210 does not come into direct contact with the gate.

[0066] Furthermore, the embodiments of the present invention do not limit the materials and thicknesses of the substrate 100, the semiconductor layer 200, and the nitrogen polar cap layer 210. Those skilled in the art can set them according to actual needs. For example, both the semiconductor layer 200 and the nitrogen polar cap layer 210 can be group III nitride materials, the thickness of the substrate 100 can be 100μm-1000μm, and the thickness of the nitrogen polar cap layer 210 can be 1nm-1μm, etc.

[0067] The epitaxial structure of the semiconductor device provided in this embodiment of the invention includes a substrate, a semiconductor layer, and a nitrogen-polarized cap layer stacked together. The surface of the semiconductor layer away from the substrate is a metallic polarized surface. The semiconductor layer with the metallic polarized surface and the nitrogen-polarized cap layer form a composite polarized epitaxial structure. During the subsequent formation of the semiconductor device, on the one hand, the nitrogen-polarized cap layer naturally exhibits strong negative charge, allowing it to form good ohmic contacts with the source and drain at room temperature, respectively, without the need for high-temperature processing, thus reducing process difficulty and increasing the process window. On the other hand, a through-hole first opening is formed in the nitrogen-polarized cap layer through wet etching, with at least a portion of the gate located within the first opening. The gate is insulated from the nitrogen-polarized cap layer, making the semiconductor layer act as a self-stopping layer for wet etching of the nitrogen-polarized cap layer. This stabilizes the threshold voltage while increasing transconductance and reducing leakage current, thereby improving device performance.

[0068] Figure 2 This is a schematic diagram of the epitaxial structure of another semiconductor device provided in an embodiment of the present invention, as shown below. Figure 2 As shown, optionally, the semiconductor layer 200 includes: a metal polar surface barrier layer 220 and a channel layer 230 located on the side of the metal polar surface barrier layer 220 near the substrate 100, wherein the metal polar surface barrier layer 220 and the channel layer 230 form a heterojunction structure.

[0069] In this embodiment, the semiconductor layer 200 may include a metal polar surface barrier layer 220 and a channel layer 230. The metal polar surface barrier layer 220 and the channel layer 230 form a heterojunction structure to provide a motion channel for the 2DEG. The channel layer 230 may be a high-resistivity group III nitride material, with a bandgap smaller than that of the metal polar surface barrier layer 220. Its thickness may be 0.01 μm to 10 μm. To achieve high-resistivity characteristics, Fe, Mg, or other elements capable of achieving high material resistance may be used as dopants. The thickness of the metal polar surface barrier layer 220 may be 1 nm to 1 μm.

[0070] When the semiconductor layer 200 includes a metal polar surface barrier layer 220 and a channel layer 230 to form a semiconductor device, when a first opening is formed in the nitrogen polar surface cap layer 210 by wet etching, the first opening can stop precisely on the surface of the metal polar surface barrier layer 220 away from the substrate 100, that is, at the interface between the metal polar surface barrier layer 220 and the nitrogen polar surface cap layer 210. This makes the metal polar surface barrier layer 220 a self-stopping layer for wet etching of the nitrogen polar surface cap layer 210, which can stabilize the threshold voltage while improving transconductance and reducing leakage current, thereby improving device performance.

[0071] Figure 3 This is a schematic diagram of the epitaxial structure of another semiconductor device provided in an embodiment of the present invention, as shown below. Figure 3As shown, based on the above embodiments, optionally, the semiconductor layer 200 may also include a buffer layer 240 located on the side of the channel layer 230 away from the metal polarity barrier layer 220, and a nucleation layer 250 located on the side of the buffer layer 240 away from the channel layer 230.

[0072] The nucleation layer 250 affects parameters such as crystal quality, surface morphology, and electrical properties of other films located above it in the epitaxial structure. The nucleation layer 250 primarily functions to match the substrate material with the semiconductor material layer in the heterojunction structure of the epitaxial structure. The nucleation layer 250 can be AlN, GaN, AlGaN, or any other material capable of growing group III nitrides, and its thickness can be 20 nm.

[0073] The buffer layer 240 can be a single-component material, a component-gradient structure, or a superlattice structure, or other material structures that can relax lattice mismatch and thermal adaptation, and its thickness can be 0.1μm-10μm.

[0074] refer to Figures 1 to 3 Optionally, the nitrogen polar cap layer 210 further includes an n-type doped material; the n-type doped material includes at least one of silicon, germanium, carbon, and oxygen; the doping concentration of the n-type doped material is D, 10 17 / cm 3 ≤D≤10 20 / cm 3 .

[0075] In this embodiment, the nitrogen-polar cap layer 210 can be n-type doped, that is, an n-type doping material, such as one or more of silicon, germanium, carbon, and oxygen, can be introduced to enhance the negative charge of the nitrogen-polar cap layer 210. This allows the nitrogen-polar cap layer 210 to form good ohmic contacts with the source and drain at room temperature during the formation of semiconductor devices, reducing process difficulty, increasing the process window, reducing leakage current, and improving device performance. The doping concentration of the n-type doping material can be 10-1. 17 / cm 3 -10 20 / cm 3 To obtain a strongly negatively charged nitrogen polar cap layer 210, further improving device performance.

[0076] Based on the same inventive concept, embodiments of the present invention provide a semiconductor device. Figure 4 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention, such as... Figure 4As shown, the semiconductor device provided in this embodiment includes: an epitaxial structure and an electrode structure 300; the epitaxial structure includes: a substrate 100; a semiconductor layer 200 located on one side of the substrate 100, the surface of the semiconductor layer 200 away from the substrate 100 being a metal polar surface; a nitrogen polar cap layer 210 located on the side of the semiconductor layer 200 away from the substrate 100, the nitrogen polar cap layer 210 having a first opening 10 that penetrates the nitrogen polar cap layer 210; an electrode structure 300 including a source 310, a gate 320, and a drain 330; the source 310 and the drain 330 are located on the side of the nitrogen polar cap layer 210 away from the substrate 100, and both the source 320 and the drain 330 form an ohmic contact with the nitrogen polar cap layer 210; at least a portion of the gate 320 is located within the first opening 10, and the gate 320 is insulated from the nitrogen polar cap layer 210.

[0077] For example, refer to Figure 4 The semiconductor device provided in this embodiment includes a substrate 100, a semiconductor layer 200, a nitrogen polar cap layer 210, and an electrode structure 300 sequentially disposed therefrom. The electrode structure 300 includes a source 310, a gate 320, and a drain 330. The material of the electrode structure 300 can be metals such as Au, Ag, Cu, Fe, Al, In, Ti, Pt, and Ni, or an alloy composed of any combination thereof.

[0078] The source 310 and drain 330 are located on the side of the nitrogen polar cap layer 210 away from the substrate 100 and are in direct contact with the nitrogen polar cap layer 210. The nitrogen polar cap layer 210 has a strong negative charge and can form good ohmic contacts with the source 310 and drain 330 at room temperature, respectively. No high-temperature treatment is required, which can reduce the process difficulty, increase the process window, reduce the leakage current of the device, and thus improve the device performance.

[0079] A through-hole opening 10 is formed in the nitrogen polar cap layer 210 by wet etching. On the one hand, wet etching causes less damage to the device compared to dry etching. On the other hand, if the first opening 10 is formed by wet etching using an alkaline solution, the alkaline solution can easily etch nitrogen polar group III nitride materials, but cannot etch metal polar group III nitride materials. Therefore, by using a composite polar epitaxial structure formed by a semiconductor layer 200 with a metal polar surface and a nitrogen polar cap layer 210, the first opening can be stopped precisely on the surface of the semiconductor layer 200 away from the substrate, that is, at the interface between the semiconductor layer 200 and the nitrogen polar cap layer 210. This makes the semiconductor layer 200 a self-stopping layer for wet etching of the nitrogen polar cap layer 210, thereby achieving low-damage and highly controllable semiconductor layer RECESS capability and stabilizing the threshold voltage. Furthermore, at least a portion of the gate 320 is located within the first opening 10. Compared to the prior art method that does not etch the epitaxial layer, the gate 320 is closer to the 2DEG in the semiconductor device, which can effectively improve transconductance characteristics, reduce leakage current, and further improve device performance. In addition, to avoid a short circuit caused by direct contact between the strongly negatively charged nitrogen-polarized cap layer 210 and the gate 320, the nitrogen-polarized cap layer 210 and the gate 320 need to be insulated from each other.

[0080] Therefore, by using a composite polar epitaxial structure formed by a semiconductor layer 200 with a metallic polar surface and a nitrogen polar surface cap layer 210, room temperature ohmic contact can be achieved, reducing process difficulty and increasing the process window. The semiconductor layer 200 can serve as a wet etching self-stopping layer for the nitrogen polar surface cap layer 210, enabling low-damage and highly controllable semiconductor layer RECESS function. While stabilizing the threshold voltage, it can also increase transconductance and reduce leakage current, thereby improving device performance.

[0081] The semiconductor device provided in this invention includes a substrate, a semiconductor layer, a nitrogen-polarized cap layer, and an electrode structure arranged sequentially. The electrode structure includes a source, a gate, and a drain. The source and drain are in direct contact with the nitrogen-polarized cap layer, while the gate is insulated from the nitrogen-polarized cap layer. The semiconductor layer with a metallic polar surface and the nitrogen-polarized cap layer form a composite polar epitaxial structure. On the one hand, the nitrogen-polarized cap layer naturally exhibits strong negative charge, allowing it to form good ohmic contacts with the source and drain at room temperature, eliminating the need for high-temperature processing, reducing process difficulty, and increasing the process window. On the other hand, a through-hole first opening is formed in the nitrogen-polarized cap layer through wet etching, with at least a portion of the gate located within the first opening. This allows the semiconductor layer to act as a self-stopping layer for wet etching of the nitrogen-polarized cap layer, stabilizing the threshold voltage while increasing transconductance and reducing leakage current, thereby improving device performance.

[0082] refer to Figure 4Optionally, the semiconductor device also includes a passivation layer 400, at least a portion of which is located within the first opening 10, and the gate 320 is insulated from the nitrogen polar cap layer 210 through the passivation layer 400.

[0083] If the strongly negatively charged nitrogen-based cap layer 210 directly contacts the gate 320, a short circuit will occur. Therefore, a passivation layer 400 is required to separate the nitrogen-based cap layer 210 from the gate 320, providing insulation and ensuring that the nitrogen-based cap layer 210 and the gate 320 do not directly contact each other. Specifically, after forming the first opening 10 in the nitrogen-based cap layer 210, a passivation layer 400 can be formed at least within the first opening 10 using methods such as vapor deposition to insulate the gate 320 located within the first opening 10 from the nitrogen-based cap layer 210. The passivation layer 400 can be SiO2 and / or SiN, or other insulating media capable of passivation, and its thickness can be 0.1 μm to 10 μm.

[0084] It should be noted that when fabricating the passivation layer 400, the passivation layer 400 can be fabricated only within the first opening 10; alternatively, the passivation layer 400 can be fabricated both within the first opening 10 and on the surface of the nitrogen polar cap layer 210 away from the substrate 100 (see reference). Figure 4 For ease of description, the passivation layer 400 is divided into a first passivation portion 410 and a second passivation portion 420. The first passivation portion 410 and the second passivation portion 420 are connected to each other. The first passivation portion 410 is located on the side of the nitrogen polar cap layer 210 away from the substrate 100, and the second passivation portion 420 is located inside the first opening 10. The first passivation portion 410 and the second passivation portion 420 can be formed simultaneously in the same process or can be fabricated separately, without limitation. For example, the second passivation portion 420 can be prepared in the first opening 10 first, and the first passivation portion 410 can be prepared later.

[0085] Furthermore, if the first passivation portion 410 and the second passivation portion 420 are formed simultaneously in the same process, a third opening 30 needs to be provided in the first passivation portion 410, and the third opening 30 penetrates the first passivation portion 410. Then, a source electrode 310 and a drain electrode 330 are provided in the third opening 30 so that both the source electrode 310 and the drain electrode 330 are in direct contact with the nitrogen polar surface cap layer 210. At room temperature, the nitrogen polar surface cap layer 210 forms good ohmic contact with the source electrode 141 and the drain electrode 142, respectively.

[0086] For ease of description, the following will use the example of a passivation layer 400 including a first passivation portion 410 and a second passivation portion 420 that are interconnected, with the first passivation portion 410 located on the side of the nitrogen polar cap layer 210 away from the substrate 100, and the second passivation portion 420 located within the first opening 10, to explain the embodiments of the present invention.

[0087] Figure 5 This is a schematic diagram of another semiconductor device provided in an embodiment of the present invention, such as... Figure 5 As shown, a second opening 20 is provided in the passivation layer 400 located within the first opening 10, and the second opening 20 at least partially penetrates the passivation layer 400; at least a portion of the gate 400 is located within the second opening 20.

[0088] refer to Figure 5 The passivation layer 400 located within the first opening 10 is the second passivation portion 420. A second opening 20 is provided within the second passivation portion 420. The second opening 20 may not penetrate the second passivation portion 420. A portion of the gate 320 is located within the second opening 20. The gate 320 is insulated from the nitrogen polarity cap layer 210 through the second passivation portion 420. Compared to... Figure 4 The passivation layer 400 does not have a second opening 20, and all of the gates 320 are located on the side of the passivation layer 400 away from the substrate 100. This can further shorten the distance between the gates 320 and the 2DEG in the semiconductor device, effectively improve the transconductance characteristics, reduce leakage current, and further improve the device performance.

[0089] Figure 6 This is a schematic diagram of the epitaxial structure of another semiconductor device provided in an embodiment of the present invention, as shown below. Figure 6 As shown, based on the above embodiment, optionally, the second opening 20 penetrates the passivation layer 400; and the second opening 20 stops on the surface of the semiconductor layer 200 away from the substrate 100; the gate 320 is in contact with the semiconductor layer 200.

[0090] In this embodiment, the second opening 20 can penetrate the second passivation portion 420, and the second opening 20 stops on the surface of the semiconductor layer 200 away from the substrate 100. At least a portion of the gate 320 is located within the second opening 20 penetrating the second passivation portion 420, so that the gate 320 can directly contact the semiconductor layer 200. The gate 320 and the semiconductor layer 200 form a Schottky contact. The distance between the gate 320 and the 2DEG in the semiconductor device is smaller, which can effectively improve the transconductance characteristics, reduce leakage current, and further improve the device performance.

[0091] It should be noted that, Figure 5 and Figure 6 The explanation is based on the example of a portion of the gate 320 being located within the second opening 20, and is not intended to be limiting. In other embodiments, the gate 320 may be entirely located within the second opening 20, as long as at least a portion of the gate 320 is located within the first opening 10. Furthermore, Figure 5 and Figure 6 The gate 320 is shown as a trapezoidal structure that is wider at the top and narrower at the bottom, but is not intended to be limiting. In other embodiments, the gate 320 may also be rectangular (see reference). Figure 4Structures such as )

[0092] It is understood that the structure, material, and thickness of each film layer in the epitaxial structure of the semiconductor device provided in the embodiments of the present invention can be referenced to the epitaxial structure provided in any embodiment of the present invention. For example, Figure 7 This is a schematic diagram of another semiconductor device provided in an embodiment of the present invention, as shown below. Figure 7 As shown, in this embodiment, the semiconductor layer 200 of the semiconductor device may include a metal polarity barrier layer 220 and a channel layer 230 located on the side of the metal polarity barrier layer 220 near the substrate 100. The channel layer 230 and the metal polarity barrier layer 220 form a heterojunction structure, providing a motion channel for the 2DEG. Further, the semiconductor layer 200 may also include a buffer layer 240 located on the side of the channel layer 230 away from the metal polarity barrier layer 220, and a nucleation layer 250 located on the side of the buffer layer 240 away from the channel layer 230. The semiconductor device may also include a protective layer 500 for protecting the electrode structure 300. The protective layer 500 may be SiO2, SiN, or other insulating media capable of passivation, with a thickness of 10 nm to 10 μm. Similarly, the nitrogen polarity cap layer 210 may also include at least one n-type doped material selected from silicon, germanium, carbon, and oxygen to enhance its electronegativity.

[0093] This invention also provides a method for fabricating an epitaxial structure of a semiconductor device. This method can fabricate the epitaxial structure provided in any embodiment of this invention. For example, Figure 8 This is a flowchart of a method for fabricating an epitaxial structure of a semiconductor device according to an embodiment of the present invention, such as... Figure 8 As shown, the preparation method includes:

[0094] S110 provides a substrate.

[0095] The substrate preparation method is not limited. For example, the substrate preparation method may be atmospheric pressure chemical vapor deposition, sub-atmospheric pressure chemical vapor deposition, metal-organic compound vapor deposition, low pressure chemical vapor deposition, high-density plasma chemical vapor deposition, ultra-high vacuum chemical vapor deposition, plasma-enhanced chemical vapor deposition, catalytic chemical vapor deposition, hybrid physical-chemical vapor deposition, rapid thermochemical vapor deposition, vapor phase epitaxy, pulsed laser deposition, ion layer epitaxy, molecular beam epitaxy, sputtering, or evaporation.

[0096] S120. A semiconductor layer is prepared on one side of the substrate, and the surface of the semiconductor layer away from the substrate is a metal polar surface.

[0097] S130. A nitrogen polar cap layer is prepared on the side of the semiconductor layer away from the substrate.

[0098] The methods and materials for preparing the semiconductor layer and the nitrogen polar cap layer are not limited, and any method and materials for forming a semiconductor layer with a metal polar surface and a nitrogen polar cap layer are within the protection scope of this invention.

[0099] A semiconductor layer with a metallic polar facet and a nitrogen-polarized cap layer form a composite polar epitaxial structure with different polar faces. During subsequent semiconductor device fabrication, a through-hole opening can be formed in the nitrogen-polarized cap layer using wet etching. This opening stops precisely on the surface of the semiconductor layer away from the substrate, allowing the semiconductor layer to act as a self-stopping layer for wet etching of the nitrogen-polarized cap layer. This achieves low-damage, highly controllable semiconductor layer recurvature capability, and allows part of the gate to be located within the first opening, stabilizing the threshold voltage while improving transconductance.

[0100] The method for fabricating the epitaxial structure of a semiconductor device provided in this invention involves forming a composite polar epitaxial structure consisting of a semiconductor layer with a metallic polar surface and a nitrogen-polarized cap layer. When subsequently forming the semiconductor device, on the one hand, the nitrogen-polarized cap layer naturally exhibits strong negative charge, allowing it to form good ohmic contacts with the source and drain at room temperature, eliminating the need for high-temperature processing, thus reducing process difficulty and increasing the process window. On the other hand, a through-hole first opening is formed in the nitrogen-polarized cap layer through wet etching, with at least a portion of the gate located within the first opening. The gate is insulated from the nitrogen-polarized cap layer, enabling the semiconductor layer to act as a self-stopping layer for wet etching of the nitrogen-polarized cap layer. This stabilizes the threshold voltage while increasing transconductance and reducing leakage current, thereby improving device performance.

[0101] Figure 9 This is a flowchart of another method for fabricating the epitaxial structure of a semiconductor device provided in an embodiment of the present invention, such as... Figure 9 As shown, the preparation method includes:

[0102] S210 provides a substrate.

[0103] S220. Prepare a channel layer on one side of the substrate.

[0104] S230. A metal polar surface barrier layer is prepared on the side of the channel layer away from the substrate, and the metal polar surface barrier layer and the channel layer form a heterojunction structure.

[0105] S240. Prepare a nitrogen polar cap layer on the side of the metal polar barrier layer away from the channel layer.

[0106] In this embodiment, the epitaxial structure includes a substrate, a semiconductor layer with a metallic polar facet, and a nitrogen-polarized cap layer. The semiconductor layer includes a metallic polarized barrier layer and a channel layer. The metallic polarized barrier layer and the channel layer form a heterojunction structure, providing a motion channel for the 2DEG. During subsequent semiconductor device fabrication, a through-hole opening is formed in the nitrogen-polarized cap layer using wet etching. At least a portion of the gate is located within the first opening, allowing the metallic polarized barrier layer to act as a self-stopping layer for wet etching of the nitrogen-polarized cap layer. This stabilizes the threshold voltage while increasing transconductance and reducing leakage current, thereby improving device performance.

[0107] Figure 10 This is a flowchart of another method for fabricating the epitaxial structure of a semiconductor device provided in an embodiment of the present invention, such as... Figure 10 As shown, the preparation method includes:

[0108] S310 provides a substrate.

[0109] S320, A nucleation layer is prepared on one side of the substrate.

[0110] S330. Prepare a buffer layer on the side of the nucleation layer away from the substrate.

[0111] S340. Prepare a channel layer on the side of the buffer layer away from the nucleation layer.

[0112] S350. A metallic polar surface barrier layer is prepared on the side of the channel layer away from the buffer layer, and the metallic polar surface barrier layer and the channel layer form a heterojunction structure.

[0113] S360. Prepare a nitrogen polar cap layer on the side of the metal polar surface barrier layer away from the substrate.

[0114] The epitaxial structure of the semiconductor device provided in this embodiment includes a substrate, a semiconductor layer, and a nitrogen-polarized cap layer sequentially disposed therefrom. The semiconductor layer includes a nucleation layer, a buffer layer, a channel layer, and a metal-polarized barrier layer. The fabrication method of this epitaxial structure involves matching the substrate material and the semiconductor material layer in the heterojunction structure of the semiconductor layer with the nucleation layer and buffer layer; forming a heterojunction structure together with the channel layer and the metal-polarized barrier layer to create a two-dimensional electron gas movement channel; and forming a composite polarized epitaxial structure with the semiconductor layer having a metal polarized surface and the nitrogen-polarized cap layer. When subsequently forming the semiconductor device, on the one hand, the strongly negatively charged nitrogen-polarized cap layer can form good ohmic contacts with the source and drain at room temperature, respectively, without the need for high-temperature processing, thus reducing process difficulty and increasing the process window; on the other hand, a through-hole first opening is formed in the nitrogen-polarized cap layer through wet etching, with at least a portion of the gate located within the first opening. This allows the metal-polarized barrier layer to act as a self-stopping layer for wet etching of the nitrogen-polarized cap layer, stabilizing the threshold voltage while increasing transconductance and reducing leakage current, thereby improving device performance.

[0115] Based on the same inventive concept, embodiments of the present invention also provide a method for fabricating a semiconductor device, used to fabricate the semiconductor device provided in any embodiment of the present invention. For example, Figure 11 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention, such as... Figure 11 As shown, the preparation method includes:

[0116] S410 provides a substrate.

[0117] S420. A semiconductor layer is prepared on one side of the substrate, and the surface of the semiconductor layer away from the substrate is a metal polar surface.

[0118] S430. A nitrogen polar cap layer is prepared on the side of the semiconductor layer away from the substrate, and a first opening is formed in the nitrogen polar cap layer, the first opening penetrating the nitrogen polar cap layer.

[0119] S440. A source and a drain are fabricated on the side of the nitrogen-polar cap layer away from the substrate, and both the source and the drain form an ohmic contact with the nitrogen-polar cap layer; a gate is fabricated at least within the first opening, and the gate is insulated from the nitrogen-polar cap layer; the source, the gate, and the drain constitute an electrode structure.

[0120] The semiconductor device fabrication method provided in this invention forms a composite polar epitaxial structure consisting of a semiconductor layer with a metallic polar surface and a nitrogen-polarized cap layer. On the one hand, the nitrogen-polarized cap layer naturally exhibits strong negative charge, allowing it to form good ohmic contacts with the source and drain at room temperature, eliminating the need for high-temperature processing, thus reducing process difficulty and increasing the process window. On the other hand, a through-hole first opening is formed in the nitrogen-polarized cap layer through wet etching, with at least a portion of the gate located within the first opening. This allows the semiconductor layer to act as a self-stopping layer for wet etching of the nitrogen-polarized cap layer, stabilizing the threshold voltage while increasing transconductance and reducing leakage current, thereby improving device performance.

[0121] Optional, Figure 12 This is a flowchart of another method for fabricating a semiconductor device provided in an embodiment of the present invention, such as... Figure 12 As shown, the preparation method includes:

[0122] S510 provides a substrate.

[0123] S520. A semiconductor layer is prepared on one side of the substrate, and the surface of the semiconductor layer away from the substrate is a metal polar surface.

[0124] S530. A nitrogen polar cap layer is prepared on the side of the semiconductor layer away from the substrate, and a first opening is formed in the nitrogen polar cap layer, the first opening penetrating the nitrogen polar cap layer.

[0125] S540, a passivation layer is prepared at least within the first opening.

[0126] By preparing a passivation layer, the gate can be insulated from the nitrogen polarity cap layer with strong negative charge, thus preventing short circuits.

[0127] S550, A gate is formed at least within the first opening, and the gate is insulated from the nitrogen polarity cap layer by a passivation layer.

[0128] S560. A source and a drain are fabricated on the side of the nitrogen polar cap layer away from the substrate, and both the source and the drain form an ohmic contact with the nitrogen polar cap layer.

[0129] Optional, Figure 13 This is a flowchart of another method for fabricating a semiconductor device provided in an embodiment of the present invention, such as... Figure 13 As shown, the preparation method includes:

[0130] S610 provides a substrate.

[0131] S620. A semiconductor layer is prepared on one side of the substrate, and the surface of the semiconductor layer away from the substrate is a metal polar surface.

[0132] S630. A nitrogen polar cap layer is prepared on the side of the semiconductor layer away from the substrate, and a first opening is formed in the nitrogen polar cap layer, the first opening penetrating the nitrogen polar cap layer.

[0133] S640, a passivation layer is prepared at least within the first opening.

[0134] S650, A second opening is formed in the passivation layer located within the first opening, the second opening at least partially penetrating the passivation layer.

[0135] S660, A gate is fabricated at least within the second opening, and the gate is insulated from the nitrogen polarity cap layer by a passivation layer.

[0136] S670. A source and a drain are fabricated on the side of the nitrogen polar cap layer away from the substrate, and both the source and the drain form an ohmic contact with the nitrogen polar cap layer.

[0137] The semiconductor device fabrication method provided in this embodiment, by setting a second opening in the passivation layer located within the first opening, with at least a portion of the gate located within the second opening, can further shorten the distance between the gate and the 2DEG in the semiconductor device, thereby effectively improving transconductance characteristics, reducing leakage current, and improving device performance.

[0138] Optional, Figure 14 This is a flowchart of another method for fabricating a semiconductor device provided in an embodiment of the present invention, as shown below. Figure 14 As shown, the preparation method includes:

[0139] S701, provides a substrate.

[0140] S702, A nucleation layer is prepared on one side of the substrate.

[0141] S703. Prepare a buffer layer on the side of the nucleation layer away from the substrate.

[0142] S704. Prepare a channel layer on the side of the buffer layer away from the nucleation layer.

[0143] S705. A metallic polar surface barrier layer is prepared on the side of the channel layer away from the buffer layer, and the metallic polar surface barrier layer and the channel layer form a heterojunction structure.

[0144] S706. A nitrogen polar facet layer is prepared on the side of the metal polar facet barrier layer away from the channel layer, and a first opening is formed in the nitrogen polar facet layer, the first opening penetrating the nitrogen polar facet layer.

[0145] S707, A passivation layer is prepared at least within the first opening.

[0146] S708. A second opening is formed in the passivation layer located within the first opening, the second opening at least partially penetrating the passivation layer.

[0147] S709. A gate is formed at least within the second opening, and the gate is insulated from the nitrogen polarity cap layer by a passivation layer.

[0148] S710. A source and a drain are fabricated on the side of the nitrogen polar cap layer away from the metal polar barrier layer, and both the source and the drain form an ohmic contact with the nitrogen polar cap layer.

[0149] S711, Prepare the protective layer.

[0150] The semiconductor device provided in this embodiment includes a substrate, a semiconductor layer, a nitrogen polar cap layer, a passivation layer, an electrode structure, and a protective layer arranged sequentially. The semiconductor layer includes a nucleation layer, a buffer layer, a channel layer, and a metal polar barrier layer. The electrode structure includes a gate, a source, and a drain. The method for fabricating this semiconductor device involves matching the substrate material and the semiconductor material layer in the heterojunction structure within the semiconductor layer using a nucleation layer and a buffer layer; forming a heterojunction structure together with a channel layer and a metal polar surface barrier layer to create a two-dimensional electron gas movement channel; and forming a composite polar epitaxial structure with a semiconductor layer having a metal polar surface and a nitrogen polar surface cap layer. On one hand, the nitrogen polar surface cap layer, which has strong negative charge, can form good ohmic contacts with the source and drain at room temperature, respectively, without the need for high-temperature processing, thus reducing the difficulty of the process and increasing the process window. On the other hand, a through-hole first opening is formed in the nitrogen polar surface cap layer through wet etching, with at least part of the gate located within the first opening. This allows the metal polar surface barrier layer to act as a self-stopping layer for wet etching of the nitrogen polar surface cap layer, stabilizing the threshold voltage while increasing transconductance and reducing leakage current, thereby improving device performance.

[0151] Based on the above embodiments, optionally, a first opening is formed in the nitrogen polar cap layer, including:

[0152] An alkaline solution is used to etch the nitrogen polar cap layer, forming a first opening in the nitrogen polar cap layer, which penetrates the nitrogen polar cap layer.

[0153] In this embodiment, an alkaline solution such as potassium hydroxide can be used to etch the nitrogen polar cap layer, thereby forming a through-hole first opening in the nitrogen polar cap layer. On the one hand, compared with dry etching, wet etching causes less damage to the device; on the other hand, alkaline solutions can easily etch nitrogen polar group III nitride materials, but cannot etch metal polar group III nitride materials. Therefore, by using a composite polar epitaxial structure formed by a semiconductor layer with a metal polar surface and a nitrogen polar cap, the semiconductor layer can act as a wet etching self-stopping layer for the nitrogen polar cap layer, thereby achieving low-damage and highly controllable semiconductor layer RECESS capability, stabilizing the threshold voltage, and improving the transconductance characteristics of the device.

[0154] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, combinations, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A semiconductor device, characterized in that, include: Epitaxial structure and electrode structure; The epitaxial structure includes: Substrate; A semiconductor layer is located on one side of the substrate, and the surface of the semiconductor layer on the side away from the substrate is a metallic polar surface; A nitrogen-polar cap layer is located on the side of the semiconductor layer away from the substrate, and a first opening is provided in the nitrogen-polar cap layer, the first opening penetrating the nitrogen-polar cap layer; The electrode structure includes a source, a gate, and a drain; the source and the drain are located on the side of the nitrogen polar cap layer away from the substrate, and both the source and the drain form an ohmic contact with the nitrogen polar cap layer using the strong negative charge of the nitrogen polar cap layer; at least a portion of the gate is located within the first opening, and the gate is insulated from the nitrogen polar cap layer; The nitrogen polar cap layer and the semiconductor layer form a composite polar epitaxial structure.

2. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes a passivation layer, at least a portion of which is located within the first opening, and the gate is insulated from the nitrogen polar cap layer through the passivation layer.

3. The semiconductor device according to claim 2, characterized in that, A second opening is provided in the passivation layer located within the first opening, and the second opening at least partially penetrates the passivation layer; At least a portion of the gate is located within the second opening.

4. The semiconductor device according to claim 3, characterized in that, The second opening penetrates the passivation layer and stops at the surface of the semiconductor layer away from the substrate; The gate is in contact with the semiconductor layer.

5. A method for fabricating a semiconductor device, used to fabricate the semiconductor device as described in any one of claims 1-4, characterized in that, include: Provide substrate; A semiconductor layer is fabricated on one side of the substrate, and the surface of the semiconductor layer on the side away from the substrate is a metallic polar surface; A nitrogen polar cap layer is prepared on the side of the semiconductor layer away from the substrate, and a first opening is formed in the nitrogen polar cap layer, the first opening penetrating the nitrogen polar cap layer; A source and a drain are fabricated on the side of the nitrogen polar cap layer away from the substrate, and both the source and the drain form an ohmic contact with the nitrogen polar cap layer. A gate electrode is formed within at least the first opening, the gate electrode being insulated from the nitrogen polar cap layer; the source electrode, the gate electrode, and the drain electrode constitute an electrode structure.

6. The preparation method according to claim 5, characterized in that, The preparation method further includes: A passivation layer is formed at least within the first opening, and the gate is insulated from the nitrogen polar cap layer through the passivation layer.

7. The preparation method according to claim 6, characterized in that, The preparation method further includes: A second opening is formed in a passivation layer located within the first opening, the second opening at least partially penetrating the passivation layer; The gate is fabricated at least within the second opening.

8. The preparation method according to claim 5, characterized in that, The formation of the first opening in the nitrogen polar cap layer includes: The nitrogen polar cap layer is etched with an alkaline solution to form a first opening in the nitrogen polar cap layer, the first opening penetrating the nitrogen polar cap layer.

Images