Ramp signal voltage boosting circuit, ramp generation circuit, and image sensor

Abstract

The application provides a ramp signal voltage lifting circuit applied to a ramp generation circuit, the ramp generation circuit comprising a ramp signal generation branch, a mirror unit and a compensation branch, the mirror unit being used for mirroring a ramp signal reference current of the ramp signal generation branch to generate a compensation reference current, the compensation branch being connected with the mirror unit and used for mirroring the compensation reference current to generate at least one compensation current, so as to pull up the level of a ramp signal output by the ramp signal generation branch through the compensation current, and through the pulling up of the level of the ramp signal, the compensation of dark current in an image sensor can be realized, so as to reduce the influence of the dark current in the image sensor. The application further provides a ramp generation circuit and an image sensor.

Description

Technical Field

[0001] This invention relates to the field of image sensor technology, and in particular to a ramp signal voltage boosting circuit, a ramp generation circuit, and an image sensor. Background Technology

[0002] Dark current noise severely impacts the image quality of CMOS image sensors (CIS). Its effects on CIS imaging quality are primarily twofold: First, the non-uniformity of dark current is a significant source of fixed-mode noise in CIS, degrading its transparency. Second, dark current inflates the average data value of the entire image, especially under high-temperature conditions, where it increases significantly. Traditional digital domain dark correction methods are insufficient to effectively reduce dark current noise, drastically reducing the image's dynamic range and severely impacting image quality.

[0003] Therefore, it is necessary to provide a novel ramp signal voltage boosting circuit, ramp generation circuit, and image sensor to solve the aforementioned problems existing in the prior art. Summary of the Invention

[0004] The purpose of this invention is to provide a ramp signal voltage boosting circuit, a ramp generation circuit, and an image sensor to reduce the influence of dark current.

[0005] To achieve the above objectives, the ramp signal voltage boosting circuit of the present invention is applied to a ramp generation circuit, the ramp generation circuit including a ramp signal generation branch, comprising:

[0006] A mirroring unit is used to mirror the ramp signal reference current of the ramp signal generating branch, thereby generating a compensation reference current; and

[0007] The compensation branch, connected to the mirror unit, is used to mirror the compensation reference current and generate at least one compensation current to raise the level of the ramp signal output by the ramp signal generation branch through the compensation current.

[0008] The beneficial effect of the ramp signal voltage boosting circuit is that: the mirror unit is used to mirror the ramp signal reference current of the ramp signal generating branch to generate a compensation reference current. The compensation branch is connected to the mirror unit and is used to mirror the compensation reference current to generate at least one compensation current. The compensation current is used to raise the level of the ramp signal output by the ramp signal generating branch. By raising the level of the ramp signal, the dark current in the image sensor can be compensated to reduce the influence of the dark current in the image sensor.

[0009] Optionally, the compensation branch includes a first group of PMOS transistors and at least one first mirror selection unit. The source of the first group of PMOS transistors is connected to the power supply voltage, and the drain of the first group of PMOS transistors is connected to the gate of the first group of PMOS transistors and the mirror unit. All the first mirror selection units are connected to the gate of the first group of PMOS transistors. The first mirror selection unit is used to selectively conduct in order to form a current mirror with the first group of PMOS transistors, mirroring the current flowing through the first group of PMOS transistors to generate the compensation current.

[0010] Optionally, the first mirror gating unit includes a second group of PMOS transistors and a first gating switch. The source of the second group of PMOS transistors is connected to the power supply voltage, the gate of the second group of PMOS transistors is connected to the gate of the first group of PMOS transistors, the drain of the second group of PMOS transistors is connected to one end of the first gating switch, and the other end of the first gating switch is used to output the compensation current.

[0011] Optionally, the width-to-length ratio of the second group of PMOS transistors is increased proportionally.

[0012] Optionally, the mirror unit includes a third group of PMOS transistors and a current mirror circuit. The source of the third group of PMOS transistors is connected to the power supply voltage, the gate of the third group of PMOS transistors is connected to the ramp signal generation branch, the drain of the third group of PMOS transistors is connected to the first branch of the current mirror circuit, and the drain of the first group of PMOS transistors is connected to the second branch of the current mirror circuit.

[0013] Optionally, the current mirror circuit includes a first NMOS transistor and a second NMOS transistor. The drain of the first NMOS transistor is connected to the gate of the first NMOS transistor, the drain of the third group of PMOS transistors, and the gate of the second NMOS transistor. The drain of the second NMOS transistor is connected to the drain of the first group of PMOS transistors. The sources of the first NMOS transistor and the second NMOS transistor are both grounded.

[0014] Optionally, the ratio of the width-to-length ratio of the first NMOS transistor to the width-to-length ratio of the second NMOS transistor is 1:1.

[0015] The present invention also provides a ramp generating circuit, comprising:

[0016] The ramp signal generation branch is used to generate and output the ramp signal; and

[0017] The ramp signal voltage boosting circuit.

[0018] The beneficial effect of the slope generation circuit is that it includes a slope signal voltage boosting circuit, which can increase the level of the slope signal to compensate for the dark current in the image sensor, thereby reducing the influence of the dark current in the image sensor.

[0019] Optionally, the ramp signal generation branch includes an amplifier, an adjustable resistor unit, a terminating resistor, a fourth group of PMOS transistors, and at least two second mirror gating units. The non-inverting input of the amplifier is connected to a reference voltage, the inverting input of the amplifier is connected to the drain of the fourth group of PMOS transistors and the adjustable resistor unit, and the output of the amplifier is connected to the gate of the fourth group of PMOS transistors. The adjustable resistor unit is used to adjust the resistance between the drain of the fourth group of PMOS transistors and ground. Each of the second mirror gating units is connected to the gate of the fourth group of PMOS transistors and one end of the terminating resistor, and the other end of the terminating resistor is grounded. The second mirror gating units are used for selective conduction to form a current mirror with the fourth group of PMOS transistors, mirroring the current flowing through the fourth group of PMOS transistors to generate a ramp signal current, thereby generating a ramp signal.

[0020] Optionally, the second mirror gating unit includes a fifth group of PMOS transistors and a second gating switch. The source of the fifth group of PMOS transistors is connected to the power supply voltage, the gate of the fifth group of PMOS transistors is connected to the output terminal of the amplifier, the drain of the fifth group of PMOS transistors is connected to one end of the second gating switch, and the other end of the second gating switch is connected to one end of the terminating resistor.

[0021] Optionally, the width-to-length ratio of the fifth group of PMOS transistors is increased proportionally.

[0022] Optionally, the adjustable resistor unit includes m resistors and n third select switches, where m is a natural number greater than or equal to 2, n is a natural number greater than or equal to 1, and mn = 1. The m resistors are connected in series between the drain of the fourth group of PMOS transistors and ground. The connection point between two resistors is the select switch connection point. The select switch connection point is connected to one end of each of the n third select switches. The other ends of the n third select switches are all grounded.

[0023] The present invention also provides an image sensor, comprising:

[0024] Pixel array unit, used to output pixel signals after light sensing;

[0025] A row selection decoding driver unit is connected to the pixel array unit and is used to drive the pixel array unit;

[0026] The ramp generating circuit;

[0027] A readout circuit, connected to the pixel array unit and the ramp generation circuit, is used to convert the pixel signal into a digital signal;

[0028] An output signal processing unit is connected to the readout circuit to convert the digital signal into an image and output it.

[0029] The timing control unit is connected to the decoding drive unit, the ramp generation circuit, the readout circuit, and the output signal processing unit, and is used to send clock signals to the decoding drive unit, the ramp generation circuit, the readout circuit, and the output signal processing unit.

[0030] The beneficial effect of the image sensor is that it includes a ramp generation circuit, which can compensate for the dark current in the image sensor by raising the level of the ramp signal, thereby reducing the influence of the dark current in the image sensor. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of the image sensor structure in some embodiments of the present invention;

[0032] Figure 2 This is a circuit diagram of a pixel unit in some embodiments of the present invention;

[0033] Figure 3 This is a timing diagram of pixel units in some embodiments of the present invention;

[0034] Figure 4 This is a circuit diagram of a ramp generation circuit in the prior art;

[0035] Figure 5 This is a circuit diagram of a ramp signal voltage boosting circuit applied to a ramp generation circuit in some embodiments of the present invention;

[0036] Figure 6 This is a timing diagram illustrating the generation principle of the ramp signal in some embodiments of the present invention;

[0037] Figure 7 This is a schematic diagram of the ramp signal in some embodiments of the present invention. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without inventive effort are within the scope of protection of this invention. Unless otherwise defined, the technical or scientific terms used herein should have the ordinary meaning understood by those skilled in the art. The terms "comprising" and similar expressions used herein mean that the element or object preceding the word covers the element or object listed following the word and its equivalents, but do not exclude other elements or objects.

[0039] To address the problems existing in the prior art, embodiments of the present invention provide an image sensor. (Refer to...) Figure 1 The image sensor 100 includes a pixel array unit 101, a readout circuit 102, a decoding drive unit 103, a ramp generation circuit 104, an output signal processing unit 105, and a timing control unit 106.

[0040] Reference Figure 1 The pixel array unit 101 is used to output pixel signals after photosensitization; the row selection decoding driving unit 103 is connected to the pixel array unit 101 and is used to drive the pixel array unit 101; the ramp generating circuit 104 is used to generate ramp signals; the readout circuit 102 is connected to the pixel array unit 101 and the ramp generating circuit 104 and is used to convert the pixel signals into digital signals; the output signal processing unit 105 is connected to the readout circuit 102 to convert the digital signals into images and output them; the timing control unit 106 is connected to the decoding driving unit 103, the ramp generating circuit 104, the readout circuit 102 and the output signal processing unit 105, and is used to send clock signals to the decoding driving unit 103, the ramp generating circuit 104, the readout circuit 102 and the output signal processing unit. The pixel array unit 101 includes at least one pixel unit 1011. The decoding driver unit 103, the output signal processing unit 105, and the timing control unit 106 are all well-known technologies in the art, and will not be described in detail here.

[0041] Figure 2 Circuit diagrams of pixel units in some embodiments of the present invention. (Refer to...) Figure 2The pixel unit 1011 includes a reset transistor Mrst, an amplifying transistor Msf, a transmission transistor Mtg, a gating transistor Msel, and a photodiode PD. The drain of the reset transistor Mrst is connected to the power supply voltage VDD, and the source of the reset transistor Mrst is connected to the gate of the amplifying transistor Msf and the drain of the transmission transistor Mtg. The gate of the reset transistor Mrst is used to receive a reset control signal RX. The source of the transmission transistor Mtg is connected to the negative terminal of the photodiode PD, and the gate of the transmission transistor Mtg is used to receive a transmission control signal TX. The positive terminal of the photodiode PD is grounded. The drain of the amplifying transistor Msf is connected to the power supply voltage VDD, and the source of the amplifying transistor Msf is connected to the drain of the gating transistor Msel. The gate of the gating transistor Msel is used to receive a gating control signal SEL, and the source of the gating transistor Msel is connected to the readout circuit 102 to send the pixel signal to the readout circuit 102.

[0042] Reference Figure 2 The reset transistor Mrst, the amplification transistor Msf, the transmission transistor Mtg, and the gate transistor Msel are all NMOS transistors.

[0043] Reference Figure 2 The drain of the transmission transistor Mtg is connected to one end of the first connection line 10111, the gate of the transmission transistor Msf is connected to the other end of the first connection line 10111, the source of the reset transistor Mrst is connected to one end of the second connection line 10112, the other end of the second connection line 10112 is connected to the first connection line 10111, and the connection point between the second connection line 10112 and the first connection line 10111 is the floating diffusion region FD.

[0044] Figure 3 This is a timing diagram of pixel units in some embodiments of the present invention. (Refer to...) Figure 2 and Figure 3 Rst represents the reset phase of the pixel unit 1011, Exp represents the exposure phase of the pixel unit 1011, Read represents the signal reading phase of the pixel unit 1011, SEL represents the gating control signal applied to the gate of the gating transistor Msel, RX represents the reset control signal applied to the gate of the reset transistor Mrst, and TX represents the transmission control signal applied to the gate of the transmission transistor Mtg.

[0045] Reference Figure 2 and Figure 3When the pixel unit 1011 is in the reset phase, the gating control signal SEL remains low, the reset control signal RX remains high, and the transmission control signal TX changes from high to low. When both the reset control signal RX and the transmission control signal TX are high, both the reset transistor Mrst and the transmission transistor Mtg are turned on, and the potential of the floating diffusion region FD is pulled high to the power supply voltage VDD to complete the reset.

[0046] Reference Figure 2 and Figure 3 After both the reset control signal RX and the transmission control signal TX change from high to low, the pixel unit 1011 enters the exposure stage from the reset stage. The gating control signal SEL remains low, the reset control signal RX remains low, and the transmission control signal TX remains low. When both the reset control signal RX and the transmission control signal TX are low, the reset transistor Mrst and the transmission transistor Mtg are both turned off, and the photodiode PD senses light and generates photoelectrons proportional to the light intensity.

[0047] Reference Figure 2 and Figure 3 After the selection control signal SEL changes from low to high, the selection transistor Msel is turned on, and the pixel unit 1011 enters the signal reading stage from the exposure stage. The reset control signal RX first changes from low to high to reset the floating diffusion region FD. At this time, the amplification transistor Msf is controlled by the potential of the floating diffusion region FD, and the source of the selection transistor Msel outputs the first reset potential. Then, the reset control signal RX changes from high to low. The transmission control signal TX changes from low to high, and the photoelectrons in the photodiode PD are transferred to the floating diffusion region FD. At this time, the amplification transistor Msf is controlled by the potential of the floating diffusion region FD, and the source of the selection transistor Msel outputs the second reset potential. Then, the transmission control signal TX changes from high to low.

[0048] In some embodiments, the readout circuit includes at least one readout unit, which includes a comparator and a counter. The counter is connected to the output of the comparator and is used to count the output signal of the comparator to output a digital signal.

[0049] Figure 4 This is a circuit diagram of a ramp generation circuit in the prior art. Figure 5 This is a circuit diagram of a ramp signal voltage boosting circuit in some embodiments of the present invention. (Refer to...) Figure 4 The ramp generation circuit includes a ramp signal generation branch 1041, used to generate and output a ramp signal. Figure 4 Based on the ramp generating circuit shown, the ramp generating circuit described in this application further includes, as well as... Figure 5 The ramp signal voltage boosting circuit 1042 shown is illustrated.

[0050] Reference Figure 4 The ramp signal generating branch 1041 includes an amplifier AMP, an adjustable resistor unit 10411, a terminating resistor 10412, a fourth group of PMOS transistors PL, and at least two second mirror gating units 10413, for example, N+1 second mirror gating units 10413, where N is an integer greater than or equal to 1. The non-inverting input terminal of the amplifier AMP is connected to a reference voltage, and the voltage value of the reference voltage is V. REF The inverting input terminal of the amplifier AMP is connected to the drain of the fourth PMOS transistor PL and the adjustable resistor unit 10411. The output terminal of the amplifier AMP is connected to the gate of the fourth PMOS transistor PL. The adjustable resistor unit 10411 is used to adjust the resistance between the drain of the fourth PMOS transistor PL and ground. The second mirror gating unit 10413 is connected to the gate of the fourth PMOS transistor PL and one end of the terminating resistor 10412. The other end of the terminating resistor 10412 is grounded. The second mirror gating unit 10413 is used to selectively conduct in order to form a current mirror with the fourth PMOS transistor PL, mirroring the current flowing through the fourth PMOS transistor PL to generate a ramp signal current, thereby generating a ramp signal.

[0051] Reference Figure 4 The second mirror gating unit 10413 includes a fifth group of PMOS transistors and a second gating switch. The source of the fifth group of PMOS transistors is connected to the power supply voltage, the gate of the fifth group of PMOS transistors is connected to the output terminal of the amplifier AMP, the drain of the fifth group of PMOS transistors is connected to one end of the second gating switch, and the other end of the second gating switch is connected to one end of the terminating resistor 10412. Then, the N+1 fifth group of PMOS transistors are P0, P1, ..., PN, and the N+1 second gating switches are K0, K1, ..., KN.

[0052] In some embodiments, the width-to-length ratio of the fifth group of PMOS transistors is increased proportionally.

[0053] Reference Figure 4 The M-factor of the fourth group of PMOS transistors PL is 2. L That is, the first group of PMOS transistors PS1 includes 2 L A series of PMOS transistors connected in parallel, wherein the M-factor of the first of the fifth group of PMOS transistors is 2. 0 The M-factor of the second group of PMOS transistors in the fifth group is 2.1 And so on, the M factor of the (N+1)th PMOS transistor in the fifth group is 2. N That is, the first of the fifth group of PMOS transistors includes 2 0 The second of the fifth group of PMOS transistors consists of 2 parallel PMOS transistors. 1 A series of parallel PMOS transistors, and so on, with the (N+1)th PMOS transistor in the fifth group comprising 2... N A group of PMOS transistors connected in parallel, wherein the ratio of the width-to-length ratio of the fourth group of PMOS transistors PS1 to the width-to-length ratios of P0, P1, ..., PN is 2. L :2 0 :2 1 :····:2 N .

[0054] In some embodiments, the adjustable resistor unit 10411 includes m resistors and n third select switches, where m is a natural number greater than or equal to 2, n is a natural number greater than or equal to 1, and mn = 1. The m resistors are connected in series between the drain of the fourth group of PMOS transistors PL and ground. The connection point between two resistors is the select switch connection point. The select switch connection point is connected to one end of each of the n third select switches, and the other end of each of the n third select switches is grounded.

[0055] Reference Figure 4 The adjustable resistor unit 10411 includes four resistors and three third selector switches. The four resistors are a first resistor 104111, a second resistor 104112, a third resistor 104113, and a fourth resistor 104114. The three third selector switches are G0, G1, and G2. One end of the first resistor 104111 is connected to the drain of the fourth PMOS transistor PL. The other end of the first resistor 104111 is connected to one end of the second resistor 104112 and one end of G0. The other end of the second resistor 104112 is connected to one end of the third resistor 104113 and one end of G1. The other end of the third resistor 104113 is connected to one end of the fourth resistor 104114 and one end of G2. The other end of the fourth resistor 104114 is grounded. The other ends of G0, G1, and G2 are all grounded.

[0056] Reference Figure 4The resistance value of the first resistor 104111 is R, the resistance value of the second resistor 104112 is R, the resistance value of the third resistor 104113 is 2R, and the resistance value of the fourth resistor 104114 is 4R. That is, the ratio of the resistance values ​​of the first resistor 104111, the second resistor 104112, the third resistor 104113, and the fourth resistor 104114 is 1:1:2:4.

[0057] Reference Figure 4 The magnitude of the current flowing through the terminating resistor 10412 is I. Z This refers to the ramp current, where the magnitude of the current flowing through P0 is I0, the magnitude of the current flowing through P1 is I1, ..., and the magnitude of the current flowing through PN is I... N , then I Z =I0+I1+·····+I N Then the voltage value of the ramp signal RAMP generated by the ramp signal generating branch 1041 is V. RAMP The resistance value of the endpoint resistor is R. Z V RAMP =R Z ×I Z .

[0058] Reference Figure 4 The magnitude of the current flowing through the fourth PMOS transistor PL is I. R When K0 is turned on, P0 and the fourth PMOS transistor PL form a current mirror. When K0 is off, I0 = 0; when K1 is on, P1 and the fourth PMOS transistor PL form a current mirror. When K1 is off, I1 = 0; when KN is on, PN and the fourth PMOS transistor PL form a current mirror. When KN is turned off, I N =0.

[0059] Reference Figure 4 G0, G1, and G2 control the slope of the ramp signal. When G0 is on and G1 and G2 are off, the effective resistance value of the adjustable resistor unit 10411 is R, then I R =V REF / R corresponds to the slope of 1 times the readout unit gain; when G1 is on and G0 and G2 are off, the effective resistance value of the adjustable resistor unit 10411 is 2R, then I R =V REF / 2R corresponds to a slope of twice the readout unit gain; when G2 is on and G0 and G1 are off, the effective resistance value of the adjustable resistor unit 10411 is 4R, then I R =VREF / 4R corresponds to a slope of 4 times the readout unit gain; when G0, G1, and G2 are all off, the effective resistance value of the adjustable resistor unit 10411 is 8R, then I R =V REF / 8R corresponds to the slope of the readout unit gain multiplied by 8. Due to different gains, I... R They are not the same, so the initial potential of the ramp signal corresponding to different gains is different. The smaller the gain, the lower the initial potential of I. R The larger I is Z The larger the value, the higher the initial potential; the greater the gain, the higher the I. R The smaller, I Z The smaller the value, the lower the initial potential.

[0060] Figure 6 This is a timing diagram illustrating the generation principle of the ramp signal in some embodiments of the present invention. (Refer to...) Figure 4 and Figure 6 RAMP1 represents the ramp signal corresponding to 1x readout unit gain; RAMP2 represents the ramp signal corresponding to 2x readout unit gain.

[0061] Reference Figure 4 and Figure 6 In the initial state, all the second selection switches are turned on, then according to I can be converted Z =(2 0 +2 1 +2 N )×I0,I1=2 1 ×I0,I N =2 N ×I0, the initial potential of the ramp signal is maintained at V RAMP .

[0062] Reference Figure 4 and Figure 6 Under the control of clock CLK_R, within each clock cycle Ts, K0, K1, ..., up to KN are sequentially turned off and then on, resulting in a stepped ramp signal. Specifically, within the first clock cycle Ts, only K0 is turned off, and the current I flowing through the terminating resistor 10412... Z This will reduce I0; during the second clock cycle Ts, only K1 is turned off, and the current I flowing through the terminating resistor 10412 will decrease. Z This will reduce I0 by 2×; and so on, during the (N+1)th clock cycle Ts, only KN is turned off, and the current I flowing through the terminating resistor 10412 will be reduced. Z Will reduce 2 N×I0. In practical applications, the frequency of the clock CLK_R is very high, and the clock period Ts is very short. Therefore, the ramp signal can be approximated as a straight line.

[0063] Reference Figure 4 and Figure 5 The ramp signal voltage boosting circuit 1042 includes a mirror unit and a compensation branch. The mirror unit is used to mirror the ramp signal reference current of the ramp signal generating branch 1041 to generate a compensation reference current. The compensation branch is connected to the mirror unit and is used to mirror the compensation reference current to generate at least one compensation current, so as to raise the level of the ramp signal output by the ramp signal generating branch 1041 through the compensation current.

[0064] Reference Figure 5 The compensation branch includes a first group of PMOS transistors PS1 and at least one first mirror gating unit 10421, for example, K+1 first mirror gating units 10421, where K is an integer greater than or equal to 0. The source of the first group of PMOS transistors PS1 is connected to the power supply voltage, and the drain of the first group of PMOS transistors PS1 is connected to the gate of the first group of PMOS transistors PS1 and the mirror unit. All first mirror gating units 10421 are connected to the gate of the first group of PMOS transistors PS1. The first mirror gating unit 10421 is used for selective conduction to form a current mirror with the first group of PMOS transistors PS1, mirroring the current flowing through the first group of PMOS transistors PS1 to generate the compensation current.

[0065] Reference Figure 4 and Figure 5 The first mirror gating unit 10421 includes a second group of PMOS transistors and a first gating switch. The source of the second group of PMOS transistors is connected to the power supply voltage, the gate of the second group of PMOS transistors is connected to the gate of the first group of PMOS transistors PS1, and the drain of the second group of PMOS transistors is connected to one end of the first gating switch. The other end of the first gating switch is used to output the compensation current. Specifically, the other end of all the first gating switches is connected to one end of the terminating resistor 10412. Then, the K+1 second group of PMOS transistors are PA0, PA1, ..., PAK, and the K+1 first gating switches are S0, S1, ..., SK.

[0066] In some embodiments, the width-to-length ratio of the second group of PMOS transistors is increased proportionally.

[0067] Reference Figure 5 The M-factor of the first group of PMOS transistors PS1 is 2. J That is, the first group of PMOS transistors PS1 includes 2 JA series of PMOS transistors connected in parallel, with the M-factor of the first and second group of PMOS transistors being 2. 0 The M-factor of the second PMOS transistor in the second group is 2. 1 And so on, the M-factor of the (K+1)th PMOS transistor in the second group is 2. K That is, the first of the second group of PMOS transistors includes 2 0 The second group of PMOS transistors consists of two parallel PMOS transistors. 1 A series of parallel PMOS transistors, and so on, with the (K+1)th PMOS transistor in the second group consisting of 2... 2 A set of PMOS transistors connected in parallel, wherein the ratio of the width-to-length ratio of PS1 to the width-to-length ratios of PA0, PA1, ..., PAK is 2. J :2 0 :2 1 :····:2 K .

[0068] Reference Figure 4 and Figure 5 The mirror unit includes a third group of PMOS transistors (PS0) and a current mirror circuit. The source of the third group of PMOS transistors (PS0) is connected to the power supply voltage. The gate of the third group of PMOS transistors (PS0) is connected to the ramp signal generation branch 1041. The drain of the third group of PMOS transistors (PS0) is connected to the first branch of the current mirror circuit, and the drain of the first group of PMOS transistors (PS1) is connected to the second branch of the current mirror circuit. Specifically, the gate of the third group of PMOS transistors (PS0) is connected to the output terminal of the amplifier (AMP).

[0069] Reference Figure 5 The current mirror circuit includes a first NMOS transistor NS0 and a second NMOS transistor NS1. The drain of the first NMOS transistor NS0 is connected to the gate of the first NMOS transistor NS0, the drain of the third group of PMOS transistors PS0, and the gate of the second NMOS transistor NS1. The drain of the second NMOS transistor NS1 is connected to the drain of the first group of PMOS transistors PS1. The sources of the first NMOS transistor NS0 and the second NMOS transistor NS1 are both grounded.

[0070] Reference Figure 5 The ratio of the width-to-length ratio of the first NMOS transistor NS0 to the width-to-length ratio of the second NMOS transistor NS1 is 1:1.

[0071] Reference Figure 4 and Figure 5If the width-to-length ratio of the third group of PMOS transistors PS0 to the width-to-length ratio of the fourth group of PMOS transistors PL is a:1, then the magnitude of the current flowing through the third group of PMOS transistors PS0 is a×I. R If the width-to-length ratio of the first NMOS transistor NS0 to the second NMOS transistor NS1 is 1:1, then the magnitude of the current flowing through the second NMOS transistor NS1 is a×I. R Therefore, the current flowing through the first PMOS transistor PS1 is a×I R .

[0072] Reference Figure 5 The magnitude of the current flowing through PA0 is I. A0 The magnitude of the current flowing through PA1 is I. A1 The magnitude of the current flowing through the PAN is I. AN The total current flowing through all the second group of PMOS transistors is I. Q I Q =I A0 +I A1 +····+I AN IZ = I0 + I1 + ... + I N +I Q V RAMP =R Z ×I Z .

[0073] Reference Figure 5 When S0 is turned on, PA0 and the first group of PMOS transistors PS1 form a current mirror, then When S0 is off, I A0 =0; When S1 is turned on, PA1 and the first group of PMOS transistors PS1 form a current mirror, then When S1 is turned off, I A1 =0; When SK is turned on, PAK and the first group of PMOS transistors PS1 form a current mirror, then When SAK is off, I AK =0.

[0074] Reference Figure 4 and Figure 5 In the first ramp phase VR, at least one of S0, S1, ..., SK is turned on according to the feedback control word pre-stored by the system. The current of the ramp signal voltage boosting circuit 1042 flows to the terminating resistor 10412, causing the current flowing through the terminating resistor 10412 to rise by IQ, thereby causing the initial potential of the ramp signal to rise by ΔV, where ΔV = I. Q ×R ZAfter the first ramp phase VR ends, S0, S1, ..., SK are all turned off, I Q =0, in the second ramp phase VS, the initial potential of the ramp signal returns to the normal potential.

[0075] Reference Figure 4 and Figure 5 , By adjusting a and 2 J The size can be set to determine the step size of the current flowing from the ramp signal voltage boosting circuit 1042 to the terminating resistor 10412, a and 2 J The smaller the ratio of a to J, the smaller the step size and the higher the accuracy of dark current compensation. Similarly, the smaller the ratio of a to J, the smaller the step size and the higher the accuracy of dark current compensation.

[0076] Figure 7 This is a schematic diagram of ramp signals in some embodiments of the present invention. (Refer to...) Figure 7 RAMP X express Figure 4 The ramp signal generated by the ramp generation circuit 104 shown is RAMP. Y express Figure 5 The ramp signal generated by the ramp generation circuit 104 shown in the diagram, during the first ramp phase VR, RAMP Y The initial potential relative to RAMP X The initial potential increased by ΔV, CNT represents the digital signal output by the readout unit, and t1 represents the value of the readout unit. Figure 4 The ramp signal generation circuit shown indicates the counting period of the timer during the first ramp phase VR, where t1' represents the timer's count cycle. Figure 5 The ramp signal generation circuit shown has the counter counting cycle during the first ramp phase VR, and during the second ramp phase RAMP. Y The initial potential relative to RAMP X The initial potentials are the same, and t2 represents the counting period of the second ramp stage VS of the counter.

[0077] Reference Figure 7 Due to RAMP Y The initial potential relative to RAMP X The initial potential rises by ΔV, t1 increases to t1', and the counter's counting period during the first ramp phase VR increases by t1'-t1. Figure 4 When the ramp signal generation circuit is shown, the count value of the timer VR in the first ramp phase is CN1, using... Figure 5 When the ramp signal generation circuit is shown, the count value of the timer VR in the first ramp phase is CN1'. Figure 4The ramp signal generation circuit shown uses the timer's count value VS during the second ramp phase and employs... Figure 5 When the ramp signal generation circuit shown is in operation, the count value of the timer VS during the second ramp phase is CN2. Therefore, the following method is used: Figure 4 When the ramp signal generation circuit shown is used, the output data of the readout unit is CN2-CN1, which is adopted. Figure 5 When the ramp signal generation circuit is shown, the output data of the readout unit is CN2-CN1'. CN2-CN1' is increased by ΔCN compared to CN2-CN1, that is, the final output data of the readout unit compensates for the ΔCN lost due to dark current.

[0078] While embodiments of the present invention have been described in detail above, it will be apparent to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations fall within the scope and spirit of the invention as set forth in the claims. Furthermore, the invention described herein may have other embodiments and can be implemented or carried out in various ways.

Claims

1. A ramp signal voltage boosting circuit, applied to a ramp generation circuit, wherein the ramp generation circuit includes a ramp signal generation branch, characterized in that, include: The mirroring unit is used to mirror the ramp signal reference current of the ramp signal generating branch to generate a compensation reference current. as well as A compensation branch, connected to the mirror unit, is used to mirror the compensation reference current to generate at least one compensation current, which is used to raise the level of the ramp signal output by the ramp signal generation branch. The compensation branch includes a first group of PMOS transistors and at least one first mirror gating unit. The source of the first group of PMOS transistors is connected to the power supply voltage, and the drain of the first group of PMOS transistors is connected to the gate of the first group of PMOS transistors and the mirror unit. All the first mirror gating units are connected to the gate of the first group of PMOS transistors. The first mirror gating units are used to selectively conduct to form a current mirror with the first group of PMOS transistors, mirroring the current flowing through the first group of PMOS transistors to generate the compensation current.

2. The ramp signal voltage boosting circuit according to claim 1, characterized in that, The first mirror gating unit includes a second group of PMOS transistors and a first gating switch. The source of the second group of PMOS transistors is connected to the power supply voltage, the gate of the second group of PMOS transistors is connected to the gate of the first group of PMOS transistors, the drain of the second group of PMOS transistors is connected to one end of the first gating switch, and the other end of the first gating switch is used to output the compensation current.

3. The ramp signal voltage boosting circuit according to claim 2, characterized in that, The width-to-length ratio of the second group of PMOS transistors increases proportionally.

4. The ramp signal voltage boosting circuit according to claim 1 or 2, characterized in that, The mirror unit includes a third group of PMOS transistors and a current mirror circuit. The source of the third group of PMOS transistors is connected to the power supply voltage. The gate of the third group of PMOS transistors is connected to the ramp signal generation branch. The drain of the third group of PMOS transistors is connected to the first branch of the current mirror circuit. The drain of the first group of PMOS transistors is connected to the second branch of the current mirror circuit.

5. The ramp signal voltage boosting circuit according to claim 4, characterized in that, The current mirror circuit includes a first NMOS transistor and a second NMOS transistor. The drain of the first NMOS transistor is connected to the gate of the first NMOS transistor, the drain of the third group of PMOS transistors, and the gate of the second NMOS transistor. The drain of the second NMOS transistor is connected to the drain of the first group of PMOS transistors. The sources of the first NMOS transistor and the second NMOS transistor are both grounded.

6. The ramp signal voltage boosting circuit according to claim 5, characterized in that, The ratio of the width-to-length ratio of the first NMOS transistor to that of the second NMOS transistor is 1:

1.

7. A ramp generating circuit, characterized in that, include: The ramp signal generation branch is used to generate and output ramp signals; as well as The ramp signal voltage boosting circuit as described in any one of claims 1 to 6.

8. The ramp generating circuit according to claim 7, characterized in that, The ramp signal generation branch includes an amplifier, an adjustable resistor unit, a terminating resistor, a fourth group of PMOS transistors, and at least two second mirror gating units. The non-inverting input of the amplifier is connected to a reference voltage, the inverting input of the amplifier is connected to the drain of the fourth group of PMOS transistors and the adjustable resistor unit, and the output of the amplifier is connected to the gate of the fourth group of PMOS transistors. The adjustable resistor unit is used to adjust the resistance between the drain of the fourth group of PMOS transistors and ground. Each of the second mirror gating units is connected to the gate of the fourth group of PMOS transistors and one end of the terminating resistor, and the other end of the terminating resistor is grounded. The second mirror gating units are used for selective conduction to form a current mirror with the fourth group of PMOS transistors, mirroring the current flowing through the fourth group of PMOS transistors to generate a ramp signal current, thereby generating a ramp signal.

9. The ramp generating circuit according to claim 8, characterized in that, The second mirror gating unit includes a fifth group of PMOS transistors and a second gating switch. The source of the fifth group of PMOS transistors is connected to the power supply voltage, the gate of the fifth group of PMOS transistors is connected to the output terminal of the amplifier, the drain of the fifth group of PMOS transistors is connected to one end of the second gating switch, and the other end of the second gating switch is connected to one end of the terminating resistor.

10. The ramp generating circuit according to claim 9, characterized in that, The width-to-length ratio of the fifth group of PMOS transistors increases proportionally.

11. The ramp generating circuit according to claim 8, characterized in that, The adjustable resistor unit includes m resistors and n third select switches, where m is a natural number greater than or equal to 2, n is a natural number greater than or equal to 1, and mn=1. The m resistors are connected in series between the drain of the fourth group of PMOS transistors and ground. The connection point between two resistors is the select switch connection point. The select switch connection point is connected to one end of each of the n third select switches. The other ends of the n third select switches are all grounded.

12. An image sensor, characterized in that, include: Pixel array unit, used to output pixel signals after light sensing; A row selection decoding driver unit is connected to the pixel array unit and is used to drive the pixel array unit; The ramp generating circuit as described in any one of claims 7 to 11; A readout circuit, connected to the pixel array unit and the ramp generation circuit, is used to convert the pixel signal into a digital signal; An output signal processing unit is connected to the readout circuit to convert the digital signal into an image and output it. The timing control unit is connected to the decoding drive unit, the ramp generation circuit, the readout circuit, and the output signal processing unit, and is used to send clock signals to the decoding drive unit, the ramp generation circuit, the readout circuit, and the output signal processing unit.

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