Current biasing circuit for high-precision current calibration and control method

Abstract

The invention relates to the technical field of integrated circuit design, in particular to a current bias circuit for high-precision current calibration and a control method, and the circuit comprises a band-gap reference circuit, a current calibration circuit, a current detection circuit and a first bias unit; the band-gap reference circuit is used for outputting reference current; the bias unit receives the reference current and outputs a bias voltage to the current calibration circuit; the current calibration circuit is used for calibrating an input current through the Trim circuit and outputting a calibrated current; and the current detection circuit receives the calibrated current and outputs an indication signal. According to the invention, the current calibration circuit is introduced, so that accurate voltage value and current value output can be realized no matter how a process corner changes.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and specifically to a high-precision current calibration current bias circuit and control method. Background Technology

[0002] With the rapid development of the digital age, electronic devices have become deeply integrated into all aspects of people's lives. Among the wireless communication functions of numerous electronic devices, WiFi technology has become one of the most mainstream wireless connection methods due to its wide coverage, high data transmission rate, and relatively convenient usage. From smartphones and tablets to smart home devices, from network deployment in workplaces to data interaction in the Industrial Internet of Things, WiFi technology is ubiquitous, and its application scenarios and user demands are experiencing explosive growth.

[0003] In-depth research on power management circuits in the WiFi field, and the development of new power management circuits with high load capacity, precise current calibration function and external status monitoring capability, are of great practical significance and urgency for promoting the continuous innovation of WiFi technology, improving the stability and reliability of WiFi chips in complex application scenarios, and meeting the growing and diversified user needs.

[0004] Traditional bandgap reference circuits are affected by the higher-order VBE effect, with the temperature coefficient of their output voltage reaching as low as 10 ppm / ℃. This effect leads to a significant decrease in the accuracy of the output voltage when there are large temperature fluctuations, resulting in significant changes in the output value. Traditional bandgap reference circuits also exhibit large output fluctuations at different process angles, which cannot be effectively adjusted, making it difficult to obtain accurate output voltage and current. Summary of the Invention

[0005] The purpose of this invention is to overcome the problems of large output fluctuations and inability to effectively adjust traditional bandgap reference circuits at different process angles, which make it difficult to obtain accurate output voltage and current, and to provide a high-precision current calibration current bias circuit and control method.

[0006] To achieve the above-mentioned objectives, the present invention provides the following technical solution:

[0007] A high-precision current calibration current bias circuit includes a bandgap reference circuit, a current calibration circuit, a current detection circuit, and a first bias unit. The bandgap reference circuit is used to output a reference current; The first bias unit receives the reference current and outputs a bias voltage for the current calibration circuit; The current calibration circuit calibrates the input current through the Trim circuit and outputs the calibrated current. The current detection circuit receives the calibrated current and outputs an indication signal.

[0008] Preferably, the current calibration circuit includes an error amplifier, a second bias unit, and a resistor unit; The error amplifier is formed into a symmetrical structure using several MOS transistors; The resistor unit includes a second resistor and a third resistor; The second resistor is connected in parallel to one side of the error amplifier to receive the input current and generate a reference voltage; The third resistor is connected in parallel to the other side of the error amplifier. The third resistor is a variable resistor, and a clamping voltage is generated across the third resistor. The second bias unit includes a parallel switching branch composed of MOS transistors. The first switching branch is used to obtain the input current from the third resistor; the second switching branch is used to generate the calibrated current; and the third switching branch is used to generate a preset current value.

[0009] Preferably, the error amplifier includes a first MOSFET PM1, a second MOSFET PM2, a third MOSFET PM3, a fourth MOSFET NM4, a fifth MOSFET NM1, a sixth MOSFET NM2, and a seventh MOSFET NM3. In the error amplifier, the sources of the first MOSFET PM1 and the second MOSFET PM2 are connected to the power supply Vdd. The gates of the first MOSFET PM1 and the second MOSFET PM2 are connected and connected to the drain of the fourth MOSFET PM4. The source of the fourth MOSFET NM4 is connected to the drain of the second MOSFET PM2. The gates of the third MOSFET PM3 and the fourth MOSFET NM4 are connected and connected to the bias voltage V generated by the bandgap reference circuit. BIAS3 The drain of the third MOSFET PM3 is connected to the drain of the fifth MOSFET PM5, and the drain of the fourth MOSFET NM4 is connected to the drain of the sixth MOSFET PM6. The fourth MOSFET NM4, together with the first MOSFET PM1 and the second MOSFET PM2, forms a self-biased structure. The gate of the fifth MOSFET PM5 is connected to the current I generated by the bandgap reference circuit. b And it is connected to one end of the second resistor R2; the source of the fifth MOSFET PM5 is connected to the source of the sixth MOSFET PM6 and to the drain of the seventh MOSFET PM7; the gate of the seventh MOSFET PM7 is connected to the bias voltage V generated by the bandgap reference circuit. BIAS3 The source of the seventh MOSFET PM7 is grounded to vss, and the source of the seventh MOSFET PM7 is also connected to the other end of the second resistor.

[0010] Preferably, the second bias unit includes an eighth MOSFET PM5, a ninth MOSFET PM6, a tenth MOSFET PM7, an eleventh MOSFET PM8, a twelfth MOSFET PM9, and a thirteenth MOSFET PM10. In the first switching branch, the source of the eighth MOSFET PM5 is connected to the power supply Vdd, and the drain of the eighth MOSFET PM5 is connected to the source of the ninth MOSFET PM6; the gate of the eighth MOSFET PM5 is connected to one end of the first resistor R1, and the gate of the ninth MOSFET PM6 is connected to the bias voltage V generated by the bandgap reference circuit. BIAS3 The drain of the ninth MOSFET PM6 is connected to the third resistor R3; In the second switching branch, the source of the tenth MOSFET PM7 is connected to the power supply Vdd, and the drain of the tenth MOSFET PM7 is connected to the source of the eleventh MOSFET PM8; the gate of the tenth MOSFET PM7 is connected to one end of the first resistor R1, and the gate of the eleventh MOSFET PM8 is connected to the bias voltage V generated by the bandgap reference circuit. BIAS3 The drain output of the eleventh MOSFET PM8 is the calibrated current; In the third switching branch, the source of the twelfth MOSFET PM9 is connected to the power supply Vdd, and the drain of the twelfth MOSFET PM9 is connected to the source of the thirteenth MOSFET PM10; the gate of the twelfth MOSFET PM9 is connected to one end of the first resistor R1, and the gate of the thirteenth MOSFET PM10 is connected to the bias voltage V generated by the bandgap reference circuit. BIAS3 The drain output of the thirteenth MOSFET PM10 is the calibrated current. The other end of the first resistor R1 is connected to the power supply Vdd through the capacitor C1.

[0011] Preferably, the current detection circuit includes MOSFET PM13, MOSFET PM11, fourth resistor R4, MOSFET PM12, MOSFET NM4, fifth resistor R5, and first comparator com; The source of MOSFET PM13 is connected to the power supply Vdd, and the gate of MOSFET PM13 is connected to the bias voltage V generated by the bandgap reference circuit. bias1 The drain of MOSFET PM13 is connected to the source of MOSFET PM11; the gate of MOSFET PM11 is connected to the bias voltage V generated by the bandgap reference circuit. bias2The drain of MOSFET PM11 is connected to the fourth resistor R4, and it outputs an uncalibrated output voltage V_rcal. The other end of the fourth resistor R4 is grounded (vss). The source of MOSFET PM12 is connected to the drain of MOSFET NM4 and receives the calibrated current. The gate of MOSFET NM4 is connected to the enable high level eni_cbc. The drain of MOSFET NM4 is connected to the fifth resistor R5, and it receives the calibrated output voltage V_extr. The other end of the fifth resistor R5 is grounded. The non-inverting input of the first comparator com is connected to the calibrated voltage V_extr, and the inverting input is connected to the uncalibrated voltage V_rcal. The calibrated voltage V_extr and the uncalibrated voltage V_rcal are output as a voltage signal rcal_readout by the first comparator com. The voltage signal rcal_readout serves as an output indicator signal.

[0012] Preferably, the bias unit includes two MOSFETs, the drain of one MOSFET is connected to the gate of the other MOSFET, and the drain of the other MOSFET is connected to a current calibration circuit; the gates of the two MOSFETs respectively receive a bias voltage V generated by a bandgap reference circuit. bias1 V bias2 .

[0013] Preferably, the bandgap reference circuit includes a startup circuit, a bias circuit, and a high-order compensation core circuit; the startup circuit, the bias circuit, and the high-order compensation core circuit are connected in parallel between the power supply and ground.

[0014] Preferably, the high-order compensation core circuit comprises three parts; The first part generates a PTAT current that is proportional to the absolute temperature. The first part forms a common source and common gate structure to increase the power supply rejection ratio of the bandgap reference circuit. The second part generates a CTAT current, which is inversely proportional to the absolute temperature, and the second part forms a common source and common gate structure. The third part forms a current mirror, thereby generating a third current that is the same as the CTAT current of the second part, and a fourth current that is the same as the PTAT current of the first part; the third current is divided into current Ictat2 and current Ictat3 through a MOS transistor; the fourth current and the current Ictat3 are added together in different proportions to generate a zero-temperature voltage Vbg.

[0015] Based on the same concept, a control method for a high-precision current calibration current bias circuit is also proposed, which constructs a high-precision current calibration current bias circuit as described in any of the above-mentioned methods; by adjusting the value of the variable resistor in the current calibration circuit, the calibrated current is output to achieve temperature compensation.

[0016] Preferably, the value of the variable resistor is adjusted so that the calibrated current I... caf_cbc Stabilize at the preset value, ; Among them, I b R1 is the reference current value output by the bandgap reference circuit; R2 is the current calibration circuit based on I... b The resistor that generates the reference voltage, R3 is a variable resistor.

[0017] Compared with the prior art, the beneficial effects of the present invention are as follows: the present invention achieves efficient signal transmission and processing through the fine circuit design between the current calibration module and the current detection module, effectively avoiding signal loss and interference, and further improving the accuracy and stability of the circuit. No matter how the process angle changes, it can achieve accurate voltage and current value output. Attached Figure Description

[0018] Figure 1 This invention provides an overall circuit for a high-precision current calibration current bias circuit. Figure 2 This is the reference bandgap circuit diagram provided by the present invention; Figure 3 This invention provides a current calibration circuit. Figure 4 This is the current detection circuit of the present invention. Detailed Implementation

[0019] The present invention will now be described in further detail with reference to specific embodiments. However, this should not be construed as limiting the scope of the present invention to the following embodiments; all technologies implemented based on the content of the present invention fall within the scope of the present invention.

[0020] Example 1 A current bias circuit with high-precision current calibration and high-order compensation, the overall circuit is as follows: Figure 1 As shown, it includes a bandgap reference circuit (BGR), a current calibration circuit, a current detection circuit, and a first bias unit; the bandgap reference circuit is used to output a reference current; the first bias unit receives the reference current and outputs a bias voltage for the current calibration circuit; the current calibration circuit calibrates the input current through a Trim circuit and outputs the calibrated current; the current detection circuit receives the calibrated current and outputs an indication signal.

[0021] Specifically, the bandgap reference source circuit outputs two bias voltages connected to the gate of the MOS transistor in the bias unit; the two bias voltages of the bandgap reference source are connected to the current detection circuit; the bias unit receives the bias voltage generated by the BGR to generate a bias current connected to the current calibration circuit; the input bias voltage of the current detection circuit is provided by the bandgap reference source, connected to the calibrated current Ical_cbc generated by the current calibration circuit, and the output is connected to an LED; the input of the current calibration circuit is connected to the Trim circuit, and the current calibration circuit is calibrated by Trim technology to generate Ic20uA and Ical_cbc.

[0022] Its working principle is explained as follows: The current generated by the BGR circuit flows into the current calibration module through the bias unit. In this module, the Trim technology is used to accurately calibrate the current to generate 20μA and 10μA currents. The calibrated current flows into the current detection module. If the external LED lights up, it indicates that the current is accurately 10μA; if it does not light up, it indicates that the calibration process failed.

[0023] Trim circuits are embedded auxiliary circuits used for precision calibration. They allow for fine-tuning of critical component parameters during manufacturing or use via physical or electrical methods to compensate for various errors and ensure the main circuit meets design specifications and performance requirements. Key implementation methods include laser trimming, fuse / anti-fuse technology, digital trimming, and electrically adjustable components.

[0024] Laser trimming: Using a laser beam to precisely cut or alter the geometry of a thin-film resistor, thereby changing its resistance value. It offers extremely high precision but is a one-time, irreversible process. It is commonly used for factory calibration of high-precision analog chips (such as reference voltage sources and ADCs / DACs).

[0025] Fuse / Anti-fuse technology: Fuse technology initially creates a closed circuit, which is then "burned out" by a large current to open the circuit. Anti-fuse technology initially creates an open circuit, which is then "broken down" by applying a high voltage to create a closed circuit. Adjustment is achieved by changing the connection relationship to connect or disconnect different resistor / capacitor units. It is also a one-time operation.

[0026] Digital fine-tuning: Uses a binary weighted resistor / capacitor array controlled by switches. Different total resistance / capacitance values ​​are achieved by programming the switch states (on / off). Digital memory can be integrated for reprogrammable or electrically erasable operation. Most common in modern chips.

[0027] Electrically adjustable components: These use a DAC or digital potentiometer to generate a programmable voltage / current / resistance that can be directly injected into or connected to the node requiring adjustment. They can be dynamically adjusted while the system is operating to compensate for temperature drift or aging in real time; this is also known as "active tuning" or "background calibration."

[0028] Furthermore, the specific circuit of the bandgap reference circuit is as follows: Figure 2 As shown, it consists of a startup circuit, a bias circuit, and a high-order compensation core circuit.

[0029] The startup circuit includes Figure 2 MOSFETs M12, M11, and M13; When the gate enable signal EN of MOSFET M12 and the second MOSFET are turned on to a low level, the first MOSFET and the second MOSFET are turned on, so that the drain and gate of the third MOSFET are connected to a high level and ground, forming a current path. The bias circuit includes a fourth MOSFET (M10), a fifth MOSFET (M9), and a sixth MOSFET (M14). The gate of the sixth MOSFET is connected to the gate of the third MOSFET to form a current mirror pair. The current generated by the startup circuit is replicated through the sixth MOSFET. The source of the fourth MOSFET is connected to the power supply VDD, and its gate and drain are connected to form a diode, which is connected to the source of the fifth MOSFET to provide bias current and bias voltage for the high-order compensation core circuit. The high-order compensation core circuit comprises three parts: the first part includes the seventh MOSFET (M3), the eighth MOSFET (M4), the ninth MOSFET (M2), the tenth MOSFET (M1), the first operational amplifier (OP1), the first resistor (R1), the first transistor (Q1), and the second transistor (Q2); the second part includes the eleventh MOSFET (M6), the twelfth MOSFET (M8), the thirteenth MOSFET (M5), the fourteenth MOSFET (M7), the second operational amplifier (OP2), and the second resistor (R2); the third part includes the third operational amplifier (OP3), the fifteenth MOSFET (M15), the sixteenth MOSFET (M16), the seventeenth MOSFET (M17), the eighteenth MOSFET (M18), the third resistor (R3), the fourth resistor (R4), the fifth resistor (R5), and the nineteenth MOSFET.

[0030] In the first part, the sources of the seventh and eighth MOSFETs are connected to the power supply VDD, their gates are connected to each other and connected to the output of the first operational amplifier, and their drains are connected to the sources of the ninth and tenth MOSFETs, respectively. The gates of the ninth and tenth MOSFETs are connected to each other and to the gate of the fifth MOSFET. The drain of the ninth MOSFET is connected to the first resistor. The inverting input of the first operational amplifier and the non-inverting input of the third operational amplifier are connected to each other. The drain of the tenth MOSFET is connected to the emitter of the second transistor, the non-inverting input of the first operational amplifier, the inverting input of the second operational amplifier, and the drain of the thirteenth MOSFET. The other end of the first resistor is connected to the emitter of the first transistor. The collectors and bases of the first and second transistors are both connected to ground (VSS). The first part generates a PTAT (proportional to absolute temperature) current. In addition, the seventh and eighth MOSFETs together with the ninth and tenth MOSFETs form a cascode (common source and common gate structure), which increases the psrr (power supply rejection ratio) of the bandgap reference circuit.

[0031] In the second part, the sources of the eleventh and twelfth MOSFETs are connected to the power supply, their gates are connected to the output of the second operational amplifier, and their drains are connected to the sources of the thirteenth and fourteenth MOSFETs, respectively. The gates of the thirteenth and fourteenth MOSFETs are connected to the gates of the fifth, ninth, and tenth MOSFETs. The drain of the thirteenth MOSFET is connected to the emitter of the second transistor, the non-inverting input of the first operational amplifier, the inverting input of the second operational amplifier, and the drain of the tenth MOSFET. The drain of the fourteenth MOSFET is connected to the non-inverting input of the second operational amplifier, one end of the second resistor, and the other end of the second resistor is grounded. The second part generates a CTAT (inversely proportional to absolute temperature) current. Similarly, the eleventh and twelfth MOSFETs together with the thirteenth and fourteenth MOSFETs form a cascode (common source, common gate structure).

[0032] The sources of the fifteenth and seventeenth MOSFETs in the third part are connected to the power supply. The drain of the fifteenth MOSFET is connected to the source of the sixteenth MOSFET, and its gate is connected to the gate of the eleventh and twelfth MOSFETs to form a current mirror, thereby copying the CTAT current generated in the second part. The drain of the seventeenth MOSFET is connected to the source of the eighteenth MOSFET, and its gate is connected to the gate of the seventh and eighth MOSFETs to form a current mirror, thereby copying the PTAT current generated in the first part. The gates of the sixteenth and eighteenth MOSFETs are connected to the gates of the fifth, ninth, tenth, thirteenth, and fourteenth MOSFETs. The drain of the sixteenth MOSFET serves as the output and is also connected to the drain of the nineteenth MOSFET and one end of the fourth resistor. The drain of the eighteenth MOSFET is connected to the other end of the fourth resistor and one end of the fifth resistor. The gate of the nineteenth MOSFET is connected to the output of the third operational amplifier, and its drain is connected to the output Vbg, the drain of the sixteenth MOSFET, one end of the fourth resistor, and one end of the third resistor. The other end of the third resistor is connected to the inverting input of the third operational amplifier and grounded (vss). The other end of the fifth resistor is grounded. The CTAT current generated by the fifteenth MOSFET is divided into Ictat2 and Ictat3 by the sixteenth MOSFET. The positive temperature current PTAT generated by the seventeenth MOSFET and the negative temperature current Ictat3 are added together in different proportions, so that the branch composed of the fourth and fifth resistors generates a zero-temperature voltage Vbg.

[0033] like Figure 3 The current calibration circuit consists of an error amplifier (EA), a second bias unit, and a variable resistor unit; The error amplifier (EA) is composed of a first MOSFET (PM1), a second MOSFET (PM2), a third MOSFET (PM3), a fourth MOSFET (PM4), a fifth MOSFET (NM1), a sixth MOSFET (NM2), and a seventh MOSFET (NM3). The resistor unit comprises a first resistor unit (R2) and a second resistor unit (R3), wherein the first resistor unit provides V to EA. REF The second resistor unit is a variable resistor unit; The second bias unit consists of the eighth MOSFET (PM5), the ninth MOSFET (PM6), the tenth MOSFET (PM7), the eleventh MOSFET (PM8), the twelfth MOSFET (PM9), and the thirteenth MOSFET (PM10); The first resistor (R1) and the first capacitor (C1) provide stability for the loop; In the error amplifier, the sources of the first and second MOSFETs are connected to the power supply (Vdd), and their gates are connected to the drain of the fourth MOSFET. The drains of the second and third MOSFETs are connected to the sources of the third and fourth MOSFETs, respectively. The drain of the first MOSFET is also connected to the first resistor. The gates of the third and fourth MOSFETs are connected and connected to the bias voltage V generated by the BGR. BIAS3 The drain of the third MOSFET is connected to the drain of the fifth MOSFET, and the drain of the fourth MOSFET is connected to the drain of the sixth MOSFET. The fourth MOSFET, together with the first and second MOSFETs, forms a self-biased structure, enabling the first, second, and fourth MOSFETs to operate. The gate of the fifth MOSFET is connected to the current Ib20 generated by the BGR and the first resistor unit, while its source is connected to the source of the sixth MOSFET and the drain of the seventh MOSFET. The gate of the sixth MOSFET is connected to the second resistor unit, and the gate of the seventh MOSFET is connected to the bias voltage V generated by the BGR. BIAS3 The source is grounded (vss); the other end of the first resistor is connected to the first capacitor, and the other end of the first capacitor is connected to the power supply (vdd). The structure formed by the first resistor and the first capacitor provides frequency compensation for the circuit; the sources of the eighth, tenth, and twelfth MOSFETs are connected to the power supply, and their gates are connected to and connected to the drain of the first MOSFET. Their drains are connected to the sources of the ninth, eleventh, and thirteenth MOSFETs, respectively; the gates of the ninth, eleventh, and thirteenth MOSFETs are connected to the bias voltage V generated by the BGR. BIAS3 Connected; the drain of the ninth MOSFET is connected to the second resistor unit, and the drain of the eleventh MOSFET outputs a calibrated current I. cal_cbc The drain output of the thirteenth MOSFET is a calibrated current Ic20.

[0034] The current calibration circuit, when the current I generated by BGR... b20 The current flows into point A, and through the first resistor unit, it generates a voltage VA. The virtual short and virtual open characteristics of the error amplifier clamp the voltage at point B, making V... A =V B The magnitude of the current I2 is adjusted by regulating the internal resistance through the input TRIM of the second resistor unit. The current is copied by a current mirror formed by the eighth, ninth, tenth, eleventh, twelfth, and thirteenth MOSFETs in the bias unit, thereby generating a calibrated current I. cal_cbc and I c20 .

[0035] like Figure 4The current detection circuit includes a first MOSFET (PM10), a second MOSFET (PM11), a first resistor (R4), a third MOSFET (PM12), a fourth MOSFET (NM4), a second resistor (R5), and a first comparator (com). The source of the first MOS transistor in the current detection circuit is connected to the power supply (Vdd), and the gate is connected to the bias voltage V generated by the BGR circuit. bias1 The drain of the second MOSFET is connected to the source of the second MOSFET; the gate of the second MOSFET is connected to the bias voltage V generated by the BGR circuit. bias2 The drain of the third MOSFET (PM12) is connected to the drain of the fourth MOSFET (NM4) and serves as the uncalibrated output voltage V_rcal. The other end of the first resistor is grounded (vss). The source of the third MOSFET (PM12) is connected to the drain of the fourth MOSFET (NM4) and fed with the calibrated current I. cal_cbc The gate is connected to the enable level eni_cbc, and the drain is connected to the second resistor, which also serves as the calibrated output voltage V_extr. The other end of the second resistor is grounded. The non-inverting input of the first comparator is connected to the calibrated voltage V_extr, and the inverting input is connected to the uncalibrated voltage V_rcal. The calibrated voltage V_extr and the uncalibrated voltage V_rcal are output as a voltage signal by the comparator. This voltage signal is then connected to an LED, and the on / off state of the LED indicates whether the current calibration was successful.

[0036] Example 2 Please see Figure 1 The overall circuit proposed in this invention (see...) Figure 1The current calibration module consists of a bandgap reference (BGR), a current calibration circuit, a current detection unit, and a bias unit. Its working principle is explained as follows: The current generated by the BGR circuit flows into the current calibration module through the bias unit. In this module, the Trim technique is used to precisely calibrate the current to generate 20μA and 10μA currents. Ib20μA is the reference current value generated by the bandgap reference. In the reference bandgap circuit, a temperature-independent current is obtained by weighting positive and negative temperature coefficient currents. Therefore, the desired current for other modules can be obtained simply by replicating it through a current mirror; Ib20μA is obtained in this way. The calibrated current flows into the current detection module. If the external LED lights up, it indicates that the current is accurately 10μA; if it does not light up, it indicates that the calibration process failed. The current calibration module and current detection module designed in this study are compact in structure, significantly functional, and occupy a small area. The designers particularly emphasized the accuracy and reliability of the modules during the design process, as these directly affect the stability of the overall circuit performance. In the current calibration module, the application of Trim technology is key; it allows for fine-tuning of the current value to ensure output accuracy. The current detection module employs a high-sensitivity design, accurately reflecting minute changes in current to determine the on / off state of the LED.

[0037] Step 1, as follows Figure 2 As shown, this bandgap circuit consists of a startup circuit, a bias circuit, and a high-order compensation core circuit. Its high-order compensation section eliminates the high-order harmonic terms of VBE by generating TlnT. The specific formula is as follows: The current in Q2 is the sum of the currents PTAT and CTAT, therefore it has a zero temperature coefficient characteristic, and thus, (1) (2) The current in Q1 consists of PTAT, so (3) (4) (5) (6) (7) As long as: (8) In other words, by adjusting the ratio of R2 and R3, TlnT can be eliminated to achieve a high-order compensation effect. Furthermore, by properly configuring the ratio between R4 and R5, the linear temperature component of the output voltage VBG can be eliminated. Therefore, the temperature coefficient of the output voltage VBG can theoretically be completely canceled out, and we can obtain a temperature-independent output voltage reference VBG, which can be expressed as follows: (9) Step 2, as follows Figure 3 The error amplifier (EA) consists of NM1~NM3 and PM1~PM4. R1 and C1 provide stability for the loop, PM5~PM10 are bias units, R2 provides Vref for EA, and R3 is a variable resistor unit. Its principle is that when the current Ib20 generated by BGR flows into point A, it generates a voltage VA: (10) (11) The voltage at point B is clamped by the virtual short and virtual open characteristics of the amplifier. (12) Adjusting the resistance of R3 yields I2. (13) Analysis of formulas 10 to 13 clearly shows that precise control of the 20μA current can be achieved by accurately setting the step value of resistor R3, and different precise current values ​​can be generated through the bias unit. This study employs a cascode structure, which not only improves the accuracy of current mirror replication but also utilizes the shielding effect of the cascode structure to enhance the power supply rejection ratio.

[0038] Step 3, as follows Figure 4 As shown, the circuit consists of three main parts: a path on the left composed of PM10, PM11, and R4; a path in the middle composed of a transmission gate (NM4 and PM2) and an external resistor R5; and a path on the right composed of a comparator. The overall structure is simple and practical. The calibrated current Ical_cbc flows into the middle path and generates a voltage v_extr through the externally connected resistor R5; the current in the left path generates a voltage v_rcal through a 10μA bias current and R4. Since the resistance of R5 is greater than that of R4, under the action of the comparator, if v_extr is greater than v_rcal, the output rcal_readout is a high voltage vdd, indicating that the current calibration is successful; if rcal_readout is vss, it indicates that the calibration is unsuccessful.

[0039] The comparator's current is supplied by a combination of two amplifier stages and a Schmitt trigger. Key performance indicators of concern include the comparator's quiescent power consumption, offset voltage, and the Schmitt trigger's turnaround voltage. To optimize the offset voltage, the low-frequency gain is primarily improved by increasing the width of the load MOSFET, as increasing the length affects the comparator's response time, resulting in slower operation. The Schmitt trigger's turnaround voltage is controlled by designing MOSFETs with different width-to-length ratios, adjusting the turnaround voltage based on their threshold voltage and supply voltage.

[0040] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A high-precision current calibration current bias circuit, characterized in that, It includes a bandgap reference circuit, a current calibration circuit, a current detection circuit, and a first bias unit; The bandgap reference circuit is used to output a reference current; The first bias unit receives the reference current and outputs a bias voltage for the current calibration circuit; The current calibration circuit calibrates the input current through the Trim circuit and outputs the calibrated current. The current detection circuit receives the calibrated current and outputs an indication signal.

2. The current bias circuit for high-precision current calibration as described in claim 1, characterized in that, The current calibration circuit includes an error amplifier, a second bias unit, and a resistor unit; The error amplifier is formed into a symmetrical structure using several MOS transistors; The resistor unit includes a second resistor and a third resistor; The second resistor is connected in parallel to one side of the error amplifier to receive the input current and generate a reference voltage; The third resistor is connected in parallel to the other side of the error amplifier. The third resistor is a variable resistor, and a clamping voltage is generated across the third resistor. The second bias unit includes a parallel switching branch composed of MOS transistors. The first switching branch is used to obtain the input current from the third resistor; the second switching branch is used to generate the calibrated current; and the third switching branch is used to generate a preset current value.

3. The high-precision current calibration current bias circuit as described in claim 2, characterized in that, The error amplifier includes a first MOSFET PM1, a second MOSFET PM2, a third MOSFET PM3, a fourth MOSFET NM4, a fifth MOSFET NM1, a sixth MOSFET NM2, and a seventh MOSFET NM3. In the error amplifier, the sources of the first MOSFET PM1 and the second MOSFET PM2 are connected to the power supply Vdd. The gates of the first MOSFET PM1 and the second MOSFET PM2 are connected and connected to the drain of the fourth MOSFET PM4. The source of the fourth MOSFET NM4 is connected to the drain of the second MOSFET PM2. The gates of the third MOSFET PM3 and the fourth MOSFET PM4 are connected and connected to the bias voltage V generated by the bandgap reference circuit. BIAS3 The drain of the third MOSFET PM3 is connected to the drain of the fifth MOSFET PM5, and the drain of the fourth MOSFET PM4 is connected to the drain of the sixth MOSFET PM6. The fourth MOSFET PM4, together with the first MOSFET PM1 and the second MOSFET PM2, forms a self-biased structure. The gate of the fifth MOSFET PM5 is connected to the current I generated by the bandgap reference circuit. b And it is connected to one end of the second resistor R2; the source of the fifth MOSFET PM5 is connected to the source of the sixth MOSFET PM6 and to the drain of the seventh MOSFET PM7; the gate of the seventh MOSFET PM7 is connected to the bias voltage V generated by the bandgap reference circuit. BIAS3 The source of the seventh MOSFET PM7 is grounded to vss, and the source of the seventh MOSFET PM7 is also connected to the other end of the second resistor.

4. The high-precision current calibration current bias circuit as described in claim 2, characterized in that, The second bias unit includes an eighth MOSFET PM5, a ninth MOSFET PM6, a tenth MOSFET PM7, an eleventh MOSFET PM8, a twelfth MOSFET PM9, and a thirteenth MOSFET PM10. In the first switching branch, the source of the eighth MOSFET PM5 is connected to the power supply Vdd, and the drain of the eighth MOSFET PM5 is connected to the source of the ninth MOSFET PM6; the gate of the eighth MOSFET PM5 is connected to one end of the first resistor R1, and the gate of the ninth MOSFET PM6 is connected to the bias voltage V generated by the bandgap reference circuit. BIAS3 The drain of the ninth MOSFET PM6 is connected to the third resistor R3; In the second switching branch, the source of the tenth MOSFET PM7 is connected to the power supply Vdd, and the drain of the tenth MOSFET PM7 is connected to the source of the eleventh MOSFET PM8; the gate of the tenth MOSFET PM7 is connected to one end of the first resistor R1, and the gate of the eleventh MOSFET PM8 is connected to the bias voltage V generated by the bandgap reference circuit. BIAS3 The drain output of the eleventh MOSFET PM8 is the calibrated current; In the third switching branch, the source of the twelfth MOSFET PM9 is connected to the power supply Vdd, and the drain of the twelfth MOSFET PM9 is connected to the source of the thirteenth MOSFET PM10; the gate of the twelfth MOSFET PM9 is connected to one end of the first resistor R1, and the gate of the thirteenth MOSFET PM10 is connected to the bias voltage V generated by the bandgap reference circuit. BIAS3 The drain output of the thirteenth MOSFET PM10 is the calibrated current. The other end of the first resistor R1 is connected to the power supply Vdd through the capacitor C1.

5. The high-precision current calibration current bias circuit as described in claim 1, characterized in that, The current detection circuit includes MOSFET PM13, MOSFET PM11, fourth resistor R4, MOSFET PM12, MOSFET NM4, fifth resistor R5, and first comparator com; The source of MOSFET PM13 is connected to the power supply Vdd, and the gate of MOSFET PM13 is connected to the bias voltage V generated by the bandgap reference circuit. bias1 The drain of MOSFET PM13 is connected to the source of MOSFET PM11; the gate of MOSFET PM11 is connected to the bias voltage V generated by the bandgap reference circuit. bias2 The drain of MOSFET PM11 is connected to the fourth resistor R4, and it outputs an uncalibrated output voltage V_rcal. The other end of the fourth resistor R4 is grounded (vss). The source of MOSFET PM12 is connected to the drain of MOSFET NM4 and receives the calibrated current. The gate of MOSFET NM4 is connected to the enable high level eni_cbc. The drain of MOSFET NM4 is connected to the fifth resistor R5, and it receives the calibrated output voltage V_extr. The other end of the fifth resistor R5 is grounded. The non-inverting input of the first comparator com is connected to the calibrated voltage V_extr, and the inverting input is connected to the uncalibrated voltage V_rcal. The calibrated voltage V_extr and the uncalibrated voltage V_rcal are output as a voltage signal rcal_readout by the first comparator com. The voltage signal rcal_readout serves as an output indicator signal.

6. The high-precision current calibration current bias circuit as described in claim 1, characterized in that, The bias unit includes two MOSFETs, the drain of one MOSFET is connected to the gate of the other MOSFET, and the drain of the other MOSFET is connected to a current calibration circuit; the gates of the two MOSFETs respectively receive a bias voltage V generated by a bandgap reference circuit. bias1 V bias2 .

7. The high-precision current calibration current bias circuit as described in claim 1, characterized in that, The bandgap reference circuit includes a startup circuit, a bias circuit, and a high-order compensation core circuit; the startup circuit, the bias circuit, and the high-order compensation core circuit are connected in parallel between the power supply and ground.

8. The high-precision current calibration current bias circuit as described in claim 7, characterized in that, The high-order compensation core circuit consists of three parts; The first part generates a PTAT current that is proportional to the absolute temperature. The first part forms a common source and common gate structure to increase the power supply rejection ratio of the bandgap reference circuit. The second part generates a CTAT current, which is inversely proportional to the absolute temperature, and the second part forms a common source and common gate structure. The third part forms a current mirror, thereby generating a third current that is the same as the CTAT current of the second part, and a fourth current that is the same as the PTAT current of the first part. The third current is divided into current Ictat2 and current Ictat3 by a MOSFET. The fourth current and the current Ictat3 are added together in different proportions to generate a zero-temperature voltage Vbg.

9. A control method for a high-precision current calibration current bias circuit, characterized in that, Construct a high-precision current calibration current bias circuit as described in any one of claims 1-8; by adjusting the value of the variable resistor in the current calibration circuit, output the calibrated current to achieve temperature compensation.

10. The control method for a high-precision current calibration current bias circuit as described in claim 9, characterized in that, Adjust the value of the variable resistor so that the calibrated current I... caf_cbc Stabilize at the preset value, ； Among them, I b R1 is the reference current value output by the bandgap reference circuit; R2 is the current calibration circuit based on I... b The resistor that generates the reference voltage, R3 is a variable resistor.

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