Display panel and display device

Abstract

The display panel and the display device are provided by the present disclosure, and belong to the technical field of display. The display panel comprises a first light emitting element located in a first display area, and a first pixel circuit and a compensation capacitor located in a peripheral area. The first pixel circuit can be coupled with the first light emitting element through a first connection trace. A first metal layer in the compensation capacitor can be coupled with a target node, and a second metal layer can be coupled with a power supply end. The target node is a node coupled by the first connection trace and the first pixel circuit. In this way, the parasitic capacitance on the first connection trace can be effectively compensated, and the light emitting brightness uniformity of each first light emitting element in the first display area is ensured to be good. Further, the display effect of the display panel can be good.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to a display panel and a display device. BACKGROUND

[0002] An organic light-emitting diode (OLED) display panel has been widely applied due to its advantages of self-emission, low driving voltage, and high response speed. The OLED display panel generally includes a plurality of pixel units, each of which includes a light-emitting element and a pixel circuit coupled with the light-emitting element.

[0003] In the related art, in order to improve the screen ratio of the display panel, the camera of the display device can be arranged in the display area of the display panel. In order to increase the transmittance of the area where the camera is located, the pixel circuit of each pixel unit in the area where the camera is located (i.e., the camera area) is generally arranged in the non-camera area. The pixel circuit located in the non-camera area is coupled with the light-emitting element located in the camera area through a connection wire, thereby providing a driving signal for the light-emitting element located in the camera area to drive the light-emitting element to emit light.

[0004] However, because the distances between the pixel circuits at different positions and the coupled light-emitting elements are different, the lengths of the different connection wires in the display panel are different, and thus the parasitic capacitances on the different connection wires are different. As a result, the light-emitting brightness of different light-emitting elements in the camera area is different, and the display effect of the display panel is poor. SUMMARY

[0005] Embodiments of the present disclosure provide a display panel and a display device, which can solve the problem of poor display effect of the display panel caused by different light-emitting brightness of different light-emitting elements due to different parasitic capacitances on different connection wires in the related art. The technical solution is as follows:

[0006] In one aspect, a display panel is provided, which includes:

[0007] a substrate, having a first display area, a second display area, and a peripheral area, the second display area at least partially surrounding the first display area, and the peripheral area at least partially surrounding the second display area;

[0008] a plurality of first light-emitting elements located in the first display area;

[0009] a plurality of first pixel circuits located in the peripheral area;

[0010] A plurality of second pixel circuits and a plurality of second light-emitting elements are located in the second display area, wherein at least one of the plurality of second pixel circuits is coupled to at least one of the plurality of second light-emitting elements;

[0011] At least one first connection trace is located in the peripheral area, the second display area and the first display area, and at least one first pixel circuit among the plurality of first pixel circuits is coupled to at least one first light-emitting element among the plurality of first light-emitting elements through the first connection trace;

[0012] At least one compensation capacitor is located in the peripheral area. The compensation capacitor includes an overlapping first metal layer and a second metal layer. The first metal layer is coupled to a target node, and the second metal layer is coupled to a power supply terminal. The target node is the node where the first pixel circuit is coupled to the first connection trace.

[0013] Optionally, the capacitance value of the compensation capacitor corresponding to each of the first pixel circuits is negatively correlated with the length of the coupled first connection trace.

[0014] Optionally, in the compensation capacitors corresponding to each of the first pixel circuits, the overlap area of ​​the two overlapping metal layers is negatively correlated with the length of the coupled first connection trace.

[0015] Optionally, the display panel includes: a plurality of pixel circuit groups, each pixel circuit group including: at least two first pixel circuits;

[0016] In this context, the capacitance values ​​of the compensation capacitors corresponding to each pixel circuit group are the same, while the capacitance values ​​of the compensation capacitors corresponding to different pixel circuit groups are different.

[0017] Optionally, the plurality of pixel circuit groups include: a first sub-pixel circuit group, a second sub-pixel circuit group, and a third sub-pixel circuit group arranged sequentially at intervals along the pixel row direction;

[0018] Wherein, the capacitance value of each compensation capacitor corresponding to the first sub-pixel circuit group is less than the capacitance value of each compensation capacitor corresponding to the second sub-pixel circuit group, and the capacitance value of each compensation capacitor corresponding to the second sub-pixel circuit group is greater than the capacitance value of each compensation capacitor corresponding to the third sub-pixel circuit group.

[0019] Optionally, the peripheral area includes: a first area and a second area arranged along the pixel column direction, wherein the second area is closer to the second display area than the first area;

[0020] Each of the first pixel circuits is located in the first region, and each of the compensation capacitors is located in the second region.

[0021] Optionally, the display panel includes a plurality of the compensation capacitors, each of the compensation capacitors having a second metal layer that is an integral structure, and each of the compensation capacitors having a first metal layer that is spaced apart along the pixel row direction.

[0022] Optionally, the at least one compensation capacitor includes a plurality of first group compensation capacitors, and at least one of the plurality of first group compensation capacitors includes an overlapping third metal layer and a fourth metal layer, wherein any two of the first metal layer, the second metal layer, the third metal layer and the fourth metal layer are located in different layers.

[0023] The third metal layer is coupled to the target node, and the fourth metal layer is coupled to the power supply terminal.

[0024] Optionally, the at least one compensation capacitor further includes: a plurality of second-group compensation capacitors and a plurality of third-group compensation capacitors;

[0025] At least one of the plurality of first-group compensation capacitors further includes overlapping first metal layers and second metal layers; at least one of the plurality of second-group compensation capacitors further includes overlapping first metal layers and second metal layers; and at least one of the plurality of third-group compensation capacitors further includes overlapping first metal layers and second metal layers.

[0026] The plurality of first-group compensation capacitors, the plurality of second-group compensation capacitors, and the plurality of third-group compensation capacitors are arranged sequentially at intervals along the pixel row direction, and the height of the first metal layer included in the second-group compensation capacitor along the pixel column direction is greater than the height of the first metal layer included in the third-group compensation capacitor along the pixel column direction, and is also greater than the height of the first metal layer included in the second-group compensation capacitor along the pixel column direction.

[0027] Optionally, the pixel circuit in the display panel includes: an active layer, a first gate metal layer, a second gate metal layer, a first source / drain metal layer, and a second source / drain metal layer arranged sequentially along a direction away from the substrate.

[0028] Wherein, the first metal layer is located in the same layer as one of the first gate metal layer and the second gate metal layer, and the second metal layer is located in the same layer as the other of the first gate metal layer and the second gate metal layer;

[0029] The third metal layer is located in the same layer as one of the first and second source / drain metal layers, and the fourth metal layer is located in the same layer as the other of the first and second source / drain metal layers.

[0030] Optionally, the first metal layer and the first gate metal layer are located in the same layer, and the second metal layer and the second gate metal layer are located in the same layer.

[0031] Optionally, the third metal layer is located in the same layer as the first source / drain metal layer, and the fourth metal layer is located in the same layer as the second source / drain metal layer.

[0032] Optionally, each of the compensation capacitors includes: overlapping first metal layers and second metal layers, and overlapping third metal layers and fourth metal layers.

[0033] Optionally, the fourth metal layer included in each of the compensation capacitors is an integral structure, and the third metal layers included in each of the compensation capacitors are arranged at intervals along the pixel row direction.

[0034] Optionally, the orthographic projection of the first metal layer on the substrate and the orthographic projection of the third metal layer on the substrate are both strip-shaped structures, and the strip-shaped structures extend along the pixel column direction.

[0035] Optionally, the display panel further includes:

[0036] At least one second connection trace is located in the surrounding area, and both the first metal layer and the third metal layer are coupled to the target node through the second connection trace.

[0037] Optionally, the peripheral area includes: a first area, a third area, and a second area arranged along the pixel column direction, wherein the second area is closer to the second display area than the first area; the first metal layer and the second connection trace are coupled through a first via, and the third metal layer and the first metal layer are coupled through a second via;

[0038] The first via is located in the third region of the peripheral area, and the second via is located in the first region of the peripheral area.

[0039] Optionally, the display panel further includes: a first planarization layer, a second planarization layer, and a third planarization layer arranged sequentially along the direction away from the substrate from the first via;

[0040] Wherein, the orthographic projection of the first planarization layer on the substrate covers the orthographic projection of the first via on the substrate, the orthographic projection of the second planarization layer on the substrate covers the orthographic projection of the first via on the substrate, and the orthographic projection of the third planarization layer on the substrate does not overlap with the orthographic projection of the first via on the substrate.

[0041] Optionally, the first planarization layer, the second planarization layer, and the third planarization layer are all located on the side of the second connection trace away from the substrate.

[0042] Optionally, the second connection trace is located on the same layer as the second source / drain metal layer included in the pixel circuit of the display panel.

[0043] Optionally, the display panel includes at least one compensation capacitor corresponding to one of the at least one first connection trace;

[0044] Each of the compensation capacitors is coupled to the target node along with a corresponding first connection trace.

[0045] Optionally, the display panel includes multiple first connection traces, and at least two of the multiple first connection traces are located on different layers.

[0046] Optionally, the plurality of first connection traces include at least one first type of first connection trace located on the same layer, at least one second type of first connection trace located on the same layer, and at least one third type of first connection trace located on the same layer.

[0047] Furthermore, any two of the first type of first connection traces, the second type of first connection traces, and the third type of first connection traces are located on different layers.

[0048] Optionally, the first connection trace is a transparent conductive line.

[0049] On the other hand, a display device is provided, wherein the display device includes: a photosensor and a display panel as described above;

[0050] The photosensor is located in the first display area of ​​the display panel.

[0051] The beneficial effects of the technical solutions provided in this disclosure can include at least the following:

[0052] A display panel and display device are provided. The display panel includes a first light-emitting element located in a first display area, and a first pixel circuit and a compensation capacitor located in a peripheral area. The first pixel circuit is coupled to the first light-emitting element via a first connection trace. The first metal layer in the compensation capacitor is coupled to a target node, and the second metal layer is coupled to a pull-down power supply terminal. The target node is the node where the first connection trace and the first pixel circuit are coupled. This effectively compensates for parasitic capacitance on the first connection trace, ensuring good uniformity of brightness for each first light-emitting element in the first display area. Consequently, the display panel exhibits better display performance. Attached Figure Description

[0053] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0054] Figure 1 This is a schematic diagram of the coupling between a first connection trace and a light-emitting element provided in an embodiment of this disclosure;

[0055] Figure 2 This is a schematic diagram of the structure of a display panel provided in an embodiment of this disclosure;

[0056] Figure 3 This is a schematic diagram of another display panel structure provided in an embodiment of this disclosure;

[0057] Figure 4 This is a schematic diagram of the structure of another display panel provided in this embodiment;

[0058] Figure 5 This is a schematic diagram of another first connection trace and light-emitting element provided in an embodiment of this disclosure;

[0059] Figure 6 This is a schematic diagram of another display panel structure provided in an embodiment of the present disclosure;

[0060] Figure 7 This is a schematic diagram of another display panel structure provided in an embodiment of the present disclosure;

[0061] Figure 8 This is a structural layout of a compensation capacitor provided in an embodiment of this disclosure;

[0062] Figure 9 This is a structural layout of a portion of the metal layer in a compensation capacitor provided in an embodiment of this disclosure;

[0063] Figure 10 This is a structural layout of the first metal layer in a compensation capacitor provided in an embodiment of the present disclosure;

[0064] Figure 11 This is a schematic diagram of a pixel circuit provided in an embodiment of the present disclosure;

[0065] Figure 12 This is a partial structural layout of a compensation capacitor in a display panel provided in another embodiment of the present disclosure;

[0066] Figure 13 This is a partial structural layout of a compensation capacitor in a display panel provided in another embodiment of the present disclosure;

[0067] Figure 14 This is a schematic diagram of another display panel structure provided in an embodiment of the present disclosure;

[0068] Figure 15 This is a schematic diagram of another display panel structure provided in an embodiment of the present disclosure;

[0069] Figure 16 This is a schematic diagram of a structure including a planarization layer and vias provided in an embodiment of this disclosure;

[0070] Figure 17 This is a schematic diagram of another display panel structure provided in an embodiment of the present disclosure;

[0071] Figure 18 This is a schematic diagram of the structure of a first connection trace provided in an embodiment of this disclosure;

[0072] Figure 19 This is a schematic diagram of a first type of first connection trace provided in an embodiment of this disclosure;

[0073] Figure 20 This is a schematic diagram of a second type of first connection trace provided in an embodiment of this disclosure;

[0074] Figure 21 This is a schematic diagram of a third type of first connection trace provided in an embodiment of this disclosure;

[0075] Figure 22 This is a schematic diagram of another display panel structure provided in an embodiment of the present disclosure;

[0076] Figure 23 This is a schematic diagram of the structure of a display device provided in an embodiment of this disclosure. Detailed Implementation

[0077] To make the objectives, technical solutions, and advantages of this disclosure clearer, the disclosure will now be described in further detail with reference to the accompanying drawings.

[0078] With the development of display technology, existing notch or waterdrop screen designs are gradually failing to meet users' demands for high screen-to-body ratios. A series of high-PPI OLED display panels with a light-transmitting display area have emerged. PPI stands for pixels per inch, representing the number of pixels per inch of a display panel. In this type of display panel, hardware such as a photosensor (e.g., a camera) can be placed in the light-transmitting display area. Thus, the light-transmitting display area can also be called the under-display camera area. In this embodiment, the first display area refers to this under-display camera area.

[0079] In this embodiment, only an electroluminescence (EL) device is retained in the under-display camera area, which is the first light-emitting element described in this embodiment. The pixel circuit that drives the EL in the under-display camera area (i.e., the first pixel circuit described in this embodiment) is located in the peripheral area surrounding the under-display camera area, such as the upper bezel of the display panel. Then, a conductive line (i.e., the first connection trace described in this embodiment) is used to couple the first pixel circuit and the first light-emitting element, thereby achieving reliable driving of the first light-emitting element. Coupling can refer to electrical connection.

[0080] For example, Figure 1 A schematic diagram showing the first connection trace coupled to the first light-emitting element is shown. (Reference) Figure 1 It can be seen that the first connection trace L1 can extend through the first pixel circuit (not shown) to the first light-emitting element 01 and be coupled to the anode of the light-emitting element 01. Assuming the node coupled to the first light-emitting element 01 is labeled P1, then refer to... Figure 1 It can be seen that there is a parasitic capacitance c0 between node P1 and the cathode of the first light-emitting element 01, and there is also a parasitic capacitance c1 on the first connection trace L1.

[0081] Testing revealed that the distances between the first pixel circuit and the coupled first light-emitting element vary at different locations, resulting in varying lengths of the first connection traces on the display panel. This leads to the aforementioned... Figure 1 The parasitic capacitance c1 shown is different, meaning the capacitance at node P1 of different first light-emitting elements 01 is different. This results in different luminous brightness of different first light-emitting elements 01, affecting the display effect.

[0082] This disclosure provides a display panel including a compensation capacitor, which can effectively compensate for the capacitance value at node P1, thereby improving the uniformity of the luminous brightness of different first light-emitting elements and achieving the goal of making the display effect of the under-screen camera area consistent with the display effect of other normal display areas.

[0083] Figure 2 This is a schematic diagram of the structure of a display panel provided in an embodiment of this disclosure. Figure 2 As shown, the display panel may include: a substrate 00, which may have a first display area A1, a second display area A2 and a peripheral area A3, wherein the second display area A2 may at least partially surround the first display area A1, and the peripheral area A3 may at least partially surround the second display area A2.

[0084] For example, Figure 2The first display area A1 is located at the upper center of the substrate 00. The second display area A2 surrounds the first display area A1, that is, the first display area A1 is surrounded by the second display area A2. And the peripheral area A3 surrounds the second display area A2, that is, the second display area A2 is surrounded by the peripheral area A3.

[0085] Of course, in some embodiments, the first display area A1 may not be located in Figure 2 The position shown, while other positions are located on the substrate 00. For example, combined with Figure 2 The first display area A1 can be located at the upper left or upper right corner of the substrate 00.

[0086] Figure 3 This is a schematic diagram of another display panel structure provided in an embodiment of this disclosure. (In conjunction with...) Figure 2 and Figure 3 As can be seen, the display panel may further include: a plurality of first light-emitting elements 01 located in the first display area A1; a plurality of first pixel circuits 02 and at least one compensation capacitor 03 located in the peripheral area A3; a plurality of second pixel circuits 04 and a plurality of second light-emitting elements 05 located in the second display area A2; and at least one first connection trace L1 located in the peripheral area A3, the second display area A2, and the first display area A1.

[0087] In this configuration, at least one of the plurality of first pixel circuits 02 and at least one of the plurality of first light-emitting elements 01 can be coupled through a first connection trace L1. (Refer to...) Figure 3 One end of the first connecting trace L1 can be coupled to the first pixel circuit 02 (the coupling point is the target node P1 shown in the figure), and the other end of the first connecting trace L1 can be coupled to the first light-emitting element 01. This achieves effective coupling between the first pixel circuit 02 and the first light-emitting element 01. The at least one first pixel circuit 02 can be used to provide a driving signal to the coupled first light-emitting element 01, thereby driving the first light-emitting element 01 to emit light. At least one of the plurality of second pixel circuits 04 can be coupled to at least one of the plurality of second light-emitting elements 05, and the at least one second pixel circuit 04 can be used to provide a driving signal to the coupled second light-emitting element 05, thereby driving the second light-emitting element 05 to emit light. For example, Figure 3 In the display panel shown, each second pixel circuit 04 is coupled to a second light-emitting element 05. Each compensation capacitor 03 can be coupled to a target node P1 to achieve capacitance compensation at the target node P1.

[0088] Optional, Figure 4 This is a schematic diagram of the structure of another display panel provided in an embodiment of this disclosure. (In conjunction with...)Figure 3 and Figure 4 It can be seen that each compensation capacitor 03 may include an overlapping first metal layer 031 and a second metal layer 032. The first metal layer 031 can be coupled to the target node P1, and the second metal layer 032 can be coupled to the power supply terminal VSS. Therefore, the overlapping of the first metal layer 031 and the second metal layer 032 effectively forms the compensation capacitor 03.

[0089] For example, in Figure 1 Based on the structure shown, combined with Figure 4 The compensation capacitor 03 shown is... Figure 5 An optional circuit structure for capacitor c2 (i.e., compensation capacitor 03) formed by the overlapping of the first metal layer 031 and the second metal layer 032 is shown. (Comparison) Figure 1 and Figure 5 As can be seen, an additional capacitor c2 is added at the target node P1 in this embodiment of the present disclosure.

[0090] Furthermore, based on the formula for calculating capacitance value, "C = εS / d, where ε is the dielectric constant of the medium between the plates (i.e., the metal layer used to form the compensation capacitor), S is the overlapping area between the plates, and d is the distance between the plates," and the principle that the length of the first connection trace L1 is positively correlated with the parasitic capacitance value, it can be understood that in this embodiment, the overlapping area of ​​the first metal layer 031 and the second metal layer 032, and / or the distance between the first metal layer 031 and the second metal layer 032, can be flexibly set based on the length of the first connection trace L1 to achieve effective compensation for the target node P1. This results in better uniformity of the luminous brightness of different first light-emitting elements.

[0091] Optionally, the first display area A1 can be a light-transmitting display area, the second display area A2 can be a light-blocking display area, and the peripheral area A3 can be a non-display area. That is, the first display area A1 described in this embodiment is light-transmitting, and the hardware structure required for display devices such as photosensors can be set in the first display area A1. In this way, not only is the foundation for the realization of a true full-screen display laid, but also, because the first display area A1 only includes the first light-emitting element 01 and does not include the first pixel circuit 02 that drives the first light-emitting element 01 to emit light, it also ensures good light transmittance of the first display area A1 and good resolution of the display panel.

[0092] Optionally, the resolution of the first display area A1 can be less than or equal to the resolution of the second display area A2. For example, the area of ​​the first display area A1 can be the same as the area of ​​the second display area A2, and the number of first light-emitting elements 01 included in the first display area A1 can be the same as the number of second light-emitting elements 05 included in the second display area A2. Or, as... Figure 2 and Figure 3As shown, the area of ​​the first display area A1 can be smaller than the area of ​​the second display area A2, and the number of first light-emitting elements 01 included in the first display area A1 can be less than the number of second light-emitting elements 05 included in the second display area A2. Thus, the second display area A2 can also be referred to as the main display area. Alternatively, the resolution of the first display area A1 can be greater than the resolution of the second display area A2. That is, the area of ​​the first display area A1 is larger than the area of ​​the second display area A2, and the number of first light-emitting elements 01 included in the first display area A1 is greater than the number of second light-emitting elements 05 included in the second display area A2.

[0093] In summary, this disclosure provides a display panel including a first light-emitting element located in a first display area, and a first pixel circuit and a compensation capacitor located in a peripheral area. The first pixel circuit can be coupled to the first light-emitting element via a first connection trace. The first metal layer in the compensation capacitor can be coupled to a target node, and the second metal layer can be coupled to a power supply terminal. The target node is the node where the first connection trace and the first pixel circuit are coupled. This effectively compensates for parasitic capacitance on the first connection trace, ensuring good uniformity of brightness for each first light-emitting element in the first display area. Consequently, the display panel exhibits better display performance.

[0094] In this embodiment, the capacitance value of the compensation capacitor 03 corresponding to each first pixel circuit 02 is negatively correlated with the length of the coupled first connection trace L1. That is, the longer the length of the first connection trace L1, the smaller the capacitance value of the compensation capacitor 03; the shorter the length of the first connection trace L1, the larger the capacitance value of the compensation capacitor 03. Here, the compensation capacitor 03 corresponding to the first pixel circuit 02 refers to the compensation capacitor 03 coupled to the target node P1 in the first pixel circuit 02.

[0095] Because the length of the first connection trace L1 is generally positively correlated with the existing parasitic capacitance. That is, the longer the first connection trace L1 is, the larger the capacitance value of the parasitic capacitance on the first connection trace L1, and the smaller the capacitance value of the parasitic capacitance on the first connection trace L1 is. Moreover, for the first connection trace L1 with a large parasitic capacitance, the capacitance value of the corresponding compensation capacitor 03 should be smaller, that is, less compensation can be made. Conversely, for the first connection trace L1 with a small parasitic capacitance, the capacitance value of the corresponding compensation capacitor 03 should be larger, that is, more compensation can be made. Therefore, by setting the capacitance value of the compensation capacitor 03 corresponding to the first pixel circuit 02 to be negatively correlated with the length of the coupled first connection trace L1, the brightness of different first light-emitting elements 01 coupled to different first connection traces L1 can be made as similar as possible, ensuring good uniformity of the light emission brightness of each first light-emitting element 01. In turn, the display effect of the display panel can be effectively improved.

[0096] Optionally, based on the calculation formula of the capacitance value described in the above embodiments, it can be seen that in the embodiments of this disclosure, the overlapping area of ​​the two overlapping metal layers in the compensation capacitors 03 corresponding to each first pixel circuit 02 is negatively correlated with the length of the coupled first connection trace L1.

[0097] For example, refer to Figure 4 Assume that the compensation capacitor 03 includes an overlapping first metal layer 031 and a second metal layer 032. If the length of the first connection trace L1 is relatively long, the overlapping area of ​​the first metal layer 031 and the second metal layer 032 can be set to be small. Conversely, if the length of the first connection trace L1 is relatively short, the overlapping area of ​​the first metal layer 031 and the second metal layer 032 can be set to be large. The same principle applies to structures including other overlapping metal layers, and will not be elaborated further in subsequent embodiments.

[0098] Optionally, in embodiments of this disclosure, combined with Figure 3 The display panel may also include: multiple pixel circuit groups, each pixel circuit group may include at least two first pixel circuits 02.

[0099] The capacitance values ​​of each compensation capacitor 03 corresponding to each pixel circuit group can be the same, and the capacitance values ​​of the compensation capacitor 03 corresponding to different pixel circuit groups can be different.

[0100] For example, refer to Figure 6 and Figure 7 Assume that the multiple pixel circuit groups may include a first sub-pixel circuit group Z11, a second sub-pixel circuit group Z12, and a third sub-pixel circuit group Z13 arranged sequentially at intervals along the pixel row direction X1. That is, the second sub-pixel circuit group Z12 is closer to the first display area A1 than the first sub-pixel circuit group Z11 and the third sub-pixel circuit group Z13. Therefore, it can be determined that, compared to the first sub-pixel circuit group Z11 and the third sub-pixel circuit group Z13, the distance between each first pixel circuit 02 included in the second sub-pixel circuit group Z12 and the first light-emitting element 01 is closer, and the first connection trace L1 used for coupling each first pixel circuit 02 to the first light-emitting element 01 is shorter. Therefore, continue referring to... Figure 6 and Figure 7It can be seen that the capacitance values ​​of the compensation capacitors 03 corresponding to the first sub-pixel circuit group Z11 are smaller than the capacitance values ​​of the compensation capacitors 03 corresponding to the second sub-pixel circuit group Z12, and the capacitance values ​​of the compensation capacitors 03 corresponding to the second sub-pixel circuit group Z12 can be larger than the capacitance values ​​of the compensation capacitors 03 corresponding to the third sub-pixel circuit group Z13. That is, the capacitance values ​​of the compensation capacitors 03 required to be set decrease along the direction from the second sub-pixel circuit group Z12 towards the first sub-pixel circuit group Z11, and along the direction from the second sub-pixel circuit group Z12 towards the third sub-pixel circuit group Z13.

[0101] It should be noted that, Figure 6 and Figure 7 Taking the overlap area of ​​the first metal layer 031 and the second metal layer 032 as an example, the capacitance values ​​of the compensation capacitor 03 corresponding to different pixel circuit groups are shown. Furthermore, Figure 6 This is achieved by setting the second metal layer 032 to a "convex" shaped structure and setting the height of the first metal layer 031 corresponding to different pixel circuit groups to be the same, so that the overlapping area of ​​the first metal layer 031 and the second metal layer 032 in the compensation capacitor 03 corresponding to different pixel circuit groups Z1 is different. Figure 7 This is achieved by setting different heights for the first metal layer 031 corresponding to different pixel circuit groups Z1, and setting the second metal layer 032 to a rectangular structure, so that the overlap area of ​​the first metal layer 031 and the second metal layer 032 in the compensation capacitor 03 corresponding to different pixel circuit groups Z1 is different. Furthermore, Figure 6 and Figure 7 The specific structure of each pixel circuit group Z1 is not shown, and the first light-emitting element O1 included in the first display area A1 is not shown.

[0102] Combination Figure 6 and Figure 7 It can be determined that, in the embodiments disclosed herein, the overlap area of ​​the two metal layers can be changed by flexibly adjusting the structure of either of the two overlapping metal layers.

[0103] Optionally, in this embodiment of the disclosure, the display panel may include at least one compensation capacitor 03 corresponding to at least one first connection trace L1, and each compensation capacitor 03 is coupled to the target node P1 with a corresponding first connection trace L1. That is, each first connection trace L1 in the display panel is provided with a corresponding compensation capacitor 03.

[0104] Optional, Figure 8 This is a schematic diagram of another display panel structure provided in an embodiment of this disclosure. For example... Figure 8 As shown, the display panel includes at least one compensation capacitor 03, which may include a plurality of first group compensation capacitors 03A. Figure 8The specific structure of each pixel circuit group is not shown, and the first light-emitting element 01 included in the first display area A1 is not shown.

[0105] Figure 9 This is a schematic diagram of another display panel structure provided in an embodiment of this disclosure. For example... Figure 9 As shown, among the multiple first-group compensation capacitors 03A, at least one first-group compensation capacitor 03A may include an overlapping third metal layer 033 and a fourth metal layer 034. The third metal layer 033 can be coupled to the target node P1, and the fourth metal layer 034 can be coupled to the power supply terminal VSS. Thus, the overlapping of the third metal layer 033 and the fourth metal layer 034 can effectively form another compensation capacitor 03.

[0106] For example, Figure 9 Each of the first group of compensation capacitors 03A shown includes an overlapping third metal layer 033 and a fourth metal layer 034, and also includes an overlapping first metal layer 031 and a second metal layer 032.

[0107] In addition, continue to refer to Figure 8 It can be seen that at least one compensation capacitor 03 may also include multiple second-group compensation capacitors 03B and multiple third-group compensation capacitors 03C.

[0108] At least one first group of compensation capacitors 03A may further include overlapping first metal layers 031 and second metal layers 032. At least one second group of compensation capacitors 03B may include overlapping first metal layers 031 and second metal layers 032, as well as overlapping third metal layers 033 and fourth metal layers 034. At least one third group of compensation capacitors 03C may include overlapping first metal layers 031 and second metal layers 032, as well as overlapping third metal layers 033 and fourth metal layers 034. It should be noted that... Figure 9 Only the optional structure of the first set of compensation capacitors 03A is shown.

[0109] Optional, combined Figure 8 It can be seen that the multiple first-group compensation capacitors 03A can correspond to the first sub-pixel circuit group Z11, the multiple second-group compensation capacitors 03B can correspond to the second sub-pixel circuit group Z12, and the multiple third-group compensation capacitors 03C can correspond to the third sub-pixel circuit group Z13.

[0110] Thus, if the height of the first metal layer 031 along the pixel column direction X2 represents the overlap area of ​​the first metal layer 031 and the second metal layer 032, then refer to Figure 7 and Figure 10It can be seen that the height of the first metal layer 031 included in the second set of compensation capacitors 03B along the pixel column direction X2 can be greater than the height of the first metal layer 031 included in the third set of compensation capacitors 03C along the pixel column direction X2, and can also be greater than the height of the first metal layer 031 included in the first set of compensation capacitors 03A along the pixel column direction X2. That is, the height of the first metal layer 031 decreases along both the direction from the second set of compensation capacitors 03B towards the first set of compensation capacitors 03A and the direction from the second set of compensation capacitors 03B towards the third set of compensation capacitors 03C.

[0111] Optionally, as can be seen from the above embodiments, among the plurality of compensation capacitors 03 included in the display panel, at least some of each compensation capacitor 03 may be formed by overlapping first metal layers 031 and second metal layers 032. Alternatively, at least some of each compensation capacitor 03 may be formed by overlapping third metal layers 033 and fourth metal layers 034. Alternatively, at least some of each compensation capacitor 03 may be formed by overlapping first metal layers 031 and second metal layers 032, and by overlapping third metal layers 033 and fourth metal layers 034. That is, each compensation capacitor 03 may include two types of capacitors.

[0112] For example, combining Figure 9 The display panel shown includes each compensation capacitor 03 comprising: an overlapping first metal layer 031 and a second metal layer 032, and overlapping third and fourth metal layers 033 and 034. That is, each compensation capacitor 03 can include two types of capacitors formed by four metal layers. By setting a larger number of compensation capacitors 03, effective compensation of the capacitance value of the target node P1 can be further achieved.

[0113] Based on this, it can also be determined that the number of metal layers included in the compensation capacitor 03 can be adjusted according to the length of the first connection trace L1 to set the capacitance value of the compensation capacitor 03. Furthermore, based on the negative correlation between the length of the first connection trace L1 and the compensation capacitor 03, and the principle that the capacitance value increases when capacitors are connected in parallel, it can be known that the longer the length of the first connection trace L1, the more likely the compensation capacitor 03 will include only the overlapping first metal layer 031 and the second metal layer 032. The shorter the length of the first connection trace L1, the more likely the compensation capacitor 03 will include overlapping first metal layers 031 and 032, as well as overlapping third metal layers 033 and fourth metal layers 034.

[0114] For example, in Figure 1 Based on the structure shown, combined with Figure 9 The compensation capacitor 03 shown is... Figure 5An alternative circuit structure for capacitor c3 (i.e., compensation capacitor 03) formed by the overlapping of the third metal layer 033 and the fourth metal layer 034 is also shown. That is, in contrast... Figure 1 and Figure 5 As can be seen, an additional capacitor c3 is added at the target node P1 in this embodiment of the present disclosure.

[0115] Optionally, as can be seen from the above embodiments, in this embodiment of the disclosure, any two of the first metal layer 031, the second metal layer 032, the third metal layer 033, and the fourth metal layer 034 included in the compensation capacitor 03 can be located in different layers. Located in different layers can mean located in different layers.

[0116] Optional, see reference Figure 11 As shown in the structure, the pixel circuit in the display panel may include: an active layer P-Si, a first gate metal layer GATE1, a second gate metal layer GATE2, a first source / drain metal layer SD1, and a second source / drain metal layer SD2 arranged sequentially along a direction away from the substrate 00. It also includes a buffer layer BUFFER located between the active layer P-Si and the substrate 00, a first gate insulating layer GI1 located between the active layer P-Si and the first gate metal layer GATE1, a second gate insulating layer GI2 located between the first gate metal layer GATE1 and the second gate metal layer GATE2, an interlayer stabilizing layer ILD located between the second gate metal layer GATE2 and the first source / drain metal layer SD1, and a passivation layer PVX located between the first source / drain metal layer SD1 and the second source / drain metal layer SD2. The first source / drain metal layer SD1 is coupled to the active layer P-Si.

[0117] In this embodiment of the disclosure, in each compensation capacitor 03, the first metal layer 031 may be located in the same layer as one of the first gate metal layers GATE1 and the second gate metal layer GATE2, and the second metal layer 032 may be located in the same layer as the other gate metal layer of the first gate metal layer GATE1 and the second gate metal layer GATE2. The third metal layer 033 may be located in the same layer as one of the first source-drain metal layers SD1 and the second source-drain metal layer SD2, and the fourth metal layer 034 may be located in the same layer as the other source-drain metal layer of the first source-drain metal layer SD1 and the second source-drain metal layer SD2.

[0118] For example, refer to Figure 9As can be seen, in this embodiment, the first metal layer 031 can be located on the same layer as the first gate metal layer GATE1, and the second metal layer 032 can be located on the same layer as the second gate metal layer GATE2. The third metal layer 033 can be located on the same layer as the first source / drain metal layer SD1, and the fourth metal layer 034 can be located on the same layer as the second source / drain metal layer SD2. In other words, each compensation capacitor 03 may include: a capacitor formed by the overlap of the first gate metal layer GATE1 and the second gate metal layer GATE2, and another capacitor formed by the overlap of the first source / drain metal layer SD1 and the second source / drain metal layer SD2.

[0119] Being in the same layer can refer to a layer structure formed by using the same film deposition process to create a film layer for a specific pattern, and then using the same photomask to pattern that film layer in a single patterning process. Depending on the specific pattern, the single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the resulting layer structure can be continuous or discontinuous. In other words, multiple elements, components, structures, and / or parts located in the same layer are made of the same material and formed through the same single patterning process.

[0120] By setting the metal layer of the compensation capacitor 03 to be located on the same layer as the metal layer in the pixel circuit, the process can be simplified and costs can be saved. Of course, in some embodiments, a metal layer independent of the pixel circuit can also be set to form the compensation capacitor described in the above embodiments.

[0121] by Figure 9 Taking the structure shown as an example, Figure 12 This diagram shows a partial structural layout of a compensation capacitor in a display panel. Figure 13 This diagram shows another part of the structural layout of a compensation capacitor in a display panel.

[0122] Optional, see reference Figure 9 , Figure 12 and Figure 13 As can be seen from the embodiments disclosed herein, the second metal layer 032 included in each compensation capacitor 03 can be an integral structure. That is, each compensation capacitor 03 can share a single second metal layer 032. Similarly, the fourth metal layer 034 included in each compensation capacitor 03 can also be an integral structure. That is, each compensation capacitor 03 can share a single fourth metal layer 034.

[0123] Furthermore, refer to Figure 13It can also be seen that the second metal layer 032 and the fourth metal layer 034 can be coupled to the power supply terminal VSS through the same adapter hole K0. Since the second metal layer 032 and the fourth metal layer 034 are coupled to the power supply terminal VSS, by setting only one second metal layer 032 and / or only one fourth metal layer 034, the structure can be simplified, costs can be saved, and the narrow bezel design of the display panel can be facilitated while ensuring effective compensation.

[0124] Of course, in some embodiments, the second metal layers 032 included in each compensation capacitor 03 may also be independent of each other and arranged at intervals. The fourth metal layers 034 included in each compensation capacitor 03 may also be independent of each other and arranged at intervals. This disclosure does not limit this aspect.

[0125] in, Figure 13 The diagram also shows two signal lines l1 and l2 that are coupled to the clock signal terminal in the pixel circuit. These two signal lines l1 and l2 are generally located between the compensation capacitor 03 and the multiple first pixel circuits 02.

[0126] Optional, combined Figure 12 and Figure 13 It can be seen that the first metal layers 031 included in each compensation capacitor 03 can be arranged at intervals along the pixel row direction X1. That is, the first metal layers 031 included in each compensation capacitor 03 can be independent of each other. The third metal layers 033 included in each compensation capacitor 03 can also be arranged at intervals along the pixel row direction X1. That is, the third metal layers 033 included in each compensation capacitor 03 can also be independent of each other.

[0127] Furthermore, combined Figure 9 and Figure 12 It can also be seen that, in the embodiments disclosed herein, the orthographic projection of the first metal layer 031 on the substrate 00 and the orthographic projection of the third metal layer 033 on the substrate 00 can both be strip-shaped structures. Furthermore, this strip-shaped structure can extend along the pixel column direction X2 and be coupled to the target node P1.

[0128] Of course, in some embodiments, the first metal layer 031 and the third metal layer 033 may not overlap, and the first metal layer 031 and the third metal layer 033 may also be in other shapes, such as ellipses.

[0129] Optional, continue to refer to Figure 12 and Figure 14 As can be seen from the structure of another display panel shown, the display panel may further include at least one second connection trace L2 located in the peripheral area A3. Both the first metal layer 031 and the third metal layer 033 can be coupled to the target node P1 through the second connection trace L2.

[0130] Example, combination Figure 12and Figure 14 It can be seen that the first metal layer 031 and the second connection trace L2 can be coupled through the first via K1, and the third metal layer 033 and the first metal layer 031 can be coupled through the second via K2. Of course, in some embodiments, the third metal layer 033 can also be coupled to the second connection trace L2 through the first via K1, and the first metal layer 031 can be coupled to the third metal layer 033 through the second via K2. That is, in this embodiment, one of the first metal layer 031 and the third metal layer 033 can be directly coupled to the second connection trace L2, and another metal layer other than the target metal layer can be directly coupled to that target metal layer. That is, for the other metal layer besides the target metal layer, its coupling with the second connection trace L2 can be indirect. In some embodiments, a portion of the first metal layer 031 and the second connection trace L2 can be coupled through the first via K1, and another portion of the third metal layer 033 can be coupled to the second connection trace L2 through the first via K1.

[0131] Optional, combined Figure 9 The second connection traces L2 included in the display panel can be located on the same layer as the second source / drain metal layer SD2 included in the pixel circuit. This simplifies the structure and saves costs.

[0132] by Figure 14 Taking the structure shown as an example, Figure 15 This illustrates a partial structural layout of a display panel. (Combined with...) Figure 12 , Figure 14 and Figure 15 It can be seen that in each compensation capacitor 03, the first metal layer 031 and the third metal layer 033 can be coupled to one end of the second connection trace L2 through a first via K1, and the other end of the second connection trace L2 is then coupled to the target node P1. Furthermore, combined with... Figure 12 , Figure 14 and Figure 15 It can be seen that each of the first vias K1 can be arranged sequentially at intervals along the pixel row direction X1, and each of the second vias K2 can also be arranged sequentially at intervals along the pixel row direction X1.

[0133] Optional, see reference Figure 16 As can be seen from the display panel shown, in this embodiment of the present disclosure, the display panel may further include: a first planarization layer PLN1, a second planarization layer PLN2 and a third planarization layer PLN3 arranged sequentially along the direction away from the substrate 00 along the first via K1.

[0134] The orthographic projection of the first planarization layer PLN1 on the substrate 00 can cover the orthographic projection of the first via K1 on the substrate 00, the orthographic projection of the second planarization layer PLN2 on the substrate 00 can cover the orthographic projection of the first via K1 on the substrate 00, and the orthographic projection of the third planarization layer PLN3 on the substrate 00 can be non-overlapping with the orthographic projection of the first via K1 on the substrate 00.

[0135] Optional, continue to refer to Figure 16 It can be seen that the first planarization layer PLN1, the second planarization layer PLN2 and the third planarization layer PLN3 can all be located on the side of the second connection trace L2 away from the substrate 00.

[0136] Thus, compared to the existing technology where the first planarization layer PLN1, the second planarization layer PLN2, and the third planarization layer PLN3 all cover the first via K1, the problem of trace breakage caused by the large stacking difference between the first planarization layer PLN1, the second planarization layer PLN2, and the third planarization layer PLN3 can be avoided.

[0137] Figure 17 This is a schematic diagram of the structure of another display panel provided in an embodiment of this disclosure. (In conjunction with...) Figure 14 and Figure 17 It can be seen that the peripheral area A3 may include: a first area A31 and a second area A32 arranged along the pixel column direction X2, and the second area A32 is closer to the second display area A2 than the first area A31.

[0138] Optionally, given that the peripheral area A3 is divided into a first area A31 and a second area A32, each first pixel circuit 02 in the display panel can be located in the second area A32, and each compensation capacitor 03 in the display panel can be located in the first area A31.

[0139] Combination Figure 14 and Figure 17 It can be seen that this configuration facilitates the coupling of the first pixel circuit 02 and the first light-emitting element 01, minimizes the length of the first connection trace L1, saves wiring costs, and simplifies wiring. Combined with... Figure 17 As can be seen from the structure shown, the multiple first pixel circuits 02 and compensation capacitors 03 shown can actually be considered to be located on the upper edge of the display panel.

[0140] In addition, Figure 17 Under the premise of the structure shown, and then refer to Figure 12 and 14It can also be seen that the first via K1 described in the above embodiment can be located in the third region A33 of the peripheral region A3, and the third region A33 can be located between the first region A31 and the second region A32 of the peripheral region A3. The second via K2 described in the above embodiment can be located in the first region A31 of the peripheral region A3.

[0141] Optionally, to further ensure good light transmittance of the first display area A1, the first connection trace L1 described in this embodiment can be a transparent conductive line. For example, the first connection trace L1 can be made of transparent materials such as indium tin oxide (ITO) or indium gallium zinc oxide (IGZO). If the first connection trace L1 is made of ITO material, then the first connection trace L1 can also be called an ITO trace.

[0142] Optionally, as can be seen from the above figures, the display panel may generally include multiple first connection traces L1, and at least two of the multiple first connection traces L1 may be located on different layers.

[0143] For example, Figure 18 This is a schematic diagram of a display panel structure including a first connecting trace L1, provided by an embodiment of this disclosure. Figure 17 As shown, multiple first connection traces L1 may include at least one first-type first connection trace L1_1 located on the same layer, at least one second-type first connection trace L1_2 located on the same layer, and at least one third-type first connection trace L1_3 located on the same layer. Combined with... Figure 18 It can be further determined that the lengths of the L1 traces in different first connections are generally different.

[0144] Among the first-type first-connection traces L1_1, L1_2, and L1_3, any two of the first-type first-connection traces L1 can be located on different layers. This facilitates routing. For example, refer to... Figures 19 to 21 It can be seen that the first type of first connection trace L1_1 can be located on the same layer as the metal layer M1, the second type of first connection trace L1_2 can be located on the same layer as the metal layer M2, and the third type of first connection trace L1_3 can be located on the same layer as the metal layer M3.

[0145] Optionally, the metal layers M1 to M3 can be located on the same layer as the metal layers in the display panel, or they can be separate, additional metal layers.

[0146] Optionally, the first display area A1 can be divided into three regions according to the pixel column direction and / or pixel row direction. Within one region, each first light-emitting element 01 can be coupled to the first pixel circuit 02 via a first type of first connection trace L1_1. Each first light-emitting element 01 within one region can be coupled to the first pixel circuit 02 via a second type of first connection trace L1_2. Each first light-emitting element 01 within one region can be coupled to the first pixel circuit 02 via a third type of first connection trace L1_3.

[0147] Optionally, taking the display panel described in the above embodiments as an example, Figure 22 A partial layout of the overall structure of a display panel is shown. (Reference) Figure 22 It can be further seen that the via that couples the compensation capacitor 03 to the second connection trace L2 is located in the third region A33 of the peripheral area A3.

[0148] In summary, this disclosure provides a display panel including a first light-emitting element located in a first display area, and a first pixel circuit and a compensation capacitor located in a peripheral area. The first pixel circuit can be coupled to the first light-emitting element via a first connection trace. The first metal layer in the compensation capacitor can be coupled to a target node, and the second metal layer can be coupled to a power supply terminal. The target node is the node where the first connection trace and the first pixel circuit are coupled. This effectively compensates for parasitic capacitance on the first connection trace, ensuring good uniformity of brightness for each first light-emitting element in the first display area. Consequently, the display panel exhibits better display performance.

[0149] Figure 23 This is a schematic diagram of the structure of a display device provided in an embodiment of this disclosure. Figure 23 As shown, the display device may include: a photosensor 10, and a display panel 000 as shown in the above figures. The photosensor 10 may be located within a first display area A1 of the display panel 000.

[0150] Optionally, the first display area A1 can be Figure 23 The rectangular area shown indicates that the area of ​​the orthographic projection of the photosensitive sensor 10 onto the substrate 00 can be less than or equal to the area of ​​the inscribed circle of the first display area A1. That is, the size of the area where the photosensitive sensor 10 is located can be less than or equal to the size of the inscribed circle of the first display area A1. For example, combined with... Figure 23 In the display panel shown, the size of the area where the photosensitive sensor 10 is located is equal to the size of the inscribed circle Y0 of the first display area A1. That is, the shape of the area where the photosensitive sensor 10 is located can be circular, and correspondingly, the area where the photosensitive sensor 10 is located can also be called a light-transmitting hole. Of course, in some embodiments, the first display area A1 can also be other shapes besides rectangles, such as circles.

[0151] Optionally, the display device can be any product or component with display function, such as an OLED display device, an active-matrix organic light-emitting diode (AMOLED) display device, a mobile phone, a tablet computer, a flexible display device, a television, or a monitor.

[0152] The terminology used in the embodiments of this disclosure is for the purpose of explaining the embodiments of this disclosure only and is not intended to limit this disclosure. Unless otherwise defined, the technical or scientific terms used in the embodiments of this disclosure should be understood in their ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains.

[0153] The terms "first," "second," "third," and similar words used in this patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms "an" or "a" do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms "comprising" or "including" mean that the elements or objects preceding "comprising" encompass the elements or objects listed after "comprising" or "including" and their equivalents, and do not exclude other elements or objects. "Above," "below," "left," "right," etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0154] In this article, "and / or" indicates that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0155] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the display substrate and display device described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0156] The above description is merely an optional embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A display panel, the display panel comprising: A substrate has a first display area, a second display area, and a peripheral area, wherein the second display area at least partially surrounds the first display area, and the peripheral area at least partially surrounds the second display area. Multiple first light-emitting elements are located in the first display area; Multiple first pixel circuits are located in the peripheral area; A plurality of second pixel circuits and a plurality of second light-emitting elements are located in the second display area, wherein at least one of the plurality of second pixel circuits is coupled to at least one of the plurality of second light-emitting elements; At least one first connection trace is located in the peripheral area, the second display area and the first display area, and at least one first pixel circuit among the plurality of first pixel circuits is coupled to at least one first light-emitting element among the plurality of first light-emitting elements through the first connection trace; At least one compensation capacitor is located in the peripheral area. The compensation capacitor includes an overlapping first metal layer and a second metal layer. The first metal layer is coupled to a target node, and the second metal layer is coupled to a power supply terminal. The target node is the node where the first pixel circuit is coupled to the first connection trace.

2. The display panel according to claim 1, wherein, The capacitance value of the compensation capacitor corresponding to each of the first pixel circuits is negatively correlated with the length of the first connection trace to which it is coupled.

3. The display panel according to claim 2, wherein, In each of the compensation capacitors corresponding to the first pixel circuit, the overlapping area of ​​the two overlapping metal layers is negatively correlated with the length of the coupled first connection trace.

4. The display panel according to any one of claims 1 to 3, wherein, The display panel includes: a plurality of pixel circuit groups, each pixel circuit group including: at least two first pixel circuits; In this context, the capacitance values ​​of the compensation capacitors corresponding to each pixel circuit group are the same, while the capacitance values ​​of the compensation capacitors corresponding to different pixel circuit groups are different.

5. The display panel according to claim 4, wherein, The plurality of pixel circuit groups include: a first sub-pixel circuit group, a second sub-pixel circuit group, and a third sub-pixel circuit group arranged at intervals along the pixel row direction; Wherein, the capacitance value of each compensation capacitor corresponding to the first sub-pixel circuit group is less than the capacitance value of each compensation capacitor corresponding to the second sub-pixel circuit group, and the capacitance value of each compensation capacitor corresponding to the second sub-pixel circuit group is greater than the capacitance value of each compensation capacitor corresponding to the third sub-pixel circuit group.

6. The display panel according to any one of claims 1-3 and 5, wherein, The peripheral area includes: a first area and a second area arranged along the pixel column direction, wherein the second area is closer to the second display area than the first area; Each of the first pixel circuits is located in the first region, and each of the compensation capacitors is located in the second region.

7. The display panel according to any one of claims 1-3 and 5, wherein, The display panel includes a plurality of the compensation capacitors, each of the compensation capacitors having a second metal layer that is an integral structure, and each of the compensation capacitors having a first metal layer that is spaced apart along the pixel row direction.

8. The display panel according to any one of claims 1-3 and 5, wherein, The at least one compensation capacitor includes a plurality of first group compensation capacitors, and at least one of the plurality of first group compensation capacitors includes an overlapping third metal layer and a fourth metal layer, wherein any two of the first metal layer, the second metal layer, the third metal layer and the fourth metal layer are located in different layers. The third metal layer is coupled to the target node, and the fourth metal layer is coupled to the power supply terminal.

9. The display panel according to claim 8, wherein, The at least one compensation capacitor further includes: a plurality of second-group compensation capacitors and a plurality of third-group compensation capacitors; At least one of the plurality of first-group compensation capacitors further includes overlapping first metal layers and second metal layers; at least one of the plurality of second-group compensation capacitors further includes overlapping first metal layers and second metal layers; and at least one of the plurality of third-group compensation capacitors further includes overlapping first metal layers and second metal layers. The plurality of first-group compensation capacitors, the plurality of second-group compensation capacitors, and the plurality of third-group compensation capacitors are arranged sequentially at intervals along the pixel row direction, and the height of the first metal layer included in the second-group compensation capacitor along the pixel column direction is greater than the height of the first metal layer included in the third-group compensation capacitor along the pixel column direction, and is also greater than the height of the first metal layer included in the second-group compensation capacitor along the pixel column direction.

10. The display panel according to claim 8, wherein, The pixel circuit in the display panel includes: an active layer, a first gate metal layer, a second gate metal layer, a first source / drain metal layer and a second source / drain metal layer arranged sequentially along a direction away from the substrate. Wherein, the first metal layer is located in the same layer as one of the first gate metal layer and the second gate metal layer, and the second metal layer is located in the same layer as the other of the first gate metal layer and the second gate metal layer; The third metal layer is located in the same layer as one of the first and second source / drain metal layers, and the fourth metal layer is located in the same layer as the other of the first and second source / drain metal layers.

11. The display panel according to claim 10, wherein, The first metal layer and the first gate metal layer are located in the same layer, and the second metal layer and the second gate metal layer are located in the same layer.

12. The display panel according to claim 10, wherein, The third metal layer is located in the same layer as the first source / drain metal layer, and the fourth metal layer is located in the same layer as the second source / drain metal layer.

13. The display panel according to any one of claims 9-12, wherein, Each of the compensation capacitors includes: overlapping first metal layers and second metal layers, and overlapping third metal layers and fourth metal layers.

14. The display panel according to any one of claims 9-12, wherein, Each of the compensation capacitors includes a fourth metal layer as an integral structure, and each of the compensation capacitors includes a third metal layer arranged at intervals along the pixel row direction.

15. The display panel according to any one of claims 9-12, wherein, The orthographic projection of the first metal layer on the substrate and the orthographic projection of the third metal layer on the substrate are both strip-shaped structures, and the strip-shaped structures extend along the pixel column direction.

16. The display panel according to any one of claims 9-12, wherein, The display panel also includes: At least one second connection trace is located in the surrounding area, and both the first metal layer and the third metal layer are coupled to the target node through the second connection trace.

17. The display panel according to claim 16, wherein, The peripheral area includes: a first area, a third area, and a second area arranged along the pixel column direction, wherein the second area is closer to the second display area than the first area; the first metal layer and the second connection trace are coupled through a first via, and the third metal layer and the first metal layer are coupled through a second via; The first via is located in the third region of the peripheral area, and the second via is located in the first region of the peripheral area.

18. The display panel according to claim 17, wherein, The display panel further includes: a first planarization layer, a second planarization layer, and a third planarization layer arranged sequentially along the direction away from the substrate along the first via; Wherein, the orthographic projection of the first planarization layer on the substrate covers the orthographic projection of the first via on the substrate, the orthographic projection of the second planarization layer on the substrate covers the orthographic projection of the first via on the substrate, and the orthographic projection of the third planarization layer on the substrate does not overlap with the orthographic projection of the first via on the substrate.

19. The display panel according to claim 18, wherein, The first planarization layer, the second planarization layer, and the third planarization layer are all located on the side of the second connection trace away from the substrate.

20. The display panel according to any one of claims 17-19, wherein, The second connection trace is located on the same layer as the second source / drain metal layer included in the pixel circuit of the display panel.

21. The display panel according to any one of claims 1-3, 5, 9-12, 17-19, wherein, The display panel includes at least one compensation capacitor corresponding to one of the at least one first connection trace; Each of the compensation capacitors is coupled to the target node along with a corresponding first connection trace.

22. The display panel according to any one of claims 1-3, 5, 9-12, 17-19, wherein, The display panel includes multiple first connection traces, and at least two of the multiple first connection traces are located on different layers.

23. The display panel according to claim 22, wherein, The plurality of first connection traces include at least one first type of first connection trace located on the same layer, at least one second type of first connection trace located on the same layer, and at least one third type of first connection trace located on the same layer. Furthermore, any two of the first type of first connection traces, the second type of first connection traces, and the third type of first connection traces are located on different layers.

24. The display panel according to any one of claims 1-3, 5, 9-12, 17-19, 23, wherein, The first connection trace is a transparent conductive line.

25. A display device, wherein, The display device includes: a photosensor, and a display panel as described in any one of claims 1 to 24; The photosensor is located in the first display area of ​​the display panel.

Images