Display substrate and display device

Abstract

A display substrate and a display device. The display substrate includes a base substrate and a plurality of sensing signal lines. The base substrate includes a display area, the display area includes a plurality of repeating units arranged in an array, each of the plurality of repeating units includes a transparent area and a pixel area arranged along a first direction. Two rows of repeating units are arranged between two adjacent ones of the plurality of sensing signal lines, the two rows of repeating units extend along a second direction, each of the plurality of sensing signal lines is connected to a sub-pixel driving circuit of a plurality of sub-pixels adjacent to it and respectively along the two rows of repeating units, and is configured to provide a reference voltage signal. The display substrate can reduce the wiring space and improve the light transmittance of the display.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a display substrate and a display device. Background Art

[0002] In the display field, the market demand for large-size high PPI (Pixels Per Inch) transparent display devices is increasing. Transparent display devices can be used in applications such as vehicles, smart homes, and store windows. At the same time, the development of transparent display technology can effectively expand the application field of OLED (Organic Light-Emitting Diode). Summary of the invention

[0003] At least one embodiment of the present disclosure provides a display substrate, which includes a substrate substrate and a plurality of sensing signal lines. The substrate substrate includes a display area, wherein the display area includes a plurality of repeating units arranged in an array, each of the plurality of repeating units includes a transparent area and a pixel area arranged along the first direction, the pixel area includes a plurality of sub-pixels, each of the plurality of sub-pixels includes a sub-pixel driving circuit and a light-emitting element, the light-emitting element is located on a side of the sub-pixel driving circuit away from the substrate substrate, and the sub-pixel driving circuit is configured to drive the light-emitting element to emit light; a plurality of sensing signal lines are arranged on the substrate substrate and extend along a second direction, wherein two rows of the repeating units are arranged between two adjacent ones of the plurality of sensing signal lines, the two rows of the repeating units extend along the second direction, each of the plurality of sensing signal lines is connected to the sub-pixel driving circuits of the plurality of sub-pixels adjacent to it and respectively along the two rows of the repeating units, and is configured to provide a reference voltage signal.

[0004] For example, the display substrate provided by at least one embodiment of the present disclosure also includes a plurality of power lines, wherein the plurality of power lines are arranged on the base substrate and extend along the second direction, in the first direction, the plurality of power lines and the plurality of sensing signal lines are alternately arranged, a row of the repeating units extending along the second direction is arranged between each of the plurality of sensing signal lines and the power line adjacent thereto, two rows of the repeating units respectively extending along the second direction are arranged between two adjacent ones of the plurality of power lines, each of the plurality of power lines is connected to the sub-pixel driving circuits of the plurality of sub-pixels of the two rows of the repeating units adjacent thereto and respectively extending along the second direction, and is configured to provide a first power supply voltage.

[0005] For example, the display substrate provided by at least one embodiment of the present disclosure also includes a peripheral area, a gate driving circuit, and a plurality of gate lines extending along the first direction, the peripheral area at least partially surrounds the display area, the gate driving circuit is located in the peripheral area, the plurality of gate lines are connected to the gate driving circuit and to the sub-pixel driving circuits of the pixel areas of the rows of the repeating units respectively extending along the first direction, the gate driving circuit is configured to output gate scanning signals one by one to drive the plurality of sub-pixels of the pixel areas of the rows of the repeating units respectively extending along the first direction, the plurality of repeating units are arranged into N rows respectively extending along the first direction, the gate driving circuit includes N cascaded shift register units, the nth stage shift register unit is connected to the sub-pixel driving circuits of the pixel areas of the nth row of repeating units, wherein 1≤n≤N, and N is an integer greater than or equal to 2.

[0006] For example, in the display substrate provided by at least one embodiment of the present disclosure, a plurality of sub-pixel driving circuits in each pixel area are arranged along the first direction, each of the sub-pixel driving circuits includes a data writing circuit, a driving circuit, a charge storage circuit and a sensing circuit, the driving circuit is connected to a first node, a second node and a third node, the third node is also connected to a first power supply voltage terminal, the first power supply voltage terminal is connected to the power line, the driving circuit is configured to receive the first power supply voltage through the third node, and control the driving current flowing through the light-emitting element under the control of the level of the first node; the data writing circuit is connected to the first node, and is configured to receive the gate scanning signal as a scanning driving signal, and respond to the gate scanning signal. The data signal is written into the first node in response to the scanning drive signal; the charge storage circuit is connected to the first node and the second node, and is configured to store the written data signal and the reference voltage signal; the sensing circuit is connected to the second node, and is configured to receive the gate scanning signal as the sensing drive signal, the sensing circuit is also connected to the sensing signal line and is configured to receive the reference voltage signal, and writes the reference voltage signal into the drive circuit or reads the sensing voltage signal from the drive circuit in response to the sensing drive signal; the light-emitting element is connected to the second node and the second power supply voltage terminal, and is configured to receive the second power supply voltage through the second power supply voltage terminal, and emit light under the drive of the driving current.

[0007] For example, in a display substrate provided in at least one embodiment of the present disclosure, the plurality of gate lines include a first gate line and a second gate line, and the first gate line is connected to a data writing circuit of a plurality of sub-pixel driving circuits in a pixel area of ​​an M-th row of repeating units extending along the first direction, a sensing circuit of a plurality of sub-pixel driving circuits in a pixel area of ​​an M-1-th row of repeating units extending along the first direction, and an output end of an M-th shift register unit, so as to output a gate scanning signal outputted from the output end of the M-th shift register unit to the data writing circuit of the plurality of sub-pixel driving circuits in the pixel area of ​​the M-th row of repeating units as a scanning driving signal, and to the sensing circuit of the plurality of sub-pixel driving circuits in the pixel area of ​​the M-1-th row of repeating units. The sensing circuit is used as a sensing drive signal, and the second gate line is connected to the sensing circuit of the multiple sub-pixel driving circuits in the pixel area of ​​the Mth row of repeating units, the data writing circuit of the multiple sub-pixel driving circuits in the pixel area of ​​the M+1th row of repeating units extending along the first direction, and the output end of the M+1th shift register unit, so as to output the gate scanning signal output by the output end of the M+1th shift register unit to the data writing circuit of the multiple sub-pixel driving circuits in the pixel area of ​​the M+1th row of repeating units as a scanning drive signal, and to the sensing circuit of the multiple sub-pixel driving circuits in the pixel area of ​​the Mth row of repeating units as the sensing drive signal, wherein 1<M<N, and M is an integer.

[0008] For example, in the display substrate provided in at least one embodiment of the present disclosure, the data writing circuit includes a data writing transistor, the driving circuit includes a driving transistor, the sensing circuit includes a sensing transistor, the active layer of the data writing transistor, the active layer of the driving transistor and the active layer of the sensing transistor extend along the second direction, and the base substrate is a flexible substrate.

[0009] For example, the display substrate provided by at least one embodiment of the present disclosure further includes a semiconductor layer, a first conductive layer, a second conductive layer, a second insulating layer and a fourth insulating layer located on the base substrate, the second conductive layer is located on a side of the semiconductor layer away from the base substrate, the fourth insulating layer is located between the second conductive layer and the semiconductor layer, the first conductive layer is located on a side of the second conductive layer away from the base substrate, the second insulating layer is located between the second conductive layer and the first conductive layer, the semiconductor layer includes an active layer of the data write transistor, an active layer of the drive transistor and an active layer of the sensing transistor, each of the multiple power lines includes a first sub-line located in the second conductive layer and a second sub-line located in the first conductive layer, the first sub-line includes a plurality of first routing segments extending along the second direction, the plurality of first routing segments are respectively located in different repeating units, the second sub-line passes through the display area, the second sub-line is stacked on a side of the first sub-line away from the base substrate, and is connected to the first sub-line through at least one first via hole penetrating the second insulating layer.

[0010] For example, in the display substrate provided in at least one embodiment of the present disclosure, each of the multiple sensing signal lines includes a third sub-line located in the second conductive layer and a fourth sub-line located in the first conductive layer, the third sub-line includes a plurality of second routing segments extending along the second direction, and the plurality of second routing segments are distributed in different repeating units, the fourth sub-line passes through the display area, the fourth sub-line is stacked on a side of the third sub-line away from the base substrate, and is connected to the third sub-line through at least one second via hole penetrating the second insulating layer.

[0011] For example, in the display substrate provided in at least one embodiment of the present disclosure, the display area includes a first repeating unit and a second repeating unit adjacently arranged along a first direction, a sensing signal line is arranged between the pixel area of ​​the first repeating unit and the transparent area of ​​the second repeating unit, the sensing signal line is connected to a plurality of sub-pixel driving circuits in the pixel areas of the first repeating unit and the second repeating unit, a power line is arranged on a side of the pixel area of ​​the second repeating unit away from the transparent area of ​​the second repeating unit, the power line is connected to a plurality of sub-pixel driving circuits in the pixel area of ​​the second repeating unit, another power line is arranged on a side of the transparent area of ​​the first repeating unit away from the pixel area of ​​the first repeating unit, the other power line is connected to a plurality of sub-pixel driving circuits in the pixel area of ​​the first repeating unit. The pixel driving circuits are connected, the multiple sub-pixel driving circuits in the pixel area of ​​the first repeating unit and the multiple sub-pixel driving circuits in the pixel area of ​​the second repeating unit respectively include a first sub-pixel driving circuit, a second sub-pixel driving circuit and a third sub-pixel driving circuit arranged in the first direction, the first conductive layer includes a first switching electrode extending along the first direction, a first electrode and a second electrode of the sensing transistor, a first end of the first switching electrode is connected to the first electrode of the sensing transistor of the third sub-pixel driving circuit of the first repeating unit, and a second end of the first switching electrode is connected to the first electrode of the sensing transistor of the first sub-pixel driving circuit of the second repeating unit, wherein the first switching electrode is cross-connected with the second sub-line of the sensing signal line.

[0012] For example, in the display substrate provided in at least one embodiment of the present disclosure, the second conductive layer includes a first connecting trace extending along the first direction, and the first connecting trace is connected to the first sub-pixel driving circuit, the second sub-pixel driving circuit and the first electrode of the sensing transistor of the third sub-pixel driving circuit of the first repeating unit or the second repeating unit through at least a portion of the third via hole, and at least a portion of the orthographic projection of the first electrode of the sensing transistor of the first sub-pixel driving circuit, the second sub-pixel driving circuit and the third sub-pixel driving circuit on the board surface of the base substrate overlaps with the orthographic projection of the first connecting trace on the board surface of the base substrate.

[0013] For example, in the display substrate provided in at least one embodiment of the present disclosure, the first electrode of the sensing transistor includes a first sub-portion and a second sub-portion connected along the second direction, a portion of the third via is configured to penetrate the second insulating layer and the fourth insulating layer to expose the active layer of the sensing transistor, another portion of the third via is configured to penetrate the second insulating layer to expose the first connecting trace, the first sub-portion is in contact with the active layer of the sensing transistor, and the second sub-portion is in contact with the first connecting trace.

[0014] For example, in the display substrate provided in at least one embodiment of the present disclosure, the charge storage circuit includes a storage capacitor, the semiconductor layer also includes a first electrode plate of the storage capacitor, the first conductive layer also includes a second electrode plate of the storage capacitor, the second electrode of the sensing transistor is connected to an end of the second electrode plate close to the sensing transistor, and the second electrode of the sensing transistor is integrally arranged with the second electrode plate.

[0015] For example, in the display substrate provided by at least one embodiment of the present disclosure, in the second direction, the data write transistor and the drive transistor are located on a side of the storage capacitor away from the sensing transistor, the drive transistor is located between the data write transistor and the storage capacitor, the first conductive layer also includes a first pole and a second pole of the data write transistor, a first pole and a second pole of the drive transistor, a second switching electrode and a third switching electrode, the second switching electrode and the third switching electrode respectively include the third node, the second pole of the drive transistor is located on a side of the drive transistor away from the storage capacitor, one end of the second switching electrode is connected to the second electrode of the drive transistor of the third sub-pixel drive circuit of the second repeating unit, and the other end of the second switching electrode is connected to a power line of the third sub-pixel drive circuit close to the second repeating unit, one end of the third switching electrode is connected to the second pole of the drive transistor of the first sub-pixel drive circuit of the first repeating unit, and the other end of the third switching electrode is connected to a power line of the transparent area close to the first repeating unit.

[0016] For example, in the display substrate provided in at least one embodiment of the present disclosure, the second conductive layer includes a second connecting trace extending along the first direction, and the second connecting trace is connected to the second electrodes of the driving transistors of the first sub-pixel driving circuit, the second sub-pixel driving circuit and the third sub-pixel driving circuit of the first repeating unit or the second repeating unit through at least a portion of the fourth via hole, and at least a portion of the orthographic projection of the second electrodes of the driving transistors of the first sub-pixel driving circuit, the second sub-pixel driving circuit and the third sub-pixel driving circuit on the surface of the base substrate overlaps with the orthographic projection of the second connecting trace on the surface of the base substrate.

[0017] For example, in the display substrate provided in at least one embodiment of the present disclosure, the first electrode of the driving transistor is connected to an end of the second electrode plate of the storage capacitor away from the sensing transistor, and the first electrode of the driving transistor and the second electrode plate are integrally arranged, and the first electrode plate of the storage capacitor is connected to the active layer of the driving transistor and is integrally arranged.

[0018] For example, in the display substrate provided in at least one embodiment of the present disclosure, the first electrode plate and the second electrode plate of the storage capacitor include strips extending along the second direction, the display substrate also includes a filter layer, the filter layer is located on the side of the light-emitting element away from the base substrate, the filter layer includes a first sub-pixel filter area, a second sub-pixel filter area and a third sub-pixel filter area, in each of the repeating units, the first sub-pixel filter area, the second sub-pixel filter area and the third sub-pixel filter area are arranged in sequence along the second direction, the second sub-pixel filter area is located between the first sub-pixel filter area and the third sub-pixel filter area, The first sub-pixel filter region overlaps with at least a portion of the sensing transistors of the multiple sub-pixel driving circuits of the pixel region, and a portion of the storage capacitor close to the sensing transistor, on the board surface of the substrate; the third sub-pixel filter region overlaps with at least a portion of the data writing transistors and the driving transistors of the multiple sub-pixel driving circuits of the pixel region, and a portion of the storage capacitor close to the driving transistor, on the board surface of the substrate; the second sub-pixel filter region overlaps with a portion of the storage capacitor of the multiple sub-pixel driving circuits of the pixel region close to the middle thereof in the first direction, on the board surface of the substrate;

[0019] For example, the display substrate provided by at least one embodiment of the present disclosure further includes a third insulating layer and a pixel defining layer, the third insulating layer is located on a side of the first conductive layer away from the base substrate, the light-emitting element is located on a side of the third insulating layer away from the base substrate, the light-emitting element of each of the plurality of sub-pixels includes a first electrode, a second electrode and a light-emitting layer located between the first electrode and the second electrode, the pixel defining layer is configured to define a light-emitting area of ​​the light-emitting element, the plurality of light-emitting elements of each of the repeating units includes a first light-emitting element, a second light-emitting element and a third light-emitting element, the first light-emitting element, the second light-emitting element and the third light-emitting element are respectively connected to the first sub-pixel The pixel filter area, the second sub-pixel filter area and the third sub-pixel filter area are correspondingly arranged, the display substrate further includes a fifth via hole, a sixth via hole and a seventh via hole that at least penetrate the third insulating layer, the fifth via hole, the sixth via hole and the seventh via hole are configured to expose the first sub-pixel driving circuit, the second sub-pixel driving circuit and the third sub-pixel driving circuit, the first electrode of the first light-emitting element is connected to the first sub-pixel driving circuit through the fifth via hole, the first electrode of the second light-emitting element is connected to the second sub-pixel driving circuit through the sixth via hole, and the first electrode of the third light-emitting element is connected to the third sub-pixel driving circuit through the seventh via hole.

[0020] For example, in the display substrate provided in at least one embodiment of the present disclosure, the orthographic projection of the fifth via hole on the board surface of the base substrate does not overlap with the orthographic projection of the light-emitting area of ​​the first light-emitting element on the board surface of the base substrate, the orthographic projection of the sixth via hole on the board surface of the base substrate does not overlap with the orthographic projection of the light-emitting area of ​​the second light-emitting element on the board surface of the base substrate, and the orthographic projection of the seventh via hole on the board surface of the base substrate does not overlap with the orthographic projection of the light-emitting area of ​​the third light-emitting element on the board surface of the base substrate.

[0021] For example, the display substrate provided by at least one embodiment of the present disclosure further includes a black matrix, wherein in the pixel area of ​​each of the repeating units, the black matrix includes a plurality of light-shielding lines extending along the first direction, and at least a portion of the orthographic projections of the plurality of light-shielding lines on the board surface of the base substrate overlaps with the intervals between the first sub-pixel filter area, the second sub-pixel filter area and the third sub-pixel filter area in the second direction, the orthographic projections of the fifth via hole and the sixth via hole on the board surface of the base substrate are close to the orthographic projections of the light-shielding lines between the first sub-pixel filter area and the second sub-pixel filter area on the board surface of the base substrate, and are located on both sides of the orthographic projections of the light-shielding lines between the first sub-pixel filter area and the second sub-pixel filter area on the board surface of the base substrate, and the orthographic projections of the seventh via hole on the board surface of the base substrate are close to the orthographic projections of the light-shielding lines between the second sub-pixel filter area and the third sub-pixel filter area on the board surface of the base substrate, and overlap with the third sub-pixel filter area.

[0022] For example, the display substrate provided by at least one embodiment of the present disclosure further includes a black matrix, wherein in the pixel area of ​​each of the repeating units, the black matrix includes a plurality of light-shielding lines extending along the first direction, at least a portion of the orthographic projections of the plurality of light-shielding lines on the board surface of the substrate overlap with the intervals between the first sub-pixel filter area, the second sub-pixel filter area and the third sub-pixel filter area in the second direction, the orthographic projection of the fifth via hole on the board surface of the substrate overlaps with the orthographic projection of one end of the first electrode plate of the storage capacitor of the first sub-pixel driving circuit connected to the second electrode of the sensing transistor on the board surface of the substrate, the orthographic projection of the sixth via hole on the board surface of the substrate is close to the orthographic projection of the light-shielding line between the first sub-pixel filter area and the second sub-pixel filter area on the board surface of the substrate, and overlaps with the second sub-pixel filter area, and the orthographic projection of the seventh via hole on the board surface of the substrate is close to the orthographic projection of the light-shielding line between the second sub-pixel filter area and the third sub-pixel filter area on the board surface of the substrate, and overlaps with the third sub-pixel filter area.

[0023] For example, the display substrate provided by at least one embodiment of the present disclosure also includes multiple data lines, which extend along the second direction. The multiple data lines include a first data line, a second data line and a third data line located in each repeating unit, the first data line and the second data line are located between the first sub-pixel driving circuit and the second sub-pixel driving circuit, and the third data line is located between the second sub-pixel driving circuit and the third sub-pixel driving circuit. The first data line, the second data line and the third data line are electrically connected to the first sub-pixel driving circuit, the second sub-pixel driving circuit and the third sub-pixel driving circuit, respectively, to provide data signals, and the first conductive layer also includes a fourth transfer electrode, a fifth transfer electrode and a sixth transfer electrode along the first direction, the fourth transfer electrode is connected to the first data line and the second pole of the data write transistor of the first sub-pixel driving circuit, the fifth transfer electrode is connected to the second data line and the second pole of the data write transistor of the second sub-pixel driving circuit, and the sixth transfer electrode is connected to the third data line and the second pole of the data write transistor of the third sub-pixel driving circuit.

[0024] For example, in the display substrate provided by at least one embodiment of the present disclosure, the first gate line and the second gate line are located in the second conductive layer, the first gate line is close to the sensing transistors of the first repeating unit and the second repeating unit, the second gate line is close to the data writing transistors of the first repeating unit and the second repeating unit, the first gate line includes a fold line portion, the fold line portion includes a first fold line portion along the first direction, a second fold line portion along the second direction respectively connected to both ends of the first fold line portion, and a third fold line portion, the first fold line portion, the second fold line portion and the third fold line portion bypass the first connecting wiring, the orthographic projection of the first fold line portion on the board surface of the base substrate overlaps with the orthographic projection of the active layer of the sensing transistor of the first sub-pixel driving circuit, the second sub-pixel driving circuit and the third sub-pixel driving circuit of the first repeating unit on the board surface of the base substrate, and the overlapping portion forms the gate of the sensing transistor.

[0025] For example, in the display substrate provided by at least one embodiment of the present disclosure, in the second direction, the portion of the first gate line and the first connecting line arranged in parallel is located on a side of the transparent area of ​​the first connecting line close to the second repeating unit.

[0026] For example, in the display substrate provided in at least one embodiment of the present disclosure, the second conductive layer also includes a third connecting route, a fourth connecting route and a fifth connecting route, and the third connecting route, the fourth connecting route and the fifth connecting route are "L"-shaped broken lines, and the fourth connecting route and the fifth connecting route have the same bending direction, and the bending direction of the third connecting route is opposite to the bending direction of the fourth connecting route and the fifth connecting route, the third connecting route is connected to the second gate line and the gate of the data writing transistor of the first sub-pixel driving circuit, the fourth connecting route is connected to the second gate line and the gate of the data writing transistor of the second sub-pixel driving circuit, and the fifth connecting route is connected to the second gate line and the gate of the data writing transistor of the third sub-pixel driving circuit.

[0027] For example, in the display substrate provided by at least one embodiment of the present disclosure, the first conductive layer includes a seventh switching electrode, an eighth switching electrode and a ninth switching electrode along the second direction, and the orthographic projections of the seventh switching electrode, the eighth switching electrode and the ninth switching electrode on the board surface of the base substrate overlap with the orthographic projection of the second connecting line on the board surface of the base substrate, the first end of the seventh switching electrode is connected to the gate of the driving transistor of the first sub-pixel driving circuit through at least a portion of an eighth via hole penetrating the second insulating layer, the second end of the seventh switching electrode is connected to the first electrode of the data writing transistor of the first sub-pixel driving circuit, the first end of the eighth switching electrode is connected to the gate of the driving transistor of the second sub-pixel driving circuit through at least a portion of a ninth via hole penetrating the second insulating layer, the second end of the eighth switching electrode is connected to the first electrode of the data writing transistor of the second sub-pixel driving circuit, the first end of the ninth switching electrode is connected to the gate of the driving transistor of the third sub-pixel driving circuit through at least a portion of a tenth via hole penetrating the second insulating layer, and the second end of the ninth switching electrode is connected to the first electrode of the data writing transistor of the third sub-pixel driving circuit.

[0028] At least one embodiment of the present disclosure further provides a display device, comprising any of the display substrates described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0030] Figure 1 A schematic diagram of a display substrate provided for at least one embodiment of the present disclosure;

[0031] Figure 2 A schematic diagram of a planar layout of a display substrate provided in at least one embodiment of the present disclosure;

[0032] Figure 3 for Figure 2 The schematic cross-sectional view of a partial structure of a display substrate is shown;

[0033] Figure 4 for Figure 3 Schematic diagram of the planar layout of the middle electrode overlap area;

[0034] Figure 5 A schematic diagram of an optical simulation of a display substrate provided by at least one embodiment of the present disclosure;

[0035] Figure 6 A schematic diagram of the layout of a sub-pixel driving circuit and a light-emitting element of a display substrate provided in at least one embodiment of the present disclosure;

[0036] Figure 7 A schematic diagram of the layout of a black matrix and a filter layer of a display substrate provided in at least one embodiment of the present disclosure;

[0037] Fig. 8A A circuit diagram of a sub-pixel driving circuit provided in at least one embodiment of the present disclosure;

[0038] Figure 8B A schematic diagram of the connection between a sub-pixel driving circuit and a register unit circuit of a sub-pixel unit circuit provided by at least one embodiment of the present disclosure;

[0039] Fig. 9A A plan view of a light shielding layer provided for at least one embodiment of the present disclosure;

[0040] Fig. 9B A plan view of a first insulating layer provided for at least one embodiment of the present disclosure;

[0041] Fig. 9C A plan view of a buffer layer provided for at least one embodiment of the present disclosure;

[0042] Fig.9D A plan view of a semiconductor layer provided for at least one embodiment of the present disclosure;

[0043] Fig.9E A layout diagram of a second conductive layer provided for at least one embodiment of the present disclosure;

[0044] Fig.9F A plan view of an interlayer insulating layer provided for at least one embodiment of the present disclosure;

[0045] Figure 9G A plan view of a first conductive layer provided for at least one embodiment of the present disclosure;

[0046] Fig.10 for FIG. 9A to FIG. 9B Layout diagram after stacking;

[0047] Fig.11A for Fig.10 Enlarged view of the middle A1 region;

[0048] Fig. 11B for Fig.11A A schematic cross-sectional view along line B1-B2;

[0049] Fig. 11C for Fig.10 A magnified view of the A2 region in the middle;

[0050] Fig. 12A A plan view of a passivation layer provided for at least one embodiment of the present disclosure;

[0051] Fig. 12B A plan view of a third insulating layer provided for at least one embodiment of the present disclosure;

[0052] Fig. 12C A plan view of a first sublayer of a first electrode layer provided in at least one embodiment of the present disclosure;

[0053] Fig.12D A plan view of a third sublayer of a first electrode layer provided in at least one embodiment of the present disclosure;

[0054] Fig.12E A plan view of a pixel defining layer provided for at least one embodiment of the present disclosure;

[0055] Fig.13 A schematic diagram of a display device provided for at least one embodiment of the present disclosure; and

[0056] Figure 14A-14F A schematic diagram of a manufacturing process of a display device provided in at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0057] In order to make the purpose, technical solution and advantages of the embodiment of the present invention clearer, the technical solution of the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings of the embodiment of the present invention. Obviously, the described embodiment is a part of the embodiment of the present invention, not all of the embodiments. Based on the described embodiment of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0058] Unless otherwise defined, the technical terms or scientific terms used in this disclosure should be understood by people with ordinary skills in the field to which the present invention belongs. The "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0059] The present disclosure is described below by several specific embodiments. In order to keep the following description of the embodiments of the present invention clear and concise, the detailed description of known functions and known components may be omitted. When any component of the embodiments of the present invention appears in more than one accompanying drawings, the component is represented by the same reference numeral in each of the accompanying drawings.

[0060] The common large-size transparent display resolution on the market is about 40PPI, and there are few high-PPI products. A bottleneck of today's large-size high-PPI transparent display devices is that as the PPI increases, the smaller the pixel size, the greater the metal wiring density, and the wiring density cannot be too large. In addition, since the top-emitting white light OLED uses a transparent cathode with a large resistance, an auxiliary cathode must be added to reduce the wiring resistance drop (IR Drop), so the conventional auxiliary cathode also needs to occupy the transparent area of ​​the transparent display device. The above reasons all lead to a smaller transparent area, which affects the transmittance and is more prone to pinhole diffraction effects. This is reflected in the actual experience that objects seen through the transparent display device have ghosting, which seriously affects the user experience. How to increase the transparent area as much as possible under the premise of high PPI is the key to the current design of transparent display devices.

[0061] At least one embodiment of the present disclosure provides a display substrate, which includes a base substrate and a light shielding layer. The base substrate includes a display area, the display area includes a plurality of repeating units arranged in an array, each of the plurality of repeating units includes a transparent area and a pixel area arranged along a first direction, the pixel area includes a plurality of sub-pixels, each of the plurality of sub-pixels includes a sub-pixel driving circuit and a light-emitting element, the light-emitting element is located on a side of the sub-pixel driving circuit away from the base substrate, the sub-pixel driving circuit is configured to drive the light-emitting element to emit light, and the light-emitting element includes a first electrode, a second electrode, and a light-emitting layer located between the first electrode and the second electrode. The light shielding layer is disposed on the base substrate and is located on a side of the sub-pixel driving circuit close to the base substrate, at least part of the orthographic projection of the light shielding layer on the board surface of the base substrate overlaps with the orthographic projection of the sub-pixel driving circuit on the board surface of the base substrate, and the light shielding layer is connected to the second electrode to be reused as an auxiliary electrode of the second electrode.

[0062] At least one embodiment of the present disclosure further provides a display device corresponding to the above-mentioned display substrate.

[0063] The display substrate provided by the above-mentioned embodiment of the present disclosure uses the shading layer for shading the sub-pixel driving circuit and is also connected to the second electrode to be reused as an auxiliary electrode of the second electrode, thereby increasing the space of the transparent area of ​​the display substrate and improving the light transmittance of the display substrate. At the same time, since the resistance of the auxiliary electrode reused by the shading layer is smaller, the effect of increasing the resistance of the second electrode is more obvious (that is, the effect of reducing the resistance drop is more obvious).

[0064] The embodiments of the present disclosure and some examples thereof are described in detail below with reference to the accompanying drawings.

[0065] Figure 1 A schematic diagram of a display substrate provided according to at least one embodiment of the present disclosure. Figure 2 A schematic diagram of a planar layout of a display substrate provided in at least one embodiment of the present disclosure. Figure 3 for Figure 2 The diagram shows a cross-sectional view of a partial structure of a display substrate.

[0066] For example, Figure 1 As shown, the display substrate 1 includes a base substrate 10. The base substrate 10 includes a display area 101. The display area 101 includes a plurality of repeating units C1 arranged in an array. The plurality of repeating units C1 are arranged in a plurality of rows along a first direction X and a second direction Y, for example, arranged in rows 1 to N extending along the first direction X, and rows 1 and F extending along the second direction Y. Each of the plurality of repeating units C1 includes a transparent area TM10 and a pixel area P10 arranged along the first direction X. The pixel area P10 includes a plurality of sub-pixels. For example, in the embodiment of the present disclosure, it is taken as an example that the pixel area P10 includes three sub-pixels.

[0067] For example, the base substrate 10 may be a flexible substrate or a rigid substrate. The base substrate 10 may be made of, for example, glass, plastic, quartz or other suitable materials, which is not limited in the embodiments of the present disclosure.

[0068] For example, Figure 1 As shown, the display substrate 1 includes a plurality of power lines VDD10 and a plurality of sensing lines SES10. The plurality of power lines VDD10 and the plurality of sensing lines SES10 are arranged on the base substrate 10 and extend along the second direction Y. The plurality of power lines VDD10 and the plurality of sensing lines SES10 are respectively connected to a plurality of sub-pixels and extend to the bonding area 103 of the display substrate 1. The power line VDD10 is connected to a column of sub-pixels corresponding to the extension in the second direction Y and provides a second power supply voltage signal. The sensing line SES10 is connected to a column of sub-pixels corresponding to the extension in the second direction Y and provides a reference voltage signal. The display substrate also includes a gate drive circuit 13 and a plurality of gate lines G10 located in the peripheral area 102, and the plurality of gate lines G10 extend along the first direction X. The gate drive circuit 13 is configured to output a gate scanning signal that drives a plurality of sub-pixel unit circuits 16 to work row by row. The gate line G10 is connected to the gate drive circuit 13 and a row of sub-pixels corresponding to the extension in the first direction X and the gate scanning signal that the sub-pixels work.

[0069] For example, Figure 2 and Figure 3 As shown, each of the plurality of sub-pixels includes a sub-pixel driving circuit 1601 (e.g., a first sub-pixel driving circuit P161, a second sub-pixel driving circuit P162, and a third sub-pixel driving circuit P163) and a light-emitting element 160. The light-emitting element 160 is located on a side of the sub-pixel driving circuit 1601 away from the substrate 10. The sub-pixel driving circuit 1601 is configured to drive the light-emitting element 160 to emit light. The light-emitting element 160 includes a first electrode 161, a second electrode 162, and a light-emitting layer 163 located between the first electrode 161 and the second electrode 162.

[0070] For example, in some embodiments, each sub-pixel driving circuit 1601 may include a pixel circuit having a circuit structure of 7T1C, 8T2C, 4T1C or 3T1C in the art. The embodiments of the present disclosure are introduced using a pixel circuit including a 3T1C circuit structure as an example, and the embodiments of the present disclosure are not limited to this.

[0071] For example, Figure 2 and Figure 3As shown, the light shielding layer 131 is disposed on the base substrate 10 and is located on the side of the sub-pixel driving circuit 1601 close to the base substrate 10 to block the irradiation of external light. At least part of the orthographic projection of the light shielding layer 131 on the board surface of the base substrate 10 (for example, the upper surface of the base substrate 10) overlaps with the orthographic projection of the sub-pixel driving circuit 1601 on the board surface of the base substrate 10. The light shielding layer 131 is connected to the second electrode 162 to be multiplexed as an auxiliary electrode of the second electrode 162. The orthographic projection of the light-shielding layer 131 on the plate surface of the base substrate 10 overlaps with the pixel area P10 of the repeating unit C1, but does not overlap with the transparent area TM10 of the repeating unit C1. The light-shielding layer 131 shields the pixel area P10 and is reused as an auxiliary electrode of the second electrode 162, thereby increasing the space of the transparent area TM10 of the display substrate 1 and improving the transmittance of the display substrate 1. At the same time, since the resistance of the auxiliary electrode reused by the light-shielding layer 131 is smaller, the effect of increasing the resistance of the second electrode 162 is more obvious (that is, the effect of reducing the resistance drop is more obvious).

[0072] For example, the material of the light shielding layer 131 can be made of a metal material, for example, the metal material includes silver, aluminum, chromium, copper, molybdenum, titanium, aluminum-neodymium alloy, copper-molybdenum alloy, molybdenum-tantalum alloy, molybdenum-neodymium alloy or any combination thereof.

[0073] For example, Figure 2 and Figure 3 As shown, the pixel area P10 includes an electrode overlapping area 12, and the electrode overlapping area 12 is located on a side of the pixel area P10 close to the transparent area TM10. That is, in a repeating unit C1, the electrode overlapping area 12 is located between the pixel area P10 and the transparent area TM10. The orthographic projection of the electrode overlapping area 12 on the plate surface of the base substrate 10 and the orthographic projection of the light shielding layer 131 on the plate surface of the base substrate 10 at least partially overlap, for example, partially overlap. The electrode overlapping area 12 includes a first composite hole structure and a first composite overlapping electrode. The first composite hole structure is configured to expose the light shielding layer 131, for example, the first composite hole structure includes a first overlapping hole F11 and a second overlapping hole F12. The first composite overlapping electrode is configured to connect the second electrode 162 and the light shielding layer 131, for example, the first composite overlapping electrode includes a first overlapping electrode FD11 and a second overlapping electrode FD12. The light shielding layer 131 is connected to the second electrode 162 through the first composite lap electrode and the first composite hole structure, so as to be reused as an auxiliary electrode of the second electrode 162 .

[0074] Figure 4 for Figure 3 Schematic diagram of the planar layout of the middle electrode overlapping area.

[0075] For example, Figure 3 and Figure 4As shown, the first composite lap electrode includes a first lap electrode FD11 and a second lap electrode FD12. The first lap electrode FD11 is located on a side of the second lap electrode FD11 close to the base substrate 11. The first composite hole structure includes a first lap hole FK11 and a second lap hole FK12, and the first lap hole FK11 is located on a side of the second lap hole FK12 close to the base substrate 10. The first lap electrode FD11 is connected to the light shielding layer 131 through the first lap hole FK11, and the second lap electrode FD12 is connected to the first lap electrode FD11 through the second lap hole FK12. The second lap electrode FK12 is also connected to the second electrode 162. For example, the second lap electrode FK12 can be indirectly connected to the second electrode 162. The second lap electrode FK12 is also separated from the second electrode 162 by a light-emitting layer 163, that is, the second lap electrode FK12 (for example, part) is connected to the second electrode 162 through the light-emitting layer 163.

[0076] For example, in other embodiments, the second bonding electrode FK12 may be directly connected to the second electrode 162 .

[0077] Fig. 8A A circuit diagram of a sub-pixel driving circuit provided in at least one embodiment of the present disclosure.

[0078] For example, Fig. 8A As shown, the sub-pixel driving circuit 1601 may adopt a pixel circuit with a 3T1C circuit structure in the art. For example, the sub-pixel driving circuit 1601 includes a data writing transistor T1, a driving transistor T2, a sensing transistor T3, and a storage capacitor CST.

[0079] For example, in some embodiments, Figure 3 As shown, the display substrate further includes a first insulating layer 132 (e.g., a blocking layer), a second insulating layer 134 (e.g., an interlayer insulating layer), a first conductive layer SD, a third insulating layer 136 (e.g., a planarizing layer), and a first electrode layer AN. The first insulating layer 132 provides a flat surface for forming a sub-pixel driving circuit 1601, and can prevent impurities that may exist in the base substrate 10 from diffusing into the sub-pixel driving circuit or the gate driving circuit 13 and adversely affecting the performance of the display substrate. The thickness of the first insulating layer 132 can also prevent the light shielding layer 131 from generating parasitic capacitance with other film layers.

[0080] For example, the material of the first insulating layer 132 may include inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, or other suitable materials.

[0081] For example, the first insulating layer 132 is located on the side of the light shielding layer 131 away from the base substrate 10. The second insulating layer 134 is located on the side of the first insulating layer 132 away from the base substrate 10, the first conductive layer SD is located on the side of the second insulating layer 134 away from the base substrate 10, the third insulating layer 136 is located on the side of the first conductive layer SD away from the base substrate 10, and the first electrode layer AN is located on the side of the third insulating layer 136 away from the base substrate 10. For example, the first electrode layer AN is a film layer where the first electrode 162 of the light emitting element 160 is located, and the first conductive layer SD is a film layer where the first electrode TSD22 (e.g., source) and the second electrode TSD21 (e.g., drain) of the driving transistor T2 are located.

[0082] For example, the materials of the first insulating layer 132 and the second insulating layer 134 may include inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, or other suitable materials.

[0083] For example, the material of the first conductive layer SD may include a metal material or an alloy material, such as a metal single layer or multilayer structure formed by molybdenum, aluminum, and titanium, for example, the multilayer structure is a multi-metal layer stack (such as a titanium, aluminum, and titanium three-layer metal stack (Ti / Al / Ti)). The embodiments of the present disclosure do not specifically limit the materials of each functional layer.

[0084] For example, the material of the third insulating layer 136 may include inorganic insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride, or may include organic insulating materials such as polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene, or phenolic resin, but the embodiments of the present disclosure are not limited to this.

[0085] For example, in some embodiments, Figure 3 and Figure 4As shown, the first overlap hole FK11 includes a first overlap sub-hole FK111 penetrating the first insulating layer 132 and a second overlap sub-hole FK112 penetrating the second insulating layer 134. The second overlap sub-hole FK112 is set in the first overlap sub-hole FK111, that is, the orthographic projection of the second overlap sub-hole FK112 on the board surface of the base substrate 10 is located at the orthographic projection of the first overlap sub-hole FK111 on the board surface of the base substrate 10. The first overlap sub-hole FK111 and the second overlap sub-hole FK112 are arranged to expose the light shielding layer 131. The first overlap electrode FD11 is located on the side of the second insulating layer 134 away from the base substrate 10. The second overlap hole FK12 penetrates the third insulating layer 136 to expose the first overlap electrode FD11. The first conductive layer SD includes the first overlap electrode FD11. The first electrode layer AN includes the second overlap electrode FD12 and the first electrode 161 of the light-emitting element 160. The first electrode 161 and the second lapped electrode FD12 are provided in the same layer and the same material, and the first electrode 161 and the second lapped electrode FD12 are spaced apart from each other. That is to say, although the first electrode 161 and the second lapped electrode FD12 are provided in the same layer and the same material, for example, they are prepared by the same process, the first electrode 161 and the second lapped electrode FD12 are disconnected or not connected. The second lapped electrode FD12 is configured to be connected to the second electrode 162 of the light-emitting element and the first lapped electrode FD11. The first electrode 161 and the second lapped electrode FD12 are prepared in the same film layer, which can reduce the composition process and the thickness of the display substrate.

[0086] For example, in some embodiments, Figure 3 and Figure 4 As shown, the display substrate further includes a buffer layer 133. The buffer layer 133 is located between the first insulating layer 132 and the second insulating layer 134, and the first overlapping hole FK11 further includes a third overlapping sub-hole FK113. The third overlapping sub-hole FK113 is sleeved between the first overlapping sub-hole FK111 and the second overlapping sub-hole FK112, and the third overlapping sub-hole FK113 penetrates the buffer layer 133 and is configured to expose the light shielding layer 131. The orthographic projection of the third overlapping sub-hole FK113 on the board surface of the base substrate 10 is located in the orthographic projection of the first overlapping sub-hole FK111 on the board surface of the base substrate 10. The first overlapping hole FK11 is a sleeve hole formed by the third overlapping sub-hole FK113, the first overlapping sub-hole FK111 and the second overlapping sub-hole FK112.

[0087] For example, the material of the buffer layer may include inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, or other suitable materials.

[0088] For example, in other embodiments, after forming the second insulating layer 134 on the display substrate, the second overlapping sub-hole FK112 may be etched first, and then the third overlapping sub-hole FK113 may be etched. In this case, the sizes of the second overlapping sub-hole FK112 and the third overlapping sub-hole FK113 are substantially the same. The second insulating layer 134 will not contact the third overlapping sub-hole FK113.

[0089] For example, Figure 3 and Figure 4 As shown, the display substrate further includes a passivation layer 135. The passivation layer 135 is located between the third insulating layer 136 and the first conductive layer SD (first bonding electrode FD11). The second bonding hole FK12 also penetrates the passivation layer 135. The passivation layer 135 can protect the first conductive layer SD from being corroded by water vapor.

[0090] For example, the material of the passivation layer 135 may include an organic insulating material or an inorganic insulating material, such as silicon nitride material, which has a high dielectric constant and good hydrophobicity and can well protect the sub-pixel driving circuit from being corroded by water vapor.

[0091] For example, in some embodiments, Figure 4 As shown, the width of the first overlapping sub-hole FK111 and the second overlapping sub-hole FK112 in the first direction X may be about 3.5-4.5 microns, for example, about 4 microns. For example, the width of the third overlapping sub-hole FK113 in the first direction X may be about 7.5-8.5 microns, for example, about 8 microns. For example, the width of the second overlapping hole FK12 in the first direction X may be about 6.5-7.5 microns, for example, about 7 microns. For example, the sizes of the first overlapping sub-hole FK111 and the second overlapping sub-hole FK112 may be equal or unequal. The sizes of the first overlapping sub-hole FK111, the second overlapping sub-hole FK112, the third overlapping sub-hole FK113 and the second overlapping hole FK12 are selected by the display substrate in the preparation process, and the embodiments of the present disclosure are not limited thereto.

[0092] It should be noted that, in the embodiments of the present disclosure, “about” means that the value may fluctuate within a range of, for example, ±15% or ±5%.

[0093] For example, in some embodiments, Figure 3As shown, the first electrode layer AN includes a first layer AN1, a second layer AN2 and a third layer AN3. The first layer AN1 is located on the side of the third insulating layer 136 away from the base substrate 10, the third layer AN3 is located on the side of the first layer AN1 away from the base substrate 10, and the second layer AN2 is located between the first layer AN1 and the third layer AN3. The first electrode 161 of the light-emitting element 160 is a three-layer structure arranged in the same layer as the first layer AN1, the second layer AN2 and the third layer AN3, and the cross section of the first electrode 161 is an I-shaped. The second electrode 162 can be arranged in part or the entire display area 101, so that it can be formed on the entire surface in the preparation process.

[0094] For example, the first electrode 161 of the light-emitting element may include a reflective layer, and the second electrode 162 of the light-emitting element may include a transparent layer or a semi-transparent layer. Thus, the first electrode 161 may reflect the light emitted from the light-emitting layer 163, and the part of the light is emitted to the external environment through the second electrode 162, thereby improving the light emission efficiency. When the second electrode 162 includes a semi-transmissive layer, some of the light reflected by the first electrode 161 is reflected again by the second electrode 162, so that the first electrode 161 and the second electrode 162 form a resonant structure, thereby improving the light emission efficiency.

[0095] For example, the material of the first layer AN1 and the second layer AN2 may include at least one transparent conductive oxide material, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), etc. For example, the material of the third layer 163 may include an alloy material, such as AlNd, etc.

[0096] For example, the light-emitting layer 163 may include small molecule organic materials or polymer molecule organic materials, and may be fluorescent luminescent materials or phosphorescent luminescent materials, and may emit red light, green light, blue light, or white light; and, as required, the light-emitting layer may further include functional layers such as an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer. For QLEDs, the light-emitting layer may include quantum dot materials, such as silicon quantum dots, germanium quantum dots, cadmium sulfide quantum dots, cadmium selenide quantum dots, cadmium telluride quantum dots, zinc selenide quantum dots, lead sulfide quantum dots, lead selenide quantum dots, indium phosphide quantum dots, and indium arsenide quantum dots, and the particle size of the quantum dots is 2-20 nm. In the embodiment of the present disclosure, the light-emitting layer 163 emitting white light is taken as an example.

[0097] For example, the second electrode 162 may include various conductive materials. For example, the second electrode 162 may include metal materials such as lithium (Li), aluminum (Al), magnesium (Mg), silver (Ag), etc. For example, the second electrode 162 may include a metal with high reflectivity as a reflective layer, such as silver (Ag).

[0098] For example, in some embodiments, Figure 3As shown, the second overlap electrode FD12 includes a first sub-electrode layer FD121, a second sub-electrode layer FD122, and a third sub-electrode layer FD123 stacked on each other. The first sub-electrode layer FD121 is located on the side of the third sub-electrode layer FD123 close to the base substrate 10, and the second sub-electrode layer FD122 is located between the first sub-electrode layer FD121 and the third sub-electrode layer FD123. The first sub-electrode layer FD121 is in the same layer and is made of the same material as the first layer AN1 of the first electrode layer AN. The second sub-electrode layer FD122 is in the same layer and is made of the same material as the second layer AN2 of the first electrode layer AN. The third sub-electrode layer FD123 is in the same layer and is made of the same material as the third layer AN3 of the first electrode layer AN. In a direction parallel to the plate surface of the base substrate 10, at least one side of the first sub-electrode layer FD121 in the circumferential direction protrudes from the second sub-electrode layer FD122. For example, as shown in the figure, the first sub-electrode layer FD121 protrudes from the second sub-electrode layer FD122 in the circumferential direction. The orthographic projection of the second sub-electrode layer FD122 on the board surface of the base substrate 10 is located in the orthographic projection of the first sub-electrode layer FD121 on the board surface of the base substrate 10. The orthographic projection of the third sub-electrode layer FD123 on the board surface of the base substrate 10 is located in the orthographic projection of the first sub-electrode layer FD121 on the board surface of the base substrate 10, and the projection area of ​​the first sub-electrode layer FD121 on the board surface of the base substrate 10 is larger than the projection area of ​​the third sub-electrode layer FD123 on the board surface of the base substrate 10. That is, the projection area of ​​the orthographic projection of the first sub-electrode layer FD121 on the board surface of the base substrate 10 is the largest, the projection area of ​​the orthographic projection of the third sub-electrode layer FD123 on the board surface of the base substrate 10 is the second largest, and the projection area of ​​the orthographic projection of the second sub-electrode layer FD122 on the board surface of the base substrate 10 is the smallest. Therefore, the portion of the first sub-electrode layer FD121 protruding from the second sub-electrode layer FD122 can be used for connection with the second electrode 162.

[0099] For example, in some embodiments, Figure 3 As shown, the projection area of ​​the second sub-electrode layer FD122 on the board surface of the base substrate 10 is respectively smaller than the projection areas of the first sub-electrode layer FD121 and the third sub-electrode layer FD123 on the board surface of the base substrate 10. The cross-sections of the first sub-electrode layer FD121, the second sub-electrode layer FD122 and the third sub-electrode layer FD123 are in an I-shape, and the first sub-electrode layer FD121 is connected to the first bonding electrode FD11 through the second bonding hole FK12.

[0100] For example, in some embodiments, Figure 4As shown, the width D3 of the first sub-electrode layer FD121 in the first direction X may be about 28-30 microns, for example, about 29 microns. The length D4 of the first sub-electrode layer FD121 in the second direction Y may be about 30-31 microns, for example, about 31.5 microns. The distance D1 between the third sub-electrode layer FD123 (or the second sub-electrode layer FD122) and the edge of the first sub-electrode layer FD121 in the first direction X may be, for example, about 5.5-6.5 microns, for example, about 6 microns.

[0101] For example, in some embodiments, the display substrate 10 further includes a pixel defining layer 138. The pixel defining layer 138 is located on a side of the first electrode 161 away from the base substrate 10. The pixel defining layer 138 includes a plurality of openings, some of which define sub-pixels and correspond to the light-emitting area of ​​the light-emitting element 160. For example, the light-emitting layer 163 is also disposed entirely on a side of the second electrode 162 close to the base substrate 10. In the electrode overlapping area 12, the pixel defining layer 138 also has an opening, and the pixel defining layer 138 partially covers the area of ​​the first sub-electrode layer FD121 protruding from the second sub-electrode layer FD122. For example, the pixel defining layer 138 extends to the area of ​​the first sub-electrode layer FD121 protruding from the second sub-electrode layer FD122 and covers the edge of the first sub-electrode layer FD121. Thus, the pixel defining layer 138 can prevent the light-emitting layer 163 from discharging due to burrs on the corners of the first sub-electrode layer FD121, resulting in poor process.

[0102] For example, in some embodiments, Figure 4 As shown, a distance D2 between the edge of the pixel defining layer 138 and the edge of the first sub-electrode layer FD121 in the second direction Y may be, for example, approximately 2.5-3.5 micrometers, for example, approximately 3 micrometers.

[0103] For example, in some embodiments, Figure 3 As shown, the light-emitting layer 163 of the light-emitting element 160 is stacked on the side of the pixel defining layer 138 away from the base substrate 10. The light-emitting layer 163 includes a first portion 1631 and a second portion 1632 located in the electrode overlapping area 12. The first portion 1631 covers at least part of the area of ​​the first sub-electrode layer FD121 protruding from the second sub-electrode layer FD122, and the first portion 1631 is in contact with the first sub-electrode layer FD121. The second portion 1632 is located on the side of the third sub-electrode layer FD123 away from the base substrate 10.

[0104] For example, in some embodiments, Figure 3As shown, the second electrode 162 of the light-emitting element 160 includes a first electrode portion 1621 and a second electrode portion 1622 located in the electrode overlapping region 12. The first electrode portion 1621 is located in a region of the first sub-electrode layer FD121 that protrudes from the second sub-electrode layer FD122, and the first electrode portion 1621 is in contact with the first sub-electrode layer FD121 and the second sub-electrode layer FD122. The second electrode portion FD122 is located on a side of the second portion 1632 of the light-emitting layer 163 that is away from the base substrate 10. The orthographic projection of the first portion 1631 of the light-emitting layer 163 on the board surface of the base substrate 10 overlaps at least partially with the orthographic projection of the first electrode portion 1621 on the board surface of the base substrate 10. That is, in the area where the first sub-electrode layer FD121 protrudes from the second sub-electrode layer FD122, the first electrode portion 1621 is in contact with the first portion 1631 of the light-emitting layer 163, the upper surface of the first sub-electrode layer FD121 (parallel to the surface of the base substrate 10), and the side surface of the second sub-electrode layer FD122 (perpendicular to the surface of the base substrate 10).

[0105] For example, in some embodiments, the display substrate 10 further includes a semiconductor layer ACT, a fourth insulating layer 137 (e.g., a gate insulating layer), and a second conductive layer GATE. The semiconductor layer ACT is located on the side of the buffer layer 133 away from the base substrate 10. The fourth insulating layer 137 is located on the side of the semiconductor layer ACT away from the base substrate 10. The second conductive layer GATE is located between the second insulating layer 134 and the fourth insulating layer 137. The semiconductor layer ACT includes an active layer TA2 of the driving transistor T2. The second conductive layer GATE includes a gate TG2 of the driving transistor T2, and the first conductive layer SD includes a first electrode TSD21 and a second electrode TSD22 of the driving transistor T2. The second conductive layer active layer TA2 has a source region corresponding to the first electrode TSD21 and a drain region corresponding to the second electrode TSD22. The semiconductor layer ACT also includes a first plate CST1 of the storage capacitor CST, and the first conductive layer SD also includes a second plate CST2 of the storage capacitor CST. The second insulating layer 134 is spaced between the first plate CST1 and the second plate CST2. For example, the second electrode plate CST2 is connected to the first electrode TSD21 of the driving transistor T2. For example, the first electrode 161 of the light emitting element 160 is connected to the first conductive layer through a via hole penetrating the passivation layer 135 and the third insulating layer 136. For example, the portion of the first electrode 161 of the light emitting element 160 in the same layer as the first sublayer AN1 of the first electrode layer AN is connected to the first electrode TSD21 of the driving transistor T2 through a via hole penetrating the passivation layer 135 and the third insulating layer 136. For example, the portion of the first electrode 161 of the light emitting element 160 in the same layer as the first sublayer AN1 of the first electrode layer AN is connected to the second electrode plate CST2 to be connected to the first electrode TSD21 of the driving transistor T2.

[0106] For example, in other embodiments, for example, a portion of the first electrode 161 of the light emitting element 160 that is in the same layer as the first sublayer AN1 of the first electrode layer AN is directly connected to the first electrode TSD21 of the driving transistor T2. That is, in a cross-sectional view perpendicular to the plate surface of the base substrate 10, the first electrode TSD21 of the driving transistor T2 is spaced apart from the first electrode plate 1 of the storage capacitor CST.

[0107] It should be noted that the cross-sectional structure of other transistors of the sub-pixel driving circuit 160 , such as the data writing transistor T1 and the driving transistor T2 , may be the same as the cross-sectional structure of the sensing transistor T3 , which will not be described in detail herein.

[0108] It should be noted that, in the embodiment of the present disclosure, the first electrode represents the source of the transistor, and the second electrode represents the drain of the transistor, and the above can also be interchanged, and the embodiment of the present disclosure is not limited to this.

[0109] For example, the material of the semiconductor layer ACT may include an oxide semiconductor, an organic semiconductor or amorphous silicon, polycrystalline silicon, etc. For example, the oxide semiconductor includes a metal oxide semiconductor (such as indium gallium zinc oxide (IGZO)), and the polycrystalline silicon includes low-temperature polycrystalline silicon or high-temperature polycrystalline silicon, etc., and the embodiments of the present disclosure are not limited to this. It should be noted that the above-mentioned source region and drain region may be regions doped with n-type impurities or p-type impurities, and the embodiments of the present disclosure are not limited to this.

[0110] For example, the material of the fourth insulating layer 137 may include inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, or other suitable materials.

[0111] For example, the material of the second conductive layer GATE may include a metal material or an alloy material, such as a metal single layer or multilayer structure formed by molybdenum, aluminum and titanium. For example, the multilayer structure is a multi-metal layer stack (such as a titanium, aluminum and titanium three-layer metal stack (Ti / Al / Ti)).

[0112] For example, in some embodiments, the display substrate 10 further includes an encapsulation layer 139. The encapsulation layer 139 is disposed on a side of the light-emitting element 160 away from the base substrate 10. The encapsulation layer 139 seals the light-emitting element 160, thereby reducing or preventing degradation of the light-emitting element 160 caused by moisture and / or oxygen included in the environment. The encapsulation layer 139 may be a single-layer structure or a composite layer structure including a stacked structure of an inorganic layer and an organic layer. The encapsulation layer 139 includes at least one encapsulation sublayer. For example, the encapsulation layer 139 may include a first inorganic encapsulation layer, a first organic encapsulation layer, and a second inorganic encapsulation layer, which are sequentially disposed.

[0113] For example, the material of the encapsulation layer 139 may include insulating materials such as silicon nitride, silicon oxide, silicon oxynitride, and polymer resin. Inorganic materials such as silicon nitride, silicon oxide, and silicon oxynitride have high density and can prevent the intrusion of water, oxygen, etc.; the material of the organic encapsulation layer may be a polymer material containing a desiccant or a polymer material that can block water vapor, such as a polymer resin, etc., to planarize the surface of the display substrate, and to relieve the stress of the first inorganic encapsulation layer and the second inorganic encapsulation layer, and may also include a desiccant and other water-absorbing materials to absorb water, oxygen, and other substances that intrude into the interior.

[0114] For example, in some embodiments, Figure 3 As shown, the display substrate 1 further includes a filter layer LG and a black matrix BM. The filter layer LG and the black matrix BM are located on the side of the light emitting element 160 away from the base substrate 10, that is, located on the encapsulation layer 139. The filter layer LG and the black matrix BM can be partially stacked, and in the stacked portion of the filter layer LG and the black matrix BM, the black matrix BM is located on the side of the filter layer LG close to the base substrate 10.

[0115] Figure 6 A schematic diagram of the layout of a sub-pixel driving circuit and a light-emitting element of a display substrate provided in at least one embodiment of the present disclosure. Figure 7 A schematic diagram of the layout of a black matrix and a filter layer of a display substrate provided in at least one embodiment of the present disclosure.

[0116] For example, in some embodiments, in combination Figure 6 and Figure 7 As shown, in each pixel area P10, the black matrix BM includes a plurality of light shielding lines extending along the first direction X (eg Figure 7BM1 / BM2 shown). The filter layer LG includes a first sub-pixel filter area LG1, a second sub-pixel rate filter area LG2, and a third sub-pixel filter area LG3. The first sub-pixel filter area LG1, the second sub-pixel rate filter area LG2, and the third sub-pixel filter area LG3 are arranged spaced apart from each other along the second direction Y. At least part of the orthographic projection of the plurality of light shielding lines on the board surface of the base substrate 10 overlaps with the interval between the first sub-pixel filter area LG1, the second sub-pixel rate filter area LG2, and the third sub-pixel filter area LG3 in the second direction Y. For example, the light shielding line BM1 of the plurality of light shielding lines overlaps with at least part of the orthographic projection on the board surface of the base substrate 10 and the interval between the first sub-pixel filter area LG1 and the second sub-pixel rate filter area LG2 in the second direction Y. For example, the light shielding line BM2 of the plurality of light shielding lines overlaps with at least part of the orthographic projection on the board surface of the base substrate 10 and the interval between the second sub-pixel rate filter area LG2 and the third sub-pixel filter area LG3 in the second direction Y. For example, the first sub-pixel filter area LG1, the second sub-pixel filter area LG2, and the third sub-pixel filter area LG3 correspond to the light-emitting elements of the sub-pixels of the pixel area P10, respectively. In addition to the plurality of light-shielding lines, on the side of the filter layer LG close to the light-transmitting area TM10, the black matrix BM does not include other light-shielding lines that do not extend along the first direction X. In other words, the black matrix BM does not include light-shielding lines that are arranged between the light-transmitting area TM10 and the pixel area P10 and extend in other directions, and only includes Figure 7 The shielding lines shown in the figure extend along the first direction and are arranged in the spacing area between the first sub-pixel filter area LG1, the second sub-pixel filter area LG2 and the third sub-pixel filter area LG3 in the second direction Y. Thus, the area of ​​the light-transmitting area TM10 can be increased to increase the transmittance of the display substrate.

[0117] For example, the angle between the first direction X and the second direction Y involved in the present disclosure is between 70° and 90°, including 70° and 90°. For example, the angle between the first direction X and the second direction Y is 70°, 90°, or 80°, etc., which can be set according to actual conditions, and the embodiments of the present disclosure are not limited to this. For example, the angle between the first direction X and the second direction Y can also be 75°, 85°, etc.

[0118] For example, the material of the filter layer may include a resin material doped with a colorant, such as a dye or a pigment, so that the resin material, such as a polymer resin material, has color. For example, the material of the black matrix BM may include an opaque black resin material.

[0119] For example, in some embodiments, the first sub-pixel filter area LG1, the second sub-pixel filter area LG2, and the third sub-pixel filter area LG3 are respectively a red light area, a green light area, and a blue light area, that is, they transmit red light, green light, and blue light respectively. The order of the colors of the light transmitted by the first sub-pixel filter area LG1, the second sub-pixel filter area LG2, and the third sub-pixel filter area LG3 can be interchanged, and the embodiments of the present disclosure are not limited thereto.

[0120] For example, in some embodiments, Figure 2 As shown, in the first direction X, on the side of the pixel area P10 close to the light transmission area TM10, the orthographic projections of the first sub-pixel filter area LG1, the second sub-pixel rate filter area LG2, and the third sub-pixel filter area LG3 on the board surface of the base substrate 10 partially overlap with the orthographic projections of the pixel defining layer 138 on the board surface of the base substrate 10. That is, in the direction perpendicular to the board surface of the base substrate 10, on the side close to the light transmission area TM10, the edges of the first sub-pixel filter area LG1, the second sub-pixel rate filter area LG2, and the third sub-pixel filter area LG3 that exceed the pixel defining layer 138 extend to the top of the pixel defining layer 138. Figure 3 As shown, the length of the orthographic projection of the first sub-pixel filter area LG1, the second sub-pixel filter area LG2 or the third sub-pixel filter area LG3 on the surface of the base substrate 10 and the overlapping portion of the pixel defining layer 138 on the surface of the base substrate 10 is D5. Thus, under the premise of not ensuring the occupation of the transparent area, it is also ensured that the light leakage of the light-emitting area of ​​the light-emitting element can be reduced at different angles to reduce the color attenuation of the display substrate.

[0121] Figure 5 A schematic diagram of an optical simulation of a display substrate provided by at least one embodiment of the present disclosure.

[0122] For example, in some embodiments, the overlapping portions of the first sub-pixel filter area LG1, the second sub-pixel filter area LG2, and the third sub-pixel filter area LG3 with the pixel defining layer 138 in a direction perpendicular to the base substrate 10 have a size range along the first direction X of, for example, approximately 5 microns to 7 microns, for example, approximately 6 microns, thereby achieving a better display effect.

[0123] For example, Figure 5 As shown, taking the case where the filter area exceeds the pixel defining layer 138 in the first direction X as an example, optical simulation in the second direction Y is performed to select a suitable value range for the filter area to exceed the pixel defining layer 138 . Figure 5 The length D5 of the middle filter layer beyond the pixel defining layer 138 in the first direction X (also as shown in FIG. Figure 3The length D5 is preferably in the range of about 5 microns to 7 microns, for example, about 6 microns. At this time, the effect of preventing light leakage is better and the display effect requirements can be met. When the value of the length D5 is larger, the effect of preventing light leakage is better. If the design size allows, a larger length D5 can be selected. It should be noted that Figure 5 The pixel defining layer 138 in FIG. 1 shows an opening area (ie, the pixel defining layer 138 is shown in reverse, and the marked area is the dug-out area).

[0124] For example, in some embodiments, Figure 3 As shown, the display substrate further includes a light-transmitting layer 1310 and a protective layer 1311. The light-transmitting layer 1310 is disposed on the side of the filter layer LG away from the base substrate 10. The protective layer 1311 is disposed on the side of the light-transmitting layer 1310 away from the base substrate 10. For example, the protective layer 1311 can be used as a cover plate, and the material of the protective layer 1311 can include a flexible material, such as transparent polyimide (CPI, Colorless Polyimide), polyethylene terephthalate (PET, Polyethylene Terephthalate) or cycloolefin polymer (COP, Cyclo Olefin Polymer) and the like. For example, the light-transmitting layer 1310 can be an optical adhesive layer, that is, it can play a role of light transmission and also play a role of bonding. For example, the material of the light-transmitting layer 1310 can include a transparent insulating material, such as a transparent organic material such as polyimide, resin, a special double-sided adhesive (OCA, Optically Clear Adhesive) with an optically transparent layer and no substrate.

[0125] For example, in some embodiments, Figure 1 As shown, the gate driving circuit 13 is configured to output gate scanning signals for driving the plurality of sub-pixels of the pixel area P10 of each row of repeating units C1 extending along the first direction X one by one through the gate line G10. The plurality of repeating units C1 are arranged in N rows extending along the first direction, and the gate driving circuit 13 includes N cascaded shift register units 170 (such as Figure 8B As shown), the n-th stage shift register unit 170 is connected to the sub-pixel driving circuit 1601 of the pixel area P10 of the n-th row of repeating units C1, wherein 1≤n≤N, and N is an integer greater than or equal to 2.

[0126] For example, Figure 2 As shown, a plurality of sub-pixel driving circuits of the pixel area P10 of each repeating unit C1 are arranged along the first direction X. The plurality of sub-pixel driving circuits are respectively connected to different light emitting elements.

[0127] As shown in 8A, the sub-pixel driving circuit 1601 of each of the plurality of sub-pixels includes a data writing circuit 1603, a driving circuit 1604, a charge storage circuit 1606, and a sensing circuit 1605. The driving circuit 1604 is connected to a first node G, a second node S, and a third node D. The third node D is also connected to a first power supply voltage terminal ELVDD. For example, the first power supply voltage terminal ELVDD is connected to a power line VDD10 that provides a first power supply voltage. The driving circuit 1604 is configured to control the driving current flowing through the light-emitting element 160 under the control of the level of the first node G. The data writing circuit 1603 is connected to the first node G and is configured to receive a gate scanning signal (for example, the gate driving circuit is provided by the gate line G10) as a scanning driving signal, and writes the data signal to the first node G in response to the scanning driving signal. The charge storage circuit 1606 is connected to the first node G and the second node S, and is configured to store the written data signal and the reference voltage signal. The first electrode 161 of the light-emitting element 160 is connected to the second node S, configured to receive the gate scan signal as a sensing drive signal, and writes the reference voltage signal to the driving circuit 1604 or reads the sensing voltage signal from the driving circuit 1604 in response to the sensing drive signal. The light-emitting element 160 (for example, the first electrode 161 of the light-emitting element 160) is connected to the second node S and the second power supply voltage terminal ELVSS, and is configured to receive the second power supply voltage through the second power supply voltage terminal ELVSS, and emit light under the driving of the driving current. For example, the second power supply voltage terminal ELVSS is connected to the power line ELVSS (not shown in the figure), and the power line ELVSS is configured to provide the second power supply voltage.

[0128] For example, in the embodiment of the present disclosure, the power line ELVSS is configured to be routed around the display area 101, and the second electrode 1602 of the light emitting element 160 is disposed on the entire surface and connected to the power line ELVSS to receive the second power voltage.

[0129] For example, Fig. 8A As shown, the data writing circuit 1603 is implemented as a data writing transistor T1, the driving circuit 1604 is implemented as a driving transistor T2, the charge storage circuit 1606 is implemented as a storage capacitor CST, and the sensing circuit 1605 is implemented as a sensing transistor T3. Figure 1 The plurality of gate lines G10 in the embodiment include a first gate line G1 and a second gate line G2.

[0130] The first electrode of the data writing transistor T1 is connected to one of the plurality of data lines DATA so as to receive a data signal, and the second electrode of the data writing transistor T1 is connected to the first node G (that is, connected to the gate TG2 of the driving transistor T2). The gate TG1 of the data writing transistor T1 is connected to the first gate line G1 of the plurality of gate lines (that is, the gate line connected to the output end of the shift register unit) so as to receive a scan driving signal.

[0131] A first electrode of the driving transistor T2 is connected to a second power supply voltage terminal ELVDD and is configured to receive a first power supply voltage. A second electrode of the driving transistor T2 is connected to a second node S (ie, connected to a first electrode of the sensing transistor T3 ).

[0132] The gate G221 of the sensing transistor T22 is configured to receive a sensing drive signal. For example, the gate G221 of the sensing transistor T22 is connected to a second gate line G2 among the plurality of gate lines (i.e., a gate line connected to the output end of the shift register unit located in a different row from the sensing transistor T22) so as to receive the sensing drive signal. The first electrode of the sensing transistor T2 is connected to the second node S, and the second electrode of the sensing transistor T2 is connected to a sensing signal line SENSE (which is Figure 1 The sensing signal line SES10 is connected to one of the plurality of sensing signal lines SES10 in the sensing signal line SES10 and is configured to receive a reference voltage signal or output a sensing voltage signal.

[0133] The first electrode (for example, the first electrode 161) of the light-emitting element 160 is connected to the second node S, that is, connected to the second electrode (for example, the second electrode 162) of the driving transistor T2 and the first electrode of the sensing transistor T3, so as to receive the driving current of the driving transistor T2; the second electrode of the light-emitting element 160 is configured to be connected to the second power supply voltage terminal ELVSS to receive the second power supply voltage. For example, in some embodiments, the second electrode of the light-emitting element 160 is configured to be grounded, and the second driving voltage is 0V. For example, the first power supply voltage is a high level voltage (for example, 5V, 10V or other suitable voltages), and the second power supply voltage is a low level voltage (for example, 0V, -5V, -10V or other suitable voltages). When the driving transistor T2 is turned on (or partially turned on), the first power supply voltage and the second power supply voltage can be regarded as a power supply, which is used to generate a driving current for driving the light-emitting element 160.

[0134] It should be noted that the light emitting element 160 may be, for example, an organic light emitting diode (OLED) or a quantum dot light emitting diode (QLED).

[0135] For example, the above transistors are all described by taking N-type transistors as an example, that is, each transistor is turned on when the gate is connected to a high level (on level), and is turned off when the gate is connected to a low level (off level). It should be noted that the present disclosure includes but is not limited to this. For example, one or more transistors in the shift register unit provided in the embodiment of the present disclosure may also adopt P-type transistors. In this case, the first electrode may be a source electrode, and the second electrode may be a drain electrode. It is only necessary to connect the polarities of the electrodes of the selected type of transistors according to the polarities of the electrodes of the corresponding transistors in the embodiment of the present disclosure.

[0136] For example, Figure 8B A schematic diagram of the connection between a sub-pixel driving circuit and a register unit circuit of a sub-pixel unit circuit provided in at least one embodiment of the present disclosure. Figure 8B As shown, the first gate line G1 is connected to the data writing circuit 1603 of the multiple sub-pixel driving circuits 1601 of the pixel area P10 of the Mth row of repeating units C1 extending along the first direction X, the sensing circuit 1605 of the multiple sub-pixel driving circuits 1601 of the pixel area P10 of the M-1th row of repeating units C1 extending along the first direction X, and the output end of the Mth row of shift register units 170, so as to output the gate scanning signal outputted from the output end of the Mth row of shift register units 170 to the data writing circuit 1603 of the multiple sub-pixel driving circuits 1601 of the pixel area P10 of the Mth row of repeating units C1 as a scanning driving signal, and to the sensing circuit 1605 of the multiple sub-pixel driving circuits 1601 of the pixel area P10 of the M-1th row of repeating units C1 as a sensing driving signal. The second gate line G2 is connected to the sensing circuit 1605 of the plurality of sub-pixel driving circuits 1601 of the pixel area P10 of the Mth row of repeating unit C1, the data writing circuit 1603 of the plurality of sub-pixel driving circuits 1601 of the pixel area P10 of the M+1th row of repeating unit C1 extending along the first direction X, and the output end of the M+1th row of shift register unit 170, so as to output the gate scanning signal outputted from the output end of the M+1th row of shift register unit 170 to the data writing circuit 1603 of the plurality of sub-pixel driving circuits 1601 of the pixel area P10 of the M+1th row of repeating unit C1 as a scanning driving signal, and to the sensing circuit 1605 of the plurality of sub-pixel driving circuits 1601 of the pixel area P10 of the Mth row of repeating unit C1 as a sensing driving signal. 1<M<N, M is an odd number greater than 1.

[0137] It should be noted that, in the embodiment of the present disclosure, the Mth row extending along the first direction X represents the Mth row in the horizontal direction, and the Mth row extending along the second direction Y represents the Mth column in the vertical direction.

[0138] Fig. 9A A plan view of a light-shielding layer provided for at least one embodiment of the present disclosure.

[0139] For example, in some embodiments, in combination Fig. 9A as well as Figure 6In each pixel area P10, the light-shielding layer 131 includes a light-shielding electrode 111, which extends along the second direction Y (for example, the length of the light-shielding electrode 111 in the second direction Y is larger), and at least a portion of the positive projection of the light-shielding electrode 111 on the board surface of the base substrate 10, for example, partially overlaps with the positive projection of multiple sub-pixel driving circuits 1601 (for example, the first sub-pixel driving circuit P161, the second sub-pixel driving circuit P162 or the third sub-pixel driving circuit P163) of each pixel area P10 on the board surface of the base substrate 10, thereby blocking external light from irradiating to the sub-pixel driving circuit, especially the active layer of the transistor, to avoid the generation of dark current.

[0140] For example, Fig. 9A As shown, the light shielding electrode 131 includes a first end 1111, a middle recess 1113, and a second end 1112 in the second direction Y, and the middle recess 1113 is located between the first end 1111 and the second end 1112. The widths of the first end 1111 and the second end 1112 in the first direction X are greater than the width of the middle recess 1113 in the first direction. Figure 6 The orthographic projections of the first end 1111 and the second end 1112 on the board surface of the base substrate 10 overlap with the orthographic projections of the active layers of the data writing transistor T1, the driving transistor T2 and the sensing transistor T3 of the sub-pixel driving circuit 1601 on the board surface of the base substrate 10. The electrode overlapping area 12 is located between the middle recess 1113 and the light-transmitting area TM10. The light-shielding electrode 131 is set in a shape with narrow ends in the middle, which can reduce the space occupied by the light-shielding electrode 131 and increase the area of ​​the light-transmitting area.

[0141] For example, Figure 6 As shown, in the second direction Y, the sensing transistor T3 is located above (for example, above the storage capacitor CST), and the driving transistor T2 and the data writing transistor T1 are located on the side of the storage capacitor CST away from the sensing transistor T3. The orthographic projections of the active layers of the data writing transistor T1 and the driving transistor T2 on the board surface of the base substrate 10 overlap with the orthographic projections of the second end 1112 of the light shielding electrode 131 on the board surface of the base substrate 10. The orthographic projection of the active layer of the sensing transistor T3 on the board surface of the base substrate 10 overlaps with the orthographic projections of the first end 1111 of the light shielding electrode 131 on the board surface of the base substrate 10. Thus, the light shielding layer can block external light from irradiating the active layers of the data writing transistor T1, the driving transistor T2, and the sensing transistor T3 of the transistor to avoid the generation of dark current.

[0142] For example, in some embodiments, Figure 6 and Figure 7As shown, the first electrode CST1 and the second electrode CST2 of the storage capacitor CST of the sub-pixel driving circuit 1601 (for example, the first sub-pixel driving circuit P161, the second sub-pixel driving circuit P162 and the third sub-pixel driving circuit P163) of the pixel area P10 include a strip extending along the second direction Y. In each repeating unit C1, the first sub-pixel filter area LG1, the second sub-pixel filter area LG2 and the third sub-pixel filter area LG3 are arranged in sequence along the second direction Y, and the second sub-pixel filter area LG2 is located between the first sub-pixel filter area LG1 and the third sub-pixel filter area LG3. The first sub-pixel filter area LG1 overlaps with at least a portion (for example, a portion close to the storage capacitor CST) of the sensing transistor T3 of the sub-pixel driving circuits of the plurality of sub-pixels of the pixel area P10, and a portion of the storage capacitor CST close to the sensing transistor T3 (for example, if the strip storage capacitor CST is divided into three parts in the first direction Y, the portion is the portion located above the storage capacitor CST) in the orthographic projection on the plate surface of the base substrate 10. The third sub-pixel filter area LG3 overlaps with the orthographic projection of at least part of the data writing transistor and the driving transistor of the sub-pixel driving circuit of the multiple sub-pixels in the pixel area P10 (for example, the part close to the storage capacitor CST), and the part of the storage capacitor CST close to the driving transistor T2 (for example, the part below the storage capacitor CST) on the board surface of the base substrate 10. The second sub-pixel filter area LG2 overlaps with the orthographic projection of the storage capacitor CST of the sub-pixel driving circuit of the multiple sub-pixels in the pixel area P10 close to the middle part of the storage capacitor CST in the first direction (for example, the part in the middle of the storage capacitor CST) on the board surface of the base substrate 10. The design of the strip storage capacitor CST and the square-like filter area can increase the area of ​​the transparent area of ​​the display substrate and improve the display effect.

[0143] For example, in other embodiments, the first sub-pixel light filtering region LG1, the second sub-pixel light filtering region LG2 and the third sub-pixel light filtering region LG3 may also be designed as strips extending along the second direction Y, but the embodiments of the present disclosure are not limited thereto.

[0144] For example, at least one embodiment of the present disclosure further provides a display substrate, which includes a base substrate and a plurality of sensing lines. The plurality of sensing signal lines are arranged on the base substrate and extend along a second direction different from the first direction, two rows of repeating units respectively along the second direction are arranged between two adjacent ones of the plurality of sensing signal lines, and each of the plurality of sensing signal lines is simultaneously connected to the sub-pixel driving circuits of the plurality of sub-pixels of the two rows of repeating units respectively along the second direction adjacent thereto, and is configured to provide a reference voltage signal. Thus, the space occupied by the signal routing is reduced, the area of ​​the transparent area is increased, and the light transmittance is improved.

[0145] For example, in some embodiments, Figure 1As shown, a plurality of sensing signal lines SES10 are arranged on the substrate 10 and extend along the second direction Y. The plurality of sensing signal lines SES10 extend to the bonding area 13, and are, for example, also connected to the contact pad (not shown) of the bonding area 13 to receive the electrical signal provided by the external driving circuit (e.g., chip). Two rows of repeating units C1 are arranged between two adjacent ones of the plurality of sensing signal lines SES10, respectively along the second direction Y. Each of the plurality of sensing signal lines SES10 is simultaneously connected to the sub-pixel driving circuits of the plurality of sub-pixels of the two rows of repeating units C10 adjacent thereto and respectively along the second direction Y, and is configured to provide a reference voltage signal. That is, two adjacent ones of each of the plurality of sensing signal lines SES10 are spaced apart by two repeating units C1 in the same row. Each of the plurality of sensing signal lines SES10 is connected to the pixel areas P10 of the two repeating units C1 on both sides thereof along the first direction X. Thus, the sub-pixel driving circuits of the multiple sub-pixels in the pixel area P10 of the two repeating units C1 share one sensing signal line SES10, thereby reducing the number of sensing signal lines and the occupied wiring space, thereby increasing the area of ​​the transparent area.

[0146] For example, in some embodiments, Figure 1 As shown, a plurality of power lines VDD10 are arranged on the substrate 10 and extend along the second direction Y. In the first direction X, the plurality of power lines VDD10 and the plurality of sensing signal lines SES10 are alternately arranged. A row of repeating units C1 extending along the second direction Y is arranged between each of the plurality of sensing signal lines SES10 and the power line VDD10 adjacent thereto. That is, the plurality of power lines VDD10 and the plurality of sensing signal lines SES10 define a space for each row of repeating units C1 extending along the second direction Y. A row of repeating units C1 extending along the second direction Y is arranged between each of the plurality of power lines VDD10 and the sensing signal line SES10 adjacent thereto. Two rows of repeating units C1 extending along the second direction Y are arranged between two adjacent ones of the plurality of power lines VDD10. Each of the plurality of power lines VDD10 is simultaneously connected to the sub-pixel driving circuits of the plurality of sub-pixels of the two rows of repeating units C1 adjacent thereto and extending along the second direction Y, and is configured to provide a first power supply voltage. That is, two adjacent power lines VDD10 are spaced apart by two repeating units C1 in the same row. Each of the power lines VDD10 is connected to the pixel areas P10 of the two repeating units C1 on both sides thereof along the first direction X. Thus, the sub-pixel driving circuits of the multiple sub-pixels of the pixel areas P10 of the two repeating units C1 share one power line VDD10, thereby reducing the number of power lines and the occupied wiring space, thereby increasing the area of ​​the transparent area.

[0147] Fig. 9B A plan view of a first insulating layer provided for at least one embodiment of the present disclosure. Fig. 9CA plan view of a buffer layer provided for at least one embodiment of the present disclosure. Fig.9D A plan view of a semiconductor layer provided for at least one embodiment of the present disclosure. Fig.9E A layout diagram of a second conductive layer provided for at least one embodiment of the present disclosure. Fig.9F A plan view of an interlayer insulating layer provided for at least one embodiment of the present disclosure. Figure 9G A plan view of a first conductive layer provided for at least one embodiment of the present disclosure. Fig.10 for FIG. 9A to FIG. 9B The layout diagram after stacking. Figure 9B-9G as well as Fig.10 The structure of the sub-pixel unit driving circuit 1601 of the plurality of sub-pixels in the pixel area is described in detail. Figure 9B-9G as well as Fig.10 The structure of one sub-pixel unit driving circuit 1601 is taken as an example for description, and the structures of other sub-pixel unit driving circuits are the same and will not be repeated.

[0148] For example, in some embodiments, Figure 2 and Figure 6 As shown, the display area 101 includes a first repeating unit C11 and a second repeating unit C12 adjacently arranged along a first direction, a sensing signal line SES11 is arranged between the pixel area of ​​the first repeating unit C11 and the transparent area TM10 of the second repeating unit C12, and the sensing signal line SES11 is connected to a plurality of sub-pixel driving circuits of the pixel area P10 of the first repeating unit C11 and the second repeating unit C12. That is, a plurality of sub-pixel driving circuits of the pixel area P10 of the first repeating unit C11 and the second repeating unit C12 share one sensing signal line. A power line VDD11 is provided on a side of the pixel area P10 of the second repeating unit C12 away from the transparent area TM10 of the second repeating unit C12, and the power line VDD11 is connected to a plurality of sub-pixel driving circuits of the pixel area P10 of the second repeating unit C12. Another power line VDD12 is provided on a side of the transparent area TM10 of the first repeating unit C11 away from the pixel area P10 of the first repeating unit C11, and the other power line VDD12 is connected to a plurality of sub-pixel driving circuits of the pixel area P10 of the first repeating unit C11. Figure 2 and Figure 6 In the repeating unit shown, if another repeating unit is drawn on the left side of the first repeating unit C11, that is, the side where the other power line VDD12 is away from the first repeating unit C11, the sub-pixels in the pixel area of ​​the other repeating unit are also connected to the other power line VDD12. Figure 2 and Figure 6In the repeating unit shown, if another repeating unit is drawn on the right side of the second repeating unit C12, that is, on the side where the power line VDD11 is away from the second repeating unit C12, the sub-pixels in the pixel area of ​​the other repeating unit are also connected to the power line VDD11. That is to say, each power line is connected to the pixel area of ​​two repeating units. Figure 2 and Figure 6 The structure shown is introduced here, and other parts with similar structures will not be illustrated and introduced in detail.

[0149] For example, in some embodiments, Figure 2 and Figure 6 As shown, the multiple sub-pixel driving circuits of the pixel area P10 of the first repeating unit C11 and the multiple sub-pixel driving circuits of the pixel area P10 of the second repeating unit layer 2 respectively include a first sub-pixel driving circuit P161, a second sub-pixel driving circuit P162 and a third sub-pixel driving circuit P163 arranged in the first direction X. The second sub-pixel driving circuit P162 is located between the first sub-pixel driving circuit P161 and the third sub-pixel driving circuit P163. The orthographic projections of the first sub-pixel driving circuit P161, the second sub-pixel driving circuit P162 and the third sub-pixel driving circuit P163 on the surface of the base substrate 10 all extend along the second direction Y. The first sub-pixel driving circuit P161 is mirror-symmetrical to the second sub-pixel driving circuit P162 and the third sub-pixel driving circuit P163.

[0150] It should be noted that in the embodiment of the present disclosure, the structurally identical parts of the first sub-pixel driving circuit P161, the second sub-pixel driving circuit P162 and the third sub-pixel driving circuit P163 are introduced taking one sub-pixel driving circuit as an example, and the other sub-pixel driving circuits will not be described in detail.

[0151] For example, Fig. 9B As shown, the first insulating layer 132 is provided with a first overlapping sub-hole FK111 located in the electrode overlapping region 12 to expose Fig. 9A The light shielding layer 131 shown, for example, the middle concave portion 1113 of the light shielding layer 131 .

[0152] For example, Fig. 9C As shown, the buffer layer 133 is provided with a third overlapping sub-hole FK113 located in the electrode overlapping region 12 to expose Fig. 9A The light shielding layer 131 shown, for example, the middle recess 1113 of the light shielding layer 131. The third overlapping sub-hole FK113 is sleeved in the first overlapping sub-hole FK111.

[0153] For example, in some embodiments, Figure 6 and Fig.9DAs shown, the orthographic projections of the data writing transistor T1, the driving transistor T2, and the sensing transistor T3 of the sub-pixel driving circuit on the base substrate 10 all extend along the second direction Y. Figure 6 In the embodiment, the semiconductor layer ACT includes an active layer TA1 of a data write transistor T1 of a sub-pixel driving circuit, an active layer TA2 of a driving transistor T2, and an active layer TA3 of a sensing transistor T3. The active layer TA1 of the data write transistor T1 of the sub-pixel driving circuit, the active layer TA2 of the driving transistor T2, and the active layer TA3 of the sensing transistor T3 all extend along the second direction Y. For example, the base substrate 10 may be a flexible substrate. Thus, when the display substrate is bent, the electrical performance of each transistor of the sub-pixel driving circuit can be ensured not to be affected, thereby ensuring the stability of the display of the display substrate.

[0154] For example, the active layer TA1 of the data writing transistor T1, the active layer TA2 of the driving transistor T2 and the active layer TA3 of the sensing transistor T3 may not be parallel to the second direction Y, for example, intersect the second direction Y at a certain angle. For example, the intersection angle is less than or equal to 20°.

[0155] For example, Fig.9D As shown, taking the first sub-pixel driving circuit P161 as an example, the structure of the active layer and storage capacitor of each transistor of the sub-pixel driving circuit is described in detail. For example, the semiconductor layer ACT also includes the first plate CST1 of the storage capacitor of the first sub-pixel driving circuit P161. The active layer TA3 of the sensing transistor T3 is located on the upper side of the first plate CST1 of the storage capacitor, the active layer TA2 of the driving transistor T2 and the active layer TA1 of the data writing transistor T1 are located on the side of the first plate CST1 of the storage capacitor away from the sensing transistor T3, and the active layer TA2 of the driving transistor T2 is located between the sensing transistor T3 and the data writing transistor T1. The first plate CST1 of the storage capacitor CST is connected to the active layer TA2 of the driving transistor T2 and is integrally arranged. The first plate CST1 of the storage capacitor is in the shape of a strip extending along the second direction Y. A convex portion CST11 protruding from one side away from the transparent area TM10 is provided at a position of the first electrode plate CST1 of the storage capacitor corresponding to the electrode overlapping area 12, and the convex portion has a notch CST12, and the notch CST12 surrounds the electrode overlapping area 12 to leave space for the electrode overlapping area 12. That is, the electrode overlapping area 12 occupies part of the space of the first electrode plate CST1, thereby reducing the space occupied by the electrode overlapping area 12 in the transparent area TM10 and increasing the area of ​​the transparent area. For example, Fig.9DAs shown, the shape of the first plate CST1 of the storage capacitor of the second sub-pixel driving circuit P162 is slightly different from that of the first plate CST1 of the storage capacitor of the first sub-pixel driving circuit P161. The first plate CST1 of the storage capacitor of the second sub-pixel driving circuit P162 is bent at the portion corresponding to the convex portion CST11 to leave a routing space between the first sub-pixel driving circuit P161 and the second sub-pixel driving circuit P162. The shape of the first plate CST1 of the storage capacitor of the third sub-pixel driving circuit P163 is slightly different from that of the first plate CST1 of the storage capacitor of the first sub-pixel driving circuit P161 and the second sub-pixel driving circuit P162. The first plate CST1 of the storage capacitor of the third sub-pixel driving circuit P163 is concave to the right side (away from the second sub-pixel driving circuit P162) at the edge of the side close to the second sub-pixel driving circuit P162 corresponding to the convex portion CST11 to leave a routing space between the second sub-pixel driving circuit P162 and the third sub-pixel driving circuit P163. That is, a structure similar to the recess CST12 surrounding the electrode overlapping region 12 may also be correspondingly disposed in the first electrode plate CST1 of the storage capacitor of the second sub-pixel driving circuit P162 and the third sub-pixel driving circuit P163.

[0156] For example, Fig.9D As shown, the active layer TA3 of the sensing transistor T3 includes a source region TS3, a channel region TP3, and a drain region TD3. For example, the active layer TA2 of the driving transistor T2 includes a source region TS2, a channel region TP2, and a drain region TD2. For example, the active layer TA1 of the data writing transistor T1 includes a source region TS1, a channel region TP1, and a drain region TD1.

[0157] For example, Fig.9E As shown, the second conductive layer GATE includes the gate TG1 of the data writing transistor T1, the gate TG2 of the driving transistor T2, and the gate TG3 of the sensing transistor T3. The orthographic projection of the channel region TP3 on the substrate partially overlaps with the orthographic projection of the gate TG3 on the substrate. The orthographic projection of the channel region TP1 on the substrate partially overlaps with the orthographic projection of the gate TG1 on the substrate. The orthographic projection of the channel region TP2 on the substrate partially overlaps with the orthographic projection of the gate TG2 on the substrate.

[0158] For example, Figure 9G As shown, the first conductive layer SD includes the first electrode TSD11 and the second electrode TSD12 of the data writing transistor T1, the first electrode TSD21 and the second electrode TSD22 of the driving transistor T2, the first electrode TSD31 and the second electrode TSD32 of the gate of the sensing transistor T3, and the second electrode CST2 of the storage capacitor CST. Fig.9DAs shown, the first electrode TSD11 and the second electrode TSD12 of the data writing transistor T1 overlap with the orthographic projections of the source region TS1 and the drain region TSD1 of the data writing transistor T1 on the substrate 10, respectively. The first electrode TSD21 and the second electrode TSD22 of the driving transistor T2 overlap with the orthographic projections of the source region TS2 and the drain region TD2 of the driving transistor T2 on the substrate 10, respectively. The first electrode TSD31 and the second electrode TSD32 of the sensing transistor T3 overlap with the orthographic projections of the source region TS3 and the drain region TD3 of the sensing transistor T3 on the substrate 10, respectively. A second insulating layer 134 is spaced between the second plate CST2 of the storage capacitor CST and the first plate CST1 of the storage capacitor to form a capacitor function. Combined Fig.9F As shown, the first electrode TSD31 of the sensing transistor T3 is connected to the source region TS3 through the third via GK3, and the second electrode TSD32 of the sensing transistor T3 is connected to the drain region TD3 through the first source-drain via SDG1 (for example, through the second insulating layer 134). The first electrode TSD21 of the driving transistor T2 is connected to the source region TS2 through the second source-drain via SDG2 (for example, through the second insulating layer 134), and the second electrode TSD22 of the driving transistor T2 is connected to the drain region TD2 through the fourth via GK3. The first electrode TD11 of the data writing transistor T1 is connected to the source region TS1 through the third source-drain via SDG3 (for example, through the second insulating layer 134), and the second electrode TD12 of the data writing transistor T1 is connected to the drain region TD1 through the fourth source-drain via SDG4 (for example, through the second insulating layer 134). Among them, the structures of the third via GK3 and the fourth via GK3 will be described in detail later.

[0159] It should be noted that the first source-drain via hole SDG1 , the second source-drain via hole SDG2 , the third source-drain via hole SDG3 , and the fourth source-drain via hole SDG4 may be disposed to pass through the second insulating layer 134 and the fourth insulating layer 137 .

[0160] For example, the size range of the first source drain via SDG1, the second source drain via SDG2, the third source drain via SDG3 and the fourth source drain via SDG4 may be about 2-4 microns, for example, about 3 microns. The sizes of the first source drain via SDG1, the second source drain via SDG2, the third source drain via SDG3 and the fourth source drain via SDG4 are selected by the display substrate during the manufacturing process.

[0161] It should be noted that a second insulating layer 134 and a fourth insulating layer 137 may be spaced between the second electrode plate CST2 and the first electrode plate CST1 of the storage capacitor CST, but the embodiment of the present disclosure is not limited thereto.

[0162] For example, Fig.9FAs shown, the second insulating layer 134 further includes a second overlapping sub-hole FK112 located in the electrode overlapping region 12 .

[0163] For example, Figure 9G As shown, the first conductive layer SD further includes a first bonding electrode FD11 located in the electrode bonding area 12 .

[0164] For example, in some embodiments, Figure 9G As shown, one end of the second plate CST2 of the storage capacitor CST close to the second electrode TSD32 of the sensing transistor T3 is connected to the second electrode TSD2 of the sensing transistor T3, and the second plate CST2 and the second electrode TSD32 of the sensing transistor T3 are integrally arranged. The first electrode TSD21 of the driving transistor T2 is connected to one end of the second plate CST2 of the storage capacitor CST far from the sensing transistor T3, and the first electrode TSD21 of the driving transistor T2 is integrally arranged with the second plate CST2 to reduce the occupied space.

[0165] For example, Fig.9E , Figure 9G and Fig.10 As shown, each of the multiple power lines, such as the power line VDD11 or the power line VDD12, includes a first sub-line VDD111 located in the second conductive layer GATE and a second sub-line VDD121 located in the first conductive layer SD. The first sub-line VDD111 includes a plurality of first routing segments VDD112 extending along the second direction Y, and the plurality of first routing segments VDD112 are respectively located in different repeating units C1, and the second sub-line VDD121 passes through the display area 101 along the second direction Y. That is, the power line is a double-layer routing, respectively in the first conductive layer SD and the second conductive layer GATE, each first routing segment VDD112 of each first sub-line VDD111 in the second conductive layer GATE is located in a repeating unit C1, and the second sub-line VDD121 of the first conductive layer SD extends along the second direction Y and passes through a row of repeating units C1 in the second direction Y, that is, the second sub-line VDD121 is arranged in the second direction Y as a whole. The second sub-line VDD121 is stacked on the side of the first sub-line VDD111 away from the substrate 10, and passes through at least one first via hole GK1 (such as Fig.9F As shown) is connected to the first sub-line VDD111. Fig.9F As shown, a plurality of first via holes GK1 are arranged along the second direction Y for connecting the second sub-line VDD121 and the first sub-line VDD111. Thus, the wiring resistance of the power line can be reduced.

[0166] For example, Fig.9E , Figure 9G and Fig.10As shown, each of the plurality of sensing signal lines, for example, the sensing line SES11 includes a third sub-line SES111 located in the second conductive layer GATE and a fourth sub-line SES121 located in the first conductive layer SD, the third sub-line SES111 includes a plurality of second routing segments SES112 extending along the second direction Y, the plurality of second routing segments SES112 are distributed in different repeating units, and the fourth sub-line SES121 passes through the display area 101 along the second direction Y. That is, the sensing line is a double-layer routing line, respectively in the first conductive layer SD and the second conductive layer GATE, each second routing segment SES112 of the third sub-line SES111 in the second conductive layer GATE is located in a repeating unit C1, and the fourth sub-line SES121 of the first conductive layer SD extends along the second direction Y and passes through a row of repeating units C1 in the second direction Y, that is, the fourth sub-line SES121 is arranged in the second direction Y as a whole. The fourth sub-line SES121 is stacked on the side of the second sub-line SES111 away from the substrate 10, and passes through at least one second via hole GK2 (eg, Fig.9F As shown) is connected to the third sub-line SES111. Fig.9F As shown, a plurality of second via holes GK2 are arranged along the second direction Y for connecting the fourth sub-line SES121 and the third sub-line SES111. Thus, the wiring resistance of the power line can be reduced.

[0167] For example, in some embodiments, Figure 9G and Fig.10 As shown, the first conductive layer SD includes a first switching electrode ZL1 extending along the first direction X. The first end ZL11 of the first switching electrode ZL1 is connected to the first electrode TSD31 of the sensing transistor T3 of the third sub-pixel driving circuit P163 of the first repeating unit C11. The second end ZL12 of the first switching electrode ZL1 is connected to the first electrode TSD31 of the sensing transistor T3 of the first sub-pixel driving circuit P161 of the second repeating unit C12, and the first switching electrode ZL1 is cross-connected with the second sub-line SES121 of the sensing signal line SES11. In other words, the sensing signal line SES11 provides a reference voltage signal to the first repeating unit C11 and the second repeating unit C12 at the same time through the first switching electrode ZL1.

[0168] Fig.11A for Fig.10 Magnified view of the A1 region.

[0169] For example, in some embodiments, Fig.9E and Fig.11AAs shown, the second conductive layer GATE includes a first connecting wire LL1 extending along the first direction X, and the first connecting wire LL1 is connected to the first sub-pixel driving circuit P161, the second sub-pixel driving circuit P162, and the first electrode TSD31 of the sensing transistor T3 of the third sub-pixel driving circuit P163 of the first repeating unit C11 or the second repeating unit C12 through at least a portion (for example, a portion) of the third via hole GK3. That is, a first connecting wire LL1 is set in the pixel area of ​​each repeating unit, so that the first electrodes TSD31 of the sensing transistors T3 of the plurality of sub-pixel driving circuits all receive the reference voltage signal provided by the sensing signal line SES11. At least a portion (for example, a portion) of the orthographic projection of the first electrode TSD31 of the sensing transistor T3 of the first sub-pixel driving circuit P161, the second sub-pixel driving circuit P162, and the third sub-pixel driving circuit P163 on the board surface of the base substrate 10 overlaps with the orthographic projection of the first connecting wire LL1 on the board surface of the base substrate 10.

[0170] For example, the first connection line LL1 may not be parallel to the first direction X, for example, it may intersect the first direction X at a certain angle. For example, the intersection angle is less than or equal to 20°.

[0171] Fig. 11B for Fig.11A Schematic diagram of the cross section along line B1-B2.

[0172] like Fig. 11B As shown, the part of the orthographic projection of the first electrode TSD31 on the board surface of the substrate 10 overlaps with the orthographic projection of the first connection line LL1 on the board surface of the substrate 10. The first electrode TSD31 of the sensing transistor T3 includes a first sub-portion TSD311 and a second sub-portion TSD312 connected along the second direction Y. The projection of the third via GK3 on the substrate 10 overlaps with the projections of the first sub-portion TSD311 and the second sub-portion TSD312 of the first electrode TSD31 on the substrate 10. A portion of the third via GK3, such as a portion overlapping with the projection of the first sub-portion TSD311 on the substrate 10, is configured to penetrate the second insulating layer 134 and the fourth insulating layer 137 to expose the active layer TA3 (e.g., the source region TS3) of the sensing transistor T3. Another portion of the third via GK3, such as a portion overlapping with the projection of the second sub-portion TSD312 on the substrate 10, is configured to penetrate the second insulating layer 134 to expose the first connection line LL1. The first sub-portion TSD311 contacts and connects to the active layer TA3 of the sensing transistor T3, and the second sub-portion TSD312 contacts and connects to the first connection line LL1. The cross-sectional structure of the third via GK3 can also be called a semi-buried via, so that the wiring space can be reduced to leave space for the transparent area.

[0173] For example, Fig.11A As shown, the width of the third via hole GK3 in the first direction X is, for example, about 2-4 microns, for example, about 3 microns. The length of the third via hole GK3 in the second direction Y is, for example, about 5-7 microns, for example, about 6 microns.

[0174] For example, in some embodiments, Figure 9G and Fig.10 As shown, the first conductive layer SD further includes a second switching electrode ZL2 and a third switching electrode ZL3, and the second switching electrode ZL2 and the third switching electrode ZL3 respectively include the third node D (as shown in FIG. Fig. 8A As shown). The second electrode TSD22 of the driving transistor T2 is located on a side of the driving transistor T2 away from the storage capacitor CST. One end of the second switching electrode ZL2 is connected to the second electrode TSD22 of the driving transistor T2 of the third sub-pixel driving circuit P163 of the second repeating unit C12, and the other end of the second switching electrode ZL2 is connected to the power line VDD11 of the third sub-pixel driving circuit P163 close to the second repeating unit C12 to provide a first power supply voltage. The second switching electrode ZL2 extends along the first direction X. One end of the third switching electrode ZL3 is connected to the second electrode TSD22 of the driving transistor T2 of the first sub-pixel driving circuit P161 of the first repeating unit C11, and the other end of the third switching electrode ZL3 is connected to the power line VDD12 of the transparent area TM10 close to the first repeating unit C11 to provide a first power supply voltage. The third transfer electrode ZL3 is routed on the lower side of the light-transmitting area TM10 (the side close to the data writing transistor T1), and is bent between the transparent area TM10 and the pixel area P10 toward the side close to the driving transistor T2 to reduce the wiring space. In other words, the power line VDD11 or the power line VDD12 is connected to a second transfer electrode ZL2 and a third transfer electrode ZL3 to connect to the sub-pixel driving circuits on both sides thereof, and the structure of the other side of the power line VDD11 and the power line VDD12 will not be repeated here.

[0175] Fig. 11C for Fig.10 Magnified view of area A2 in the middle.

[0176] For example, in some embodiments, Figure 9G and Fig. 11CAs shown, the second conductive layer includes a second connecting wire LL2 extending along the first direction X, and the second connecting wire LL2 is connected to the first sub-pixel driving circuit P161, the second sub-pixel driving circuit P162 and the second pole TSD22 of the driving transistor T2 of the third sub-pixel driving circuit P163 of the first repeating unit C11 or the second repeating unit C12 through at least a portion (for example, a portion) of the fourth via GK4. In other words, the plurality of sub-pixel driving circuits in the pixel area are all connected to the power line through the second connecting wire LL2. The orthographic projection of the second pole TSD22 of the driving transistor T2 of the first sub-pixel driving circuit P161, the second sub-pixel driving circuit P162 and the third sub-pixel driving circuit P163 on the board surface of the base substrate 10 overlaps with the orthographic projection of the second connecting wire LL2 on the board surface of the base substrate 10. The cross-sectional structure of the fourth via GK4 is similar to that of the third via GK3 and will not be described in detail here.

[0177] For example, the second connection line LL2 may not be parallel to the first direction X, for example, it may intersect the first direction X at a certain angle. For example, the intersection angle is less than or equal to 20°.

[0178] For example, in some embodiments, Figure 9G and Fig.10 As shown, the display substrate 1 further includes a plurality of data lines, the plurality of data lines extend along the second direction Y, and the plurality of data lines include a first data line DR, a second data line DG, and a third data line DB located in each repeating unit. The first data line DR and the second data line DB are located between the first sub-pixel driving circuit P161 and the second sub-pixel driving circuit P162, and the third data line DB is located between the second sub-pixel driving circuit P162 and the third sub-pixel driving circuit P163. The first data line DR, the second data line DG, and the third data line DB are bent and routed at a position corresponding to the electrode overlapping area 12. The first data line DR, the second data line DG, and the third data line DB are electrically connected to the first sub-pixel driving circuit P161, the second sub-pixel driving circuit P162, and the third sub-pixel driving circuit P163, respectively, to provide data signals, respectively. The first conductive layer further includes a fourth transfer electrode ZL4, a fifth transfer electrode ZL5, and a sixth transfer electrode ZL6 along the first direction X. The fourth transfer electrode ZL4 is connected to the first data line DR and the second electrode TSD12 of the data write transistor T1 of the first sub-pixel driving circuit P161, the fifth transfer electrode ZL5 is connected to the second data line DG and the second electrode TSD12 of the data write transistor T1 of the second sub-pixel driving circuit P162, and the sixth transfer electrode ZL6 is connected to the third data line DB and the second electrode TSD12 of the data write transistor T1 of the third sub-pixel driving circuit P163.

[0179] For example, the fourth switching electrode ZL4 , the fifth switching electrode ZL5 , and the sixth switching electrode ZL6 may not be parallel to the first direction X, for example, they may intersect the first direction X at a certain angle. For example, the intersection angle is less than or equal to 20°.

[0180] For example, Figure 9G and Fig.10 As shown, the second electrode TSD12 and the fourth switching electrode ZL4 of the data writing transistor T1 of the first sub-pixel driving circuit P161 are mirror-symmetrical with the second electrode TSD12 and the fifth switching electrode ZL5 of the data writing transistor T1 of the second sub-pixel driving circuit P162.

[0181] For example, in some embodiments, Fig.9E and Fig.11A As shown, the first gate line G1 and the second gate line G2 are located in the second conductive layer GATE, the first gate line G1 is close to the sensing transistor T3 of the first repeating unit C11 and the second repeating unit C12, and the second gate line G2 is close to the data writing transistor T1 of the first repeating unit C11 and the second repeating unit C12. The first gate line G1 includes a fold line portion, and the fold line portion includes a first fold line portion G111 along the first direction X, a second fold line portion G112 along the second direction Y respectively connected to both ends of the first fold line portion G111, and a third fold line portion G113. The first fold line portion G111, the second fold line portion G111, and the third fold line portion G113 bypass the first connecting line ZL1. The orthographic projection of the first fold line portion G111 on the board surface of the base substrate 10 overlaps with the orthographic projection of the active layer TA3 of the sensing transistor T3 of the first sub-pixel driving circuit P161, the second sub-pixel driving circuit P162 and the third sub-pixel driving circuit P163 of the first repeating unit C10 on the board surface of the base substrate 10, and the overlapping part forms the gate TG3 of the sensing transistor T3.

[0182] For example, Figure 9G and Fig.10As shown, the second conductive layer GATE also includes a third connection line LL3, a fourth connection line LL4 and a fifth connection line LL5. The third connection line LL3, the fourth connection line LL4 and the fifth connection line LL5 are roughly "L"-shaped broken lines, and the bending directions of the fourth connection line LL4 and the fifth connection line LL5 are the same (for example, toward the first sub-pixel driving circuit P161), and the bending direction of the third connection line LL3 (for example, toward the second sub-pixel driving circuit P162) is opposite to the bending direction of the fourth connection line LL4 and the fifth connection line LL5. The third connection line LL3 is connected to the second gate line G2 and the gate TG1 of the data write transistor T1 of the first sub-pixel driving circuit P161. The fourth connection line LL4 is connected to the second gate line G2 and the gate TG1 of the data write transistor T1 of the second sub-pixel driving circuit P162. The fifth connection line LL5 is connected to the second gate line G2 and the gate TG1 of the data write transistor T1 of the third sub-pixel driving circuit P163.

[0183] For example, in some embodiments, Figure 9G and Fig.10 As shown, the first conductive layer SD further includes a seventh transfer electrode ZL7, an eighth transfer electrode ZL8, and a ninth transfer electrode ZL9 along the second direction Y. The orthographic projections of the seventh transfer electrode ZL7, the eighth transfer electrode ZL8, and the ninth transfer electrode ZL9 on the board surface of the base substrate 10 overlap with the orthographic projections of the second connection trace ZL2 on the board surface of the base substrate 10. The first end (the end located at the upper end) of the seventh transfer electrode ZL7 is connected to the gate TG2 of the driving transistor T2 of the first sub-pixel driving circuit P161 through at least a portion (for example, a portion) of the eighth via hole GK8 penetrating the second insulating layer 134, and the second end (the end located at the lower end) of the seventh transfer electrode ZL7 is connected to the first electrode TSD11 of the data writing transistor T1 of the first sub-pixel driving circuit P161. The first end (the end located at the top) of the eighth transfer electrode ZL8 is connected to the gate TG2 of the driving transistor T2 of the second sub-pixel driving circuit P162 through at least a portion (for example, a portion) of the ninth via hole GK9 penetrating the second insulating layer 134, and the second end (the end located at the bottom) of the eighth transfer electrode ZL8 is connected to the first electrode TSD11 of the data writing transistor T1 of the second sub-pixel driving circuit P162. The first end (the end located at the top) of the ninth transfer electrode ZL9 is connected to the gate TG3 of the driving transistor T3 of the third sub-pixel driving circuit P163 through at least a portion (for example, a portion) of the tenth via hole GK10 penetrating the second insulating layer 134, and the second end (the end located at the bottom) of the ninth transfer electrode ZL9 is connected to the first electrode TSD11 of the data writing transistor T1 of the third sub-pixel driving circuit P163.

[0184] For example, the seventh switching electrode ZL7 , the eighth switching electrode ZL8 , and the ninth switching electrode ZL9 may not be parallel to the first direction X, for example, they may intersect the first direction X at a certain angle. For example, the intersection angle is less than or equal to 20°.

[0185] For example, the structures of the eighth via hole GK8 , the ninth via hole GK9 , and the tenth via hole GK10 may be similar to the structure of the third via hole GK3 , and will not be described in detail herein.

[0186] For example, in some embodiments, Fig.10 As shown, in the second direction Y, the portion where the first gate line G1 and the first connecting line ZL1 are arranged in parallel is located on one side of the transparent area TM10 of the first connecting line ZL1 close to the second repeating unit C12. In the second direction Y, the first connecting line ZL1 is spaced apart from the first fold line G111 of the first gate line G1, and the second connecting line ZL2 is spaced apart from the second gate line G2, so as to reduce interference between routing signals.

[0187] Fig. 12A A plan view of a passivation layer provided for at least one embodiment of the present disclosure. Fig. 12B A plan view of a third insulating layer provided for at least one embodiment of the present disclosure. Fig. 12C A plan view of a first sublayer of a first electrode layer provided for at least one embodiment of the present disclosure. Fig.12D A plan view of the third sublayer of the first electrode layer provided for at least one embodiment of the present disclosure. Fig.12E A plan view of a pixel defining layer provided in at least one embodiment of the present disclosure. FIG. 12A to FIG. 12E The structure of the display substrate is introduced in detail.

[0188] For example, in some embodiments, Figure 6 , Figure 7 as well as Fig. 12CAs shown, the plurality of light emitting elements 160 of each repeating unit C1 include a first light emitting element 164, a second light emitting element 165, and a third light emitting element 166. The first light emitting element 164, the second light emitting element 165, and the third light emitting element 166 are respectively arranged corresponding to the first sub-pixel filter area LG1, the second sub-pixel filter area LG2, and the third sub-pixel filter area LG3. The display substrate 1 also includes a fifth via hole GK5, a sixth via hole GK6, and a seventh via hole GK7 that at least penetrate the third insulating layer 136 (and may also penetrate the passivation layer 135). The fifth via hole GK5, the sixth via hole GK6, and the seventh via hole GK7 are respectively configured to expose the first sub-pixel driving circuit P161, the second sub-pixel driving circuit P162, and the third sub-pixel driving circuit P163. The first electrode 161 of the first light emitting element 164 is connected to the first sub-pixel driving circuit P161 through the fifth via hole GK5. The first electrode 161 of the second light emitting element 165 is connected to the second sub-pixel driving circuit P162 through the sixth via hole GK6. The first electrode 161 of the third light emitting element 166 is connected to the third sub-pixel driving circuit P163 through the seventh via hole GK7.

[0189] For example, Fig. 12A and Fig. 12B As shown, the fifth via GK5, the sixth via GK6 and the seventh via GK7 respectively penetrate the third insulating layer 136 and the passivation layer 135 to connect the first light-emitting element 164 to the first sub-pixel driving circuit P161, the second light-emitting element 165 to the second sub-pixel driving circuit P162, and the third light-emitting element 166 to the third sub-pixel driving circuit P163.

[0190] It should be noted that Fig. 12A and Fig. 12B The third insulating layer 136 and the through passivation layer 135 shown are inverted structures, that is, the filled portion is the dug-out (non-existent) portion.

[0191] For example, Figure 6 As shown, the orthographic projection of the fifth via GK5 on the board surface of the base substrate 10 does not overlap with the orthographic projection of the light-emitting area of ​​the first light-emitting element 164 on the board surface of the base substrate 10, so as to improve the flatness of the light-emitting area of ​​the first light-emitting element 164. The orthographic projection of the sixth via GK6 on the board surface of the base substrate 10 does not overlap with the orthographic projection of the light-emitting area of ​​the second light-emitting element 165 on the board surface of the base substrate 10, so as to improve the flatness of the light-emitting area of ​​the second light-emitting element 165. The orthographic projection of the seventh via GK7 on the board surface of the base substrate 10 does not overlap with the orthographic projection of the light-emitting area of ​​the third light-emitting element 166 on the board surface of the base substrate 10, so as to improve the flatness of the light-emitting area of ​​the third light-emitting element 166.

[0192] For example, the size range of the fifth via hole GK5, the sixth via hole GK6 and the seventh via hole GK7 can be about 9-12 microns. For example, the size of the fifth via hole GK5, the sixth via hole GK6 and the seventh via hole GK7 is selected to be about 10 or 11 microns. The size of the fifth via hole GK5, the sixth via hole GK6 and the seventh via hole GK7 is selected by the display substrate during the preparation process.

[0193] For example, in some embodiments, Figure 2 , Figure 6 as well as Figure 7 As shown, the orthographic projections of the fifth via hole GK5 and the sixth via hole GK6 on the board surface of the substrate 10 are close to the orthographic projection of the light shielding line BM1 between the first sub-pixel filter area LG1 and the second sub-pixel filter area LG2 on the board surface of the substrate 10, and are located on both sides of the orthographic projection of the light shielding line BM1 between the first sub-pixel filter area LG1 and the second sub-pixel filter area LG2 on the board surface of the substrate 10. That is, the fifth via hole GK5 is below the light-emitting area of ​​the first light-emitting element 164 and is located on the upper side of the light shielding line BM1, and the sixth via hole GK6 is located on the upper side of the light-emitting area of ​​the second light-emitting element 165. In this way, the areas of the light-emitting areas of the first light-emitting element 164 and the second light-emitting element 165 can be increased. The orthographic projection of the seventh via hole GK7 on the board surface of the substrate 10 is close to the orthographic projection of the light shielding line BM2 between the second sub-pixel filter area LG2 and the third sub-pixel filter area LG3 on the board surface of the substrate 10, and overlaps with the third sub-pixel filter area LG3. That is, the seventh via hole GK7 is located at the upper side of the light emitting area of ​​the third light emitting element 166 to increase the area of ​​the light emitting area of ​​the third light emitting element 166. It should be noted that in this embodiment, the position of the fifth via hole GK5 is Figure 6 The position of the fifth via hole GK5 shown in FIG. 1 is different.

[0194] For example, in some other embodiments, Figure 2 , Figure 6 as well as Figure 7As shown, the orthographic projection of the fifth via hole GK5 on the board surface of the base substrate 10 overlaps with the orthographic projection of one end of the first electrode plate CST1 of the storage capacitor CST of the first sub-pixel driving circuit P161 connected to the second electrode TSD31 of the sensing transistor T3 on the board surface of the base substrate 10. That is, the fifth via hole GK5 is located on the upper side of the light-emitting area of ​​the first light-emitting element 164 to reduce the impact on the light-emitting area of ​​the first light-emitting element 164. The orthographic projection of the sixth via hole GK6 on the board surface of the base substrate 10 is close to the orthographic projection of the light-shielding line BM1 between the first sub-pixel filter area LG1 and the second sub-pixel filter area LG2 on the board surface of the base substrate 10, and overlaps with the second sub-pixel filter area LG2. That is, the sixth via hole GK6 is located on the upper side of the light-emitting area of ​​the second light-emitting element 165 to increase the area of ​​the light-emitting area of ​​the first light-emitting element 164. The orthographic projection of the seventh via hole GK7 on the board surface of the base substrate 10 is close to the orthographic projection of the light shielding line BM2 between the second sub-pixel filter area LG2 and the third sub-pixel filter area LG3 on the board surface of the base substrate 10, and overlaps with the third sub-pixel filter area LG3. In other words, the seventh via hole GK7 is located on the upper side of the light emitting area of ​​the third light emitting element 166 to increase the area of ​​the light emitting area of ​​the third light emitting element 166.

[0195] For example, Fig. 12C As shown, the first layer AN1 of the first electrode layer AN includes a first sub-electrode layer FD121 and a first electrode of the first light-emitting element 164, the second light-emitting element 165 and the third light-emitting element 163, which is close to the base substrate 10. The first electrode of the first light-emitting element 164, the second light-emitting element 165 and the third light-emitting element 163, which is close to the base substrate 10, is connected to the first sub-pixel driving circuit P161, the second sub-pixel driving circuit P162 and the third sub-pixel driving circuit P163 through the fifth via GK5, the sixth via GK6 and the seventh via GK7 respectively. The first sub-electrode layer FD121 is connected to the first sub-pixel driving circuit P161, the second sub-pixel driving circuit P162 and the third sub-pixel driving circuit P163 through the fifth via GK5, the sixth via GK6 and the seventh via GK7 respectively. Fig. 12A and Fig. 12B The second strap hole FD12 penetrating the passivation layer 135 and the third insulating layer 136 is connected to the first strap electrode FD11 .

[0196] For example, Fig.12D As shown, the third layer AN3 of the first electrode layer AN includes the second electrode layer FD122 and a layer away from the base substrate 10 of the first electrodes of the first light emitting element 164 , the second light emitting element 165 and the third light emitting element 163 .

[0197] For example, Fig.12EAs shown, the pixel defining layer 138 has a plurality of openings defining the light-transmitting region TM10, the light-emitting regions of the first light-emitting element 164, the second light-emitting element 165 and the third light-emitting element 163, and the electrode overlapping region 12. It should be noted that the pixel defining layer 138 has a plurality of openings defining the light-transmitting region TM10, the light-emitting regions of the first light-emitting element 164, the second light-emitting element 165 and the third light-emitting element 163, and the electrode overlapping region 12. Fig.12E The structure in the figure is an inverted structure, that is, the filled part in the figure represents the dug-out part.

[0198] For example, the first conductive layer SD ( Figure 9G The width of each trace that surrounds the via hole is 4 to 5 microns. Fig.9E The width of each wiring of the package (as shown) is 4-5 microns. For example, the first electrode or the second electrode of the data writing transistor T1 and the driving transistor T2 exceeds the via hole by 1 micron, for example, 4.0-4.5 microns.

[0199] For example, in some examples, the thickness of the second conductive layer GATE is 2000-300 angstroms, and the thickness of the first conductive layer SD is 5000-8000 angstroms, which is not limited in the embodiments of the present disclosure.

[0200] At least one embodiment of the present disclosure further provides a display device. Fig.13 A schematic diagram of a display device provided by at least one embodiment of the present disclosure. Fig.13 As shown, the display device 2 includes a display substrate 1 provided by any embodiment of the present disclosure, for example, Figure 2 The display substrate 1 shown in FIG.

[0201] It should be noted that the display device 2 may be a product or component with a transparent display function. The display device 2 may also include other components, such as a data drive circuit, a timing controller, etc., which are not limited in the embodiments of the present disclosure.

[0202] It should be noted that, for the sake of clarity and simplicity, the embodiments of the present disclosure do not provide all the components of the display device. To realize the substrate function of the display device, those skilled in the art may provide and set other structures not shown according to specific needs, and the embodiments of the present disclosure are not limited to this.

[0203] The technical effects of the display device 2 provided in the above embodiment may refer to the technical effects of the display substrate 1 provided in the embodiment of the present disclosure, which will not be described in detail here.

[0204] Figure 14A-14F A schematic diagram of a manufacturing process of a display device provided in at least one embodiment of the present disclosure.

[0205] For example, Fig.14AAs shown, a base substrate 10 is provided, and a metal material is deposited on the base substrate to form a light shielding layer 131 through a patterning process. For example, the metal material includes silver, aluminum, chromium, copper, molybdenum, titanium, aluminum-neodymium alloy, copper-molybdenum alloy, molybdenum-tantalum alloy, molybdenum-neodymium alloy or any combination thereof. An insulating material is deposited on the light shielding layer 131 to form a first insulating layer 132 through a patterning process. The first insulating layer 132 includes a first overlapping sub-hole FK111. For example, the material of the first insulating layer 132 may include inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, or other suitable materials. An insulating material is deposited on the first insulating layer 132 to form a buffer layer 133 through a patterning process. The buffer layer 133 includes a third overlapping sub-hole FK113. Semiconductor material is deposited on the buffer layer 133 to form the active layer TA2 of the driving circuit T2 of the sub-pixel driving circuit and the first plate CST1 of the storage capacitor CST through a patterning process, that is, to form Fig.9D The semiconductor layer ACT shown in FIG.

[0206] For example, Fig.14A As shown, an insulating material is deposited on the semiconductor layer ACT to form a fourth insulating layer 137 through a patterning process. A metal material is deposited on the fourth insulating layer 137 to form the gate TG2 of the driving circuit T2 of the sub-pixel driving circuit, that is, to form a gate TG2 of the sub-pixel driving circuit T2. Fig.9E The second conductive layer GATE shown. The material of the gate TG2 of the driving circuit T2 includes, for example, a metal material or an alloy material, such as a metal single layer or multilayer structure formed by molybdenum, aluminum and titanium, for example, the multilayer structure is a multi-metal layer stack (such as a three-layer metal stack of titanium, aluminum and titanium (Ti / Al / Ti)). An insulating material is deposited on the second conductive layer GATE to form a second insulating layer 134 through a patterning process. The second insulating layer 134 includes a second overlapping sub-hole FK112. A metal material is deposited on the second insulating layer 134 to form a first pole TSD21 and a second pole TSD22 of the driving circuit T2 and a first overlapping electrode FD11, that is, a first conductive layer SD through a patterning process. For example, the material of the first pole TSD21 and the second pole TSD22 of the driving circuit T2 and the first overlapping electrode FD11 may include a metal material or an alloy material, such as a metal single layer or multilayer structure formed by molybdenum, aluminum and titanium, for example, the multilayer structure is a multi-metal layer stack (such as a three-layer metal stack of titanium, aluminum and titanium (Ti / Al / Ti)). A passivation layer 135 and a third insulating layer 136 are sequentially formed on the first conductive layer SD. The passivation layer 135 and the third insulating layer 136 include a second overlapping hole FK12 and a via hole exposing the sub-pixel driving circuit.

[0207] For example, Fig.14AAs shown, a metal material is deposited on the third insulating layer 136 to form a first layer AN1 of the first electrode layer AN through a patterning process. The first layer AN1 of the first electrode layer AN includes two parts spaced apart from each other, namely, the first sub-electrode layer FD121 of the second lap electrode FD12 and a layer of the first electrode 161 of the light-emitting element 160 close to the substrate. The first sub-electrode layer FD121 of the second lap electrode FD12 is connected to the first lap electrode through the second lap hole FK12. A layer of the first electrode 161 of the light-emitting element 160 close to the substrate is connected to the sub-pixel driving circuit through the via holes in the cladding layer 135 and the third insulating layer 136. For example, the material of the first layer AN1 of the first electrode layer AN includes at least one transparent conductive oxide material, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), etc.

[0208] For example, Fig. 14B As shown, a material layer M2 is formed on the first layer AN1 of the first electrode layer AN, for example, by evaporation, and the material layer M2 is used to form the second layer AN2 of the first electrode 161. For example, the material layer M2 may include an alloy material, such as AlNd or the like.

[0209] For example, Fig. 14C As shown, a material layer M3 is formed on the material layer M2, for example, by magnetron sputtering, and the material layer M3 is used to form the third layer AN3 of the first electrode 161. For example, the material layer M3 may include at least one transparent conductive oxide material, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), etc.

[0210] For example, Fig.14D As shown, the material layer M3 is patterned to form a third sub-electrode layer FD123 of the second bonding electrode FD12 and a layer of the first electrode 161 of the light-emitting element 160 away from the substrate, that is, a third layer AN3.

[0211] For example, Fig.14E As shown, the material layer M2 is patterned to form the second sub-electrode layer FD122 of the second bonding electrode FD12 and the intermediate layer of the first electrode 161 of the light-emitting element 160, that is, the second layer AN2.

[0212] pass FIG. 14A to FIG. 14E The preparation process of the first electrode layer AN where the first electrode 161 of the first light-emitting element is located can make the cross-section of the first electrode 161 of the light-emitting element 160 to be I-shaped, and the cross-sections of the first sub-electrode layer FD121, the second sub-electrode layer FD122 and the third sub-electrode layer FD123 to be I-shaped.

[0213] For example, Fig.14FAs shown, a pixel defining layer 138, a light emitting layer 163 of the light emitting element 160, a second electrode 162 of the light emitting element 160, an encapsulation layer 139, a black matrix BM, a filter layer LG, a light-transmitting layer 1310 and a protective layer 1311 are formed one by one on the first electrode layer AN. The detailed preparation process of the above film layers will not be repeated.

[0214] It should be noted that the structures of the various film layers formed during the preparation of the display substrate 2 can refer to Figure 3 The introduction will not be repeated in detail here.

[0215] There are a few points to note:

[0216] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure, and other structures may refer to the general design.

[0217] (2) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to obtain new embodiments.

[0218] The above description is merely an exemplary embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure. The protection scope of the present disclosure is determined by the appended claims.

Claims

1. A display substrate, comprising: A substrate, comprising a display area, wherein the display area comprises a plurality of repeating units arranged in an array, each of the plurality of repeating units comprises a transparent area and a pixel area arranged along a first direction, the pixel area comprises a plurality of sub-pixels, each of the plurality of sub-pixels comprises a sub-pixel driving circuit and a light-emitting element, the light-emitting element is located on a side of the sub-pixel driving circuit away from the substrate, and the sub-pixel driving circuit is configured to drive the light-emitting element to emit light; and A plurality of sensing signal lines are arranged on the substrate and extend along the second direction, wherein two rows of the repeating units are arranged between two adjacent ones of the plurality of sensing signal lines, the two rows of the repeating units extend along the second direction, each of the plurality of sensing signal lines is connected to a sub-pixel driving circuit of a plurality of sub-pixels adjacent to it and respectively along the two rows of the repeating units, and is configured to provide a reference voltage signal, A plurality of sub-pixel driving circuits in each pixel area are arranged along the first direction, each of the sub-pixel driving circuits comprises a data writing circuit, a driving circuit, a charge storage circuit and a sensing circuit, the data writing circuit comprises a data writing transistor, the driving circuit comprises a driving transistor, the sensing circuit comprises a sensing transistor, the charge storage circuit comprises a storage capacitor, in the second direction, the data writing transistor and the driving transistor are located on a side of the storage capacitor away from the sensing transistor, and the driving transistor is located between the data writing transistor and the storage capacitor, The display substrate further comprises a first conductive layer located on the base substrate, the first conductive layer comprises a first electrode and a second electrode of the driving transistor, and a third switching electrode, the second electrode of the driving transistor is located on a side of the driving transistor away from the storage capacitor, The display area includes a first repeating unit, a plurality of sub-pixel driving circuits in a pixel area of ​​the first repeating unit include a first sub-pixel driving circuit, a second sub-pixel driving circuit, and a third sub-pixel driving circuit arranged in the first direction, a power line is arranged on a side of the transparent area of ​​the first repeating unit away from the pixel area of ​​the first repeating unit, and the power line is connected to the plurality of sub-pixel driving circuits in the pixel area of ​​the first repeating unit, One end of the third switching electrode is connected to the second electrode of the driving transistor of the first sub-pixel driving circuit of the first repeating unit, and the other end of the third switching electrode is connected to the power line close to the transparent area of ​​the first repeating unit. The third switching electrode is routed on the lower side of the transparent area of ​​the first repeating unit, and is bent between the transparent area and the pixel area of ​​the first repeating unit toward a side close to the driving transistor.

2. The display substrate according to claim 1, further comprising a plurality of power lines, in, The multiple power lines are arranged on the base substrate and extend along the second direction. In the first direction, the multiple power lines and the multiple sensing signal lines are arranged alternately. A row of the repeating units extending along the second direction is arranged between each of the multiple sensing signal lines and the power line adjacent thereto. Two rows of the repeating units extending along the second direction are arranged between two adjacent ones of the multiple power lines. Each of the multiple power lines is connected to the sub-pixel driving circuits of the multiple sub-pixels of the two rows of the repeating units adjacent thereto and extending along the second direction respectively, and is configured to provide a first power supply voltage.

3. The display substrate according to claim 2, further comprising a peripheral area, a gate driving circuit, and a plurality of gate lines extending along the first direction, wherein the peripheral area at least partially surrounds the display area, the gate driving circuit is located in the peripheral area, the plurality of gate lines are connected to the gate driving circuit and are connected to sub-pixel driving circuits of pixel areas of each row of the repeating unit extending along the first direction, The gate driving circuit is configured to output gate scanning signals one by one to drive a plurality of sub-pixels of the pixel regions of the repetitive units in each row extending along the first direction to work. The plurality of repeating units are arranged in N rows extending along the first direction respectively, the gate driving circuit comprises N cascaded shift register units, the nth stage shift register unit is connected to the sub-pixel driving circuit of the pixel area of ​​the nth row of repeating units, wherein: 1≤n≤N, where N is an integer greater than or equal to 2.

4. The display substrate according to claim 3, wherein: The driving circuit is connected to a first node, a second node and a third node, the third node is also connected to a first power supply voltage terminal, the first power supply voltage terminal is connected to the power line, and the driving circuit is configured to receive the first power supply voltage through the third node, and control the driving current flowing through the light emitting element under the control of the level of the first node; The data writing circuit is connected to the first node and is configured to receive the gate scanning signal as a scanning driving signal and write a data signal into the first node in response to the scanning driving signal; The charge storage circuit is connected to the first node and the second node, and is configured to store the written data signal and the reference voltage signal; The sensing circuit is connected to the second node and configured to receive the gate scanning signal as a sensing driving signal. The sensing circuit is also connected to the sensing signal line and configured to receive the reference voltage signal, and write the reference voltage signal to the driving circuit or read the sensing voltage signal from the driving circuit in response to the sensing driving signal. The light emitting element is connected to the second node and a second power supply voltage terminal, and is configured to receive a second power supply voltage through the second power supply voltage terminal and emit light under the driving of the driving current.

5. The display substrate according to claim 4, wherein: The plurality of gate lines include a first gate line and a second gate line, The first gate line is connected to the data writing circuit of the multiple sub-pixel driving circuits of the pixel area of ​​the Mth row of repeating units extending along the first direction, the sensing circuit of the multiple sub-pixel driving circuits of the pixel area of ​​the M-1th row of repeating units extending along the first direction, and the output end of the Mth shift register unit, so as to output the gate scanning signal output by the output end of the Mth shift register unit to the data writing circuit of the multiple sub-pixel driving circuits of the pixel area of ​​the Mth row of repeating units as a scanning driving signal, and to the sensing circuit of the multiple sub-pixel driving circuits of the pixel area of ​​the M-1th row of repeating units as a sensing driving signal, The second gate line is connected to the sensing circuit of the multiple sub-pixel driving circuits in the pixel area of ​​the Mth row of repeating units, the data writing circuit of the multiple sub-pixel driving circuits in the pixel area of ​​the M+1th row of repeating units extending along the first direction, and the output end of the M+1th shift register unit, so as to output the gate scanning signal output by the output end of the M+1th shift register unit to the data writing circuit of the multiple sub-pixel driving circuits in the pixel area of ​​the M+1th row of repeating units as a scanning driving signal, and to the sensing circuit of the multiple sub-pixel driving circuits in the pixel area of ​​the Mth row of repeating units as the sensing driving signal, Among them, 1<M<N, M is an integer.

6. The display substrate according to claim 5, wherein: The active layer of the data writing transistor, the active layer of the driving transistor, and the active layer of the sensing transistor extend along the second direction, and the base substrate is a flexible substrate.

7. The display substrate according to claim 6, further comprising a semiconductor layer, a second conductive layer, a second insulating layer and a fourth insulating layer located on the base substrate, wherein the second conductive layer is located on a side of the semiconductor layer away from the base substrate, the fourth insulating layer is located between the second conductive layer and the semiconductor layer, the first conductive layer is located on a side of the second conductive layer away from the base substrate, and the second insulating layer is located between the second conductive layer and the first conductive layer. The semiconductor layer includes an active layer of the data writing transistor, an active layer of the driving transistor, and an active layer of the sensing transistor, Each of the plurality of power lines includes a first sub-line located in the second conductive layer and a second sub-line located in the first conductive layer, the first sub-line includes a plurality of first routing segments extending along the second direction, the plurality of first routing segments are respectively located in different repeating units, and the second sub-line passes through the display area. The second sub-line is stacked on a side of the first sub-line away from the base substrate, and is connected to the first sub-line through at least one first via hole penetrating the second insulating layer.

8. The display substrate according to claim 7, wherein: Each of the plurality of sensing signal lines includes a third sub-line located in the second conductive layer and a fourth sub-line located in the first conductive layer, the third sub-line includes a plurality of second routing segments extending along the second direction, the plurality of second routing segments are distributed in different repeating units, and the fourth sub-line passes through the display area. The fourth sub-line is stacked on a side of the third sub-line away from the base substrate, and is connected to the third sub-line through at least one second via hole penetrating the second insulating layer.

9. The display substrate according to claim 7, wherein: The display area includes a second repeating unit arranged adjacent to the first repeating unit along the first direction, a sensing signal line is arranged between the pixel area of ​​the first repeating unit and the transparent area of ​​the second repeating unit, and the sensing signal line is connected to a plurality of sub-pixel driving circuits of the pixel areas of the first repeating unit and the second repeating unit, Another power line is arranged on a side of the pixel area of ​​the second repeating unit away from the transparent area of ​​the second repeating unit, and the other power line is connected to a plurality of sub-pixel driving circuits in the pixel area of ​​the second repeating unit, and the plurality of sub-pixel driving circuits in the pixel area of ​​the second repeating unit respectively include a first sub-pixel driving circuit, a second sub-pixel driving circuit, and a third sub-pixel driving circuit arranged in the first direction. The first conductive layer includes a first switching electrode extending along the first direction, a first electrode and a second electrode of the sensing transistor, a first end of the first switching electrode is connected to a first electrode of the sensing transistor of the third sub-pixel driving circuit of the first repeating unit, and a second end of the first switching electrode is connected to a first electrode of the sensing transistor of the first sub-pixel driving circuit of the second repeating unit. The first switching electrode is cross-connected with the second sub-line of the sensing signal line.

10. The display substrate according to claim 9, wherein: The second conductive layer includes a first connecting trace extending along the first direction, The first connecting wire is connected to the first electrodes of the sensing transistors of the first sub-pixel driving circuit, the second sub-pixel driving circuit, and the third sub-pixel driving circuit of the first repeating unit or the second repeating unit through at least a portion of the third via hole. At least part of the orthographic projection of the first electrodes of the sensing transistors of the first sub-pixel driving circuit, the second sub-pixel driving circuit and the third sub-pixel driving circuit on the board surface of the substrate overlaps with the orthographic projection of the first connecting trace on the board surface of the substrate.

11. The display substrate according to claim 10, wherein: The first electrode of the sensing transistor includes a first sub-portion and a second sub-portion connected along the second direction, A portion of the third via hole is configured to penetrate the second insulating layer and the fourth insulating layer to expose the active layer of the sensing transistor, and another portion of the third via hole is configured to penetrate the second insulating layer to expose the first connecting trace. The first sub-portion is in contact with an active layer of the sensing transistor, and the second sub-portion is in contact with a first connecting trace.

12. The display substrate according to claim 10, wherein: The semiconductor layer further includes a first plate of a storage capacitor, and the first conductive layer further includes a second plate of a storage capacitor. The second electrode of the sensing transistor is connected to an end of the second electrode plate close to the sensing transistor, and the second electrode of the sensing transistor is integrally arranged with the second electrode plate.

13. The display substrate according to claim 12, wherein: The first conductive layer further includes a first electrode, a second electrode, and a second switching electrode of the data writing transistor, and the second switching electrode and the third switching electrode respectively include the third node. One end of the second switching electrode is connected to the second electrode of the driving transistor of the third sub-pixel driving circuit of the second repeating unit, and the other end of the second switching electrode is connected to a power line of the third sub-pixel driving circuit close to the second repeating unit.

14. The display substrate according to claim 13, wherein: The second conductive layer includes a second connecting trace extending along the first direction, The second connecting wire is connected to the second electrodes of the driving transistors of the first sub-pixel driving circuit, the second sub-pixel driving circuit and the third sub-pixel driving circuit of the first repeating unit or the second repeating unit through at least a portion of the fourth via hole. At least part of the orthographic projection of the second electrodes of the driving transistors of the first sub-pixel driving circuit, the second sub-pixel driving circuit and the third sub-pixel driving circuit on the board surface of the base substrate overlaps with the orthographic projection of the second connecting trace on the board surface of the base substrate.

15. The display substrate according to claim 13, wherein: The first electrode of the driving transistor is connected to an end of the second electrode plate of the storage capacitor away from the sensing transistor, and the first electrode of the driving transistor is integrally arranged with the second electrode plate. The first electrode plate of the storage capacitor is connected to the active layer of the driving transistor and is integrally arranged.

16. The display substrate according to claim 13, wherein: The first electrode plate and the second electrode plate of the storage capacitor include strips extending along the second direction, The display substrate further comprises a filter layer, and the filter layer is located on a side of the light emitting element away from the base substrate. The filter layer includes a first sub-pixel filter region, a second sub-pixel filter region and a third sub-pixel filter region. In each of the repeating units, the first sub-pixel filter area, the second sub-pixel filter area and the third sub-pixel filter area are arranged in sequence along the second direction, and the second sub-pixel filter area is located between the first sub-pixel filter area and the third sub-pixel filter area. The first sub-pixel filter region overlaps with at least a portion of the sensing transistors of the plurality of sub-pixel driving circuits of the pixel region and a portion of the storage capacitor close to the sensing transistor in an orthographic projection on the plate surface of the substrate. The third sub-pixel filter area overlaps with at least part of the data writing transistors and driving transistors of the plurality of sub-pixel driving circuits of the pixel area, and the orthographic projection of the part of the storage capacitor close to the driving transistor on the board surface of the substrate. The second sub-pixel filter region overlaps with the orthographic projection of a portion of the storage capacitors of the plurality of sub-pixel driving circuits of the pixel region close to the middle thereof in the first direction on the plate surface of the base substrate.

17. The display substrate according to claim 16, further comprising a third insulating layer and a pixel defining layer, wherein the third insulating layer is located on a side of the first conductive layer away from the base substrate, the light emitting element is located on a side of the third insulating layer away from the base substrate, the light emitting element of each of the plurality of sub-pixels comprises a first electrode, a second electrode and a light emitting layer located between the first electrode and the second electrode, and the pixel defining layer is configured to define a light emitting area of ​​the light emitting element, The plurality of light-emitting elements of each of the repeating units includes a first light-emitting element, a second light-emitting element and a third light-emitting element, The first light emitting element, the second light emitting element and the third light emitting element are respectively arranged corresponding to the first sub-pixel filter area, the second sub-pixel filter area and the third sub-pixel filter area, The display substrate further includes a fifth via hole, a sixth via hole, and a seventh via hole that at least penetrate the third insulating layer, and the fifth via hole, the sixth via hole, and the seventh via hole are configured to expose the first sub-pixel driving circuit, the second sub-pixel driving circuit, and the third sub-pixel driving circuit. The first electrode of the first light emitting element is connected to the first sub-pixel driving circuit through the fifth via hole. The first electrode of the second light emitting element is connected to the second sub-pixel driving circuit through the sixth via hole. The first electrode of the third light emitting element is connected to the third sub-pixel driving circuit through the seventh via hole.

18. The display substrate according to claim 17, wherein: The orthographic projection of the fifth via hole on the surface of the base substrate does not overlap with the orthographic projection of the light-emitting area of ​​the first light-emitting element on the surface of the base substrate, The orthographic projection of the sixth via hole on the surface of the base substrate does not overlap with the orthographic projection of the light-emitting area of ​​the second light-emitting element on the surface of the base substrate, The orthographic projection of the seventh via hole on the board surface of the base substrate does not overlap with the orthographic projection of the light-emitting area of ​​the third light-emitting element on the board surface of the base substrate.

19. The display substrate according to claim 17, further comprising a black matrix, In the seventh switching electrode of the pixel area of ​​each of the repeating units, the black matrix includes a plurality of light-shielding lines extending along the first direction, At least a portion of the orthographic projections of the plurality of light-shielding lines on the surface of the base substrate overlaps with the intervals between the first sub-pixel filter area, the second sub-pixel filter area, and the third sub-pixel filter area in the second direction, The orthographic projections of the fifth via hole and the sixth via hole on the board surface of the base substrate are close to the orthographic projection of the light shielding line between the first sub-pixel filter area and the second sub-pixel filter area on the board surface of the base substrate, and are located on both sides of the orthographic projection of the light shielding line between the first sub-pixel filter area and the second sub-pixel filter area on the board surface of the base substrate. The orthographic projection of the seventh via hole on the surface of the base substrate is close to the orthographic projection of the light shielding line between the second sub-pixel filter area and the third sub-pixel filter area on the surface of the base substrate, and overlaps with the third sub-pixel filter area.

20. The display substrate according to claim 17, further comprising a black matrix, In the pixel area of ​​each of the repeating units, the black matrix includes a plurality of light-shielding lines extending along the first direction, At least a portion of the orthographic projections of the plurality of light-shielding lines on the surface of the base substrate overlaps with the intervals between the first sub-pixel filter area, the second sub-pixel filter area, and the third sub-pixel filter area in the second direction, The orthographic projection of the fifth via hole on the board surface of the base substrate overlaps with the orthographic projection of one end of the first electrode plate of the storage capacitor of the first sub-pixel driving circuit connected to the second electrode of the sensing transistor on the board surface of the base substrate, The orthographic projection of the sixth via hole on the board surface of the base substrate is close to the orthographic projection of the light shielding line between the first sub-pixel filter area and the second sub-pixel filter area on the board surface of the base substrate, and overlaps with the second sub-pixel filter area. The orthographic projection of the seventh via hole on the surface of the base substrate is close to the orthographic projection of the light shielding line between the second sub-pixel filter area and the third sub-pixel filter area on the surface of the base substrate, and overlaps with the third sub-pixel filter area.

21. The display substrate according to claim 9, further comprising a plurality of data lines extending along the second direction, the plurality of data lines comprising a first data line, a second data line and a third data line located in each repeating unit, The first data line and the second data line are located between the first sub-pixel driving circuit and the second sub-pixel driving circuit, and the third data line is located between the second sub-pixel driving circuit and the third sub-pixel driving circuit. The first data line, the second data line and the third data line are electrically connected to the first sub-pixel driving circuit, the second sub-pixel driving circuit and the third sub-pixel driving circuit respectively to provide data signals. The first conductive layer further includes a fourth switching electrode, a fifth switching electrode and a sixth switching electrode along the first direction, The fourth transfer electrode is connected to the first data line and the second electrode of the data writing transistor of the first sub-pixel driving circuit. The fifth switching electrode is connected to the second data line and the second electrode of the data writing transistor of the second sub-pixel driving circuit. The sixth transfer electrode is connected to the third data line and the second electrode of the data writing transistor of the third sub-pixel driving circuit.

22. The display substrate according to any one of claims 10 to 20, wherein: The first gate line and the second gate line are located in the second conductive layer, the first gate line is close to the sensing transistors of the first repeating unit and the second repeating unit, and the second gate line is close to the data writing transistors of the first repeating unit and the second repeating unit. The first gate line includes a fold line portion, the fold line portion includes a first fold line portion along the first direction, a second fold line portion and a third fold line portion along the second direction respectively connected to two ends of the first fold line portion, the first fold line portion, the second fold line portion and the third fold line portion bypass the first connection line, The orthographic projection of the first fold line portion on the surface of the base substrate overlaps with the orthographic projection of the active layer of the sensing transistor of the first sub-pixel driving circuit, the second sub-pixel driving circuit and the third sub-pixel driving circuit of the first repeating unit on the surface of the base substrate, and the overlapping portion forms the gate of the sensing transistor.

23. The display substrate according to claim 22, wherein: In the second direction, a portion of the first gate line and the first connecting line arranged in parallel is located on a side of the first connecting line close to the transparent area of ​​the second repeating unit.

24. The display substrate according to claim 22, wherein: The second conductive layer further includes a third connecting wire, a fourth connecting wire and a fifth connecting wire. The third connection line, the fourth connection line and the fifth connection line are "L"-shaped broken lines, the fourth connection line and the fifth connection line have the same bending direction, and the bending direction of the third connection line is opposite to the bending direction of the fourth connection line and the fifth connection line. The third connecting wire is connected to the second gate line and the gate of the data writing transistor of the first sub-pixel driving circuit, The fourth connecting wire is connected to the second gate line and the gate of the data writing transistor of the second sub-pixel driving circuit, The fifth connecting wire is connected to the second gate line and a gate of the data writing transistor of the third sub-pixel driving circuit.

25. The display substrate according to claim 14, wherein: The first conductive layer includes a seventh switching electrode, an eighth switching electrode and a ninth switching electrode along the second direction, The orthographic projections of the seventh transfer electrode, the eighth transfer electrode, and the ninth transfer electrode on the board surface of the base substrate overlap with the orthographic projection of the second connecting trace on the board surface of the base substrate, The first end of the seventh switching electrode is connected to the gate electrode of the driving transistor of the first sub-pixel driving circuit through at least a portion of the eighth via hole penetrating the second insulating layer, and the second end of the seventh switching electrode is connected to the first electrode of the data writing transistor of the first sub-pixel driving circuit. The first end of the eighth switching electrode is connected to the gate electrode of the driving transistor of the second sub-pixel driving circuit through at least a portion of a ninth via hole penetrating the second insulating layer, and the second end of the eighth switching electrode is connected to the first electrode of the data writing transistor of the second sub-pixel driving circuit. The first end of the ninth switching electrode is connected to the gate of the driving transistor of the third sub-pixel driving circuit through at least a portion of the tenth via hole penetrating the second insulating layer, and the second end of the ninth switching electrode is connected to the first electrode of the data writing transistor of the third sub-pixel driving circuit.

26. A display device comprising the display substrate according to any one of claims 1-25.

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