Display substrate, preparation method thereof and display device

Abstract

A display substrate includes: a first electrode layer, a pixel definition layer, an organic light-emitting layer, a second electrode layer, and a first encapsulation layer, sequentially disposed away from a substrate. The pixel definition layer has multiple openings, at least one of which exposes the first electrode layer. The pixel definition layer has a first ramp and a second ramp at an edge near at least one opening, wherein the distance from the surface of the second ramp away from the substrate to the substrate is greater than the distance from the surface of the first ramp away from the substrate to the substrate; the slope angles of the first ramp and the second ramp are different. The first encapsulation layer has a first encapsulation ramp and a second encapsulation ramp, wherein the distance from the surface of the second encapsulation ramp away from the substrate to the substrate is greater than the distance from the surface of the first encapsulation ramp away from the substrate to the substrate; the slope angles of the first encapsulation ramp and the second encapsulation ramp are different.

Description

Technical Field

[0001] This article relates to, but is not limited to, the field of display technology, and in particular to a display substrate and its preparation method, and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, and extremely fast response speed. With the continuous development of display technology, display devices that use OLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become the mainstream products in the display field. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] This disclosure provides a display substrate, a method for preparing the same, and a display device.

[0005] On one hand, this disclosure provides a display substrate, comprising: a first electrode layer, a pixel definition layer, an organic light-emitting layer, a second electrode layer, and a first encapsulation layer sequentially disposed away from a substrate. The pixel definition layer has multiple openings, at least one of which exposes the first electrode layer. The pixel definition layer has a first ramp and a second ramp at its edge near at least one opening. The distance from the surface of the second ramp away from the substrate to the substrate is greater than the distance from the surface of the first ramp away from the substrate to the substrate; the slope angles of the first ramp and the second ramp are different. The first encapsulation layer has a first encapsulation ramp and a second encapsulation ramp. The distance from the surface of the second encapsulation ramp away from the substrate to the substrate is greater than the distance from the surface of the first encapsulation ramp away from the substrate to the substrate; the slope angles of the first encapsulation ramp and the second encapsulation ramp are different. The slope angle is the angle between the tangent of the ramp and a plane parallel to the substrate.

[0006] In some exemplary embodiments, the slope angle of the first climbing section is smaller than the slope angle of the second climbing section.

[0007] In some exemplary embodiments, the orthographic projection of the first package ramp portion on the substrate overlaps at least partially with the orthographic projection of the first ramp portion on the substrate.

[0008] In some exemplary embodiments, the first ramp portion has at least one first step. The orthographic projection of the first encapsulation ramp portion of the first encapsulation layer on the substrate at least partially overlaps with the orthographic projection of the first step on the substrate.

[0009] In some exemplary embodiments, the first step has a first flat portion and a first slope, the first flat portion being connected between the first slope and the second climbing portion.

[0010] In some exemplary embodiments, the slope angle of the first slope is approximately equal to the slope angle of the second climbing section.

[0011] In some exemplary embodiments, in a plane parallel to the display substrate, the first length of the first flat portion is less than the first length of the adjacent opening. The first length is a dimension along a first direction, which is parallel to the plane containing the substrate and intersects the centerline of the opening.

[0012] In some exemplary embodiments, the thickness of the first encapsulation layer is approximately 600 nanometers to 3 micrometers. In a direction perpendicular to the substrate, the distance from the surface of the first planar portion away from the substrate to the first electrode layer is greater than or equal to 200 nanometers.

[0013] In some exemplary embodiments, the pixel definition layer further has a second flat portion near the edge of at least one opening, the second flat portion being connected to the second ramp portion; the distance from the surface of the second flat portion away from the substrate to the substrate is greater than the distance from the surface of the second ramp portion away from the substrate to the substrate.

[0014] In some exemplary embodiments, the orthographic projection of the second flat portion on the substrate does not overlap with the orthographic projection of the second ramp portion on the substrate.

[0015] In some exemplary embodiments, the orthographic projection of the second flat portion on the substrate includes the orthographic projection of the second ramp portion on the substrate.

[0016] In some exemplary embodiments, the first ramp portion has a plurality of first steps arranged sequentially in a direction away from adjacent openings. The first encapsulation layer also has at least one third encapsulation ramp portion, which is connected between the second encapsulation ramp portion and the first encapsulation ramp portion. The orthographic projection of the third encapsulation ramp portion on the substrate overlaps with the orthographic projection of at least one first step on the substrate.

[0017] In some exemplary embodiments, the pixel definition layer includes: a first pixel definition layer and a second pixel definition layer stacked together. The first pixel definition layer has a plurality of first openings, and the second pixel definition layer has a plurality of second openings. The plurality of first openings and the plurality of second openings are connected in a one-to-one correspondence and expose a first electrode layer. The first pixel definition layer has at least a first ramp portion at an edge near at least one first opening, and the second pixel definition layer has at least a second ramp portion at an edge near at least one second opening.

[0018] In some exemplary embodiments, the material of the first pixel definition layer is different from the material of the second pixel definition layer.

[0019] In some exemplary embodiments, the first encapsulation layer further includes a first encapsulation flattening portion and a second encapsulation flattening portion, wherein the first encapsulation flattening portion is connected to a first encapsulation ramp portion, and the second encapsulation flattening portion is connected to a second encapsulation ramp portion. The distance from the surface of the first encapsulation flattening portion away from the substrate to the substrate is less than the distance from the surface of the first encapsulation ramp portion away from the substrate to the substrate; the distance from the surface of the second encapsulation flattening portion away from the substrate to the substrate is greater than the distance from the surface of the second encapsulation ramp portion away from the substrate to the substrate.

[0020] In some exemplary embodiments, the display substrate further includes a second encapsulation layer located on the side of the first encapsulation layer away from the substrate. The first encapsulation layer is made of an inorganic material, the second encapsulation layer is made of an organic material, and the refractive index of the first encapsulation layer is greater than the refractive index of the second encapsulation layer.

[0021] In some exemplary embodiments, the refractive index of the pixel definition layer is approximately 1.4 to 2, and the refractive index of the first encapsulation layer is approximately 1.45 to 2.2.

[0022] On the other hand, embodiments of this disclosure provide a display device including a display substrate as described above.

[0023] On the other hand, this disclosure provides a method for fabricating a display substrate, comprising: sequentially forming a first electrode layer, a pixel definition layer, an organic light-emitting layer, a second electrode layer, and a first encapsulation layer on a substrate. The pixel definition layer has multiple openings, at least one of which exposes the first electrode layer. The pixel definition layer has a first ramp and a second ramp at its edge near at least one opening. The distance from the surface of the second ramp away from the substrate to the substrate is greater than the distance from the surface of the first ramp away from the substrate to the substrate; the slope angles of the first ramp and the second ramp are different. The first encapsulation layer has a first encapsulation ramp and a second encapsulation ramp. The distance from the surface of the second encapsulation ramp away from the substrate to the substrate is greater than the distance from the surface of the first encapsulation ramp away from the substrate to the substrate; the slope angles of the first encapsulation ramp and the second encapsulation ramp are different. The slope angle is the angle between the tangent of the ramp and a plane parallel to the substrate.

[0024] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0025] The accompanying drawings are provided to further illustrate the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure. The shape and size of one or more components in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure.

[0026] Figure 1 This is a schematic diagram of the structure of a display device;

[0027] Figure 2 This is a schematic diagram of a planar structure of a display substrate;

[0028] Figure 3 This is a schematic diagram of a cross-sectional structure of a display substrate;

[0029] Figure 4 This is a schematic diagram of light emission from a planar light-emitting element.

[0030] Figure 5 This is a partial planar schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0031] Figure 6 for Figure 5 A partial cross-sectional view along the PP direction;

[0032] Figure 7 This is a schematic diagram of the optical path of at least one embodiment of the present disclosure;

[0033] Figure 8 This is another partial cross-sectional schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0034] Figure 9 This is another optical path schematic diagram of at least one embodiment of the present disclosure;

[0035] Figure 10 This is another partial cross-sectional schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0036] Figure 11 This is another partial cross-sectional schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0037] Figure 12 This is another optical path schematic diagram of at least one embodiment of the present disclosure;

[0038] Figure 13 This is another partial cross-sectional schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0039] Figure 14 This is another optical path schematic diagram of at least one embodiment of the present disclosure. Detailed Implementation

[0040] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. The implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be varied in many ways without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as being limited only to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0041] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shape and size of one or more parts in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0042] The ordinal numbers such as "first," "second," and "third" used in this specification are used to avoid confusion among the constituent elements, not to limit the quantity. The term "multiple" in this disclosure refers to two or more quantities.

[0043] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the direction in which the constituent elements are described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0044] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or joint; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate.

[0045] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain terminal, drain region, or drain) and the source electrode (source terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In this specification, the channel region refers to the region through which current primarily flows.

[0046] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0047] In this specification, "connection" includes the situation where constituent elements are connected together by a component that has a certain electrical function. There are no particular limitations on the "component that has a certain electrical function," as long as it enables the transmission of electrical signals between the connected constituent elements. Examples of "components that have a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components.

[0048] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0049] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0050] In this disclosure, "thickness" refers to the distance between the surface of the film layer away from the substrate and the surface near the substrate.

[0051] Figure 1 This is a schematic diagram of the structure of a display device. Figure 1As shown, an OLED display device may include a timing controller, a data signal driver, a scan signal driver, a light emission signal driver, and a pixel array. The pixel array may include multiple scan signal lines (e.g., S1 to Sm), multiple data signal lines (e.g., D1 to Dn), multiple light emission signal lines (e.g., E1 to Eo), and multiple sub-pixels Pxij. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals of specifications suitable for the data signal driver to the data signal driver, provide clock signals, scan start signals, etc. of specifications suitable for the scan signal driver to the scan signal driver, and provide clock signals, emission stop signals, etc. of specifications suitable for the light emission signal driver to the light emission signal driver. The data signal driver may use the grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to the data signal lines D1, D2, D3, ..., Dn. For example, the data signal driver may sample the grayscale values ​​using a clock signal and apply the data voltage corresponding to the grayscale values ​​to the data signal lines D1 to Dn on a pixel-row basis, where n can be a natural number. The scan signal driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ..., Sm by receiving clock signals, scan start signals, etc., from a timing controller. For example, the scan signal driver can sequentially provide scan signals with on-level pulses to scan signal lines S1 to Sm. For example, the scan signal driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals in the form of on-level pulses to the next stage circuit under the control of a clock signal, where m can be a natural number. The light emission signal driver can generate transmit signals to be provided to light emission signal lines E1, E2, E3, ..., Eo by receiving clock signals, transmit stop signals, etc., from a timing controller. For example, the light emission signal driver can sequentially provide transmit signals with off-level pulses to light emission signal lines E1 to Eo. For example, the light emission signal driver can be configured as a shift register and can generate light emission signals by sequentially transmitting light emission stop signals in the form of off-level pulses to the next stage circuit under the control of a clock signal, where o can be a natural number. The pixel array can include multiple sub-pixels Pxij. Each sub-pixel Pxij can be connected to the corresponding data signal line, the corresponding scan signal line, and the corresponding light emission signal line, where i and j can be natural numbers. A sub-pixel Pxij can refer to a sub-pixel whose transistor is connected to the i-th scan signal line and to the j-th data signal line.

[0052] Figure 2 This is a schematic diagram of a planar structure of a display substrate. Figure 2As shown, in a plane parallel to the display substrate, multiple sub-pixels of the display area can be arranged as follows: In each row, a repeating unit consisting of one first sub-pixel P1, two second sub-pixels P2, and one third sub-pixel P3 is arranged, with the two second sub-pixels P2 in the repeating unit arranged along the column direction. The first sub-pixel P1 emits a first color light, the second sub-pixel P2 emits a second color light, and the third sub-pixel P3 emits a third color light. In some examples, the repeating units between adjacent rows are shifted in the row direction. The two second sub-pixels P2 can be pentagons (e.g., rounded pentagons), symmetrical to each other, with their axis of symmetry parallel to the row direction. The first sub-pixel P1 and the third sub-pixel P3 are both hexagons (e.g., rounded hexagons). The length of the first sub-pixel P1 along the column direction can be greater than the length of the third sub-pixel P3 along the column direction, and the length of the third sub-pixel P3 along the column direction can be greater than the length of the second sub-pixel P2 along the column direction. In some examples, the first sub-pixel P1 can be a red (R) sub-pixel, the second sub-pixel P2 can be a green (G) sub-pixel, and the third sub-pixel P3 can be a blue (B) sub-pixel. Correspondingly, the first color light can be red light, the second color light can be green light, and the third color light can be blue light. In this example, the three sub-pixels of a pixel unit are arranged in a triangular pattern. However, this embodiment does not limit the shape and arrangement of multiple sub-pixels in the display area. For example, sub-pixels can be rectangular, rhomboid, pentagonal, or hexagonal. In some examples, when a pixel unit includes three sub-pixels, the three sub-pixels can be arranged horizontally or vertically side-by-side; when a pixel unit includes four sub-pixels, the four sub-pixels can be arranged horizontally, vertically, or in a square pattern.

[0053] In some examples, the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 each include a pixel driving circuit and a light-emitting element. The pixel driving circuits in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are respectively connected to a scan signal line, a data signal line, and a light-emitting signal line. The pixel driving circuits are configured to receive the data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting element. The light-emitting elements in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are respectively connected to the pixel driving circuit of their respective sub-pixels. The light-emitting elements are configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of their respective sub-pixels.

[0054] Figure 3 This is a cross-sectional structural diagram of a display substrate, illustrating the structure of a sub-pixel of an OLED display substrate. Figure 3As shown, on a plane perpendicular to the display substrate, the display substrate may include a substrate 10, a driving circuit layer 20 disposed on the substrate 10, a light-emitting structure layer 30 disposed on the side of the driving circuit layer 20 away from the substrate 10, and an encapsulation layer 40 disposed on the side of the light-emitting structure layer 30 away from the substrate 10. In some possible implementations, the display substrate may include other film layers, such as spacers, etc., which are not limited herein.

[0055] In some examples, the driving circuit layer 20 for each sub-pixel may include multiple transistors and storage capacitors constituting the pixel driving circuit. For example, the pixel driving circuit may be a 3T1C (i.e., three thin-film transistors and one capacitor), 4T1C (i.e., four thin-film transistors and one capacitor), 5T1C (i.e., five thin-film transistors and one capacitor), 5T2C (i.e., five thin-film transistors and two capacitors), or 7T1C (i.e., seven thin-film transistors and one capacitor) structure. The light-emitting structure layer 30 includes a pixel definition layer 302 and multiple light-emitting elements. At least one light-emitting element includes a first electrode 301, a second electrode 304, and an organic light-emitting layer 303 disposed between the first electrode 301 and the second electrode 304. For example, the first electrode 301 may be a total reflection anode, and the second electrode 304 may be a partial reflection cathode. The first electrode 301 is located on the side of the second electrode 304 closest to the substrate 10. The first electrode 301 can be connected to the pixel driving circuit of the driving circuit layer 20 through a via. The organic light-emitting layer 303 is connected to the first electrode 301, and the second electrode 304 is connected to the organic light-emitting layer 303. The organic light-emitting layer 303 emits light of the corresponding color under the drive of the first electrode 301 and the second electrode 304. The encapsulation layer 40 may include a first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403 stacked together. The first encapsulation layer 401 and the third encapsulation layer 403 may be made of inorganic materials, while the second encapsulation layer 402 may be made of organic materials. The second encapsulation layer 402 is disposed between the first encapsulation layer 401 and the third encapsulation layer 403 to ensure that external moisture cannot enter the light-emitting element.

[0056] Figure 4 This is a schematic diagram of light emission from a planar light-emitting element. (Example:) Figure 4 As shown, the light emitted by the light-emitting element EL passes sequentially through the first encapsulation layer 401, the second encapsulation layer 402, and the third encapsulation layer 403 before entering the air. The condition for total internal reflection of light entering the encapsulation layers is:

[0057] n1·sinθ1=n2·sinθ2=n3·sinθ3=n 空 ·sin90°.

[0058] Wherein, n1 is the refractive index of the first encapsulation layer 401, n2 is the refractive index of the second encapsulation layer 402, n3 is the refractive index of the third encapsulation layer 403, θ1 is the incident angle of the second encapsulation layer 402, θ2 is the incident angle of the third encapsulation layer 403, and θ3 is the incident angle of the air entering the air.

[0059] Therefore, when the refractive index n1 of the first encapsulation layer 401 is approximately 1.75 and the refractive index n2 of the second encapsulation layer 402 is approximately 1.5, the critical angle for total internal reflection at the interface of the second encapsulation layer 402 with the light entering the first encapsulation layer 401 from the light-emitting element EL can be calculated as: θ1 = arcsin(1.5 / 1.75) ≈ 59°. Thus, when the angle of the light entering the first encapsulation layer 401 from the light-emitting element EL is approximately 59 degrees, the light will be confined within the encapsulation layer by total internal reflection. This portion of the waveguide light has a larger spectral peak width compared to the light that can be emitted normally. For a purely planar light-emitting element, this portion of the waveguide light cannot be emitted. However, as... Figure 3 As shown, due to the slope of the pixel definition layer 302, the total internal reflection waveguide light in the first encapsulation layer 401 will be reflected and emitted in a specific area of ​​the pixel definition layer 302. This portion of the total internal reflection waveguide light will be superimposed on the normal emitted light of the light-emitting element EL, resulting in severe large-viewing-angle wave offset. For example, in Figure 3 In the process, the first influencing ray La and the second influencing ray Lb are reflected by the slope of the pixel definition layer 302 and then emitted. The first influencing ray La represents the light emitted from a position close to the adjacent pixel definition layer 302 within the light-emitting area of ​​the sub-pixel, and the second influencing ray Lb represents the light emitted from a position far from the adjacent pixel definition layer 302 within the light-emitting area of ​​the sub-pixel. The intensity of the first influencing ray La is higher than the intensity of the second influencing ray Lb.

[0060] This disclosure provides at least one embodiment of a display substrate, comprising: a first electrode layer, a pixel definition layer, an organic light-emitting layer, a second electrode layer, and a first encapsulation layer sequentially disposed away from a substrate. The pixel definition layer has multiple openings, at least one of which exposes the first electrode layer. The pixel definition layer has a first ramp portion and a second ramp portion at its edge near at least one opening. The distance from the surface of the second ramp portion away from the substrate to the substrate is greater than the distance from the surface of the first ramp portion away from the substrate to the substrate, and the slope angles of the first ramp portion and the second ramp portion are different. The first encapsulation layer has a first encapsulation ramp portion and a second encapsulation ramp portion. The distance from the surface of the second encapsulation ramp portion away from the substrate to the substrate is greater than the distance from the surface of the first encapsulation ramp portion away from the substrate to the substrate, and the slope angles of the first encapsulation ramp portion and the second encapsulation ramp portion are different. The slope angle is the angle between the tangent of the ramp portion and a plane parallel to the substrate.

[0061] The display substrate provided in this embodiment improves the large viewing angle color offset of the display substrate by changing the morphology of the pixel definition layer and the first encapsulation layer so that the waveguide light inside the first encapsulation layer cannot be emitted.

[0062] In some exemplary embodiments, the slope angle of the first ramp portion can be smaller than that of the second ramp portion. In this exemplary embodiment, by setting the slope angle of the first ramp portion to be smaller than that of the second ramp portion, the light rays reflected by the first encapsulation layer and the pixel definition layer can contact the reflective surfaces of the first and second encapsulation layers at a large angle, thereby confining them within the encapsulation layer and preventing large-viewing-angle glare from emanating out.

[0063] In some exemplary embodiments, the orthographic projection of the first encapsulation ramp portion on the substrate at least partially overlaps with the orthographic projection of the first ramp portion on the substrate. In this exemplary embodiment, the morphology of the first encapsulation layer matches the morphology of the pixel definition layer. The morphology of the first encapsulation layer changes according to the changes in the morphology of the pixel definition layer.

[0064] In some exemplary embodiments, the first ramp portion has at least one first step. The orthographic projection of the first encapsulation ramp portion of the first encapsulation layer on the substrate at least partially overlaps with the orthographic projection of the first step on the substrate. In this exemplary embodiment, the direction of the influence light reflected by the first encapsulation layer and the pixel definition layer is adjusted by at least one first step, thereby improving the large viewfinder color shift.

[0065] In some exemplary embodiments, the first step has a first flat portion and a first ramp, with the first flat portion connecting the first ramp and the second ramp portion. In this exemplary embodiment, the first flat portion of the first step is used to reflect the light, allowing it to contact the reflective surfaces of the first and second encapsulation layers at a large angle, thereby improving angular deflection at large viewing angles.

[0066] In some exemplary embodiments, the slope angle of the first slope is approximately equal to the slope angle of the second climbing section. However, this embodiment is not limited to this. For example, the slope angle of the first slope may be smaller than the slope angle of the second climbing section.

[0067] In some exemplary embodiments, in a plane parallel to the display substrate, the first length of the first flat portion is less than the first length of the adjacent opening. The first length is a dimension along a first direction, which is parallel to the plane containing the substrate and intersects the centerline of the opening.

[0068] In some exemplary embodiments, the thickness of the first encapsulation layer is approximately 600 nanometers to 3 micrometers, for example, 1 micrometer; and in a direction perpendicular to the substrate, the distance from the surface of the first flat portion away from the substrate to the first electrode layer is greater than or equal to 200 nanometers, for example, 300 nanometers. However, this embodiment is not limited in this respect.

[0069] In some exemplary embodiments, the pixel definition layer further has a second flat portion near the edge of at least one opening, the second flat portion being connected to a second ramp portion; the distance from the surface of the second flat portion away from the substrate to the substrate is greater than the distance from the surface of the second ramp portion away from the substrate to the substrate. In this example, the second flat portion and the second ramp portion form a second step.

[0070] In some exemplary embodiments, the orthographic projection of the second flat portion on the substrate does not overlap with the orthographic projection of the second ramp portion on the substrate. For example, in a plane perpendicular to the substrate, the second step formed by the second ramp portion and the second flat portion can be trapezoidal. However, this embodiment is not limited to this.

[0071] In some exemplary embodiments, the orthographic projection of the second flat portion onto the substrate includes the orthographic projection of the second ramp portion onto the substrate. For example, in a plane perpendicular to the substrate, the second step formed by the second ramp portion and the second flat portion can be an inverted trapezoid. However, this embodiment is not limited to this.

[0072] In some exemplary embodiments, the first ramp portion has a plurality of first steps arranged sequentially in a direction away from adjacent openings. The first encapsulation layer also has at least one third encapsulation ramp portion, which connects the second encapsulation ramp portion and the first encapsulation ramp portion. The orthographic projection of the third encapsulation ramp portion on the substrate overlaps with the orthographic projection of at least one first step on the substrate.

[0073] In some exemplary embodiments, the pixel definition layer includes: a first pixel definition layer and a second pixel definition layer stacked together, the first pixel definition layer having a plurality of first openings, and the second pixel definition layer having a plurality of second openings, the plurality of first openings and the plurality of second openings being connected in a one-to-one correspondence and exposing a first electrode layer. The first pixel definition layer has at least a first ramp portion at an edge near at least one first opening, and the second pixel definition layer has at least a second ramp portion at an edge near at least one second opening.

[0074] In some exemplary embodiments, the material of the first pixel definition layer is different from the material of the second pixel definition layer. However, this embodiment is not limited in this respect.

[0075] In some exemplary embodiments, the first encapsulation layer further includes a first encapsulation flattening portion and a second encapsulation flattening portion, the first encapsulation flattening portion being connected to a first encapsulation ramp portion, and the second encapsulation flattening portion being connected to a second encapsulation ramp portion. The distance from the surface of the first encapsulation flattening portion away from the substrate to the substrate is less than the distance from the surface of the first encapsulation ramp portion away from the substrate to the substrate. The distance from the surface of the second encapsulation flattening portion away from the substrate to the substrate is greater than the distance from the surface of the second encapsulation ramp portion away from the substrate to the substrate.

[0076] In some exemplary embodiments, the display substrate further includes a second encapsulation layer located on the side of the first encapsulation layer away from the substrate. The first encapsulation layer is made of an inorganic material, the second encapsulation layer is made of an organic material, and the refractive index of the first encapsulation layer is greater than the refractive index of the second encapsulation layer.

[0077] In some exemplary embodiments, the refractive index of the pixel definition layer ranges from about 1.4 to 2, and the refractive index of the first encapsulation layer ranges from about 1.45 to 2.2. However, this embodiment is not limited thereto.

[0078] The following examples illustrate the solution of this embodiment.

[0079] Figure 5 This is a partial planar schematic diagram of a display substrate according to at least one embodiment of the present disclosure, illustrating four sub-pixels. Figure 6 for Figure 5 A partial cross-sectional view along the PP direction illustrates the structure of a sub-pixel. Figure 7 This is a schematic diagram of the optical path of at least one embodiment of the present disclosure.

[0080] In some exemplary implementations, such as Figure 5 and Figure 6 As shown, on a plane perpendicular to the display substrate, the display substrate includes: a substrate 50 and a driving circuit layer 60, a light-emitting structure layer 70 and an encapsulation layer 80 sequentially disposed on the substrate 50.

[0081] In some exemplary embodiments, the substrate 50 may be a flexible substrate or a rigid substrate. The driving circuit layer 60 for each sub-pixel may include a plurality of transistors and storage capacitors constituting the pixel driving circuit. Figure 6The sub-pixels shown in the image only include one first transistor 601 and one storage capacitor 602 as an example. In some examples, the driving circuit layer 20 includes a semiconductor layer, a first gate metal layer, a second gate metal layer, and a source / drain metal layer sequentially disposed on the substrate 50. A first insulating layer 51 is disposed between the semiconductor layer and the substrate 50, a second insulating layer 52 is disposed between the semiconductor layer and the first gate metal layer, a third insulating layer 53 is disposed between the first gate metal layer and the second gate metal layer, a fourth insulating layer 54 is disposed between the second gate metal layer and the source / drain metal layer, and a fifth insulating layer 55 is disposed on the side of the source / drain metal layer away from the substrate 50. The semiconductor layer includes at least a first active layer of the first transistor 601, the first gate metal layer includes at least a first gate electrode of the first transistor 601 and a first capacitor electrode of the storage capacitor 602, the second gate metal layer includes at least a second capacitor electrode of the storage capacitor 602, and the source / drain metal layer includes at least a first source electrode and a first drain electrode of the first transistor 601. In some examples, the first insulating layer 51 to the fourth insulating layer 54 may be inorganic insulating layers, and the fifth insulating layer 55 may be an organic insulating layer. However, this embodiment is not limited to this.

[0082] In some exemplary embodiments, the light-emitting structure layer 70 of each sub-pixel includes a pixel definition layer 72 and a light-emitting element EL. The light-emitting element EL may include a stacked first electrode 71, an organic light-emitting layer 73, and a second electrode 74. The first electrode 71 is connected to the first drain electrode of the first transistor 601 through a via, the organic light-emitting layer 73 is connected to the first electrode 71, and the second electrode 74 is connected to the organic light-emitting layer 73. The organic light-emitting layer 73 emits light of a corresponding color under the drive of the first electrode 71 and the second electrode 74.

[0083] In some exemplary embodiments, the organic light-emitting layer 73 may include stacked hole injection layer (HIL), hole transport layer (HTL), electron block layer (EBL), emitting layer (EML), hole block layer (HBL), electron transport layer (ETL), and electron injection layer (EIL). In some examples, the hole injection layer of all sub-pixels may be a common layer connected together, the electron injection layer of all sub-pixels may be a common layer connected together, the hole transport layer of all sub-pixels may be a common layer connected together, the electron transport layer of all sub-pixels may be a common layer connected together, and the hole block layer of all sub-pixels may be a common layer connected together. The emitting layers of adjacent sub-pixels may have a small overlap or may be isolated, and the electron block layers of adjacent sub-pixels may have a small overlap or may be isolated.

[0084] In some exemplary implementations, such as Figure 6 As shown, the pixel definition layer 72 is located on the side of the first electrode 71 away from the substrate 50. The pixel definition layer 71 has an opening that exposes the surface of the first electrode 71. The portion of the light-emitting element EL located in the opening of the pixel definition layer 71 is used for light emission; this portion is the light-emitting area of ​​the light-emitting element EL. Figure 6 and Figure 7As shown, the pixel definition layer 71 has a first ramp portion, a second ramp portion 723, and a second flat portion 724 connected sequentially near the edge of the opening. The first ramp portion has a first step. The first step has a first slope surface 721 and a first flat portion 722 sequentially arranged in a direction away from the adjacent opening. The first flat portion 722 connects the first slope surface 721 and the second ramp portion 723. The second ramp portion 723 and the second flat portion 724 can form a second step. In this example, the distance from the surface of the first platform portion 722 away from the substrate 50 to the substrate 50 is greater than the distance from the surface of the first slope surface 721 away from the substrate 50 to the substrate 50, the distance from the surface of the second ramp portion 723 away from the substrate 50 to the substrate 50 is greater than the distance from the surface of the first platform portion 722 away from the substrate 50 to the substrate 50, and the distance from the surface of the second platform portion 724 away from the substrate 50 to the substrate 50 is greater than the distance from the surface of the second ramp portion 723 away from the substrate 50 to the substrate 50. In this example, when the surface of the ramp (or flat section or slope) away from the substrate is not parallel to the plane of the substrate, the distance from the surface of the ramp (or flat section or slope) away from the substrate to the substrate can be the average distance from the surface of the ramp (or flat section or slope) away from the substrate to the substrate. However, this embodiment is not limited to this.

[0085] In some exemplary implementations, such as Figure 7 As shown, the first climbing portion has a first slope angle α1, the second climbing portion 723 has a second slope angle α2, and the first slope surface 721 has a third slope angle α3. The slope angle is the angle between the tangent of the climbing portion and the plane parallel to the substrate. In this example, since the first climbing portion has a first step, the first slope angle α1 of the first climbing portion refers to the angle between the tangent of the imaginary slope formed by the end of the first flat portion 722 away from the first slope surface 721 and the end of the first slope surface 721 away from the first flat portion 722, and the plane parallel to the substrate (e.g., a horizontal plane). The second slope angle α2 of the second climbing portion 723 is the angle between the tangent of the plane containing the second climbing portion 723 and the plane parallel to the substrate. The third slope angle α3 of the first slope surface 721 is the angle between the tangent of the first slope surface 721 and the plane parallel to the substrate. In some examples, the first slope angle a1 may be less than the second slope angle a2, and the second slope angle a2 may be approximately equal to the third slope angle a3. For example, both the third slope angle a3 and the second slope angle a2 may be approximately 45 degrees. However, this embodiment is not limited to this. For example, the second slope angle a2 may be less than the third slope angle a3, or the second slope angle a2 may be greater than the third slope angle a3.

[0086] In some exemplary implementations, such as Figure 6 and Figure 7As shown, the plane containing the first flat portion 722 and the plane containing the second flat portion 724 can be parallel to each other and both are parallel to the plane containing the substrate 50. However, this embodiment is not limited to this. For example, the plane containing the first flat portion 722 can be at a certain angle to the plane containing the second flat portion 724.

[0087] In some exemplary implementations, such as Figure 6 and Figure 7 As shown, the orthographic projections of the first slope 721, the first flat portion 722, the second slope 723, and the second flat portion 724 onto the substrate 50 do not overlap. The orthographic projection of the first slope 721 onto the substrate 50 may overlap with the orthographic projection of the first electrode 71 onto the substrate 50. In a plane parallel to the display substrate, as... Figure 5 As shown, the orthographic projection of the first slope 721 onto the substrate 50 can be an annular structure surrounding the opening of the pixel definition layer 72; the orthographic projection of the first flat portion 722 onto the substrate 50 can be an annular structure surrounding the orthographic projection of the first slope 721 onto the substrate 50; and the orthographic projection of the second slope portion 723 onto the substrate 50 can be an annular structure surrounding the orthographic projection of the first flat portion 722 onto the substrate 50. The second flat portions 724 around the different openings are interconnected.

[0088] In some exemplary implementations, such as Figure 6 and Figure 7 As shown, the first slope 721 and the second climbing portion 723 can be inclined arc surfaces. However, this embodiment is not limited to this. For example, the first slope 721 and the second climbing portion 723 can be inclined planes.

[0089] In some exemplary implementations, such as Figure 6 As shown, the encapsulation layer 80 may include a first encapsulation layer 81, a second encapsulation layer 82 and a third encapsulation layer 83 stacked together. The first encapsulation layer 81 and the third encapsulation layer 83 may be made of inorganic materials, while the second encapsulation layer 82 may be made of organic materials. The second encapsulation layer 82 is disposed between the first encapsulation layer 81 and the third encapsulation layer 83, which can ensure that external moisture cannot enter the light-emitting element EL.

[0090] In some exemplary implementations, such as Figure 6 and Figure 7As shown, the first encapsulation layer 81 may have a first encapsulation flat portion 812, a first encapsulation ramp portion 811, a second encapsulation ramp portion 813, and a second encapsulation flat portion 814 connected in sequence. The distance from the surface of the first encapsulation ramp portion 811 away from the substrate 50 to the substrate 50 is greater than the distance from the surface of the first encapsulation flat portion 812 away from the substrate 50 to the substrate 50. The distance from the surface of the second encapsulation ramp portion 813 away from the substrate 50 to the substrate 50 is greater than the distance from the surface of the first encapsulation flat portion 812 away from the substrate 50 to the substrate 50. The distance from the surface of the second encapsulation flat portion 814 away from the substrate 50 to the substrate 50 is greater than the distance from the surface of the second encapsulation ramp portion 813 away from the substrate 50 to the substrate 50. The ramp angle of the first encapsulation ramp portion 811 is the angle between the tangent of the plane containing the first encapsulation ramp portion 811 and the plane parallel to the substrate. The slope angle of the second package ramp portion 813 is the angle between the tangent of the plane containing the second package ramp portion 813 and the plane parallel to the substrate. The slope angles of the first package ramp portion 811 and the second package ramp portion 813 are different. For example, the slope angle of the first package ramp portion 811 is smaller than the slope angle of the second package ramp portion 813.

[0091] In some exemplary implementations, such as Figure 6 and Figure 7 As shown, the orthographic projection of the first encapsulation ramp portion 811 on the substrate 50 at least partially overlaps with the orthographic projection of the first step of the pixel definition layer 72 on the substrate 50, and the orthographic projection of the first encapsulation ramp portion 811 on the substrate 50 at least partially overlaps with the orthographic projection of the first flat portion 722 on the substrate 50. For example, the orthographic projection of the first encapsulation ramp portion 811 on the substrate 50 may cover the orthographic projection of the first ramp surface 721 on the substrate 50 and partially overlap with the orthographic projection of the first flat portion 722 on the substrate 50. The orthographic projection of the second encapsulation ramp portion 813 on the substrate 50 overlaps with the orthographic projections of the first flat portion 722 and the second ramp portion 723 of the pixel definition layer 72 on the substrate 50. The orthographic projection of the second encapsulation flat portion 814 on the substrate 50 overlaps with the orthographic projections of the second ramp portion 723 and the second flat portion 724 of the pixel definition layer 72 on the substrate 50. However, this embodiment is not limited in this respect.

[0092] In some exemplary implementations, such as Figure 6 and Figure 7As shown, the orthographic projection of the first encapsulation flat portion 812 of the first encapsulation layer 81 onto the substrate 50 overlaps with the orthographic projection of the light-emitting area of ​​the light-emitting element EL onto the substrate 50. The orthographic projection of the first encapsulation ramp portion 811 of the first encapsulation layer 81 onto the substrate 50 can be an annular structure surrounding the orthographic projection of the first encapsulation flat portion 812 onto the substrate 50, and the orthographic projection of the second encapsulation ramp portion 813 onto the substrate 50 can be an annular portion surrounding the orthographic projection of the first encapsulation ramp portion 811 onto the substrate 50. However, this embodiment is not limited to this.

[0093] In some exemplary embodiments, the refractive index of the pixel definition layer 72 may be approximately 1.4 to 2. The refractive index of the organic light-emitting layer 73 may be approximately 1.5 to 2.2. The refractive index of the first encapsulation layer 81 may be greater than the refractive index of the second encapsulation layer 82. For example, the difference between the refractive index of the first encapsulation layer 81 and the refractive index of the second encapsulation layer 82 may be greater than 0.1. For example, the refractive index of the first encapsulation layer 81 may be approximately 1.45 to 2.2, the refractive index of the second encapsulation layer 82 may be approximately 1.4 to 1.7, and the refractive index of the third encapsulation layer 83 may be approximately 1.45 to 2.2. However, this embodiment is not limited in this respect.

[0094] In some exemplary implementations, such as Figure 7 As shown, in a plane perpendicular to the substrate, the first height H1 of the first flat portion 722 of the pixel definition layer 72, from the surface away from the substrate 50 to the surface near the first electrode layer, is related to the thickness of the first encapsulation layer 81. For example, if the thickness of the first encapsulation layer 81 is approximately 1 micrometer (µm), the first height H1 of the first flat portion 722 is not less than 200 nanometers (nm), for example, the first height H1 can be approximately 300 nm. The first height H2 of the second flat portion 724, from the surface away from the substrate 50 to the surface near the first electrode layer, can be approximately 2 µm. The total thickness of the organic light-emitting layer 73 and the second electrode 74 of the light-emitting element EL can be approximately 200 nm. However, this embodiment is not limited to this.

[0095] In some exemplary implementations, such as Figure 7 As shown, in a plane parallel to the substrate, the first length W1 of the first flat portion 722 is less than the first length of the adjacent opening. The first length is a dimension along a first direction, which is parallel to the plane of the substrate and intersects the centerline of the opening adjacent to the first flat portion 722. For example, the first length W1 of the first flat portion 722 can be approximately 800 nm. The first length W2 of the first slope 721 can be approximately 300 nm, and the first length W3 of the second ramp portion 723 can be approximately 1700 nm. However, this embodiment is not limited to these dimensions.

[0096] In some exemplary embodiments, with Figure 7 The following explanation uses two light rays, L1 and L2, as an example. Figure 7 As shown, the light L1 emitted by the light-emitting element EL from the light-emitting area closest to the first flat portion 722 of the pixel definition layer 72, after being reflected by the first encapsulation ramp portion 811 of the first encapsulation layer 81 and the first flat portion 722 of the pixel definition layer 72, contacts the reflective surfaces of the first encapsulation layer 81 and the second encapsulation layer 82 at a large angle, thus confining it within the encapsulation layer 80 and preventing large viewing angle color shift caused by emission. The light L2 emitted by the light-emitting element EL from the light-emitting area furthest from the first flat portion 722 of the pixel definition layer 72, after being reflected by the first encapsulation ramp portion 811 of the first encapsulation layer 81, the first flat portion 722 or the second ramp portion 723 of the pixel definition layer 72, and the second encapsulation ramp portion 813 of the first encapsulation layer 81, contacts the reflective surfaces of the first encapsulation layer 81 and the second encapsulation layer 82 at a large angle, thus confining it within the encapsulation layer 80 and preventing large viewing angle color shift caused by emission.

[0097] In this exemplary embodiment, by forming a first platform portion 722 and a second ramp portion 723 near the edge of the opening in the pixel definition layer 72, and correspondingly forming a first encapsulation ramp portion 811 and a second encapsulation ramp portion 813 in the first encapsulation layer 81, the total internal reflection waveguide light in the first encapsulation layer 81 is confined in the encapsulation layer 80 and cannot be emitted, thereby improving the large viewing angle angular deviation of the display substrate and enhancing the display effect.

[0098] The structure of the display substrate according to embodiments of this disclosure is illustrated below through examples of the fabrication process of the display substrate. The "patterning process" mentioned in this disclosure includes processes such as depositing a film layer, coating photoresist, mask exposure, development, etching, and photoresist stripping. Deposition can be performed using any one or more selected from sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more selected from spraying and spin coating; and etching can be performed using any one or more selected from dry etching and wet etching. A "thin film" refers to a thin film of a certain material fabricated on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." When the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern."

[0099] The phrase "A and B are set in the same layer" in this disclosure means that A and B are formed simultaneously through the same drafting process. "Same layer" does not always mean that the layer thickness or layer height is the same in the cross-sectional view. "The projection of A includes the projection of B" means that the projection of B falls within the projection range of A, or the projection of A covers the projection of B.

[0100] In some exemplary embodiments, the fabrication process of the display substrate in this embodiment includes the following steps.

[0101] (1) Provide a substrate.

[0102] In some exemplary embodiments, the substrate 50 may be a rigid substrate, such as a quartz substrate or a glass substrate, or it may be a flexible substrate, such as an organic resin substrate. However, this embodiment is not limited to this.

[0103] (2) A driving circuit layer is fabricated on the substrate. The driving circuit layer includes multiple pixel driving circuits, and each pixel driving circuit includes multiple transistors and at least one storage capacitor. For example... Figure 6 As shown, a sub-pixel is used as an example, and this sub-pixel is illustrated using only a first transistor 601 and a storage capacitor 602.

[0104] In some exemplary embodiments, a first insulating film and an active layer film are sequentially deposited on a substrate 50, and the active layer film is patterned by a patterning process to form a first insulating layer 51 covering the entire substrate 50, and an active layer pattern disposed on the first insulating layer 51, wherein the active layer pattern includes at least the first active layer.

[0105] Subsequently, a second insulating film and a first metal film are deposited sequentially. The first metal film is patterned using a patterning process to form a second insulating layer 52 covering the active layer pattern, and a first gate metal layer pattern disposed on the second insulating layer 52. The first gate metal layer pattern includes at least a first gate electrode and a first capacitor electrode.

[0106] Subsequently, a third insulating film and a second metal film are deposited sequentially. The second metal film is patterned using a patterning process to form a third insulating layer 53 covering the first gate metal layer, and a second gate metal layer pattern disposed on the third insulating layer 53. The second gate metal layer pattern includes at least a second capacitor electrode, and the position of the second capacitor electrode corresponds to the position of the first capacitor electrode.

[0107] Subsequently, a fourth insulating film is deposited, and the fourth insulating film is patterned by a patterning process to form a pattern of a fourth insulating layer 54 covering the second gate metal layer. At least two first vias are formed on the fourth insulating layer 54. The fourth insulating layer 54, the third insulating layer 53 and the second insulating layer 52 in the two first vias are etched away to expose the surface of the first active layer.

[0108] Subsequently, a third metal thin film is deposited, and the third metal thin film is patterned using a patterning process to form a source / drain metal layer pattern on the fourth insulating layer 54. The source / drain metal layer includes at least a first source electrode and a first drain electrode. The first source electrode and the first drain electrode can be connected to the first active layer through first vias, respectively.

[0109] like Figure 6 As shown, the first active layer, the first gate electrode, the first source electrode, and the first drain electrode can form a first transistor 601, and the first capacitor electrode and the second capacitor electrode can form a storage capacitor 602.

[0110] In some exemplary embodiments, the first insulating layer 51, the second insulating layer 52, the third insulating layer 53, and the fourth insulating layer 54 are any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be single-layer, multi-layer, or composite layers. The first insulating layer 51 is called a buffer layer, used to improve the substrate's resistance to water and oxygen; the second insulating layer 52 and the third insulating layer 53 are called gate insulator (GI) layers; and the fourth insulating layer 54 is called an interlayer dielectric (ILD) layer. The first metal thin film, the second metal thin film, and the third metal thin film are made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and can be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti. The active layer thin film uses one or more materials such as amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, and polythiophene. That is, this disclosure is applicable to transistors manufactured based on oxide technology, silicon technology, and organic technology.

[0111] In some exemplary embodiments, a planarization film of organic material is coated on the substrate 50 on which the aforementioned pattern is formed to form a fifth insulating layer 55 covering the entire substrate 50. A second via is formed on the fifth insulating layer 55 in the display area through a masking, exposure, and development process. The fifth insulating layer 55 within the second via is developed away, exposing the surface of the first drain electrode of the first transistor 601 of the pixel driving circuit. The fifth insulating layer 55 may also be referred to as a planarization (PLN) layer.

[0112] (3) A first electrode pattern is formed on the substrate on which the aforementioned pattern is formed. In some examples, the first electrode is a reflective anode.

[0113] In some exemplary embodiments, a conductive thin film is deposited on the substrate 50 on which the aforementioned pattern is formed, and the conductive thin film is patterned by a patterning process to form a first electrode pattern. The first electrode 71 can be connected to the first drain electrode of the first transistor 601 through a second via.

[0114] In some examples, the first electrode 71 may be made of a metallic material, such as any one or more of magnesium (Mg), silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo), or an alloy of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). It may be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti, or a stacked structure formed of metal and transparent conductive material, such as reflective materials such as ITO / Ag / ITO, Mo / AlNd / ITO, etc.

[0115] (4) A pixel definition layer pattern is formed on the substrate on which the aforementioned pattern is formed.

[0116] In some exemplary embodiments, a pixel definition film is coated on the substrate 50 on which the aforementioned pattern is formed, and a pixel definition layer 72 pattern is formed by a masking, exposure, and development process. The pixel definition layer 72 has an opening that exposes the first electrode. In some examples, the same mask with multiple transmittances can be used to form the first slope 721, the first flat portion 722, the second slope 723, and the second flat portion 724 of the pixel definition layer 72. However, this embodiment is not limited to this.

[0117] In some examples, the pixel definition layer 72 can be made of polyimide, acrylic, or polyethylene terephthalate, etc.

[0118] (5) An organic light-emitting layer and a second electrode are sequentially formed on the substrate on which the aforementioned pattern is formed. In some examples, the second electrode 74 is a transparent cathode. The light-emitting element can emit light from the side away from the substrate 50 through the transparent cathode, achieving top emission. In some examples, the organic light-emitting layer 73 of the light-emitting element may include: a hole injection layer, a hole transport layer, an electron blocking layer, a light-emitting layer, a hole blocking layer, an electron transport layer, and an electron injection layer.

[0119] In some exemplary embodiments, a hole injection layer, a hole transport layer, and an electron blocking layer are sequentially deposited on the substrate 50 on which the aforementioned pattern is formed using an open mask. Then, light-emitting layers of different colors, such as a blue, green, and red light-emitting layer, are sequentially deposited using a fine metal mask (FMM). Then, a hole blocking layer, an electron transport layer, and an electron injection layer are sequentially deposited using an open mask. However, this embodiment is not limited to this approach.

[0120] In some exemplary embodiments, the organic light-emitting layer can be formed within the opening of the pixel definition layer, thereby connecting the organic light-emitting layer 73 to the first electrode 71. The second electrode 74 is formed on the second flat portion 724 of the pixel definition layer 72 and is connected to the organic light-emitting layer 73.

[0121] In some exemplary embodiments, the second electrode 74 may be made of any one or more of magnesium (Mg), silver (Ag), and aluminum (Al), or an alloy made of any one or more of the above metals, or a transparent conductive material, such as indium tin oxide (ITO), or a multilayer composite structure of metal and transparent conductive material. However, this embodiment is not limited in this respect.

[0122] In some exemplary embodiments, an optical coupling layer (CPL) may be formed on the side of the second electrode 74 away from the substrate 50. The CPL may be a common layer for multiple sub-pixels. The CPL can work in conjunction with a transparent cathode to increase light output. For example, the CPL may be made of a semiconductor material. The refractive index of the CPL may be approximately 1.4 to 2.3. However, this embodiment is not limited to this.

[0123] (6) An encapsulation layer is formed on the substrate on which the aforementioned pattern is formed.

[0124] In some exemplary embodiments, an encapsulation layer 80 is formed on the substrate 50 on which the aforementioned pattern is formed. The encapsulation layer 80 may include a first encapsulation layer 81, a second encapsulation layer 82, and a third encapsulation layer 83 stacked together. The first encapsulation layer 81 is made of an inorganic material and covers the second electrode 73. The second encapsulation layer 82 is made of an organic material. The third encapsulation layer 83 is made of an inorganic material and covers the first encapsulation layer 81 and the second encapsulation layer 82. The first encapsulation layer 81 has a first encapsulation flattening portion 812, a first encapsulation ramp portion 811, a second encapsulation ramp portion 812, and a second encapsulation flattening portion 814. However, this embodiment is not limited to this. In some examples, the encapsulation layer 80 may adopt a five-layer structure of inorganic / organic / inorganic / organic / inorganic.

[0125] The display substrate provided in this exemplary embodiment improves the large viewing angle color deviation of the display substrate by improving the morphology of the pixel definition layer and the first encapsulation layer.

[0126] The structure and fabrication process of the display substrate in this disclosure are merely illustrative. In some exemplary embodiments, the corresponding structure and patterning processes can be modified and increased or decreased as needed. For example, the driving circuit layer may include two source and drain metal layers, wherein the first electrode can be connected to the first drain electrode of the pixel driving circuit via a connecting electrode. However, this embodiment is not limited in this respect.

[0127] The structure (or method) shown in this embodiment can be appropriately combined with the structure (or method) shown in other embodiments.

[0128] Figure 8 This is another partial cross-sectional schematic diagram of a display substrate according to at least one embodiment of the present disclosure, illustrating the structure of a sub-pixel. Figure 9 This is another optical path schematic diagram of at least one embodiment of the present disclosure.

[0129] In some exemplary implementations, such as Figure 8 and Figure 9 As shown, the pixel definition layer 72 has a first ramp portion 720, a second ramp portion 723, and a second flat portion 724 connected sequentially near the edge of the opening. The first ramp portion 720 is close to the first electrode 71. The distance between the surface of the second flat portion 724 away from the substrate 50 and the substrate 50 is greater than the distance between the surface of the second ramp portion 723 away from the substrate 50 and the substrate 50. The distance between the surface of the second ramp portion 723 away from the substrate 50 and the substrate 50 is greater than the distance between the surface of the first ramp portion 720 away from the substrate 50 and the substrate 50. In this example, as... Figure 9 As shown, the first climbing portion 720 has a first slope angle α1, and the second climbing portion 723 has a second slope angle α2. In this example, the first slope angle α1 of the first climbing portion 720 is the angle between the tangent to the plane containing the first climbing portion 720 and the plane parallel to the substrate. The second slope angle α2 of the second climbing portion 723 is the angle between the tangent to the plane containing the second climbing portion 723 and the plane parallel to the substrate. The first slope angle α1 is smaller than the second slope angle α2.

[0130] In some exemplary implementations, such as Figure 8 and Figure 9 As shown, the orthographic projections of the first ramp portion 720, the second ramp portion 723, and the second flat portion 724 on the substrate 50 do not overlap. In a plane parallel to the display substrate, the orthographic projection of the first ramp portion 720 on the substrate 50 can be a ring-shaped structure surrounding the light-emitting area of ​​the light-emitting element EL, and the orthographic projection of the second ramp portion 723 on the substrate 50 can be a ring-shaped structure surrounding the orthographic projection of the first ramp portion 720 on the substrate 50. However, this embodiment is not limited in this respect.

[0131] In some exemplary implementations, such as Figure 8 and Figure 9As shown, the first encapsulation layer 81 may have a first encapsulation flat portion 812, a first encapsulation ramp portion 811, a second encapsulation ramp portion 813, and a second encapsulation flat portion 814 connected in sequence. For example, the ramp angle of the first encapsulation ramp portion 811 is smaller than the ramp angle of the second encapsulation ramp portion 813. The orthographic projection of the first encapsulation ramp portion 811 on the substrate 50 overlaps with the orthographic projection of the first ramp portion 720 on the substrate 50. The orthographic projection of the second encapsulation ramp portion 813 on the substrate 50 overlaps with the orthographic projections of the first ramp portion 720 and the second ramp portion 723 on the substrate 50. However, this embodiment is not limited in this respect.

[0132] In this exemplary embodiment, such as Figure 9 As shown, the light L1 emitted by the light-emitting element EL from the light-emitting area near the pixel definition layer 72 is reflected by the first encapsulation ramp portion 811 of the first encapsulation layer 81 and the first ramp portion 720 of the pixel definition layer 72, and then contacts the reflective surfaces of the first encapsulation layer 81 and the second encapsulation layer 82 at a large angle, thus confining it within the encapsulation layer 80 and preventing large viewing angle distortion caused by outgoing light. Similarly, the light L2 emitted by the light-emitting element EL from the light-emitting area away from the pixel definition layer 72 is reflected by the first encapsulation ramp portion 811 of the first encapsulation layer 81 and the second ramp portion 723 of the pixel definition layer 72, and then contacts the reflective surfaces of the first encapsulation layer 81 and the second encapsulation layer 82 at a large angle, thus confining it within the encapsulation layer 80 and preventing large viewing angle distortion caused by outgoing light.

[0133] The remaining structure of the display substrate in this embodiment can be referred to the description of the foregoing embodiments, and therefore will not be repeated here. The structure (or method) shown in this embodiment can be appropriately combined with the structure (or method) shown in other embodiments.

[0134] Figure 10 This is another partial cross-sectional schematic diagram of a display substrate according to at least one embodiment of the present disclosure, illustrating the structure of a sub-pixel. In some exemplary embodiments, such as Figure 10As shown, a first pixel definition layer 72a and a second pixel definition layer 72b are sequentially stacked on the side of the first electrode 71 away from the substrate 50. The first pixel definition layer 72a has a plurality of first openings, and the second pixel definition layer 72b has a plurality of second openings, with each of the first and second openings corresponding to one another. The first openings communicate with their corresponding second openings, exposing the first electrode 71. The first pixel definition layer 72a has a first step near the edge of the first opening, and the first step has a first slope 721 and a first flat portion 722. The second pixel definition layer 72b has a second step near the edge of the second opening, and the second step has a second ramp portion 723 and a second flat portion 724. In this example, both the first step and the second step can be trapezoidal in a plane perpendicular to the substrate. The first encapsulation layer 81 has a first encapsulation flat portion 812, a first encapsulation ramp portion 811, a second encapsulation ramp portion 813, and a second encapsulation flat portion 814.

[0135] In some exemplary embodiments, the material of the first pixel definition layer 72a may be different from the material of the second pixel definition layer 72b. For example, the first pixel definition layer 72a and the second pixel definition layer 72b may be different organic materials.

[0136] The remaining structure and optical path of the display substrate in this embodiment can be described with reference to the description of the foregoing embodiments, and therefore will not be repeated here. The structure (or method) shown in this embodiment can be appropriately combined with the structure (or method) shown in other embodiments.

[0137] Figure 11 This is another partial cross-sectional schematic diagram of a display substrate according to at least one embodiment of the present disclosure, illustrating the structure of a sub-pixel. Figure 12 This is another optical path schematic diagram of at least one embodiment of the present disclosure.

[0138] In some exemplary implementations, such as Figure 11 and Figure 12 As shown, the first pixel definition layer 72a has a first step near the edge of the first opening, the first step having a first slope 721 and a first flat portion 722. The second pixel definition layer 72b has a second step near the edge of the second opening, the second step having a second ramp portion 723 and a second flat portion 724. In this example, in a plane perpendicular to the substrate, the first step can be trapezoidal, and the second step can be an inverted trapezoid. The orthographic projection of the second flat portion 724 onto the substrate 50 can cover the orthographic projection of the second ramp portion 723 onto the substrate 50, and overlaps with the orthographic projection of the first flat portion 722 onto the substrate 50. However, this embodiment is not limited to this. For example, the orthographic projection of the second flat portion 724 onto the substrate 50 can cover the orthographic projections of both the second ramp portion 723 and the first flat portion 722 onto the substrate 50.

[0139] In some exemplary implementations, such as Figure 11 and Figure 12 As shown, the first encapsulation layer 81 has a first encapsulation flat portion 812, a first encapsulation ramp portion 811, a second encapsulation ramp portion 813, and a second encapsulation flat portion 814. The orthographic projection of the second encapsulation flat portion 814 on the substrate 50 can cover the orthographic projection of the second encapsulation ramp portion 813 on the substrate 50, and overlaps with the orthographic projection of the first encapsulation ramp portion 811 on the substrate 50. The orthographic projection of the first encapsulation ramp portion 811 on the substrate 50 overlaps with the orthographic projection of the first step of the pixel definition layer 72 on the substrate 50. However, this embodiment is not limited in this respect.

[0140] In this exemplary embodiment, such as Figure 12 As shown, the light L1 emitted by the light-emitting element EL from the light-emitting area near the pixel definition layer 72 is reflected by the first encapsulation ramp portion 811 of the first encapsulation layer 81 and the first flat portion 722 of the pixel definition layer 72, changing its emission direction and confining it within the encapsulation layer 80 to prevent large viewing angle distortion. Similarly, the light L2 emitted by the light-emitting element EL from the light-emitting area away from the pixel definition layer 72 is reflected by the first encapsulation ramp portion 811 of the first encapsulation layer 81 and the second ramp portion 723 of the pixel definition layer 72, changing its emission direction to prevent large viewing angle distortion.

[0141] The remaining structure of the display substrate in this embodiment can be referred to the description of the foregoing embodiments, and therefore will not be repeated here. The structure (or method) shown in this embodiment can be appropriately combined with the structure (or method) shown in other embodiments.

[0142] Figure 13 This is another partial cross-sectional schematic diagram of a display substrate according to at least one embodiment of the present disclosure, illustrating the structure of a sub-pixel. Figure 14 This is another optical path schematic diagram of at least one embodiment of the present disclosure.

[0143] In some exemplary embodiments, the pixel definition layer 72 has a first ramp portion, a second ramp portion 723, and a second flat portion 724 connected sequentially near the edge of the opening. The first ramp portion has two first steps arranged sequentially in a direction away from the adjacent opening, namely, the first ramp portion has a first slope surface 721, a first flat portion 722, a second slope surface 725, and a third flat portion 726 connected sequentially. The first slope surface 721 and the first flat portion 722 form the first first step, and the second slope surface 725 and the third flat portion 726 form the second first step. The second ramp portion 723 and the second ramp portion 724 form the second step. In this example, in a plane perpendicular to the substrate, the two first steps and the second step can be trapezoids of different sizes.

[0144] In some exemplary implementations, such as Figure 13 and Figure 14 As shown, the first encapsulation layer 81 may have a first encapsulation flat portion 812, a first encapsulation ramp portion 811, a third encapsulation ramp portion 815, a second encapsulation ramp portion 813, and a second encapsulation flat portion 814 connected in sequence. The orthographic projection of the first encapsulation ramp portion 811 on the substrate 50 overlaps with the orthographic projection of the first first step on the substrate 50; the orthographic projection of the third encapsulation ramp portion 815 on the substrate 50 overlaps with the orthographic projection of the second first step on the substrate 50; and the orthographic projection of the second encapsulation ramp portion 813 on the substrate 50 overlaps with the orthographic projections of the second step and the second first step on the substrate 50. However, this embodiment is not limited in this respect.

[0145] In this exemplary embodiment, such as Figure 14 As shown, the light L1 emitted by the light-emitting element EL from its light-emitting area near the pixel definition layer 72 is reflected by the first encapsulation ramp 811 of the first encapsulation layer 81 and the first step of the pixel definition layer 72, and then contacts the reflective surfaces of the first encapsulation layer 81 and the second encapsulation layer 82 at a large angle, thus confining it within the encapsulation layer 80 and preventing large viewing angle distortion caused by outgoing light. Similarly, the light L2 emitted by the light-emitting element EL from its light-emitting area away from the pixel definition layer 72 is reflected by the first encapsulation ramp 811 of the first encapsulation layer 81 and the second step of the pixel definition layer 72, and then contacts the reflective surfaces of the first encapsulation layer 81 and the second encapsulation layer 82 at a large angle, thus confining it within the encapsulation layer 80 and preventing large viewing angle distortion caused by outgoing light.

[0146] The remaining structure of the display substrate in this embodiment can be referred to the description of the foregoing embodiments, and therefore will not be repeated here. The structure (or method) shown in this embodiment can be appropriately combined with the structure (or method) shown in other embodiments.

[0147] This disclosure also provides a method for fabricating a display substrate, comprising: sequentially forming a first electrode layer, a pixel definition layer, an organic light-emitting layer, a second electrode layer, and a first encapsulation layer on a substrate. The pixel definition layer has multiple openings, at least one of which exposes the first electrode layer. The pixel definition layer has a first ramp and a second ramp at its edge near at least one opening. The distance from the surface of the second ramp away from the substrate to the substrate is greater than the distance from the surface of the first ramp away from the substrate to the substrate, and the slope angles of the first ramp and the second ramp are different. The first encapsulation layer has a first encapsulation ramp and a second encapsulation ramp. The distance from the surface of the second encapsulation ramp away from the substrate to the substrate is greater than the distance from the surface of the first encapsulation ramp away from the substrate to the substrate, and the slope angles of the first encapsulation ramp and the second encapsulation ramp are different. The slope angle is the angle between the tangent of the ramp and a plane parallel to the substrate.

[0148] The method for preparing the display substrate in this embodiment can be referred to the description of the foregoing embodiment, and therefore will not be repeated here.

[0149] At least one embodiment of this disclosure also provides a display device, including the display substrate of the foregoing embodiments. In some examples, the display substrate may be an OLED display substrate. The display device may be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. However, this embodiment is not limited thereto.

[0150] The accompanying drawings in this disclosure only illustrate the structures relevant to this disclosure; other structures can be referenced to common designs. Unless otherwise specified, embodiments of this disclosure, i.e., features within the embodiments, can be combined with each other to obtain new embodiments.

[0151] Those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions disclosed herein without departing from the spirit and scope of the technical solutions disclosed herein, and all such modifications and substitutions should be covered within the scope of the claims of this disclosure.

Claims

1. A display substrate, comprising: A first electrode layer, a pixel definition layer, an organic light-emitting layer, a second electrode layer, and a first encapsulation layer are sequentially disposed away from the substrate. The pixel definition layer has multiple openings, with at least one opening exposing the first electrode layer; The pixel definition layer has a first ramp and a second ramp at an edge near at least one opening, wherein the distance from the surface of the second ramp away from the substrate to the substrate is greater than the distance from the surface of the first ramp away from the substrate to the substrate; the slope angles of the first ramp and the second ramp are different. In a plane parallel to the display substrate, the first ramp portion is annular in its orthogonal projection onto the substrate and is arranged around the light-emitting area. The first encapsulation layer has a first encapsulation ramp portion and a second encapsulation ramp portion. The distance from the surface of the second encapsulation ramp portion away from the substrate to the substrate is greater than the distance from the surface of the first encapsulation ramp portion away from the substrate to the substrate. The slope angles of the first encapsulation ramp portion and the second encapsulation ramp portion are different. The slope angle is the angle between the tangent of the slope and the plane parallel to the substrate. The first ramp portion has at least one first step, the first step having a first flat portion and a first slope, the first flat portion being connected between the first slope and the second ramp portion; the pixel definition layer also has a second flat portion near the edge of at least one opening, the second flat portion being connected to the second ramp portion; the distance from the surface of the second flat portion away from the substrate to the substrate is greater than the distance from the surface of the second ramp portion away from the substrate to the substrate; the second ramp portion and the second flat portion form a second step; in a plane perpendicular to the substrate, the first step is trapezoidal, and the second step is an inverted trapezoidal; The thickness of the first encapsulation layer is 600 nanometers to 3 micrometers, and in the direction perpendicular to the substrate, the distance from the surface of the first flat portion away from the substrate to the first electrode layer is greater than or equal to 200 nanometers.

2. The display substrate according to claim 1, wherein, The slope angle of the first climbing section is smaller than that of the second climbing section.

3. The display substrate according to claim 1, wherein, The orthographic projection of the first package ramp portion on the substrate overlaps at least partially with the orthographic projection of the first ramp portion on the substrate.

4. The display substrate according to any one of claims 1 to 3, wherein, The orthographic projection of the first encapsulation ramp portion of the first encapsulation layer on the substrate overlaps at least partially with the orthographic projection of the first step on the substrate.

5. The display substrate according to claim 1, wherein, The slope angle of the first slope is equal to the slope angle of the second climbing section.

6. The display substrate according to claim 1, wherein, In a plane parallel to the display substrate, the first length of the first flat portion is less than the first length of the adjacent opening; The first length is a dimension along a first direction, which is parallel to the plane of the substrate and intersects the center line of the opening.

7. The display substrate according to claim 1, wherein, The orthographic projection of the second flat portion onto the substrate includes the orthographic projection of the second ramp portion onto the substrate.

8. The display substrate according to claim 4, wherein, The first climbing section has a plurality of first steps arranged sequentially in a direction away from the adjacent opening; The first encapsulation layer also has at least one third encapsulation ramp, which is connected between the second encapsulation ramp and the first encapsulation ramp; The orthographic projection of the third encapsulation ramp on the substrate overlaps with the orthographic projection of at least one first step on the substrate.

9. The display substrate according to claim 1, wherein, The pixel definition layer includes: a first pixel definition layer and a second pixel definition layer stacked together, the first pixel definition layer having a plurality of first openings, the second pixel definition layer having a plurality of second openings, the plurality of first openings and the plurality of second openings being connected in a one-to-one correspondence and exposing the first electrode layer; The first pixel definition layer has at least a first ramp portion at an edge near at least one first opening, and the second pixel definition layer has at least a second ramp portion at an edge near at least one second opening.

10. The display substrate according to claim 9, wherein, The material of the first pixel definition layer is different from the material of the second pixel definition layer.

11. The display substrate according to claim 1, wherein, The first encapsulation layer also has a first encapsulation flat portion and a second encapsulation flat portion, wherein the first encapsulation flat portion is connected to the first encapsulation ramp portion, and the second encapsulation flat portion is connected to the second encapsulation ramp portion. The distance from the surface of the first package flat portion away from the substrate to the substrate is less than the distance from the surface of the first package ramp portion away from the substrate to the substrate. The distance from the surface of the second package flat portion away from the substrate to the substrate is greater than the distance from the surface of the second package ramp portion away from the substrate to the substrate.

12. The display substrate according to claim 1, further comprising: The second encapsulation layer is located on the side of the first encapsulation layer away from the substrate. The first encapsulation layer is made of inorganic material, the second encapsulation layer is made of organic material, and the refractive index of the first encapsulation layer is greater than the refractive index of the second encapsulation layer.

13. The display substrate according to claim 1, wherein, The refractive index of the pixel definition layer ranges from 1.4 to 2, and the refractive index of the first encapsulation layer ranges from 1.45 to 2.

2.

14. A display device comprising a display substrate as claimed in any one of claims 1 to 13.

15. A method for preparing a display substrate, comprising: A first electrode layer, a pixel definition layer, an organic light-emitting layer, a second electrode layer, and a first encapsulation layer are sequentially formed on a substrate. The pixel definition layer has multiple openings, with at least one opening exposing the first electrode layer; The pixel definition layer has a first ramp portion and a second ramp portion at the edge near at least one opening. The distance from the surface of the second ramp portion away from the substrate to the substrate is greater than the distance from the surface of the first ramp portion away from the substrate to the substrate. The slope angles of the first ramp portion and the second ramp portion are different. In a plane parallel to the display substrate, the orthographic projection of the first ramp portion onto the substrate is annular and is arranged around the light-emitting area. The first encapsulation layer has a first encapsulation ramp portion and a second encapsulation ramp portion. The distance from the surface of the second encapsulation ramp portion away from the substrate to the substrate is greater than the distance from the surface of the first encapsulation ramp portion away from the substrate to the substrate. The slope angles of the first encapsulation ramp portion and the second encapsulation ramp portion are different. The slope angle is the angle between the tangent of the ramp portion and the plane parallel to the substrate. The first ramp portion has at least one first step, the first step having a first flat portion and a first slope, the first flat portion being connected between the first slope and the second ramp portion; the pixel definition layer also has a second flat portion near the edge of at least one opening, the second flat portion being connected to the second ramp portion; the distance from the surface of the second flat portion away from the substrate to the substrate is greater than the distance from the surface of the second ramp portion away from the substrate to the substrate; the second ramp portion and the second flat portion form a second step; in a plane perpendicular to the substrate, the first step is trapezoidal, and the second step is an inverted trapezoidal; The thickness of the first encapsulation layer is 600 nanometers to 3 micrometers, and in the direction perpendicular to the substrate, the distance from the surface of the first flat portion away from the substrate to the first electrode layer is greater than or equal to 200 nanometers.

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