A simulation system and process program loading method for RISCV processor system

Abstract

The present invention relates to a simulation system and process program loading method for a RISC-V processor system, belonging to the field of simulation testing. The system of the present invention comprises: a Test_top module, a RISC-V processor module, a bus structure module, a FLASH model, a peripheral unit, and an iRAM module. The present invention can implement a full-process simulation test starting from reset. Since the present invention does not need to consider the problem of loss of storage space content during power failure, the same program segment can be stored in the off-chip non-volatile storage structure FLASH and the on-chip program storage structure iRAM. The jump address in the startup program of the present invention can be flexibly modified according to actual needs.

Description

Technical Field

[0001] The present invention belongs to the field of simulation testing, and in particular relates to a simulation system of a RISC-V processor system and a process program loading method. Background Art

[0002] The RISCV processor is an open-source processor instruction set that can be tailored and designed by hardware. During the development process of the SOC chip built based on the RISCV processor, prototype simulation verification needs to be carried out. In this link, the operation of the processor and the loading simulation process of the application software need to be completed. This patent proposes a feasible loading method for the simulation link.

[0003] Typically, when an FPGA-based processor system completes the power-on startup loading process during the prototype verification phase, the startup program is generally stored in the non-volatile storage space outside the chip, and the program is read into the memory program execution space. The processor then executes the program in the program execution space. However, prototype simulation verification based on the RISC-V processor requires the use of a FLASH simulation model to complete simulation testing of reading data from the non-volatile storage space outside the chip, and the pre-storage of program data in FLASH becomes a problem that needs to be solved.

[0004] During prototype verification, after the system is powered on, the hardware FPGA begins running first. The hardware's processor core controls the program, reading the boot program from the Flash memory and then switching to the application program for execution via the address set in the boot program. During simulation testing, however, the processor runs immediately and completes a series of initialization operations while reading the program from the Flash memory. These two operations require coordinated timing to complete. This is one of the issues addressed by this patent. Summary of the Invention

[0005] (1) Technical issues to be resolved

[0006] The technical problem to be solved by the present invention is how to provide a simulation system and a process program loading method for a RISCV processor system to solve the problems existing in prototype simulation verification based on the RISCV processor.

[0007] (2) Technical solution

[0008] In order to solve the above technical problems, the present invention proposes a simulation system for a RISCV processor system, which includes: a Test_top module, a RISCV processor module, a bus structure module, a FLASH model, a peripheral unit and an iRAM module;

[0009] Test_top module: This module is the top-level module of the simulation test, which is used to initialize the simulation clock reset, instantiate the functional modules, and initialize the mapping of the storage space;

[0010] The RISCV processor module is the control core of the simulation system;

[0011] Bus structure module: It acts as a bridge between the RISC-V processor module and the functional modules, and includes various types of bus structures; the functional modules include FLASH modules, peripheral units, and iRAM modules;

[0012] FLASH model: used for system startup loading, as a non-volatile storage structure, simulating the storage and loading process of the startup program;

[0013] Peripheral unit: contains various functional units of the system. After the system is loaded, different test programs are executed according to different test stimuli, corresponding to different peripheral modules;

[0014] iRAM module: Serves as a storage space for program instructions and is used for application storage and execution.

[0015] Furthermore, the FLASH model storage space is mapped to a one-dimensional array with a variable name of mem1, and read and write access to the FLASH model storage space is achieved through read and write access to the mem1 array; the iRAM module storage space is mapped to a one-dimensional array with a variable name of mem2, and read and write access to the iRAM module storage space is achieved through read and write access to the mem2 array.

[0016] Furthermore, in the test file, the definition correspondence between the storage space and the array is completed through the define instruction, and then the write operation of the program file to the array is completed through the read file command, thereby realizing the initialization operation of the storage space during the simulation process;

[0017] The instructions include:

[0018] `define mem1 test_top.RISCV.bus.FLASH.memory

[0019] `define mem2 test_top.RISCV.bus.iram.memory

[0020] Among them, test_top.RISCV.bus.FLASH.memory points to the FLASH model storage space, which is mapped to the mem1 array through macro definition; test_top.RISCV.bus.iram.memory points to the iRAM module storage space, which is mapped to the mem2 array through macro definition.

[0021] Furthermore, the FLASH model storage space stores the startup program, and the iRAM module storage space stores the application program. In the actual storage process, the startup program and the application program are pieced together to form program 3, and program 3 is stored in the FLASH model storage space and the iRAM module storage space at the same time. During execution, only the startup program part of program 3 is executed in the FLASH model storage space, and only the application program part of program 3 is executed in the iRAM module storage space.

[0022] Furthermore, the startup program in the FLASH model storage space starts execution from the address 0x0000_0000. The startup program includes the processor parameter configuration and the program jump address; the storage address of the application in the iRAM module storage space is consistent with the jump address, that is, the size and storage location of the startup program need to be determined so that it can accurately jump to the application storage segment in the iRAM during the program jump process.

[0023] The present invention provides a process program loading method for a RISC-V processor system, the method comprising the following steps:

[0024] S1. According to the code flow of the startup program, the jump address set at the end of the startup program is address X in the iRAM module storage space;

[0025] S2, simulation starts, completing the initialization of FLASH model storage space and iRAM module storage space;

[0026] S3. After the RISCV processor is reset, it reads the startup program from the address 0x0000_0000 in the FLASH model storage space and executes it. When the startup program is finished, it executes the jump instruction in the jump address and jumps to the address X in the iRAM module storage space to continue executing the application program.

[0027] S4. The startup program is fixed, and the application program is changed and replaced according to different simulation test requirements.

[0028] Furthermore, the jump address in step S1 is 0x0000_0050, and the content in the jump address is X=0x1000_0050, where the offset address 0x1000_0000 is the address allocated by the system for the iRAM module storage space, 0x50 is the address of the application in the program segment, and the size of the offset address 0x50 is the address space occupied by the startup program.

[0029] Furthermore, in step S2, the FLASH model storage space and the iRAM module storage space map the same program segment to the storage space, and the same program segment includes a startup program and an application program.

[0030] Furthermore, in step S3, when the RISCV processor executes to the address 0x0000_0050, the instruction at the address is an address jump instruction, that is, the program needs to jump, and the jump position is the address 0x1000_0050. After that, the program enters 0x1000_0050 to continue executing the application program.

[0031] Furthermore, in step S4, when the application is changed and replaced, the address X in the jump address is adjusted as needed.

[0032] (3) Beneficial effects

[0033] The present invention provides a simulation system and a process program loading method for a RISC-V processor system, which can realize a full-process simulation test starting from reset;

[0034] Since the present invention does not need to consider the problem of loss of storage space content during power failure, it can realize the storage of the same program segment in the off-chip non-volatile storage structure FLASH and the on-chip program storage structure iRAM;

[0035] The jump address in the startup program of the present invention can be flexibly modified according to actual needs. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 The hardware structure diagram of the simulation system based on RISCV processor of the present invention;

[0037] Figure 2 It is a sample diagram for program storage and execution;

[0038] Figure 3 Schematic diagram of program segment division in iRAM. DETAILED DESCRIPTION

[0039] In order to make the purpose, content and advantages of the present invention more clear, the specific implementation methods of the present invention are further described in detail below with reference to the accompanying drawings and examples.

[0040] The present invention establishes a memory access mapping relationship with a program storage model and an instruction storage module.

[0041] Memory access literally means access to storage; here it means: mapping the FLASH model storage space to a one-dimensional array with a variable name of mem1, and implementing read and write access to the FLASH model storage space by reading and writing access to the mem1 array. Similarly, mapping the iRAM module storage space to a one-dimensional array with a variable name of mem2, and implementing read and write access to the iRAM module storage space by reading and writing access to the mem2 array. In the FPGA prototype simulation verification stage, the usual practice for program initialization is to load init file, that is, to load the program file to the iRAM instruction storage space. This approach cannot fully simulate the actual application scenario, and the power-on startup function of FLASH cannot be simulated and tested. The memory access mapping method of the present invention can fully simulate the actual application environment, starting from powering on FLASH, running the startup program in FLASH, and then jumping to the application in iRAM through the startup program, and executing the application.

[0042] In the test file, the definition correspondence between the storage space and the array is completed through the define instruction, and then the write operation of the program file to the array is completed through the read file command, thereby realizing the initialization operation of the storage space memory during the simulation process.

[0043] The main instructions involved are:

[0044] `define mem1 test_top.RISCV.bus.FLASH.memory

[0045] `define mem2 test_top.RISCV.bus.iram.memory

[0046] Among them, test_top.RISCV.bus.FLASH.memory points to the FLASH model storage space, which is mapped to the mem1 array through macro definition; test_top.RISCV.bus.iram.memory points to the iRAM module storage space, which is mapped to the mem2 array through macro definition.

[0047] In this invention, the software program design includes a boot program and an application program. Generally, FLASH is a non-volatile memory that stores the boot program and persists during power outages. However, iRAM is volatile, and the program disappears when power is lost. The storage method of the boot program and application program, as well as the flexible jump during execution, are key inventions of this patent.

[0048] like Figure 2As shown in the figure, the startup program in the FLASH model storage space starts execution from the address 0x0000_0000. The startup program mainly contains the parameter configuration of the processor and the jump address of the program. The storage address of the application in the iRAM module storage space is consistent with the actual jump address. That is, the size and storage location of the startup program need to be determined so that when a program jump occurs, it can accurately jump to the application storage segment in the iRAM.

[0049] Among them, the startup program is stored in the FLASH model storage space, and the application is stored in the iRAM module storage space. In the actual storage process, the startup program and the application are pieced together to form program 3, and program 3 is stored in the FLASH model storage space and the iRAM module storage space at the same time. During execution, only the startup program part in program 3 is executed in the FLASH model storage space, and only the application part in program 3 is executed in the iRAM module storage space. The purpose of this is to store the same program in two storage spaces for easy processing.

[0050] In the simulation test, the Figure 1 The simulation system architecture shown includes: Test_top module, RISCV processor module, bus structure module, FLASH model, peripheral unit and iRAM module. The main functions and connection relationships of each module are as follows:

[0051] Test_top module: This module is the top-level module of the simulation test, which is used for initializing the simulation clock reset, instantiating the functional modules, initializing the mapping of the storage space, etc.

[0052] RISCV processor module: mainly includes RISCV processor unit module, which is the control core of the simulation system.

[0053] Bus structure module: It mainly acts as a bridge between the RISC-V processor module and the functional module, and includes various types of bus structures, collectively referred to as bus structure modules; functional modules include FLASH modules, peripheral units, and iRAM modules;

[0054] FLASH model: used for system startup loading. As a non-volatile storage structure, it mainly simulates the storage and loading process of the startup program.

[0055] Peripheral unit: Contains various functional units of the system. After the system is loaded, different test programs are executed according to different test stimuli, corresponding to different peripheral modules, collectively referred to as peripheral units.

[0056] iRAM module: As a storage space for program instructions, it is mainly used for application storage and execution.

[0057] The present invention relies on the above-mentioned hardware simulation test system to build a simulation test platform, and completes the simulation loading process based on the RISCV processor according to the following implementation method.

[0058] S1. According to the code flow of the startup program, the jump address set at the end of the startup program is as follows Figure 3 The address X in the iRAM module storage space, for example, the jump address is 0x0000_0050, and the content in the jump address is X=0x1000_0050, where the offset address 0x1000_0000 is the address allocated by the system for the iRAM module storage space, and 0x50 is the address of the application in the program segment. Here, the size of the offset address 0x50 is the size of the address space occupied by the startup program.

[0059] S2, simulation starts, completes the initialization of FLASH model storage space and iRAM module storage space; Figure 2 As shown, the same program segments are mapped to the storage space in FLASH.memory and iRAM.memory;

[0060] Among them, the startup program is executed in FLASH, and the application is executed in iRAM. In the actual storage process, the startup program and the application are pieced together to form Program 3, and Program 3 is stored in FLASH and iRAM at the same time. It is just storage. During execution, only the startup program part in Program 3 is executed in FLASH, and only the application part in Program 3 is executed in iRAM. The purpose of this is to store the same program in two storage spaces for easy processing.

[0061] S3. After the RISCV processor is reset, it first reads the startup program from the address 0x0000_0000 in the FLASH model storage space and executes it. When the startup program is finished, the jump instruction in the jump address is executed to jump to the address X in the iRAM module storage space to continue executing the application program. For example, when the address 0x0000_0050 is executed, the instruction at this address is an address jump instruction, that is, the program needs to jump to the address 0x1000_0050. After that, the program enters 0x1000_0050 to continue executing the application program.

[0062] S4. The startup program is fixed, and the application program can be changed or replaced according to different simulation test requirements, and the address X in the jump address can be adjusted as needed.

[0063] The present invention can realize the whole process simulation test starting from reset;

[0064] Since the present invention does not need to consider the problem of loss of storage space content during power failure, it can realize the storage of the same program segment in the off-chip non-volatile storage structure FLASH and the on-chip program storage structure iRAM;

[0065] The jump address in the startup program of the present invention can be flexibly modified according to actual needs.

[0066] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A simulation system for a RISC-V processor system, characterized in that: The system includes: Test_top module, RISCV processor module, bus structure module, FLASH module, peripheral unit and iRAM module; Test_top module: This module is the top-level module of the simulation test, which is used to initialize the simulation clock reset, instantiate the functional modules, and initialize the mapping of the storage space; The RISCV processor module is the control core of the simulation system; Bus structure module: It acts as a bridge between the RISC-V processor module and the functional modules, and includes various types of bus structures; the functional modules include the FLASH module, peripheral units, and iRAM modules; FLASH module: used for system startup loading, as a non-volatile storage structure, simulating the storage and loading process of the startup program; Peripheral unit: contains various functional units of the system. After the system is loaded, different test programs are executed according to different test stimuli, corresponding to different peripheral modules; iRAM module: serves as a storage space for program instructions, used for application storage and execution; in, The FLASH module storage space is mapped to a one-dimensional array with a variable name of mem1, and read and write access to the FLASH module storage space is achieved by reading and writing access to the mem1 array; the iRAM module storage space is mapped to a one-dimensional array with a variable name of mem2, and read and write access to the iRAM module storage space is achieved by reading and writing access to the mem2 array; The FLASH module storage space stores the startup program, and the iRAM module storage space stores the application program. In the actual storage process, the startup program and the application program are pieced together to form Program 3, which is stored in both the FLASH module storage space and the iRAM module storage space. During execution, only the startup program portion of Program 3 is executed in the FLASH module storage space, and only the application program portion of Program 3 is executed in the iRAM module storage space. The startup program in the FLASH module storage space starts execution from address 0x0000_0000. The startup program includes the processor parameter configuration and the program jump address. The storage address of the application in the iRAM module storage space must be consistent with the jump address. That is, the size and storage location of the startup program must be determined so that when a program jump occurs, it can accurately jump to the application storage segment in iRAM.

2. The simulation system of the RISCV processor system according to claim 1, wherein: In the test file, the definition correspondence between the storage space and the array is completed through the define instruction, and then the program file is written to the array through the read file command, thereby realizing the initialization operation of the storage space during the simulation process; The instructions include: `define mem1 test_top.RISCV.bus.FLASH.memory `define mem2 test_top.RISCV.bus.iram.memory Among them, test_top.RISCV.bus.FLASH.memory points to the FLASH module storage space, which is mapped to the mem1 array through macro definition; test_top.RISCV.bus.iram.memory points to the iRAM module storage space, which is mapped to the mem2 array through macro definition.

3. A process program loading method for a RISC-V processor system based on the system according to any one of claims 1 to 2, characterized in that: The method comprises the following steps: S1. According to the code flow of the startup program, the jump address set at the end of the startup program is address X in the iRAM module storage space; S2, simulation starts, completes the initialization of the FLASH module storage space and the iRAM module storage space; S3. After the RISCV processor is reset, it reads the startup program from the address 0x0000_0000 in the FLASH module storage space and executes it. When the startup program is finished, it executes the jump instruction in the jump address and jumps to the address X in the iRAM module storage space to continue executing the application program. S4. The startup program is fixed, and the application program is changed and replaced according to different simulation test requirements.

4. The process program loading method of the RISCV processor system according to claim 3, characterized in that: The jump address in step S1 is 0x0000_0050, and the content in the jump address is X=0x1000_0050, where the offset address 0x1000_0000 is the address allocated by the system for the iRAM module storage space, 0x50 is the address of the application in the program segment, and the size of the offset address 0x50 is the address space occupied by the startup program.

5. The process program loading method of the RISCV processor system according to claim 4, characterized in that: In step S2, the FLASH module storage space and the iRAM module storage space map the same program segment to the storage space, and the same program segment includes a startup program and an application program.

6. The process program loading method of the RISCV processor system according to claim 4, characterized in that: In step S3, when the RISC V processor executes to the address 0x0000_0050, the instruction at the address is an address jump instruction, that is, the program needs to jump, and the jump position is the address 0x1000_0050. After that, the program enters 0x1000_0050 to continue executing the application program.

7. The process program loading method of the RISCV processor system according to claim 3, characterized in that: In step S4, when the application is changed or replaced, the address X in the jump address is adjusted as needed.

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