A communication device using three SPIs instead of SSI multiple slaves

Abstract

The present invention relates to a communication device that uses three SPIs to replace multiple SSI slaves. The device comprises an SSI master and multiple SPI slaves that communicate with the SSI master. Each SPI slave includes a first SPI interface for data transmission, a second SPI interface for controlling the data transmission time of the first SPI interface, a third SPI interface for controlling the transmission and stopping of the first SPI interface, and a tri-state gate buffer for preventing data transmission conflicts between multiple slaves. Compared with the prior art, the present invention has the advantages of low implementation cost and preventing conflicts when multiple slaves transmit data simultaneously.

Description

Technical Field

[0001] The present invention relates to a communication device, in particular to a communication device which adopts three SPIs to replace SSI multiple slaves. Background Art

[0002] Serial communication is a common communication method in the field of modern electronic communications. Commonly used serial communication interfaces include SPI (Serial Peripheral Interface) interface and SSI (Synchronous Serial Interface) interface.

[0003] SSI is a full-duplex serial interface with a high communication speed, usually up to 2Mbps or above. Figure 1 As shown, the SSI protocol timing diagram is as follows Figure 2 shown.

[0004] SPI is also a full-duplex synchronous communication bus interface. The SPI multi-slave diagram is as follows: Figure 3 As shown, the SPI protocol timing diagram is as follows Figure 4 shown.

[0005] Current mainstream chips, such as the 51 series, STM32 series, and their domestic counterparts, do not support the SSI protocol. Due to their high communication speeds, IO port simulation is often not feasible. SSI-capable chips, such as Atmel's SAM4S series, are relatively rare and expensive. This limited chip selection limits availability and makes porting and switching platforms difficult.

[0006] Therefore, for master and slave devices, how to replace the expensive SSI with the relatively cheap SPI and realize SSI communication has become a technical problem that needs to be solved. Summary of the Invention

[0007] The purpose of the present invention is to overcome the defects of the above-mentioned prior art and provide a communication device that uses three SPIs instead of SSI multiple slaves.

[0008] The purpose of the present invention can be achieved by the following technical solutions:

[0009] According to one aspect of the present invention, a communication device is provided that uses three SPIs to replace multiple SSI slaves. The device includes an SSI master and multiple SPI slaves that communicate with the SSI master, wherein each SPI slave includes a first SPI interface for implementing data transmission, a second SPI interface for controlling the data transmission time of the first SPI interface, a third SPI interface for controlling the transmission and stopping of the first SPI interface, and a tri-state gate buffer for avoiding data transmission conflicts between multiple slaves.

[0010] As a preferred technical solution, the first SPI interface includes a first signal input pin SPI1 MOSI, a first signal output pin SPI1 MISO, a first clock signal input pin SPI1 Clock, and a control pin SPI1 CS.

[0011] As a preferred technical solution, the first signal input pin SPI1 MOSI is connected to the signal output interface Data Out of the SSI host; the first signal output pin SPI1 MISO is connected to the signal input interface Data In of the SSI host through a three-state gate buffer; and the first clock signal input pin SPI1 Clock is connected to the clock signal output interface SSI Clock of the SSI host.

[0012] As a preferred technical solution, the second SPI interface includes a second signal output pin SPI2 MISO and a second clock signal input pin SPI2 Clock, the second signal output pin SPI2 MISO is respectively connected to the control pin SPI1 CS and the control pin of the three-state gate buffer, and the second clock signal input pin SPI2 Clock is connected to the clock signal output interface SSI Clock of the SSI host.

[0013] As a preferred technical solution, the third SPI interface includes a frame synchronization signal receiving pin SPI3 CS and a third clock signal input pin SPI1 Clock. The frame synchronization signal receiving pin SPI3 CS is connected to the frame synchronization signal output interface Frame Sync of the SSI host, and the third clock signal input pin SPI1 Clock is connected to the clock signal output interface SSI Clock of the SSI host.

[0014] As a preferred technical solution, the frame synchronization signal receiving pin SPI3 CS is a receiving pin that can capture the pulse signal in the frame synchronization signal, which is used to capture the pulse signal in the frame synchronization signal, so that the third SPI interface tracks the frame synchronization signal, and then controls the transmission and stop of the first SPI interface through the third SPI interface.

[0015] As a preferred technical solution, the input pin of the tri-state gate buffer is connected to the first signal output pin SPI1MISO, and the output pin of the tri-state gate buffer is connected to the signal input interface Data In of the SSI host.

[0016] As a preferred technical solution, the third SPI interface is an SPI that supports TI mode, and the first SPI interface and the second SPI interface are universal SPIs.

[0017] As a preferred technical solution, the first SPI interface is an SPI using a DMA transmission mode.

[0018] As a preferred technical solution, the first SPI interface is an SPI using an interrupt or blocking transmission mode.

[0019] Compared with the prior art, the present invention has the following advantages:

[0020] 1) Compared with using a dedicated SSI chip, the present invention only needs to add 4 interfaces and 1 three-state gate device to achieve the same effect as SSI communication. For most chips, there are many interface resources, and adding 4 interfaces is much more convenient than replacing the chip.

[0021] 2) The tri-state gate buffer prevents data conflicts between multiple slaves when sending data simultaneously. The device is small, measuring only 2.4mm by 2.15mm, and typically costs less than 2 yuan, making it cost-effective. It is also a universal device, making it easy to purchase and replace.

[0022] 3) The SPI supporting TI mode usually transmits data with a length not exceeding 32 bits BITS and cannot support SSI protocol data with a longer data length. The present invention combines one SPI supporting TI mode with two general SPIs to customize the data reception length and be compatible with various situations in the SSI protocol. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 This is a schematic diagram of existing SSI multi-slave hardware;

[0024] Figure 2 This is the SSI protocol signal timing diagram;

[0025] Figure 3 This is a schematic diagram of SPI multiple slaves;

[0026] Figure 4 SPI protocol signal timing diagram

[0027] Figure 5 It is a structural schematic diagram of the present invention;

[0028] Figure 6 It is a specific circuit diagram of the present invention. DETAILED DESCRIPTION

[0029] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0030] like Figure 5 and 6 As shown, the present invention discloses a communication device that uses three SPIs to replace SSI multiple slaves. The device includes an SSI master and multiple SPI slaves that communicate with the SSI master. Each SPI slave includes a first SPI interface SPI1 for data transmission, a second SPI interface SPI2 for controlling the data transmission time of the first SPI interface, a third SPI interface SPI3 for controlling the transmission and stopping of the first SPI interface, and a tri-state gate buffer for preventing data conflicts between multiple slaves. The present invention combines the three SPIs, using a single SPI3 supporting TI (Texas Instruments) mode to provide frame synchronization, SPI1 for data transmission, SPI2 for controlling SPI1 transmission, and a tri-state gate buffer to prevent data conflicts between multiple slaves. This achieves a communication mode in which SPI replaces SSI multiple slaves.

[0031] The first SPI interface includes a first signal input pin SPI1 MOSI, a first signal output pin SPI1 MISO, a first clock signal input pin SPI1 Clock, and a control pin SPI1 CS. The first signal input pin SPI1 MOSI is connected to the signal output interface Data Out of the SSI host; the first signal output pin SPI1 MISO is connected to the signal input interface Data In of the SSI host via a tri-state gate buffer; and the first clock signal input pin SPI1 Clock is connected to the clock signal output interface SSI Clock of the SSI host.

[0032] The second SPI interface includes a second signal output pin SPI2 MISO and a second clock signal input pin SPI2 Clock. The second signal output pin SPI2 MISO is respectively connected to the control pin SPI1 CS and the control pin of the three-state gate buffer, and the second clock signal input pin SPI2 Clock is connected to the clock signal output interface SSIClock of the SSI host.

[0033] The third SPI interface includes a frame synchronization signal receiving pin SPI3 CS and a third clock signal input pin SPI1 Clock. The frame synchronization signal receiving pin SPI3 CS is connected to the frame synchronization signal output interface FrameSync of the SSI host, and the third clock signal input pin SPI1 Clock is connected to the clock signal output interface SSIClock of the SSI host. The frame synchronization signal receiving pin SPI3 CS is a receiving pin that can capture pulse signals in the frame synchronization signal. This is used to capture pulse signals in the frame synchronization signal, allowing the third SPI interface to track the frame synchronization signal, and then controlling the transmission and stopping of the first SPI interface through the third SPI interface. The input pin of the tri-state gate buffer is connected to the first signal output pin SPI1 MISO, and the output pin of the tri-state gate buffer is connected to the signal input interface Data In of the SSI host.

[0034] The data sending process of the present invention is as follows:

[0035] The SSI protocol clock signal is sent to the SPI1 clock, SPI2 clock, and SPI3 clock of each slave device. The SSI protocol frame synchronization signal is sent to the SPI3 CS pin of each slave device. SPI3, which supports TI mode, captures the pulse signal in the frame synchronization signal, allowing SPI3 to track the frame synchronization signal. SPI3 then controls the transmission and stopping of SPI1, ensuring slave synchronization. The SSI protocol data output signal is sent to the SPI1 MOSI pin of each slave device, and the SPI1 MISO pin is connected to the input pin of a tri-state buffer, allowing data communication through SPI1. The SSI protocol data input signal is connected to the output of the tri-state buffer of each slave device. The SPI2 MISO pin of each slave device outputs the control signal corresponding to the corresponding slave time slot, which is sent to the SPI1 CS pin and the control pin of the tri-state buffer. This controls the data transmission timing of SPI1 and avoids data conflicts between different slaves.

[0036] The third SPI interface is an SPI that supports TI mode, and the first and second SPI interfaces are universal SPIs. An SPI that supports TI mode typically transmits data with a length not exceeding 32 bits and cannot support SSI protocol data with a longer data length. By combining one SPI that supports TI mode with two universal SPIs, the present invention can customize the data reception length and is compatible with various situations in the SSI protocol.

[0037] The first SPI interface uses SPI in DMA transfer mode. This not only reduces CPU resource usage but also enables continuous clock output. DMA can operate in either single-shot (Normal) or circular (Circular) modes. In single-shot mode, the DMA interface is re-enabled after each interrupt, while in circular mode, re-enabling is not required.

[0038] In another embodiment, the SPI in the present invention is not limited to the DMA transmission mode, and may also adopt an interrupt or blocking transmission mode.

[0039] The present invention can use common chips such as ST (STMicroelectronics), GD (GigaDevice), SH (SinoWing Electronics), and 51 single-chip microcomputers that support SPI communication. This eliminates the need for the chip to support the SSI communication protocol, greatly reducing development and transplantation costs, significantly increasing selectivity, and making the price more affordable. Currently, chips are in short supply on the international market, and choosing domestically produced chips makes them easier to obtain and can also significantly reduce costs. The SPI protocol is partially similar to the SSI protocol, so it cannot be directly replaced. However, after the improvement of the present invention, SPI can be used to replace the SSI protocol for communication.

[0040] like Figure 6 As shown, the communication device further includes an MCU connected to the first SPI interface SPI1, the second SPI interface SP2 and the third SPI interface respectively. The MCU is also connected to a power supply circuit and a crystal oscillator circuit, etc.

[0041] Explanation of terms specific to the present invention

[0042] SSI (Synchronous Serial Interface);

[0043] SPI (Serial Peripheral Interface);

[0044] DMA (Direct Memory Access);

[0045] CS (Chip Select from device);

[0046] MISO (slave device data output);

[0047] MOSI (slave data input);

[0048] NSS (Negative Slave Select);

[0049] Frame Sync (frame synchronization signal);

[0050] TI (Texas Instruments).

[0051] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and such modifications or substitutions are intended to be within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope of protection of the claims.

Claims

1. A communication device using three SPIs instead of SSI multiple slaves, characterized in that: The invention comprises an SSI host and a plurality of SPI slaves respectively communicating with the SSI host, wherein each SPI slave comprises a first SPI interface for realizing data transmission, a second SPI interface for controlling the data transmission time of the first SPI interface, a third SPI interface for controlling the transmission and stop of the first SPI interface, and a tri-state gate buffer for avoiding data transmission conflicts among multiple slaves; The first SPI interface includes a first signal input pin SPI1 MOSI, a first signal output pin SPI1 MISO, a first clock signal input pin SPI1 Clock and a control pin SPI1 CS; The second SPI interface includes a second signal output pin SPI2 MISO and a second clock signal input pin SPI2Clock, the second signal output pin SPI2 MISO is respectively connected to the control pin SPI1 CS and the control pin of the tri-state gate buffer, and the second clock signal input pin SPI2 Clock is connected to the clock signal output interface SSIClock of the SSI host; The third SPI interface includes a frame synchronization signal receiving pin SPI3 CS and a third clock signal input pin SPI3Clock, wherein the frame synchronization signal receiving pin SPI3 CS is connected to the frame synchronization signal output interface Frame Sync of the SSI host, and the third clock signal input pin SPI3 Clock is connected to the clock signal output interface SSI Clock of the SSI host; The clock signal of the SSI protocol is sent to the SPI1 Clock, SPI2 Clock and SPI3 Clock of each slave device; the frame synchronization signal of the SSI protocol is sent to the SPI3 CS of each slave device; the pulse signal in the frame synchronization signal is captured by SPI3 supporting TI mode, so that SPI3 can track the frame synchronization signal, and then the transmission and stop of SPI1 are controlled by SPI3 to ensure the synchronization of the slave devices; the data output signal of the SSI protocol is sent to the SPI1 MOSI of each slave device, and SPI1 MISO is connected to the input pin of the three-state gate buffer. Data communication is carried out through SPI1, and the data input signal of the SSI protocol is connected to the output end of the three-state gate buffer of each slave device. The SPI2 MISO of each slave device outputs the control signal of the corresponding time slot of different slave devices, which is sent to the SPI1 CS and the control pin of the three-state gate buffer to control the data sending time of SPI1 and avoid data sending conflicts between different slave devices.

2. A communication device using three SPIs instead of SSI multiple slaves according to claim 1, characterized in that: The first signal input pin SPI1 MOSI is connected to the signal output interface Data Out of the SSI host; the first signal output pin SPI1 MISO is connected to the signal input interface Data In of the SSI host through a three-state gate buffer; the first clock signal input pin SPI1 Clock is connected to the clock signal output interface SSI Clock of the SSI host.

3. A communication device using three SPIs instead of SSI multiple slaves according to claim 1, characterized in that: The frame synchronization signal receiving pin SPI3 CS is a receiving pin that can capture the pulse signal in the frame synchronization signal, and is used to capture the pulse signal in the frame synchronization signal, so that the third SPI interface tracks the frame synchronization signal, and then controls the transmission and stop of the first SPI interface through the third SPI interface.

4. A communication device using three SPIs instead of SSI multiple slaves according to claim 1, characterized in that: The input pin of the tri-state gate buffer is connected to the first signal output pin SPI1 MISO, and the output pin of the tri-state gate buffer is connected to the signal input interface Data In of the SSI host.

5. The communication device according to claim 1, wherein the communication device adopts three SPIs instead of SSI multiple slaves, The third SPI interface is an SPI supporting TI mode, and the first SPI interface and the second SPI interface are general SPIs.

6. The communication device according to claim 1, wherein the communication device adopts three SPIs instead of SSI multiple slaves, The first SPI interface is an SPI using a DMA transmission mode.

7. The communication device according to claim 1, wherein the device adopts three SPIs to replace the SSI multi-slave. The first SPI interface is an SPI that adopts an interrupt or blocking transmission mode.

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