Semiconductor element and method for manufacturing the same

Abstract

A semiconductor device and a method for fabricating the same are disclosed. The method for fabricating the semiconductor device includes forming a metal gate on a substrate, a spacer around the metal gate, and a first interlayer dielectric layer around the spacer, performing a plasma treatment process to convert the spacer into a first lower half and a first upper half, performing a cleaning process to remove the first upper half, and forming a second interlayer dielectric layer on the metal gate and the first interlayer dielectric layer.

Description

Technical Field

[0001] This invention relates to a method for manufacturing semiconductor devices, and more particularly to a method for manufacturing metal gate transistors. Background Technology

[0002] In the current semiconductor industry, polysilicon is widely used in semiconductor devices such as metal-oxide-semiconductor (MOS) transistors as the standard gate fill material. However, as the size of MOS transistors continues to shrink, traditional polysilicon gates suffer from problems such as reduced device performance due to the boron penetration effect and the unavoidable depletion effect. This leads to an increase in the equivalent gate dielectric layer thickness, a decrease in gate capacitance, and consequently, a decline in device drive capability. Therefore, the semiconductor industry is exploring new gate fill materials, such as work function metals, to replace traditional polysilicon gates as control electrodes to match high-k gate dielectric layers.

[0003] However, in current metal gate transistor fabrication processes, the removal of the polysilicon gate material layer may simultaneously remove some adjacent spacer walls, contact hole etch stop layers, and even parts of the interlayer dielectric layer. This can cause short circuits between the subsequently filled work function metal layer and low impedance metal layer, as well as the contact plugs on both sides, affecting device performance. Therefore, improving current fabrication processes to solve these problems is an important current research topic. Summary of the Invention

[0004] This invention discloses a method for fabricating a semiconductor device. First, a metal gate is formed on a substrate, a spacer surrounds the metal gate, and a first interlayer dielectric layer surrounds the spacer. Then, a plasma processing process is performed to convert the spacer into a first lower half and a first upper half. A cleaning process is then performed to remove the first upper half. Finally, a second interlayer dielectric layer is formed on the metal gate and the first interlayer dielectric layer.

[0005] Another embodiment of the present invention discloses a semiconductor device, which mainly includes a metal gate disposed on a substrate, a spacer surrounding the metal gate, a source / drain region disposed next to the spacer, and a contact hole etch stop layer surrounding the spacer, wherein the spacer and the contact hole etch stop layer have different heights. Attached Figure Description

[0006] Figures 1 to 7 This is a schematic diagram of a method for fabricating a semiconductor device according to an embodiment of the present invention.

[0007] Explanation of main component symbols

[0008] 12: Base

[0009] 14: Fin-like structure

[0010] 16: Gate Structure

[0011] 18: Gate dielectric layer

[0012] 20: Gate material layer

[0013] 22: Spacer wall

[0014] 24: Source / Drain Region

[0015] 26: Misaligned spacer wall

[0016] 28: Main spacer wall

[0017] 30: Contact hole etching stop layer

[0018] 32: Interlayer dielectric layer

[0019] 34: Groove

[0020] 36: Groove

[0021] 38: Dielectric layer

[0022] 40: High dielectric constant dielectric layer

[0023] 42: Work function metal layer

[0024] 44: Low-resistivity metal layer

[0025] 46: Metal gate

[0026] 48: Plasma processing technology

[0027] 50: Part 1 (Second Half)

[0028] 52: First Half

[0029] 54: Second half

[0030] 56: Part Two (First Half)

[0031] 58: Dielectric section

[0032] 60: Groove

[0033] 62: Interlayer dielectric layer

[0034] 64: Contact plug

[0035] 66: Second Half

[0036] 68: Upper Half Detailed Implementation

[0037] Please refer to Figures 1 to 7 , Figures 1 to 7 This is a schematic diagram illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention. Figure 1 As shown, a substrate 12, such as a silicon substrate or a silicon-on-insulator (SOI) substrate, is first provided, on which a transistor region, such as a PMOS transistor region or an NMOS transistor region, can be defined. The substrate 12 has at least one fin structure 14 and an insulating layer (not shown), wherein the bottom of the fin structure 14 is covered by the insulating layer, such as silicon oxide, to form a shallow trench isolation. It should be noted that although this embodiment uses the fabrication of a non-planar field-effect transistor, such as a fin structure field-effect transistor, as an example, it is not limited thereto. The present invention can also be applied to general planar field-effect transistors, and this embodiment is also within the scope of the present invention.

[0038] According to one embodiment of the present invention, the fin structure 14 is preferably fabricated using sidewall image transfer (SIT) technology. The procedure generally includes: providing a layout pattern to a computer system and performing appropriate calculations to define the corresponding pattern in a photomask. Subsequently, multiple equidistant and equally wide patterned sacrificial layers are formed on the substrate using photolithography and etching processes, giving each layer a strip-like appearance. Then, deposition and etching processes are sequentially performed to form spacers on the sidewalls of the patterned sacrificial layers. The patterned sacrificial layers are then removed, and etching is performed under the cover of the spacers, transferring the pattern formed by the spacers into the substrate. Finally, a fin cut process is performed to obtain the desired patterned structure, such as a strip-shaped patterned fin structure.

[0039] In addition, the formation of the fin structure 14 may also include first forming a patterned mask (not shown) on the substrate 12, and then transferring the pattern of the patterned mask to the substrate 12 through an etching process to form the fin structure. Alternatively, the fin structure may be formed by first forming a patterned hard mask layer (not shown) on the substrate 12, and then using an epitaxial fabrication process to grow a semiconductor layer, such as silicon-germanium, on the substrate 12 exposed above the patterned hard mask layer. This semiconductor layer can then serve as the corresponding fin structure. These embodiments of forming fin structures are all within the scope of this invention.

[0040] Next, at least one gate structure 16 or a dummy gate can be formed on the substrate 12. In this embodiment, the gate structure 16 can be fabricated according to the fabrication process requirements, such as a gate-first fabrication process, a high-k-first fabrication process for gate-last fabrication, or a high-k-last fabrication process for gate-last fabrication. Taking the high-k-last fabrication process of this embodiment as an example, a gate dielectric layer or dielectric layer, a gate material layer composed of polysilicon, and a selective hard mask can be formed sequentially on the substrate 12. A patterned photoresist (not shown) is used as a mask to perform a pattern transfer fabrication process. In a single etching or successive etching step, part of the gate material layer and part of the gate dielectric layer are removed. Then, the patterned photoresist is stripped to form a gate structure 16 composed of a patterned gate dielectric layer 18 and a patterned gate material layer 20 on the substrate 12.

[0041] Then, at least one spacer wall 22 is formed on the sidewall of the gate structure 16. Next, a source / drain region 24 and / or an epitaxial layer (not shown) are formed in the fin structure 14 and / or the substrate 12 on both sides of the spacer wall 22. Selectively, a metal silicide (not shown) is formed on the surface of the source / drain region 24 and / or the epitaxial layer. In this embodiment, the spacer wall 22 can be a single spacer wall or a composite spacer wall, for example, it may include a bias spacer wall 26 and a main spacer wall 28. The bias spacer wall 26 and the main spacer wall 28 may contain the same or different materials. In this embodiment, the bias spacer wall 26 preferably contains silicon carbide, but both can be selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide. The source / drain region 24 may contain different dopants depending on the conductivity type of the transistor being disposed, for example, it may contain P-type dopants or N-type dopants.

[0042] Then as Figure 2 As shown, a contact hole etch stop layer 30 is first formed on the surface of the substrate 12 and the gate structure 16, and then an interlayer dielectric layer 32 is formed on the contact hole etch stop layer 30. Then a planarization process is performed, for example, by using chemical mechanical polishing (CMP) to remove part of the interlayer dielectric layer 32, part of the contact hole etch stop layer 30, and even part of the spacer 22 and part of the gate material layer 20, exposing the gate material layer 20 made of polysilicon, so that the upper surface of each gate material layer 20 is flush with the upper surface of the interlayer dielectric layer 32.

[0043] like Figure 3As shown, a metal gate replacement fabrication process is then performed to convert the gate structure 16 into a metal gate. For example, a selective dry etching or wet etching process can be performed first, such as using an etching solution such as ammonia (NH4OH) or tetramethylammonium hydroxide (TMAH) to remove the gate material layer 20 and even the gate dielectric layer 18 in the gate structure 16, so as to form grooves 34 and 36 in the interlayer dielectric layer 32.

[0044] It is worth noting that the etching process performed in this stage preferably removes part of the spacer wall 22, part of the contact hole etch stop layer 30, and even part of the interlayer dielectric layer 32 while removing all the gate material layer 20 to form grooves 34 and 36. The larger groove 34 preferably exposes the surface of the substrate 12, while the grooves on both sides expose the remaining spacer wall 22 and the contact hole etch stop layer 30. In addition, when removing the spacer wall 22 and the contact hole etch stop layer 30 by etching in this stage, it is preferable to remove less spacer wall 22 and more contact hole etch stop layer 30 due to the different selectivity of the two. This makes the groove 36 directly above the remaining contact hole etch stop layer 30 slightly deeper than the groove 36 directly above the remaining spacer wall 22. Alternatively, from another perspective, the top of the remaining contact hole etch stop layer 30 is preferably slightly lower than the top of the remaining spacer wall 22 after etching.

[0045] like Figure 4 As shown, a selective dielectric layer 38 or a gate dielectric layer, a high dielectric constant dielectric layer 40, a work function metal layer 42, and a low impedance metal layer 44 are then sequentially formed in the recesses 34 and 36. A planarization process is then performed, for example, by using CMP to remove part of the low impedance metal layer 44 to form the metal gate 46. It should be noted that the high dielectric constant dielectric layer 40, work function metal layer 42, and low impedance metal layer 44 formed in this stage are preferably filled simultaneously in both recesses 34 and 36, completely filling them; that is, both recesses 34 and 36 contain the same material.

[0046] In this embodiment, the high dielectric constant dielectric layer 40 comprises a dielectric material with a dielectric constant greater than 4, such as hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), zirconium oxide (ZrO2), strontium titanate oxide (SrTiO3), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO4), and strontium bismuth tantalum oxide. lead zirconate titanate (SrBi₂Ta₂O₉, SBT) and lead zirconate titanate (PbZr) x Ti 1-x O3, PZT), barium strontium titanate (Ba x Sr 1- x The group consisting of TiO3, BST, or combinations thereof.

[0047] The work function metal layer 42 is preferably used to adjust the work function of the metal gate to make it suitable for N-type transistors (NMOS) or P-type transistors (PMOS). If the transistor is an N-type transistor, the work function metal layer 42 can be made of a metal material with a work function of 3.9 electron volts (eV) to 4.3 eV, such as titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl), hafnium aluminide (HfAl), or TiAlC (titanium aluminum carbide), but is not limited thereto; if the transistor is a P-type transistor, the work function metal layer 42 can be made of a metal material with a work function of 4.8 eV to 5.2 eV, such as titanium nitride (TiN), tantalum nitride (TaN), or tantalum carbide (TaC), but is not limited thereto. Another barrier layer (not shown) may be included between the work function metal layer 42 and the low impedance metal layer 44. The barrier layer may be made of materials such as titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN). The low impedance metal layer 44 may be selected from low-resistance materials such as copper (Cu), aluminum (Al), tungsten (W), titanium-aluminum alloy (TiAl), cobalt-tungsten phosphide (CoWP), or combinations thereof. Since converting a dummy gate into a metal gate using a metal gate replacement fabrication process is a well-known technique in this field, it will not be elaborated upon here.

[0048] like Figure 5 As shown, a plasma processing fabrication process 48 is then performed to transform the spacer wall 22 into a first lower half 50 and a first upper half 52, and simultaneously transform the contact hole etch stop layer 30 into a second lower half 54 and a second upper half 56. More specifically, the plasma processing fabrication process 48 performed in this stage preferably introduces a reactive gas, such as nitrous oxide (N2O), to react with the conductive material directly above the spacer wall 22 and the contact hole etch stop layer 30, as well as the top of the spacer wall 22 and the contact hole etch stop layer 30. This transforms the conductive material directly above the spacer wall 22 and the contact hole etch stop layer 30, including a low-resistivity metal layer 44 and a work function metal layer 42 made of aluminum, into a dielectric portion 58 mainly composed of aluminum oxide (Al2O3). At the same time, the spacer wall 22 is transformed into two parts, including a first lower half 50 located below and a first upper half 52 located above, and the contact hole etch stop layer 30 is also transformed into two parts, including a second lower half 54 located below and a second upper half 56 located above.

[0049] In this embodiment, the first upper half 52 is preferably converted to silicon carbide oxynitride (SiCON) through a plasma processing process, the first lower half 50 is still composed of silicon carbide, the second upper half 56 is preferably converted to silicon oxynitride (SiON) through a plasma processing process, and the second lower half 54 is still composed of silicon nitride. Since the upper halves of the spacer wall 22 and the contact hole etch stop layer 30 have reacted with oxygen-containing gas during the aforementioned plasma processing process 48, the oxygen concentration of the lower halves of the spacer wall 22 and the contact hole etch stop layer 30 is preferably lower than that of the upper halves. For example, the oxygen concentration of the first lower half 50 is lower than that of the first upper half 52, and the oxygen concentration of the second lower half 54 is lower than that of the second upper half 56. Structurally, the top surface of the second lower half 54 formed in this stage is preferably slightly lower than the top surface of the first lower half 50, the top surface of the second upper half 56 is slightly lower than the top surface of the first upper half 52, and the bottom surface of the dielectric part 58 located directly above the second upper half 56 is also slightly lower than the bottom surface of the dielectric part 58 located directly above the first upper half 52.

[0050] like Figure 6 As shown, a cleaning process is then performed to remove the dielectric portion 58, the first upper portion 52, and the second upper portion 56 to form a groove 60. More specifically, the cleaning process performed in this stage preferably uses a diluted hydrofluoric acid (dHF) of approximately between 10:1 and 100:1 to remove all dielectric portions 58 and all of the first upper portion 52 and the second upper portion 56 to form a groove 60 that exposes the underlying first lower portion 50 and the second lower portion 54.

[0051] Subsequently, as Figure 7 As shown, another interlayer dielectric layer 62 is formed on the metal gate 46 and the interlayer dielectric layer 32, filling the groove 60. A pattern transfer fabrication process can then be performed, for example, using a patterned mask to remove a portion of the interlayer dielectric layer 62 next to the metal gate 46 and a portion of the contact hole etching stop layer 30 to form multiple contact holes (not shown) and expose the underlying source / drain regions 24. Then, the desired metal material is filled into each contact hole, such as a barrier layer material including titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc., and a low-resistance metal layer selected from low-resistance materials such as tungsten (W), copper (Cu), aluminum (Al), titanium-aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), or combinations thereof. A planarization fabrication process is then performed, for example, by chemical mechanical polishing to remove some of the metal material to form contact plugs 64 in each contact hole, electrically connecting the source / drain regions 24. This completes the fabrication of a semiconductor element according to an embodiment of the present invention.

[0052] Please refer to again Figure 7 , Figure 7 A schematic diagram of the structure of a semiconductor device according to an embodiment of the present invention is also disclosed. For example... Figure 7 As shown, the semiconductor device mainly includes at least one metal gate 46 disposed on the substrate 12, a spacer 22 surrounding the metal gate 46, a source / drain region 24 disposed next to the spacer 22, a contact hole etch stop layer 30 surrounding the spacer 22, an interlayer dielectric layer 32 surrounding the contact hole etch stop layer 30, and another interlayer dielectric layer 62 disposed on the metal gate 46 and the interlayer dielectric layer 32.

[0053] In detail, the spacer wall 22 and the contact hole etch stop layer 30 preferably have different heights. The top surface of the contact hole etch stop layer 30 is lower than the top surface of the spacer wall 22, the top surface of the contact hole etch stop layer 30 is lower than the top surface of the metal gate 46, and the top surface of the spacer wall 22 is lower than the top surface of the metal gate 46. Furthermore, the interlayer dielectric layer 62 further includes a lower half 66 disposed between the metal gate 46 and the interlayer dielectric layer 32 and an upper half 68 disposed on the metal gate 46. The lower half 66 contacts the spacer wall 22 and the contact hole etch stop layer 30, and the bottom surface of the lower half 66 that contacts the contact hole etch stop layer 30 is lower than the bottom surface of the lower half 66 that contacts the spacer wall 22.

[0054] Generally, current metal gate replacement fabrication processes may simultaneously remove some adjacent spacer walls, contact hole etch stop layers, and even some interlayer dielectric layers when hollowing out the gate material layer composed of polysilicon, forming a groove extending directly above the source / drain region. This causes the subsequent filling of conductive materials such as work function metal layers and low impedance metal layers into the groove to form an expanded metal gate, which not only easily leads to short circuits with the contact plugs on both sides but also reduces yield. To improve this problem, this invention mainly performs a plasma processing process after the metal gate is formed to convert the conductive material extending directly above the spacer walls and contact hole etch stop layers into dielectric material. Then, a cleaning process is used to completely remove the dielectric material and fill it with the upper interlayer dielectric layer. This avoids the excess low impedance metal layer and work function metal layer in the expanded metal gate from short-circuiting with the contact plugs on both sides and affecting device performance.

[0055] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, Include: A metal gate is formed on the substrate, a spacer surrounds the metal gate, a contact hole etch stop layer surrounds the spacer, and a first interlayer dielectric layer surrounds the contact hole etch stop layer; The plasma processing fabrication process converts the conductive material extending outward from the gap wall and directly above the contact hole etch stop layer into a dielectric part, converts the gap wall into a first lower half and a first upper half, and converts the contact hole etch stop layer into a second lower half and a second upper half. The dielectric portion, the first upper half, and the second upper half are removed by a cleaning process to form a third groove; as well as A second interlayer dielectric layer is formed on the metal gate and the first interlayer dielectric layer, as well as in the third groove.

2. The method of claim 1, further comprising: A gate structure is formed on the substrate, the gate structure comprising a gate material layer; The gap wall is formed next to the gate structure; A source / drain region is formed next to the gap wall; Remove the gate material layer and the spacer wall to form the first groove and the second groove; A functional metal layer is formed in the first groove and the second groove; A low-impedance metal layer is formed on the work function metal layer; as well as The low-impedance metal layer and the work function metal layer are planarized to form the metal gate.

3. The method of claim 2, further comprising removing the gap wall and the contact hole etching stop layer to form the second groove.

4. The method of claim 2, further comprising removing the gap wall, the contact hole etch stop layer, and the first interlayer dielectric layer to form the second groove.

5. The method of claim 1, wherein the second lower half top surface is lower than the first lower half top surface.

6. The method of claim 1, wherein the oxygen concentration of the second lower half is lower than the oxygen concentration of the second upper half.

7. The method of claim 1, wherein the oxygen concentration in the first lower half is lower than the oxygen concentration in the first upper half.

8. The method of claim 1, wherein the plasma treatment process comprises nitrous oxide.

9. A semiconductor device manufactured by the method according to any one of claims 1-8, characterized in that, Include: A metal gate is disposed on a substrate; Spacer walls surround the metal gate; The source / drain region is located beside the gap wall; and A contact hole etch stop layer surrounds the gap wall, wherein the gap wall and the contact hole etch stop layer have different heights, and the top surface of the gap wall that directly contacts the contact hole etch stop layer and the metal gate is lower than the top surface of the metal gate and higher than the top surface of the contact hole etch stop layer.

10. The semiconductor device of claim 9, wherein the top surface of the contact hole etch stop layer is lower than the top surface of the metal gate.

11. The semiconductor device of claim 9, further comprising: The first interlayer dielectric layer, the etch stop layer surrounding the contact hole; and The second interlayer dielectric layer is disposed on the metal gate and the first interlayer dielectric layer.

12. The semiconductor device of claim 9, wherein the second interlayer dielectric layer comprises: The lower half is disposed between the metal gate and the first interlayer dielectric layer; and The upper part is located on the metal gate.

13. The semiconductor element of claim 12, wherein the lower half contacts the gap wall.

14. The semiconductor device of claim 12, wherein the lower half contacts the contact hole etch stop layer.

15. The semiconductor device of claim 12, wherein the lower half bottom surface of the contact hole etch stop layer is lower than the lower half bottom surface of the contact gap wall.

Images