A method for generating S-boxes with optimal algebraic immunity and high nonlinearity

Abstract

This invention discloses an S-box generation method with optimal algebraic immunity and high nonlinearity, belonging to the field of cryptography. The invention comprises: a control signal register receiving and storing control signals from a nonlinear transformation controller; an information memory receiving and storing 8 bits of information to be processed; an expansion transformer expanding and transforming the information to be processed into 12 bits; a segmenter segmenting it into 6-bit groups LT and RT; the nonlinear transformation controller reading its control signal from the control signal register; if the signal is 1, the control sequence LT enters nonlinear transformation unit 1, and the sequence RT enters nonlinear transformation unit 2; if the signal is 0, the opposite occurs; a connector connecting the output sequences of nonlinear transformation units 1 and 2 yields the information output Y, which is stored in the information memory. This invention, while ensuring optimal algebraic immunity, high nonlinearity, and balance of the S-box, increases the difficulty of deciphering encrypted information by thoroughly obfuscating the plaintext.

Description

Technical Field

[0001] This invention belongs to the field of modern cryptography, and in particular relates to a method for generating S-boxes with optimal algebraic immunity, high nonlinearity, and balance. Background Technology

[0002] Block ciphers are the mainstream algorithms for data encryption. The first well-known block cipher algorithm was the DES algorithm, a data encryption standard published by the National Institute of Standards and Technology (NIST) in 1977. The DES algorithm uses the classic Feistel network structure and obtains its output after 16 rounds of iteration. The DES key length is 64 bits, but its effective length is 56 bits. With the continuous improvement of computer processing power and cryptanalysis techniques, the security of DES faced serious challenges in the early 1990s. In 1998, NIST launched a new round of data encryption standard solicitation. After three rounds of selection, the Rijindal algorithm designed by a Belgian was finally selected in 2003 as the new data encryption standard, namely the Advanced Encryption Standard (AES).

[0003] Block cipher design and analysis are two research directions that are both contradictory and interdependent. The S-box is the only non-linear component in a block cipher algorithm, and it largely determines the security strength of the algorithm. Therefore, the design and analysis of S-boxes has always been an important research topic in block ciphers.

[0004] The S-box is the most crucial non-linear component of a cryptographic algorithm, and its security largely determines the algorithm's overall security strength. Essentially, the S-box can be viewed as a mapping S(x) = (f1(x), ..., f...). i (x),…,f m (x)): S(x) is usually simply referred to as an n×m S-box. When the parameters and their values ​​are large, it complicates the design of the S-box and increases the storage requirements of the algorithm. Currently, the 8×8 S-box is more popular. Metrics for evaluating the cryptographic properties of an S-box include nonlinearity, algebraic immunity, and differential uniformity. Each metric corresponds to the S-box's ability to resist a particular cryptographic attack method. For linear analysis, a higher nonlinearity of the S-box is better; differential uniformity, introduced for differential cryptanalysis, measures the ability of a cryptographic function to resist differential cryptanalysis. Summary of the Invention

[0005] This invention provides an S-box generation method with optimal algebraic immunity and high nonlinearity, wherein the generated S-box has high nonlinearity and excellent algebraic immunity.

[0006] The technical solution adopted in this invention is as follows:

[0007] A method for generating S-boxes with optimal algebraic immunity and high nonlinearity, comprising the following steps:

[0008] Step 1: The control signal register receives and stores the control signal from the nonlinear converter controller, and the information memory receives and stores the information X to be processed, wherein the length of information X is 8 bits.

[0009] Step 2: The expansion converter reads information X from the information memory and expands and transforms it into 12-bit information;

[0010] Step 3: The splitter splits the 12-bit information output by the extended converter into two 6-bit groups, LT and RT.

[0011] Step 4: The nonlinear converter reads the control signal from the control signal register. If the signal is 1, the control sequence LT enters nonlinear converter unit 1 and the sequence RT enters nonlinear converter unit 2; if the signal is 0, the opposite occurs.

[0012] Step 5: Connect the output sequences of nonlinear transformation unit 1 and nonlinear transformation unit 2 through a connector to obtain information output Y and send it to the information memory for storage;

[0013] The nonlinear transformations of nonlinear transformation unit 1 and nonlinear transformation unit 2 are configured as follows: The value of parameter s is set, with different values ​​of s corresponding to different nonlinear transformations. Based on two different values ​​of parameter s, the nonlinear transformations of nonlinear transformation unit 1 and nonlinear transformation unit 2 are obtained respectively. The range of parameter s is: 0 ≤ s ≤ 2. n -2, where n is a positive integer.

[0014] Furthermore, in step 2, the expanding transformer expands the 8-bit input sequence x = (x0, x1, x2, x3, x4, x5, x6, x7) as follows:

[0015] (x0,x1,x2,x3,x4,x5,x6,x7)→(x7,x0,x1,x2,x3,x4,x3,x4,x5,x6,x7,x0).

[0016] Furthermore, the nonlinear transformation tables for nonlinear transformation unit 1 and nonlinear transformation unit 2 are as follows:

[0017] Table 1 Nonlinear transformation table of nonlinear transformation unit 1

[0018] 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 F 0 4 1 8 2 5 A C B 6 D 9 7 E 3 1 E 3 0 7 1 4 9 B A 5 C 8 6 D 2 F 2 2 E 6 0 3 8 A 9 4 B 7 5 C 1 F D 3 D 5 E 2 7 9 8 3 A 6 4 B 0 F C 1

[0019] Table 2 Nonlinear transformation table of nonlinear transformation unit 2

[0020]

[0021]

[0022] In Tables 1 and 2, the first row represents the hexadecimal number corresponding to the middle 4 bits of the 6-bit information sequence, and the first column represents the 4-bit number corresponding to the first and last 2 bits of the 6-bit information sequence.

[0023] The technical solution provided by this invention brings at least the following beneficial effects:

[0024] This invention first splits the 8-bit input into two 4-bit groups, then obtains the corresponding ciphertext through inverse multiplication, affine transformation, and two nonlinear transformations. Finally, the two ciphertext groups are concatenated to obtain the result. This invention, while ensuring optimal algebraic immunity, high nonlinearity, and balance of the S-box, increases the complexity of the algorithm and the difficulty of deciphering it by thoroughly obfuscating the plaintext. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a schematic diagram of the processing procedure of an S-box generation method with optimal algebraic immunity and high nonlinearity provided in an embodiment of the present invention. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0028] like Figure 1 As shown, the S-box generation method with optimal algebraic immunity and high nonlinearity provided by this embodiment of the invention realizes the reception, storage and transmission of information through input information memory, control signal register, output information memory, extended converter and nonlinear transformation unit; the control module has a nonlinear transformation controller to realize the transformation process of the entire S-box.

[0029] like Figure 1 As shown, the extended transformer expands the 8-bit input sequence x = (x0, x1, x2, x3, x4, x5, x6, x7) in the following manner:

[0030] (x0,x1,x2,x3,x4,x5,x6,x7)→(x7,x0,x1,x2,x3,x4,x3,x4,x5,x6,x7,x0)

[0031] like Figure 1 As shown, nonlinear transformation unit 1 and nonlinear transformation unit 2 are selected by a nonlinear transformation controller: if the control signal of the nonlinear transformation controller is 1, then sequence LT enters nonlinear transformation unit 1 and sequence RT enters nonlinear transformation unit 2; if the control signal of the nonlinear transformation controller is 0, then the opposite occurs.

[0032] The preset nonlinear transformation tables in nonlinear transformation unit 1 and nonlinear transformation unit 2 are shown in Table 1 and Table 2, respectively. In the table, the first row represents the hexadecimal number corresponding to the middle 4-bit sequence of 6-bit information, and the first column represents the quaternary number corresponding to the first and last 2-bit sequence of 6-bit information.

[0033] Table 1 Nonlinear transformation table of nonlinear transformation unit 1

[0034] 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 F 0 4 1 8 2 5 A C B 6 D 9 7 E 3 1 E 3 0 7 1 4 9 B A 5 C 8 6 D 2 F 2 2 E 6 0 3 8 A 9 4 B 7 5 C 1 F D 3 D 5 E 2 7 9 8 3 A 6 4 B 0 F C 1

[0035] Table 2 Nonlinear transformation table of nonlinear transformation unit 2

[0036] 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 3 F 0 4 1 8 2 5 A C B 6 D 9 7 E 1 D 2 F E 3 0 7 1 4 9 B A 5 C 8 6 2 5 C 1 F D 2 E 6 0 3 8 A 9 4 B 7 3 6 4 B 0 F C 1 D 5 E 2 7 9 8 3 A

[0037] like Figure 1 As shown, the data processing procedure of this invention is as follows:

[0038] Step S1: The control signal register receives and stores the control signal from the nonlinear converter controller, and the information memory receives and stores the information X to be processed, wherein the length of information X is 8 bits.

[0039] Step S2: The expansion converter reads information X from the information memory and expands and transforms it into 12-bit information;

[0040] Step S3: The splitter segments the 12-bit information output by the extended converter into 6-bit groups LT and RT. Step S4: The nonlinear converter reads the control signal from the control signal register. If the signal is 1, the control sequence LT enters nonlinear converter unit 1 and the sequence RT enters nonlinear converter unit 2. If the signal is 0, the opposite occurs.

[0041] Step S5: Connect the output sequences of nonlinear transformation unit 1 and nonlinear transformation unit 2 through a connector to obtain information output Y and send it to the information memory for storage.

[0042] In this embodiment, the value of the nonlinear transformation controller is 1, meaning that sequence LT enters nonlinear transformation unit 1, sequence RT enters nonlinear transformation unit 2, and so on, traversing all... The corresponding S-box can then be obtained:

[0043] Table 3 Input-output correspondence table of S-box

[0044] 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 95 65 7D 2A AE 2B 7E CB 96 52 43 66 FE 3 C1 2E 1 8E DC 6D 78 57 D6 B BA B1 38 10 49 18 DF 1C 89 2 DA FC 47 9 A7 74 F5 3D 86 83 91 EC 0 D B4 4 3 BC 2F C2 14 4F 79 6E 59 8F 3B D8 DD 31 33 F8 20 4 35 BE A2 9A F3 EA 16 FA 60 40 22 C4 1 8C B8 E 5 CF 5 B5 9E E9 15 C3 5F BD A1 1F 30 19 80 26 E0 6 CD 8A 1D 5D D5 A 48 B0 DB 6C 2D FD C5 EE 69 23 7 93 61 41 C9 73 F4 EB 85 FB 46 88 17 4A 4B 4C 11 8 12 B2 39 4D 4E 58 D7 3A BB 13 B3 C C6 70 E3 EF 9 5B 24 6A D3 AD CA 42 51 94 29 7B 62 1A 7 A5 81 A D1 E1 27 AB E8 5E 1E A0 CE 9D B7 8B 67 C7 71 44 B F0 97 53 E4 D4 AF 2C 6B CC 5C 25 7F 32 F7 99 34 C 3F 21 F9 F2 E6 9B A3 A9 36 55 76 BF ED 68 C8 92 D 45 87 84 72 E5 A8 75 54 3E F1 98 F6 DE 1B 8 D9 E 82 90 3C A6 AC 50 7A 28 5A D2 E2 6F 2 C0 77 8D F 37 F B9 56 E7 9F B6 9C D0 AA A4 6 FF 63 7C 64

[0045] In Table 3, the rows represent the hexadecimal numbers corresponding to the first four bits of the 8-bit input information, and the columns represent the hexadecimal numbers corresponding to the last four bits of the 8-bit input information.

[0046] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

[0047] The above descriptions are merely some embodiments of the present invention. Those skilled in the art can make various modifications and improvements without departing from the inventive concept of the present invention, and these all fall within the scope of protection of the present invention.

Claims

1. A method for generating S-boxes with optimal algebraic immunity and high nonlinearity, characterized in that, Includes the following steps: Step 1: The control signal register receives and stores the control signal from the nonlinear converter controller, and the information memory receives and stores the information X to be processed, wherein the length of information X is 8 bits. Step 2: The expansion converter reads information X from the information memory and expands and transforms it into 12-bit information; Step 3: The splitter processes the 12-bit information output by the extended converter into 6-bit groups. LT and RT ; Step 4: The nonlinear converter controller reads the control signal from the control signal register. If the signal is 1, then the control sequence... LT Entering nonlinear transformation unit 1, sequence RT Enter nonlinear transformation unit 2; if it is 0, then the opposite applies; Step 5: Connect the output sequences of nonlinear transformation unit 1 and nonlinear transformation unit 2 through a connector to obtain information output Y and send it to the information memory for storage; The nonlinear transformations of nonlinear transformation unit 1 and nonlinear transformation unit 2 are configured as follows: Parameter settings The value of the parameter Different values ​​of the parameter correspond to different nonlinear transformations, based on the parameter Two different values ​​of respectively yield the nonlinear transformation of nonlinear transformation unit 1 and the nonlinear transformation of nonlinear transformation unit 2, where the parameter The range of values ​​is: , It is a positive integer.

2. The method as described in claim 1, characterized in that, In step 2, the expansion transformer converts the 8-bit input sequence Expand as follows: 。

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