Data reading method, memory storage device and memory control circuit unit

Abstract

This invention provides a data reading method, a memory storage device, and a memory control circuit unit. The method includes: receiving a plurality of read instructions from a host system, which at least instruct the reading of first data stored in a first plane and second data stored in a second plane; sending a plurality of read instruction sequences according to the plurality of read instructions, which at least instruct the execution of a first read operation on the first plane to obtain the first data and a second read operation on the second plane to obtain the second data; determining a data transmission order based on the performance of the first and second read operations; and receiving the first data and the second data sequentially from a rewritable non-volatile memory module according to the data transmission order. This improves the data reading performance for different planes within the same chip enable region.

Description

TECHNICAL FIELD

[0001] The present invention relates to a memory management technique, and more particularly, to a data read method, a memory storage device, and a memory control circuit unit. BACKGROUND

[0002] Electronic devices such as mobile phones and notebook computers have grown rapidly in recent years, resulting in a rapid increase in consumer demand for storage media. Rewritable non-volatile memory modules (e.g., flash memory) are very suitable for being built into various portable multimedia devices exemplified above due to their data non-volatility, power saving, small size, and lack of mechanical structure.

[0003] A rewritable non-volatile memory module can include one or more dies. A die is obtained by laser cutting from a wafer. Each die can be divided into one or more chip enable (CE) regions. Each chip enable region can include one or more planes (also referred to as memory planes). Each plane can include a plurality of physical blocks. Each physical block can include a plurality of physical pages. Each physical page can include a plurality of memory cells. A memory cell is the smallest physical element in a rewritable non-volatile memory module for storing data.

[0004] Generally, when receiving read commands for different planes in the same chip enable region from a host system in succession, the read commands are executed in sequence according to the receiving order to read data from the corresponding planes. Then, the read data can be returned to the host system in sequence according to the read order. However, in practice, this standardized read mechanism can easily result in system performance waste. SUMMARY

[0005] The present invention provides a data read method, a memory storage device, and a memory control circuit unit, which can improve data read performance for different planes in the same chip enable region.

[0006] An exemplary embodiment of the present disclosure provides a data reading method for a rewritable non-volatile memory module. The rewritable non-volatile memory module includes a plurality of chip enable regions. A first chip enable region of the plurality of chip enable regions includes a plurality of planes. The plurality of planes includes a first plane and a second plane. The data reading method includes receiving a plurality of read commands from a host system, wherein the plurality of read commands are indicative of at least reading first data stored in the first plane and second data stored in the second plane; sending a plurality of read command sequences to the rewritable non-volatile memory module according to the plurality of read commands, wherein the plurality of read command sequences are indicative of at least performing a first read operation on the first plane to obtain the first data and performing a second read operation on the second plane to obtain the second data; determining a data transfer order according to performances of the first read operation and the second read operation; and sequentially receiving the first data and the second data from the rewritable non-volatile memory module according to the data transfer order.

[0007] In an exemplary embodiment of the present disclosure, determining the data transfer order according to the performances of the first read operation and the second read operation includes determining the data transfer order as receiving the first data before receiving the second data in response to a performance of the first read operation being better than a performance of the second read operation.

[0008] In an exemplary embodiment of the present disclosure, the performances of the first read operation and the second read operation are reflected by a first execution time length of the first read operation and a second execution time length of the second read operation.

[0009] In an exemplary embodiment of the present disclosure, determining the data transfer order according to the performances of the first read operation and the second read operation includes evaluating the performances of the first read operation and the second read operation according to a first type of first physical units storing the first data in the first plane and a second type of second physical units storing the second data in the second plane.

[0010] In an exemplary embodiment of the present disclosure, an order position of one bit stored by the first physical units of the first type in a plurality of bits stored in a memory cell is different from an order position of one bit stored by the second physical units of the second type in the plurality of bits stored in the memory cell.

[0011] In an example embodiment of this disclosure, the first data obtained by the first read operation and the second data obtained by the second read operation are buffered in a buffer in the rewritable non-volatile memory module, and the step of sequentially receiving the first data and the second data from the rewritable non-volatile memory module according to the data transfer order comprises sequentially sending a plurality of Direct Memory Access (DMA) instruction sequences to the rewritable non-volatile memory module according to the data transfer order, wherein the plurality of DMA instruction sequences are at least used to instruct transferring the first data and the second data in the buffer.

[0012] In an example embodiment of this disclosure, the data reading method further comprises buffering the received read instructions in at least one instruction queue, and a total number of the at least one instruction queue is less than a total number of the plurality of planes.

[0013] In an example embodiment of this disclosure, the plurality of read instructions comprises a first read instruction and a second read instruction, the first read instruction is used to instruct reading the first data stored in the first plane, the second read instruction is used to instruct reading the second data stored in the second plane, and the step of buffering the received read instructions in the at least one instruction queue comprises buffering the first read instruction and the second read instruction in a first instruction queue in the at least one instruction queue.

[0014] In an example embodiment of this disclosure, the plurality of read instructions comprises a first read instruction and a second read instruction, the first read instruction is used to instruct reading the first data stored in the first plane, the second read instruction is used to instruct reading the second data stored in the second plane, and the step of buffering the received read instructions in the at least one instruction queue comprises buffering the first read instruction in a first instruction queue in the at least one instruction queue, and buffering the second read instruction in a second instruction queue in the at least one instruction queue.

[0015] In an example embodiment of this disclosure, the step of sequentially receiving the first data and the second data from the rewritable non-volatile memory module according to the data transfer order comprises recording information reflecting the data transfer order, and sequentially receiving the first data and the second data from the rewritable non-volatile memory module according to the data transfer order without adjusting an order of the plurality of read instructions buffered in the at least one instruction queue.

[0016] An exemplary embodiment of the present invention provides a memory storage device, which includes a connection interface unit, a rewritable non-volatile memory module, and a memory control circuit unit. The connection interface unit is used to connect to a host system. The rewritable non-volatile memory module includes multiple chip enable regions. A first chip enable region among the multiple chip enable regions includes multiple planes. The multiple planes include a first plane and a second plane. The memory control circuit unit is connected to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit is configured to: receive multiple read instructions from the host system, wherein the multiple read instructions are at least used to instruct the reading of first data stored in the first plane and second data stored in the second plane; send multiple read instruction sequences to the rewritable non-volatile memory module according to the multiple read instructions, wherein the multiple read instruction sequences are at least used to instruct the execution of a first read operation on the first plane to obtain the first data and a second read operation on the second plane to obtain the second data; determine the data transmission order according to the performance of the first read operation and the second read operation; and receive the first data and the second data sequentially from the rewritable non-volatile memory module according to the data transmission order.

[0017] In an exemplary embodiment of the present invention, the operation of the memory control circuit unit to determine the data transmission order based on the performance of the first read operation and the second read operation includes: in response to the fact that the performance of the first read operation is better than the performance of the second read operation, determining the data transmission order to receive the first data first and then receive the second data.

[0018] In an exemplary embodiment of the present invention, the operation of the memory control circuit unit to determine the data transmission order based on the performance of the first read operation and the second read operation includes: evaluating the performance of the first read operation and the second read operation based on the first type of the first entity unit storing the first data in the first plane and the second type of the second entity unit storing the second data in the second plane.

[0019] In an exemplary embodiment of the present invention, the first data obtained through the first read operation and the second data obtained through the second read operation are cached in a buffer in the rewritable non-volatile memory module, and the operation of the memory control circuit unit to receive the first data and the second data sequentially from the rewritable non-volatile memory module according to the data transmission order includes: sequentially sending a plurality of direct memory access instruction sequences to the rewritable non-volatile memory module according to the data transmission order, wherein the plurality of direct memory access instruction sequences are at least used to indicate the transmission of the first data and the second data in the buffer.

[0020] In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to: cache the received plurality of read instructions in at least one instruction queue, wherein the total number of the at least one instruction queue is less than the total number of the plurality of planes.

[0021] In an exemplary embodiment of the present invention, the plurality of read instructions include a first read instruction and a second read instruction. The first read instruction is used to instruct the reading of the first data stored in the first plane, and the second read instruction is used to instruct the reading of the second data stored in the second plane. The operation of the memory control circuit unit to cache the received plurality of read instructions in the at least one instruction queue includes: caching the first read instruction and the second read instruction in the first instruction queue of the at least one instruction queue.

[0022] In an exemplary embodiment of the present invention, the plurality of read instructions include a first read instruction and a second read instruction. The first read instruction is used to instruct the reading of the first data stored in the first plane, and the second read instruction is used to instruct the reading of the second data stored in the second plane. The operation of the memory control circuit unit to cache the received plurality of read instructions in the at least one instruction queue includes: caching the first read instruction in the first instruction queue of the at least one instruction queue; and caching the second read instruction in the second instruction queue of the at least one instruction queue.

[0023] In an exemplary embodiment of the present invention, the operation of the memory control circuit unit to sequentially receive the first data and the second data from the rewritable non-volatile memory module according to the data transmission order includes: recording information reflecting the data transmission order; and receiving the first data and the second data sequentially from the rewritable non-volatile memory module according to the data transmission order without adjusting the order of the plurality of read instructions cached in the at least one instruction queue.

[0024] An exemplary embodiment of the present invention provides a memory control circuit unit for controlling a rewritable non-volatile memory module. The rewritable non-volatile memory module includes multiple chip enable regions. A first chip enable region within the multiple chip enable regions includes multiple planes, including a first plane and a second plane. The memory control circuit unit includes a host interface, a memory interface, and a memory management circuit. The host interface is used to connect to a host system. The memory interface is used to connect to the rewritable non-volatile memory module. The memory management circuit is connected to the host interface and the memory interface. The memory management circuit is configured to: receive multiple read instructions from the host system, wherein the multiple read instructions are at least used to instruct the reading of first data stored in the first plane and second data stored in the second plane; send multiple read instruction sequences to the rewritable non-volatile memory module according to the multiple read instructions, wherein the multiple read instruction sequences are at least used to instruct the execution of a first read operation on the first plane to obtain the first data and a second read operation on the second plane to obtain the second data; determine the data transmission order according to the performance of the first read operation and the second read operation; and receive the first data and the second data sequentially from the rewritable non-volatile memory module according to the data transmission order.

[0025] In an exemplary embodiment of the present invention, the operation of the memory management circuit to determine the data transmission order based on the performance of the first read operation and the second read operation includes: in response to the performance of the first read operation being superior to that of the second read operation, determining the data transmission order to receive the first data first and then receive the second data.

[0026] In an exemplary embodiment of the present invention, the operation of the memory management circuit to determine the data transmission order based on the performance of the first read operation and the second read operation includes: evaluating the performance of the first read operation and the second read operation based on the first type of the first entity unit storing the first data in the first plane and the second type of the second entity unit storing the second data in the second plane.

[0027] In an exemplary embodiment of the present invention, the first data obtained through the first read operation and the second data obtained through the second read operation are cached in a buffer in the rewritable non-volatile memory module, and the operation of the memory management circuit receiving the first data and the second data sequentially from the rewritable non-volatile memory module according to the data transmission order includes: sequentially sending a plurality of direct memory access instruction sequences to the rewritable non-volatile memory module according to the data transmission order, wherein the plurality of direct memory access instruction sequences are at least used to indicate the transmission of the first data and the second data in the buffer.

[0028] In an exemplary embodiment of the present invention, the memory management circuit is further configured to: cache the received plurality of read instructions in at least one instruction queue, wherein the total number of the at least one instruction queue is less than the total number of the plurality of planes.

[0029] In an exemplary embodiment of the present invention, the plurality of read instructions include a first read instruction and a second read instruction. The first read instruction is used to instruct the reading of the first data stored in the first plane, and the second read instruction is used to instruct the reading of the second data stored in the second plane. The operation of the memory management circuit to cache the received plurality of read instructions in the at least one instruction queue includes: caching the first read instruction and the second read instruction in the first instruction queue of the at least one instruction queue.

[0030] In an exemplary embodiment of the present invention, the plurality of read instructions include a first read instruction and a second read instruction. The first read instruction is used to instruct the reading of the first data stored in the first plane, and the second read instruction is used to instruct the reading of the second data stored in the second plane. The operation of the memory management circuit to cache the received plurality of read instructions in the at least one instruction queue includes: caching the first read instruction in the first instruction queue of the at least one instruction queue; and caching the second read instruction in the second instruction queue of the at least one instruction queue.

[0031] In an exemplary embodiment of the present invention, the operation of the memory management circuit receiving the first data and the second data sequentially from the rewritable non-volatile memory module according to the data transmission order includes: recording information reflecting the data transmission order; and receiving the first data and the second data sequentially from the rewritable non-volatile memory module according to the data transmission order without adjusting the order of the plurality of read instructions cached in the at least one instruction queue.

[0032] Based on the above, upon receiving multiple read commands from the host system, a sequence of read commands can be sent accordingly. This sequence of read commands can instruct data read operations to be performed on different planes within the same chip enable region. A data transfer order can be determined based on the performance of the performed data read operations. Subsequently, according to this data transfer order, the data read from these planes can be sequentially sent from the rewritable non-volatile memory module in a customized order. This improves the data read performance for different planes within the same chip enable region. Attached Figure Description

[0033] Figure 1 This is a schematic diagram of a host system, memory storage device, and input / output (I / O) device according to an exemplary embodiment of the present invention;

[0034] Figure 2 This is a schematic diagram of a host system, a memory storage device, and an I / O device according to an exemplary embodiment of the present invention;

[0035] Figure 3 This is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention;

[0036] Figure 4 This is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention;

[0037] Figure 5 This is a schematic diagram of a memory control circuit unit according to an exemplary embodiment of the present invention;

[0038] Figure 6 This is a schematic diagram illustrating the management of a rewritable non-volatile memory module according to an exemplary embodiment of the present invention;

[0039] Figure 7 This is a schematic diagram illustrating the management of a rewritable non-volatile memory module according to an exemplary embodiment of the present invention;

[0040] Figure 8 This is a schematic diagram illustrating, according to an exemplary embodiment of the present invention, caching multiple read instructions in an instruction queue;

[0041] Figure 9 This is a schematic diagram illustrating the sending of a read instruction sequence and a direct memory access instruction sequence according to a preset rule, as shown in an exemplary embodiment of the present invention;

[0042] Figure 10 This is a schematic diagram illustrating a performance comparison between caching multiple read instructions in an instruction queue and performing multiple read operations, as shown in an exemplary embodiment of the present invention.

[0043] Figure 11 This is a schematic diagram illustrating the sending of a read instruction sequence and a direct memory access instruction sequence based on a performance comparison result, according to an exemplary embodiment of the present invention.

[0044] Figure 12 This is a schematic diagram illustrating a performance comparison between caching multiple read instructions in multiple instruction queues and performing multiple read operations, as shown in an exemplary embodiment of the present invention.

[0045] Figure 13 This is a schematic diagram illustrating the sending of a read instruction sequence and a direct memory access instruction sequence based on a performance comparison result, according to an exemplary embodiment of the present invention.

[0046] Figure 14 This is a schematic diagram illustrating a performance comparison between caching multiple read instructions in multiple instruction queues and performing multiple read operations, as shown in an exemplary embodiment of the present invention.

[0047] Figure 15 This is a schematic diagram illustrating the sending of a read instruction sequence and a direct memory access instruction sequence based on a performance comparison result, according to an exemplary embodiment of the present invention.

[0048] Figure 16 This is a flowchart illustrating a data reading method according to an exemplary embodiment of the present invention. Detailed Implementation

[0049] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0050] Generally, a memory storage device (also known as a memory storage system) includes a rewritable non-volatile memory module and a controller (also known as a control circuit). The memory storage device can be used with a host system to enable the host system to write data to or read data from the memory storage device.

[0051] Figure 1 This is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device according to an exemplary embodiment of the present invention. Figure 2 This is a schematic diagram of a host system, a memory storage device, and an I / O device according to an exemplary embodiment of the present invention.

[0052] Please refer to Figure 1 and Figure 2The host system 11 may include a processor 111, random access memory (RAM) 112, read-only memory (ROM) 113, and a data transfer interface 114. The processor 111, RAM 112, ROM 113, and data transfer interface 114 may be connected to the system bus 110.

[0053] In one exemplary embodiment, the host system 11 can be connected to the memory storage device 10 via a data transmission interface 114. For example, the host system 11 can store data to or read data from the memory storage device 10 via the data transmission interface 114. Furthermore, the host system 11 can be connected to the I / O device 12 via a system bus 110. For example, the host system 11 can transmit output signals to or receive input signals from the I / O device 12 via the system bus 110.

[0054] In one exemplary embodiment, the processor 111, random access memory 112, read-only memory 113, and data transfer interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. Through the data transfer interface 114, the motherboard 20 can be connected to the memory storage device 10 via wired or wireless means.

[0055] In one exemplary embodiment, the memory storage device 10 may be, for example, a USB flash drive 201, a memory card 202, a solid-state drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 may be, for example, a Near Field Communication (NFC) memory storage device, a WiFi wireless fax memory storage device, a Bluetooth memory storage device, or a Bluetooth Low Energy (BLE) memory storage device (e.g., iBeacon), or other memory storage devices based on various wireless communication technologies. Furthermore, the motherboard 20 may also be connected via the system bus 110 to various I / O devices such as a Global Positioning System (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, and a speaker 210. For example, in one exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 via the wireless transmission device 207.

[0056] In one exemplary embodiment, the host system 11 is a computer system. In another exemplary embodiment, the host system 11 may be any system capable of substantially cooperating with a memory storage device to store data. In one exemplary embodiment, the memory storage device 10 and the host system 11 may each include… Figure 3 The memory storage device 30 and the host system 31.

[0057] Figure 3 This is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention.

[0058] Please refer to Figure 3 The memory storage device 30 can be used in conjunction with the host system 31 to store data. For example, the host system 31 can be a digital camera, camcorder, communication device, audio player, video player, or tablet computer. For example, the memory storage device 30 can be various non-volatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34 used by the host system 31. The embedded storage device 34 includes various types of embedded storage devices that directly connect the memory module to the substrate of the host system, such as an embedded Multi Media Card (eMMC) 341 and / or an embedded Multi Chip Package (eMCP) storage device 342.

[0059] Figure 4 This is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention.

[0060] Please refer to Figure 4 The memory storage device 10 includes a connection interface unit 41, a memory control circuit unit 42, and a rewritable non-volatile memory module 43.

[0061] The connection interface unit 41 is used to connect the memory storage device 10 to the host system 11. The memory storage device 10 can communicate with the host system 11 through the connection interface unit 41. In an exemplary embodiment, the connection interface unit 41 is compatible with the Peripheral Component Interconnect Express (PCI Express) standard. In one exemplary embodiment, the connection interface unit 41 may also conform to the Serial Advanced Technology Attachment (SATA) standard, the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronics Engineers (IEEE) 1394 standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed-I (UHS-I) interface standard, the Ultra High Speed-II (UHS-II) interface standard, the Memory Stick (MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash Storage (UFS) interface standard, the eMCP interface standard, the CF interface standard, the Integrated Device Electronics (IDE) standard, or other suitable standards. The connection interface unit 41 can be packaged in a chip with the memory control circuit unit 42, or the connection interface unit 41 can be disposed outside a chip containing the memory control circuit unit 42.

[0062] The memory control circuit unit 42 is connected to the connection interface unit 41 and the rewritable non-volatile memory module 43. The memory control circuit unit 42 is used to execute multiple logic gates or control instructions implemented in hardware or firmware, and to perform operations such as writing, reading and erasing data in the rewritable non-volatile memory module 43 according to the instructions of the host system 11.

[0063] The rewritable non-volatile memory module 43 is used to store data written by the host system 11. The rewritable non-volatile memory module 43 may include a single-level cell (SLC) NAND flash memory module (i.e., a flash memory module that can store 1 bit in one memory cell), a multi-level cell (MLC) NAND flash memory module (i.e., a flash memory module that can store 2 bits in one memory cell), a triple-level cell (TLC) NAND flash memory module (i.e., a flash memory module that can store 3 bits in one memory cell), a quad-level cell (QLC) NAND flash memory module (i.e., a flash memory module that can store 4 bits in one memory cell), other flash memory modules, or other memory modules with the same characteristics.

[0064] Each memory cell in the rewritable non-volatile memory module 43 stores one or more bits by changing a voltage (hereinafter also referred to as the threshold voltage). Specifically, each memory cell has a charge trapping layer between its control gate and channel. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also called "writing data to the memory cell" or "programming the memory cell". As the threshold voltage changes, each memory cell in the rewritable non-volatile memory module 43 has multiple storage states. By applying a read voltage, it can be determined which storage state a memory cell belongs to, thereby retrieving the one or more bits stored in that memory cell.

[0065] In one exemplary embodiment, the memory cells of the rewritable non-volatile memory module 43 can constitute multiple physical programmable units, and these physical programmable units can constitute multiple physical erase units. Specifically, memory cells on the same word line can form one or more physical programmable units. If a memory cell can store more than two bits, then physical programmable units on the same word line can be classified into lower physical programmable units and upper physical programmable units. For example, the least significant bit (LSB) of a memory cell belongs to the lower physical programmable unit, and the most significant bit (MSB) of a memory cell belongs to the upper physical programmable unit. Generally, in MLC NAND flash memory, the write speed of the lower physical programmable unit is greater than that of the upper physical programmable unit, and / or the reliability of the lower physical programmable unit is higher than that of the upper physical programmable unit.

[0066] In one exemplary embodiment, a physical programming unit is the smallest unit of programming. That is, a physical programming unit is the smallest unit for writing data. For example, a physical programming unit can be a physical page or a physical sector. If the physical programming unit is a physical page, these physical programming units may include data bit areas and redundancy bit areas. The data bit area contains multiple physical sectors for storing user data, while the redundancy bit area is used to store system data (e.g., management data such as error correction codes). In one exemplary embodiment, the data bit area contains 32 physical sectors, and the size of one physical sector is 512 bytes (B). However, in other exemplary embodiments, the data bit area may also contain 8, 16, or more or fewer physical sectors, and the size of each physical sector may also be larger or smaller. On the other hand, a physical erase unit is the smallest unit of erasure. That is, each physical erase unit contains a minimum number of storage units to be erased together. For example, a physical erase unit is a physical block.

[0067] Figure 5 This is a schematic diagram of a memory control circuit unit according to an exemplary embodiment of the present invention.

[0068] Please refer to Figure 5The memory control circuit unit 42 includes a memory management circuit 51, a host interface 52, and a memory interface 53. The memory management circuit 51 controls the overall operation of the memory control circuit unit 42. Specifically, the memory management circuit 51 has multiple control instructions, and these control instructions are executed when the memory storage device 10 is operating to perform operations such as writing, reading, and erasing data. The following description of the operation of the memory management circuit 51 is equivalent to a description of the operation of the memory control circuit unit 42.

[0069] In one exemplary embodiment, the control instructions of the memory management circuit 51 are implemented in firmware form. For example, the memory management circuit 51 has a microprocessor unit (not shown) and a read-only memory (not shown), and these control instructions are burned into the read-only memory. When the memory storage device 10 is operating, these control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

[0070] In one exemplary embodiment, the control instructions of the memory management circuit 51 may also be stored in program code form in a specific area of ​​the rewritable non-volatile memory module 43 (e.g., a system area in the memory module dedicated to storing system data). Furthermore, the memory management circuit 51 includes a microprocessor unit (not shown), a read-only memory (not shown), and a random access memory (not shown). Specifically, this read-only memory has a boot code, and when the memory control circuit unit 42 is enabled, the microprocessor unit first executes this boot code to load the control instructions stored in the rewritable non-volatile memory module 43 into the random access memory of the memory management circuit 51. Subsequently, the microprocessor unit executes these control instructions to perform operations such as writing, reading, and erasing data.

[0071] In one exemplary embodiment, the control instructions for the memory management circuit 51 can also be implemented in hardware. For example, the memory management circuit 51 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, memory write circuit, memory read circuit, memory erase circuit, and data processing circuit are connected to the microcontroller. The memory cell management circuit manages the memory cells or groups of memory cells in the rewritable non-volatile memory module 43. The memory write circuit issues a sequence of write instructions to the rewritable non-volatile memory module 43 to write data into the rewritable non-volatile memory module 43. The memory read circuit issues a sequence of read instructions to the rewritable non-volatile memory module 43 to read data from the rewritable non-volatile memory module 43. The memory erase circuit issues a sequence of erase instructions to the rewritable non-volatile memory module 43 to erase data from the rewritable non-volatile memory module 43. The data processing circuit is used to process data to be written to and read from the rewritable non-volatile memory module 43. The write instruction sequence, read instruction sequence, and erase instruction sequence may each include one or more program codes or instruction codes and are used to instruct the rewritable non-volatile memory module 43 to perform corresponding write, read, and erase operations. In an exemplary embodiment, the memory management circuit 51 may also issue other types of instruction sequences to the rewritable non-volatile memory module 43 to instruct it to perform corresponding operations.

[0072] The host interface 52 is connected to the memory management circuit 51. The memory management circuit 51 can communicate with the host system 11 through the host interface 52. The host interface 52 can be used to receive and identify instructions and data transmitted by the host system 11. For example, instructions and data transmitted by the host system 11 can be transmitted to the memory management circuit 51 through the host interface 52. In addition, the memory management circuit 51 can transmit data to the host system 11 through the host interface 52. In this exemplary embodiment, the host interface 52 is compatible with the PCI Express standard. However, it should be understood that the present invention is not limited thereto, and the host interface 52 may also be compatible with the SATA standard, PATA standard, IEEE 1394 standard, USB standard, SD standard, UHS-I standard, UHS-II standard, MS standard, MMC standard, eMMC standard, UFS standard, CF standard, IDE standard, or other suitable data transmission standards.

[0073] The memory interface 53 is connected to the memory management circuit 51 and is used to access the rewritable non-volatile memory module 43. For example, the memory management circuit 51 can access the rewritable non-volatile memory module 43 through the memory interface 53. That is, data to be written to the rewritable non-volatile memory module 43 is converted into a format acceptable to the rewritable non-volatile memory module 43 through the memory interface 53. Specifically, if the memory management circuit 51 needs to access the rewritable non-volatile memory module 43, the memory interface 53 will transmit a corresponding instruction sequence. For example, these instruction sequences may include a write instruction sequence indicating the writing of data, a read instruction sequence indicating the reading of data, an erase instruction sequence indicating the erasure of data, and corresponding instruction sequences for indicating various memory operations (e.g., changing the read voltage level or performing garbage collection operations, etc.). These instruction sequences are generated by the memory management circuit 51 and transmitted to the rewritable non-volatile memory module 43 through the memory interface 53. These instruction sequences may include one or more signals or data on the bus. These signals or data may include instruction codes or program codes. For example, a read instruction sequence may include information such as the read identification code and memory address.

[0074] In one exemplary embodiment, the memory control circuit unit 42 further includes an error checking and correction circuit 54, a buffer memory 55, and a power management circuit 56.

[0075] Error checking and correction circuit 54 is connected to memory management circuit 51 and is used to perform error checking and correction operations to ensure data integrity. Specifically, when memory management circuit 51 receives a write command from host system 11, error checking and correction circuit 54 generates a corresponding error correcting code (ECC) and / or error detecting code (EDC) for the data corresponding to the write command, and memory management circuit 51 writes the data corresponding to the write command and the corresponding error correcting code and / or error detecting code to rewritable non-volatile memory module 43. Subsequently, when memory management circuit 51 reads data from rewritable non-volatile memory module 43, it simultaneously reads the corresponding error correcting code and / or error detecting code for this data, and error checking and correction circuit 54 performs error checking and correction operations on the read data based on the error correcting code and / or error detecting code.

[0076] The buffer memory 55 is connected to the memory management circuit 51 and is used to cache data. The power management circuit 56 is connected to the memory management circuit 51 and is used to control the power supply of the memory storage device 10.

[0077] In one exemplary embodiment, Figure 4 The rewritable non-volatile memory module 43 may include a flash memory module. In one exemplary embodiment, Figure 4 The memory control circuit unit 42 may include a flash memory controller. In one exemplary embodiment, Figure 5 The memory management circuit 51 may include a flash memory management circuit.

[0078] Figure 6 This is a schematic diagram illustrating the management of a rewritable non-volatile memory module according to an exemplary embodiment of the present invention.

[0079] Please refer to Figure 6 The memory management circuit 51 can logically group the physical units 610(0) to 610(B) in the rewritable non-volatile memory module 43 into the storage area 601 and the spare area 602. Each physical unit can refer to one or more physical erase units, one or more physical programming units, or other physical management units.

[0080] Entity cells 610(0) to 610(A) in storage area 601 are used to store user data (e.g., from...) Figure 1 (User data of host system 11). For example, entity units 610(0) to 610(A) in storage area 601 may store valid data and / or invalid data. Entity units 610(A+1) to 610(B) in free area 602 do not store data (e.g., valid data). For example, if an entity unit does not store valid data, this entity unit may be associated (or added) to free area 602. In addition, entity units (or entity units that do not store valid data) in free area 602 may be erased. When new data is written, one or more entity units may be retrieved from free area 602 to store this new data. In an exemplary embodiment, free area 602 is also referred to as a free pool.

[0081] The memory management circuit 51 can configure logic units 612(0) to 612(C) to map physical units 610(0) to 610(A) in the memory area 601. In one exemplary embodiment, each logic unit corresponds to a logical address. For example, a logical address may include one or more logical block addresses (LBAs) or other logical management units. In one exemplary embodiment, a logic unit may also correspond to a logical programmable unit or consist of multiple consecutive or non-consecutive logical addresses. A, B, and C are all positive integers and can be adjusted according to practical needs; this invention does not impose any limitations.

[0082] It should be noted that a logical unit can be mapped to one or more entity units. If an entity unit is currently mapped to a logical unit, it means that the data currently stored in this entity unit includes valid data. Conversely, if an entity unit is not currently mapped to any logical unit, it means that the data currently stored in this entity unit is invalid data.

[0083] The memory management circuit 51 can record management data (also known as logic-to-entity mapping information) describing the mapping relationship between logic units and physical units in at least one logic-to-entity mapping table. When the host system 11 wants to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 51 can access the rewritable non-volatile memory module 43 according to the information in this logic-to-entity mapping table.

[0084] Figure 7 This is a schematic diagram illustrating the management of a rewritable non-volatile memory module according to an exemplary embodiment of the present invention.

[0085] Please refer to Figure 7 The rewritable non-volatile memory module 43 may include multiple chip-enabled (CE) regions CE(0) to CE(M). For example, the rewritable non-volatile memory module 43 may include one or more dies. Dies are obtained from wafers by laser cutting. Each die may be divided into one or more chip-enabled regions. Each chip-enabled region among the chip-enabled regions CE(0) to CE(M) may include one or more planes (also called memory planes). Each plane may include multiple physical cells.

[0086] It should be noted that whether a certain chip enable region can be accessed can be controlled by the chip enable signal corresponding to that chip enable region. For example, when the chip enable signal corresponding to the chip enable region CE(i) is pulled up, the rewritable non-volatile memory module 43 can read data from or store data in the chip enable region CE(i). However, if the chip enable signal corresponding to the chip enable region CE(i) is not pulled up, the rewritable non-volatile memory module 43 cannot read data from or store data in the chip enable region CE(i).

[0087] It should be noted that in this exemplary embodiment, each of the chip enable regions CE(0) to CE(M) contains the same number (i.e., P) of planes. For example, chip enable region CE(0) contains planes 701(0) to 701(P), and chip enable region CE(M) contains planes 702(0) to 702(P), and so on. However, the total number of planes in different chip enable regions may also be different, and this invention does not impose any limitations.

[0088] The memory management circuit 51 can access the rewritable non-volatile memory module 43 through channels 71(0) to 71(N). In particular, each of channels 71(0) to 71(N) can be used to access one or more specific chip enable regions. For example, channel 71(0) can be used to access the chip enable region CE(0) (and planes 701(0) to 701(P)), and channel 71(N) can be used to access the chip enable region CE(M) (and planes 702(0) to 702(P)), and so on, and N can be the same as or different from M. In addition, N, M and P are all positive integers and can be adjusted according to practical needs, which is not limited by the present invention.

[0089] In one exemplary embodiment, the memory management circuit 51 may receive multiple read instructions from the host system 11. These read instructions are at least used to instruct the reading of data (also referred to as first data) stored in a plane (also referred to as first plane) within a chip enable region (also referred to as a first chip enable region) and data (also referred to as second data) stored in another plane (also referred to as a second plane) within the same chip enable region (i.e., the first chip enable region). For example, the first chip enable region may be a chip enable region CE(0), the first plane may be plane 701(0), and the second plane may be plane 701(1), and the invention is not limited thereto. In other words, these read instructions can be used to read data in different planes (e.g., plane 701(0) and plane 701(1)) within the same chip enable region (e.g., chip enable region CE(0)).

[0090] In one exemplary embodiment, the memory management circuit 51 may send a plurality of read instruction sequences to the rewritable non-volatile memory module 43 according to these read instructions. These read instruction sequences are at least used to instruct the execution of a read operation (also referred to as a first read operation) on the first plane to obtain the first data and to execute a read operation (also referred to as a second read operation) on the second plane to obtain the second data. Specifically, the data read by the first read operation (i.e., the first data) and the data read by the second read operation (i.e., the second data) may be cached in a buffer within the rewritable non-volatile memory module 43 (e.g., a buffer memory within the rewritable non-volatile memory module 43) and await transmission to the memory management circuit 51 (or the memory control circuit unit 42).

[0091] In one exemplary embodiment, the memory management circuit 51 may determine a data transfer order based on the performance of the first read operation and the second read operation. This data transfer order is used to control, manage, or limit the order in which the memory management circuit 51 receives the first data and the second data from the rewritable non-volatile memory module 43. According to this data transfer order, the memory management circuit 51 may receive the first data and the second data sequentially from the rewritable non-volatile memory module 43 in a customized order. For example, the memory management circuit 51 may receive the first data and the second data sequentially from the rewritable non-volatile memory module 43 through channel 71(0) based on the data transfer order.

[0092] In one exemplary embodiment, the memory management circuit 51 can determine whether the performance of the first read operation is superior to that of the second read operation. In response to the superior performance of the first read operation, the memory management circuit 51 can determine the data transmission order to receive the first data first, followed by the second data. Alternatively, in response to the superior performance of the second read operation, the memory management circuit 51 can determine the data transmission order to receive the second data first, followed by the first data. By prioritizing the transmission of data obtained from read operations with higher read performance, multiple data transfers can be performed more effectively using the same channel (e.g., channel 71(0)), thereby improving overall data read performance.

[0093] In one exemplary embodiment, the performance of a read operation can be reflected by its execution time. The execution time of a read operation can represent the time or duration required to complete the read operation. For example, the performance of a read operation can be negatively correlated with its execution time. A longer execution time indicates a less efficient read operation, and vice versa. Therefore, in one exemplary embodiment, the performance of the first read operation and the second read operation can be reflected by their respective execution times (also referred to as the first execution time) and second read operation.

[0094] In one exemplary embodiment, the memory management circuit 51 may evaluate the performance of the first read operation and the second read operation based on a first execution time length and a second execution time length, respectively. The memory management circuit 51 may compare the first execution time length and the second execution time length. In response to the first execution time length being shorter than the second execution time length, the memory management circuit 51 may determine that the performance of the first read operation is superior to the performance of the second read operation. Alternatively, in response to the second execution time length being shorter than the first execution time length, the memory management circuit 51 may determine that the performance of the second read operation is superior to the performance of the first read operation.

[0095] In one exemplary embodiment, the memory management circuit 51 can obtain the type (also referred to as the first type) of the entity unit (also referred to as the first entity unit) storing the first data in the first plane and the type (also referred to as the second type) of the entity unit (also referred to as the second entity unit) storing the second data in the second plane. The memory management circuit 51 can evaluate the performance of the first read operation and the second read operation based on the first type and the second type. For example, the memory management circuit 51 can pre-record the execution time of the read operation corresponding to different types of entity units in a data table. Then, the memory management circuit 51 can query the data table according to the type of entity unit to be read to obtain the execution time of the read operation corresponding to that type of entity unit.

[0096] In one exemplary embodiment, the memory management circuit 51 can obtain a corresponding first execution time length based on the type of the first physical unit (i.e., the first type). Simultaneously, the memory management circuit 51 can obtain a corresponding second execution time length based on the type of the second physical unit (i.e., the second type). The first type may be the same as or different from the second type. The memory management circuit 51 can evaluate the performance of the first read operation and the second read operation based on the first and second execution time lengths. Then, the memory management circuit 51 can determine the data transfer order based on the performance evaluation results.

[0097] In one exemplary embodiment, the type of an entity unit may reflect whether the entity unit belongs to an upper, middle, or lower entity unit. In one exemplary embodiment, an upper entity unit is also called an upper page, a middle entity unit is also called a middle page, and a lower entity unit is also called a lower page. However, the type of entity unit may also be classified according to other rules, such as the data type stored by the entity unit, the frequency of access to the entity unit, the wear and tear of the entity unit, and / or the bit error rate of the data stored by the entity unit, etc., which are not limited by this invention.

[0098] In one exemplary embodiment, the type of an entity unit may reflect the order position of a bit stored in that entity unit within a plurality of bits stored in a memory unit. Alternatively, in one exemplary embodiment, the memory management circuit 51 may determine the type of an entity unit based on the order position of the bit stored in that entity unit within a plurality of bits stored in a memory unit. For example, suppose a memory unit can store n bits. The memory management circuit 51 may determine the type of the entity unit based on whether the bit stored in that entity unit is the i-th bit among those n bits, for example, determining whether the entity unit belongs to a lower entity unit, a middle entity unit, a lower entity unit, or another type of entity unit.

[0099] In one exemplary embodiment, the order of a bit stored in a first entity unit of the first type within a plurality of bits stored in a memory unit may differ from the order of a bit stored in a second entity unit of the second type within the plurality of bits stored in that memory unit. For example, suppose a memory unit can store n bits. If the bit stored in the first entity unit is the i-th bit among these n bits, and the bit stored in the second entity unit is the j-th bit among these n bits, and i is not equal to j, then the memory management circuit 51 can determine that the type of the first entity unit (i.e., the first type) is different from the type of the second entity unit (i.e., the second type). Then, the memory management circuit 51 can evaluate the performance of the first read operation and the second read operation respectively according to the respective types of the first entity unit and the second entity unit. Alternatively, in one exemplary embodiment, if i is equal to j, then the memory management circuit 51 can determine that the type of the first entity unit (i.e., the first type) is the same as the type of the second entity unit (i.e., the second type).

[0100] In one exemplary embodiment, the execution time of a read operation on a lower entity programmable unit may be shorter than the execution time of a read operation on an upper entity programmable unit, and / or the execution time of a read operation on an upper entity programmable unit may be shorter than the execution time of a read operation on a middle entity programmable unit. Therefore, in one exemplary embodiment, the performance of a read operation on a lower entity programmable unit may be better than the performance of a read operation on an upper entity programmable unit, and / or the performance of a read operation on an upper entity programmable unit may be better than the performance of a read operation on a middle entity programmable unit. However, the performance evaluation method for different types of entity units can also be adjusted according to practical needs, and this invention is not limited thereto.

[0101] In one exemplary embodiment, after the first data obtained through the first read operation and the second data obtained through the second read operation are cached in a buffer in the rewritable non-volatile memory module 43, the memory management circuit 51 may sequentially send a plurality of Direct Memory Access (DMA) instruction sequences to the rewritable non-volatile memory module 43 according to the determined data transfer order. These DMA instruction sequences may at least be used to instruct the rewritable non-volatile memory module 43 to sequentially send out the first data and the second data in the buffer according to the determined data transfer order.

[0102] In one exemplary embodiment, it is assumed that the read instructions received from the host system 11 include a first read instruction and a second read instruction. The first read instruction is used to instruct the reading of data (i.e., first data) from a certain logical unit (also referred to as the first logical unit). The first logical unit is mapped to a first physical unit in a first plane. The second read instruction is used to instruct the reading of data (i.e., second data) from another logical unit (also referred to as the second logical unit). The second logical unit is mapped to a second physical unit in a second plane. Both the first plane and the second plane are located in the first chip enable region.

[0103] According to a first read instruction, the memory management circuit 51 can send a read instruction sequence (also referred to as the first read instruction sequence) to the rewritable non-volatile memory module 43. This first read instruction sequence can be used to instruct the rewritable non-volatile memory module 43 to read first data from a first physical cell in the first plane. Furthermore, according to a second read instruction, the memory management circuit 51 can send another read instruction sequence (also referred to as the second read instruction sequence) to the rewritable non-volatile memory module 43. This second read instruction sequence can be used to instruct the rewritable non-volatile memory module 43 to read second data from a second physical cell in the second plane.

[0104] According to the first read instruction sequence, the rewritable non-volatile memory module 43 can perform a first read operation on the first physical unit to obtain first data and cache the first data in a buffer within the rewritable non-volatile memory module 43. Furthermore, according to the second read instruction sequence, the rewritable non-volatile memory module 43 can perform a second read operation on the second physical unit to obtain second data and cache the second data in the buffer. Then, the rewritable non-volatile memory module 43 can begin waiting for a direct memory access instruction sequence corresponding to the first read operation (or the first read instruction sequence) and / or the second read operation (or the second read instruction sequence).

[0105] In one exemplary embodiment, assuming the determined data transmission order is to receive the first data first and then the second data, the memory management circuit 51 may, according to this data transmission order, first transmit the direct memory access instruction sequence (also referred to as the first direct memory access instruction sequence) corresponding to the first read operation (or the first read instruction) to the rewritable non-volatile memory module 43, and then transmit the direct memory access instruction sequence (also referred to as the second direct memory access instruction sequence) corresponding to the second read operation (or the second read instruction) to the rewritable non-volatile memory module 43. In response to the first received direct memory access instruction sequence, the rewritable non-volatile memory module 43 may first send out the first data in the buffer, for example, through channel 71(0) to the memory management circuit 51. Then, in response to the second received direct memory access instruction sequence, after sending out the first data, the rewritable non-volatile memory module 43 may subsequently send out the second data in the buffer, for example, through the same channel 71(0) to the memory management circuit 51. Conversely, if the determined data transmission order is to receive the second data first and then the first data, then according to this data transmission order, the memory management circuit 51 can first transmit the second direct memory access instruction sequence to the rewritable non-volatile memory module 43, and then transmit the first direct memory access instruction sequence to the rewritable non-volatile memory module 43. Then, the rewritable non-volatile memory module 43 can, according to this data transmission order, send out the second data first and then the first data.

[0106] In one exemplary embodiment, the memory management circuitry 51 may cache multiple received read instructions in at least one instruction queue. In particular, the total number of said at least one instruction queue may be less than the total number of planes in a single chip enable region. Figure 7 For example, assuming the total number of planes in the enable region of a single chip is P, the total number of the at least one instruction queue can be Q, and Q is less than P. For example, P can be 4, 6, or 8, and Q can be 2, and the values ​​of P and Q can be adjusted according to practical needs.

[0107] In one exemplary embodiment, the memory management circuit 51 may cache the first read instruction and the second read instruction in the same instruction queue (also referred to as the first instruction queue) within the at least one instruction queue. The memory management circuit 51 may analyze multiple read instructions (i.e., the first read instruction and the second read instruction) in the first instruction queue without crossing instruction queues to evaluate the performance of the read operations performed corresponding to these read instructions. After sending the read instruction sequence (i.e., the first read instruction sequence and the second read instruction sequence), the memory management circuit 51 may determine the data transmission order based on the performance evaluation results and sequentially receive the multiple data items to be read (i.e., the first data and the second data) according to this data transmission order. The relevant operational details have been described above and will not be repeated here.

[0108] In one exemplary embodiment, the memory management circuit 51 may also cache the first read instruction and the second read instruction in different instruction queues within the at least one instruction queue. For example, the memory management circuit 51 may cache the first read instruction in one instruction queue (i.e., the first instruction queue) and the second read instruction in another instruction queue (i.e., the second instruction queue). Then, the memory management circuit 51 may analyze multiple read instructions (i.e., the first read instruction and the second read instruction) across these instruction queues to evaluate the performance of the read operations performed corresponding to these read instructions. Then, the memory management circuit 51 may determine the data transmission order based on the performance evaluation results and receive the first data and the second data sequentially according to this data transmission order. The relevant operational details have been described above and will not be repeated here.

[0109] In one exemplary embodiment, the memory management circuit 51 may determine whether to cache the read instruction in a specific instruction queue based on the plane in which the physical unit to be read is located, as indicated by the read instruction. For example, in response to a first read instruction for reading data from a first plane, the memory management circuit 51 may cache the first read instruction in a first instruction queue. Furthermore, in response to a second read instruction for reading data from a second plane, the memory management circuit 51 may cache the second read instruction in a second instruction queue.

[0110] In one exemplary embodiment, after determining the data transmission order, the memory management circuit 51 may record information reflecting this data transmission order. For example, the memory management circuit 51 may cache the information reflecting this data transmission order. Figure 5 The buffer memory 55. Then, without adjusting the order of the plurality of read instructions cached in the instruction queue, the memory management circuit 51 can sequentially receive the first data and the second data from the rewritable non-volatile memory module 43 according to this data transmission order.

[0111] Figure 8 This is a schematic diagram illustrating, according to an exemplary embodiment of the present invention, caching multiple read instructions in an instruction queue.

[0112] Please refer to Figure 8 Assume that the read instructions from host system 11 include read instructions CMD(0) to CMD(5). Read instructions CMD(0) to CMD(5) can be cached in instruction queue 81. For example, read instructions CMD(0) to CMD(5) are ordered in instruction queue 81 in a First In First Out (FIFO) manner. Read instruction CMD(0) instructs to read data from a middle programmable unit (labeled page (M)) in plane (3) of the chip enable region CE(0). Read instruction CMD(1) instructs to read data from an upper programmable unit (labeled page (U)) in plane (2) of the chip enable region CE(0). Read instruction CMD(2) instructs to read data from a middle programmable unit in plane (2) of the chip enable region CE(0). The read instruction CMD(3) instructs data to be read from a lower physical programmed unit (labeled as page (L)) in plane (1) of the chip enable region CE(0). The read instruction CMD(4) instructs data to be read from an upper physical programmed unit in plane (0) of the chip enable region CE(0). The read instruction CMD(5) instructs data to be read from a lower physical programmed unit in plane (0) of the chip enable region CE(0). It should be noted that the total number of read instructions CMD(0) to CMD(5), the plane to be accessed by each read instruction, and the type of physical unit to be accessed by each read instruction are all exemplary and are not limited by this invention.

[0113] Figure 9 This is a schematic diagram illustrating the sending of a read instruction sequence and a direct memory access instruction sequence according to a preset rule, as shown in an exemplary embodiment of the present invention.

[0114] Please refer to Figure 8 and Figure 9 In one exemplary embodiment, the memory management circuit 51 can sequentially transmit the read instruction sequence CMS(0) to CMS(5) and the direct memory access instruction sequence DMA(0) to DMA(5) to the rewritable non-volatile memory module 43 according to preset rules and the read instructions CMD(0) to CMD(5) in the instruction sequence 81, so as to read the required data. The specific transmission order of the instruction sequence is as follows: Figure 9 As shown.

[0115] It should be noted that the read instruction sequence CMS(i) and the direct memory access instruction sequence DMA(i) are generated based on the read instruction (i). According to the read instruction sequence CMS(i), the rewritable non-volatile memory module 43 can execute the read operation (i) corresponding to the read instruction CMD(i) and buffer the read data (i) in a buffer inside the rewritable non-volatile memory module 43. Then, according to the direct memory access instruction sequence DMA(i), the rewritable non-volatile memory module 43 can send the data (i) from the buffer and sequentially transfer it to the memory management circuit 51. It should be noted that in... Figure 9 In the exemplary embodiment, the time taken to complete the overall data reading operation corresponding to the read instructions CMD(0) to CMD(5) can be represented by ΔT(1).

[0116] Figure 10 This is a schematic diagram illustrating a performance comparison between caching multiple read instructions in an instruction queue and performing multiple read operations, as shown in an exemplary embodiment of the present invention.

[0117] Please refer to Figure 10 In one exemplary embodiment, the memory management circuit 51 can perform a performance comparison (1) on the read operations corresponding to the read instructions CMD(0) and CMD(1), respectively. For example, in the performance comparison (1), the memory management circuit 51 can compare the execution time of the read operations corresponding to the read instructions CMD(0) and CMD(1), respectively. Furthermore, the memory management circuit 51 can perform a performance comparison (2) on the read operations corresponding to the read instructions CMD(2) and CMD(3), respectively. For example, in the performance comparison (2), the memory management circuit 51 can compare the execution time of the read operations corresponding to the read instructions CMD(2) and CMD(3), respectively.

[0118] Figure 11 This is a schematic diagram illustrating the sending of a read instruction sequence and a direct memory access instruction sequence based on a performance comparison result, according to an exemplary embodiment of the present invention.

[0119] Please refer to Figure 10 and Figure 11 The memory management circuit 51 can continuously send read instruction sequences CMS(0) and CMS(1) to the rewritable non-volatile memory module 43 according to the read instructions CMD(0) and CMD(1) in the instruction sequence 81. In response to the read instruction sequences CMS(0) and CMS(1), planes (2) and (3) in the chip enable region CE(0) can simultaneously or sequentially enter a busy state to perform the corresponding read operation. Then, the rewritable non-volatile memory module 43 can store the read data into the buffer inside the rewritable non-volatile memory module 43.

[0120] On the other hand, based on the performance comparison (1), the memory management circuit 51 can perform sorting (1) on the direct memory access instruction sequences DMA (0) and DMA (1). Based on the sorting result of sorting (1), the memory management circuit 51 can sequentially transmit the direct memory access instruction sequences DMA (1) and DMA (0) to the rewritable non-volatile memory module 43. For example, in response to the performance of reading data from the upper physical programming unit being better than the performance of reading data from the middle physical programming unit, the direct memory access instruction sequence DMA (1) can be transmitted to the rewritable non-volatile memory module 43 before DMA (0). Thus, the data that is read first can be returned to the memory management circuit 51 first, thereby avoiding wasting the bandwidth of channel 71 (0).

[0121] After completing the read instructions CMD(0) and CMD(1), the memory management circuit 51 can continuously send the read instruction sequence CMS(2) and CMS(3) to the rewritable non-volatile memory module 43 according to the read instructions CMD(2) and CMD(3) in the instruction sequence 81. In response to the read instruction sequence CMS(2) and CMS(3), planes (1) and (2) in the chip enable region CE(0) can simultaneously or sequentially enter the busy state to perform the corresponding read operation. Then, the rewritable non-volatile memory module 43 can store the read data into the buffer inside the rewritable non-volatile memory module 43.

[0122] On the other hand, based on the performance comparison (2), the memory management circuit 51 can perform sorting (2) on the direct memory access instruction sequences DMA (2) and DMA (3). Based on the sorting result of sorting (2), the memory management circuit 51 can sequentially transmit the direct memory access instruction sequences DMA (3) and DMA (2) to the rewritable non-volatile memory module 43. For example, in response to the performance of reading data from the lower physical programming unit being better than the performance of reading data from the middle physical programming unit, the direct memory access instruction sequence DMA (3) can be transmitted to the rewritable non-volatile memory module 43 before DMA (2). Thus, the data that is read first can be returned to the memory management circuit 51 first, thereby avoiding wasting the bandwidth of channel 71 (0).

[0123] After completing the read instructions CMD(2) and CMD(3), the memory management circuit 51 can sequentially transmit the read instruction sequence CMS(4) and CMS(5) and the direct memory access instruction sequence DMA(4) and DMA(5) to the rewritable non-volatile memory module 43 according to the remaining read instructions CMD(4) and CMD(5) in the instruction queue 81, in order to read the required data. The specific instruction sequence transmission order is as follows:Figure 11 As shown.

[0124] It should be noted that, in Figure 11 In the exemplary embodiment, the time taken to complete the overall data reading operation corresponding to the read instructions CMD(0) to CMD(5) can be represented by ΔT(2). In particular, under the condition of no special interference, ΔT(2) can be less than ΔT(1), thereby improving the data reading performance.

[0125] Figure 12 This is a schematic diagram illustrating a performance comparison between caching multiple read instructions in multiple instruction queues and performing multiple read operations, as shown in an exemplary embodiment of the present invention.

[0126] Please refer to Figure 12 In one exemplary embodiment, the memory management circuit 51 can cache the read instruction CMD(i) in one of the instruction queues 1201 and 1202 according to the plane to be read by the read instruction CMD(i). For example, in response to the read instructions CMD(0) to CMD(2) being planes (2) and (3) in the chip enable region CE(0), the memory management circuit 51 can store the read instructions CMD(0) to CMD(2) in instruction queue 1201. Furthermore, in response to the read instructions CMD(3) to CMD(5) being planes (0) and (1) in the chip enable region CE(0), the memory management circuit 51 can store the read instructions CMD(3) to CMD(5) in instruction queue 1202.

[0127] The memory management circuit 51 can perform a cross-instruction queue performance comparison (1) on the read operations corresponding to the read instructions CMD(0) and CMD(3), respectively. For example, in the performance comparison (1), the memory management circuit 51 can compare the execution time of the read operations corresponding to the read instructions CMD(0) and CMD(3), respectively. Similarly, the memory management circuit 51 can perform a cross-instruction queue performance comparison (2) on the read operations corresponding to the read instructions CMD(1) and CMD(4), respectively. For example, in the performance comparison (2), the memory management circuit 51 can compare the execution time of the read operations corresponding to the read instructions CMD(1) and CMD(4), respectively. Similarly, the memory management circuit 51 can perform a cross-instruction queue performance comparison (3) on the read operations corresponding to the read instructions CMD(2) and CMD(5), respectively. For example, in the performance comparison (3), the memory management circuit 51 can compare the execution time of the read operations corresponding to the read instructions CMD(2) and CMD(5), respectively.

[0128] Figure 13This is a schematic diagram illustrating the sending of a read instruction sequence and a direct memory access instruction sequence based on a performance comparison result, according to an exemplary embodiment of the present invention.

[0129] Please refer to Figure 12 and Figure 13 The memory management circuit 51 can continuously send read instruction sequences CMS(0) and CMS(3) to the rewritable non-volatile memory module 43 according to the read instructions CMD(0) and CMD(3) in the instruction sequences 1201 and 1202. In response to the read instruction sequences CMS(0) and CMS(3), planes (1) and (3) in the chip enable region CE(0) can simultaneously or sequentially enter a busy state to perform the corresponding read operation. Then, the rewritable non-volatile memory module 43 can store the read data into the buffer inside the rewritable non-volatile memory module 43.

[0130] On the other hand, based on the performance comparison (1), the memory management circuit 51 can perform sorting (1) on the direct memory access instruction sequences DMA (0) and DMA (3). Based on the sorting result of sorting (1), the memory management circuit 51 can sequentially transmit the direct memory access instruction sequences DMA (3) and DMA (0) to the rewritable non-volatile memory module 43. For example, in response to the performance of reading data from the lower physical programming unit being better than the performance of reading data from the middle physical programming unit, the direct memory access instruction sequence DMA (3) can be transmitted to the rewritable non-volatile memory module 43 before DMA (0). Thus, the data that is read first can be returned to the memory management circuit 51 first, thereby avoiding wasting the bandwidth of channel 71 (0).

[0131] After completing the read instructions CMD(0) and CMD(3), the memory management circuit 51 can continuously send the read instruction sequence CMS(1) and CMS(4) to the rewritable non-volatile memory module 43 according to the read instructions CMD(1) and CMD(4) in the instruction sequence 1201 and 1202. In response to the read instruction sequence CMS(1) and CMS(4), plane (0) and plane (2) in the chip enable region CE(0) can simultaneously or sequentially enter the busy state to perform the corresponding read operation. Then, the rewritable non-volatile memory module 43 can store the read data into the buffer inside the rewritable non-volatile memory module 43.

[0132] On the other hand, based on the performance comparison (2), the memory management circuit 51 can perform sorting (2) on the direct memory access instruction sequences DMA (1) and DMA (4). Based on the sorting result of sorting (2), the memory management circuit 51 can sequentially transmit the direct memory access instruction sequences DMA (1) and DMA (4) to the rewritable non-volatile memory module 43. It should be noted that in this example, both read instructions CMD (1) and CMD (4) are for reading data from the upper-level programmed unit, so there is no difference in read performance between the two. Therefore, the direct memory access instruction sequence DMA (1) can be transmitted to the rewritable non-volatile memory module 43 before or after DMA (4). Whether the direct memory access instruction sequence DMA (1) or DMA (4) is transmitted first, it does not affect the bandwidth of channel 71 (0).

[0133] After completing the read instructions CMD(1) and CMD(4), the memory management circuit 51 can continuously send the read instruction sequence CMS(2) and CMS(5) to the rewritable non-volatile memory module 43 according to the read instructions CMD(2) and CMD(5) in the instruction sequence 1201 and 1202. In response to the read instruction sequence CMS(2) and CMS(5), plane (0) and plane (2) in the chip enable region CE(0) can simultaneously or sequentially enter the busy state to perform the corresponding read operation. Then, the rewritable non-volatile memory module 43 can store the read data into the buffer inside the rewritable non-volatile memory module 43.

[0134] On the other hand, based on the performance comparison (3), the memory management circuit 51 can perform sorting (3) on the direct memory access instruction sequences DMA (2) and DMA (5). Based on the sorting result of sorting (3), the memory management circuit 51 can sequentially transmit the direct memory access instruction sequences DMA (5) and DMA (2) to the rewritable non-volatile memory module 43. For example, in response to the performance of reading data from the lower physical programming unit being better than the performance of reading data from the middle physical programming unit, the direct memory access instruction sequence DMA (5) can be transmitted to the rewritable non-volatile memory module 43 before DMA (2). Thus, the data that is read first can be returned to the memory management circuit 51 first, thereby avoiding wasting the bandwidth of channel 71 (0). The specific transmission order of the instruction sequence is as follows: Figure 13 As shown.

[0135] It should be noted that, in Figure 13In the exemplary embodiment, the time taken to complete the overall data reading operation corresponding to the read instructions CMD(0) to CMD(5) can be represented by ΔT(3). In particular, under the condition of no special interference, ΔT(3) can be less than ΔT(2), thereby improving the data reading performance.

[0136] Figure 14 This is a schematic diagram illustrating a performance comparison between caching multiple read instructions in multiple instruction queues and performing multiple read operations, as shown in an exemplary embodiment of the present invention.

[0137] Please refer to Figure 14 In one exemplary embodiment, the memory management circuit 51 may perform a cross-instruction-series performance comparison (1) on the read operations corresponding to the read instructions CMD(0), CMD(1), CMD(3), and CMD(4), respectively. For example, in the performance comparison (1), the memory management circuit 51 may compare the execution time of the read operations corresponding to the read instructions CMD(0), CMD(1), CMD(3), and CMD(4), respectively. Similarly, the memory management circuit 51 may perform a cross-instruction-series performance comparison (2) on the read operations corresponding to the read instructions CMD(2) and CMD(5), respectively. For example, in the performance comparison (2), the memory management circuit 51 may compare the execution time of the read operations corresponding to the read instructions CMD(2) and CMD(5), respectively.

[0138] Figure 15 This is a schematic diagram illustrating the sending of a read instruction sequence and a direct memory access instruction sequence based on a performance comparison result, according to an exemplary embodiment of the present invention.

[0139] Please refer to Figure 14 and Figure 15 The memory management circuit 51 can continuously send the read instruction sequence CMS(0), CMS(1), CMS(3), and CMS(4) to the rewritable non-volatile memory module 43 according to the read instructions CMD(0), CMD(1), CMD(3), and CMD(4) in the instruction sequence 1201 and 1202. In response to the read instruction sequence CMS(0), CMS(1), CMS(3), and CMS(4), planes (0) to (3) in the chip enable region CE(0) can simultaneously or sequentially enter a busy state to perform the corresponding read operation. Then, the rewritable non-volatile memory module 43 can store the read data into the buffer inside the rewritable non-volatile memory module 43.

[0140] On the other hand, based on the performance comparison (1), the memory management circuit 51 can perform sorting (1) on the direct memory access instruction sequence DMA (0), DMA (1), DMA (3), and DMA (4). Based on the sorting result of sorting (1), the memory management circuit 51 can sequentially transmit the direct memory access instruction sequence DMA (3), DMA (1), DMA (4), and DMA (0) to the rewritable non-volatile memory module 43. Thus, the data that is read first can be returned to the memory management circuit 51 first, thereby avoiding wasting the bandwidth of channel 71 (0).

[0141] After completing the read instructions CMD(0), CMD(1), CMD(3), and CMD(4), the memory management circuit 51 can continuously send the read instruction sequence CMS(2) and CMS(5) to the rewritable non-volatile memory module 43 according to the read instructions CMD(2) and CMD(5) in the instruction sequences 1201 and 1202. In response to the read instruction sequence CMS(2) and CMS(5), planes (0) and (2) in the chip enable region CE(0) can simultaneously or sequentially enter a busy state to perform the corresponding read operation. Then, the rewritable non-volatile memory module 43 can store the read data into the buffer inside the rewritable non-volatile memory module 43. Furthermore, based on the performance comparison (2), the memory management circuit 51 can perform sorting (2) on the direct memory access instruction sequences DMA (2) and DMA (5) and sequentially transmit the direct memory access instruction sequences DMA (5) and DMA (2) to the rewritable non-volatile memory module 43. Thus, the data that is read first can be returned to the memory management circuit 51 first, thereby avoiding wasting the bandwidth of channel 71 (0).

[0142] It should be noted that, in Figure 15 In the exemplary embodiment, the time taken to complete the overall data reading operation corresponding to the read instructions CMD(0) to CMD(5) can be represented by ΔT(4). In particular, under the condition of no special interference, ΔT(4) can be less than ΔT(3), thereby improving the data reading performance.

[0143] Figure 16 This is a flowchart illustrating a data reading method according to an exemplary embodiment of the present invention.

[0144] Please refer to Figure 16In step S1601, multiple read instructions are received from the host system, wherein the multiple read instructions are at least used to instruct the reading of first data stored in the first plane and second data stored in the second plane. In step S1602, a multiple read instruction sequence is sent to the rewritable non-volatile memory module according to the multiple read instructions, wherein the multiple read instruction sequence is at least used to instruct the execution of a first read operation on the first plane to obtain the first data and a second read operation on the second plane to obtain the second data. In step S1603, the data transmission order is determined based on the performance of the first read operation and the second read operation. In step S1604, the first data and the second data are received sequentially from the rewritable non-volatile memory module according to the data transmission order.

[0145] However, Figure 16 Each step has been explained in detail above and will not be repeated here. It is worth noting that... Figure 16 Each step can be implemented as multiple program codes or circuits, and this invention is not limited thereto. Furthermore, Figure 16 The method can be used in conjunction with the above examples and embodiments, or it can be used alone. This invention does not impose any limitations.

[0146] In summary, upon receiving multiple read commands from the host system, a sequence of read commands can be sent accordingly. This sequence of read commands can instruct data read operations to be performed on different planes within the same chip enable region. A data transfer order can be determined based on the performance of the performed data read operations. Subsequently, according to this data transfer order, the data read from these planes can be sequentially sent from the rewritable non-volatile memory module in a customized order. This improves the data read performance for different planes within the same chip enable region.

[0147] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A data reading method, characterized in that, A rewritable non-volatile memory module is used, wherein the rewritable non-volatile memory module includes multiple chip enable regions, a first chip enable region among the multiple chip enable regions includes multiple planes, the multiple planes include a first plane and a second plane, and the data reading method includes: Receive multiple read instructions from the host system, wherein the multiple read instructions are at least used to instruct the reading of first data stored in the first plane and second data stored in the second plane; According to the plurality of read instructions, a plurality of read instruction sequences are sent to the rewritable non-volatile memory module, wherein the plurality of read instruction sequences are at least used to instruct the first plane to perform a first read operation to obtain the first data and the second plane to perform a second read operation to obtain the second data; The performance of the first read operation and the second read operation is compared to obtain the comparison result; Based on the comparison result, the first direct memory access instruction sequence corresponding to the first read operation and the second direct memory access instruction sequence corresponding to the second read operation are sorted to obtain a sorting result. Both the first and second direct memory access instruction sequences are used to read data from the buffer of the rewritable non-volatile memory module through a specific channel after the first read operation for the first plane and the second read operation for the second plane are executed synchronously. Based on the sorting result, the first direct memory access instruction sequence and the second direct memory access instruction sequence are sent sequentially to the rewritable non-volatile memory module to read the first data and the second data from the buffer.

2. The data reading method according to claim 1 further includes: In response to the fact that the performance of the first read operation is better than that of the second read operation, the data transmission order is determined to receive the first data first and then the second data.

3. The data reading method according to claim 1, wherein the efficiency of the first reading operation and the second reading operation is reflected by the first execution time length of the first reading operation and the second execution time length of the second reading operation.

4. The data reading method according to claim 1, wherein the step of performing the performance comparison between the first reading operation and the second reading operation to obtain the comparison result includes: The performance of the first read operation and the second read operation is evaluated based on the first type of the first entity unit storing the first data in the first plane and the second type of the second entity unit storing the second data in the second plane.

5. The data reading method according to claim 4, wherein the sorting position of a bit stored in the first entity unit of the first type in a plurality of bits stored in a storage unit is different from the sorting position of a bit stored in the second entity unit of the second type in the plurality of bits stored in the storage unit.

6. The data reading method according to claim 1, wherein the first data obtained by the first read operation and the second data obtained by the second read operation are cached in the buffer of the rewritable non-volatile memory module.

7. The data reading method according to claim 1, further comprising: The received read instructions are cached in at least one instruction queue, and the total number of the at least one instruction queue is less than the total number of the multiple planes.

8. The data reading method according to claim 7, wherein the plurality of read instructions includes a first read instruction and a second read instruction, the first read instruction being used to instruct the reading of the first data stored in the first plane, the second read instruction being used to instruct the reading of the second data stored in the second plane, and the step of caching the received plurality of read instructions in the at least one instruction queue includes: The first read instruction and the second read instruction are cached in the first instruction queue of the at least one instruction queue.

9. The data reading method according to claim 7, wherein the plurality of read instructions includes a first read instruction and a second read instruction, the first read instruction being used to instruct the reading of the first data stored in the first plane, the second read instruction being used to instruct the reading of the second data stored in the second plane, and the step of caching the received plurality of read instructions in the at least one instruction queue includes: The first read instruction is cached in the first instruction queue of the at least one instruction queue; as well as The second read instruction is cached in the second instruction queue of the at least one instruction queue.

10. The data reading method according to claim 1, further comprising: Record information reflecting the order of data transmission; as well as Without adjusting the order of the plurality of read instructions cached in at least one instruction queue, the first data and the second data are received sequentially from the rewritable non-volatile memory module according to the data transmission order.

11. A memory storage device, characterized in that, include: A connection interface unit for connecting to the host system; A rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes multiple chip enable regions, a first chip enable region among the multiple chip enable regions including multiple planes, and the multiple planes including a first plane and a second plane; and The memory control circuit unit is connected to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit is used to: The host system receives multiple read instructions, wherein the multiple read instructions are at least used to instruct the reading of first data stored in the first plane and second data stored in the second plane; According to the plurality of read instructions, a plurality of read instruction sequences are sent to the rewritable non-volatile memory module, wherein the plurality of read instruction sequences are at least used to instruct the first plane to perform a first read operation to obtain the first data and the second plane to perform a second read operation to obtain the second data; The performance of the first read operation and the second read operation is compared to obtain the comparison result; Based on the comparison result, the first direct memory access instruction sequence corresponding to the first read operation and the second direct memory access instruction sequence corresponding to the second read operation are sorted to obtain a sorting result. The first direct memory access instruction sequence and the second direct memory access instruction sequence are both used to read data from the buffer of the rewritable non-volatile memory module through a specific channel after the first read operation for the first plane and the second read operation for the second plane are executed synchronously. as well as Based on the sorting result, the first direct memory access instruction sequence and the second direct memory access instruction sequence are sent sequentially to the rewritable non-volatile memory module to read the first data and the second data from the buffer.

12. The memory storage device according to claim 11, wherein the memory control circuit unit is further configured to: In response to the fact that the performance of the first read operation is better than that of the second read operation, the data transmission order is determined to receive the first data first and then the second data.

13. The memory storage device according to claim 11, wherein the performance of the first read operation and the second read operation is reflected by the first execution time length of the first read operation and the second execution time length of the second read operation.

14. The memory storage device of claim 11, wherein the operation of the memory control circuit unit performing the performance comparison between the first read operation and the second read operation to obtain the comparison result includes: The performance of the first read operation and the second read operation is evaluated based on the first type of the first entity unit storing the first data in the first plane and the second type of the second entity unit storing the second data in the second plane.

15. The memory storage device of claim 14, wherein the sorting position of a bit stored in the first entity unit of the first type among a plurality of bits stored in a storage unit is different from the sorting position of a bit stored in the second entity unit of the second type among the plurality of bits stored in the storage unit.

16. The memory storage device of claim 11, wherein the first data obtained by the first read operation and the second data obtained by the second read operation are cached in the buffer of the rewritable non-volatile memory module.

17. The memory storage device according to claim 11, wherein the memory control circuit unit is further configured to: The received read instructions are cached in at least one instruction queue, and the total number of the at least one instruction queue is less than the total number of the multiple planes.

18. The memory storage device of claim 17, wherein the plurality of read instructions includes a first read instruction and a second read instruction, the first read instruction instructing the reading of the first data stored in the first plane, the second read instruction instructing the reading of the second data stored in the second plane, and the operation of the memory control circuit unit caching the received plurality of read instructions in the at least one instruction queue includes: The first read instruction and the second read instruction are cached in the first instruction queue of the at least one instruction queue.

19. The memory storage device of claim 17, wherein the plurality of read instructions includes a first read instruction and a second read instruction, the first read instruction instructing the reading of the first data stored in the first plane, the second read instruction instructing the reading of the second data stored in the second plane, and the operation of the memory control circuit unit caching the received plurality of read instructions in the at least one instruction queue includes: The first read instruction is cached in the first instruction queue of the at least one instruction queue; as well as The second read instruction is cached in the second instruction queue of the at least one instruction queue.

20. The memory storage device according to claim 17, wherein the memory control circuit unit is further configured to: Record information reflecting the order of data transmission; and Without adjusting the order of the plurality of read instructions cached in the at least one instruction queue, the first data and the second data are received sequentially from the rewritable non-volatile memory module according to the data transmission order.

21. A memory control circuit unit, characterized in that, This is used to control a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes multiple chip enable regions, the first chip enable region among the multiple chip enable regions includes multiple planes, the multiple planes include a first plane and a second plane, and the memory control circuit unit includes: Host interface, used to connect to the host system; A memory interface for connecting to the rewritable non-volatile memory module; and The memory management circuit is connected to the host interface and the memory interface. The memory management circuit mentioned above is used for: The host system receives multiple read instructions, wherein the multiple read instructions are at least used to instruct the reading of first data stored in the first plane and second data stored in the second plane; According to the plurality of read instructions, a plurality of read instruction sequences are sent to the rewritable non-volatile memory module, wherein the plurality of read instruction sequences are at least used to instruct the first plane to perform a first read operation to obtain the first data and the second plane to perform a second read operation to obtain the second data; The performance of the first read operation and the second read operation is compared to obtain the comparison result; Based on the comparison result, the first direct memory access instruction sequence corresponding to the first read operation and the second direct memory access instruction sequence corresponding to the second read operation are sorted to obtain a sorting result. Both the first and second direct memory access instruction sequences are used to read data from the buffer of the rewritable non-volatile memory module through a specific channel after the first read operation for the first plane and the second read operation for the second plane are executed synchronously. Based on the sorting result, the first direct memory access instruction sequence and the second direct memory access instruction sequence are sent sequentially to the rewritable non-volatile memory module to read the first data and the second data from the buffer.

22. The memory control circuit unit according to claim 21, wherein the memory management circuit is further configured to: In response to the fact that the performance of the first read operation is better than that of the second read operation, the data transmission order is determined to receive the first data first and then the second data.

23. The memory control circuit unit according to claim 21, wherein the performance of the first read operation and the second read operation is reflected by the first execution time length of the first read operation and the second execution time length of the second read operation.

24. The memory control circuit unit of claim 21, wherein the operation of the memory management circuit performing the performance comparison between the first read operation and the second read operation to obtain the comparison result includes: The performance of the first read operation and the second read operation is evaluated based on the first type of the first entity unit storing the first data in the first plane and the second type of the second entity unit storing the second data in the second plane.

25. The memory control circuit unit of claim 24, wherein the sorting position of a bit stored in the first entity unit of the first type in a plurality of bits stored in a memory unit is different from the sorting position of a bit stored in the second entity unit of the second type in the plurality of bits stored in the memory unit.

26. The memory control circuit unit of claim 21, wherein the first data obtained by the first read operation and the second data obtained by the second read operation are cached in the buffer of the rewritable non-volatile memory module.

27. The memory control circuit unit of claim 21, wherein the memory management circuit is further configured to: The received read instructions are cached in at least one instruction queue, and the total number of the at least one instruction queue is less than the total number of the multiple planes.

28. The memory control circuit unit of claim 27, wherein the plurality of read instructions includes a first read instruction and a second read instruction, the first read instruction being used to instruct the reading of the first data stored in the first plane, the second read instruction being used to instruct the reading of the second data stored in the second plane, and the operation of the memory management circuit caching the received plurality of read instructions in the at least one instruction queue includes: The first read instruction and the second read instruction are cached in the first instruction queue of the at least one instruction queue.

29. The memory control circuit unit of claim 27, wherein the plurality of read instructions includes a first read instruction and a second read instruction, the first read instruction being used to instruct the reading of the first data stored in the first plane, the second read instruction being used to instruct the reading of the second data stored in the second plane, and the operation of the memory management circuit caching the received plurality of read instructions in the at least one instruction queue includes: The first read instruction is cached in the first instruction queue of the at least one instruction queue; as well as The second read instruction is cached in the second instruction queue of the at least one instruction queue.

30. The memory control circuit unit according to claim 21, wherein the memory management circuit is further configured to: Record information reflecting the order of data transmission; and Without adjusting the order of the plurality of read instructions cached in at least one instruction queue, the first data and the second data are received sequentially from the rewritable non-volatile memory module according to the data transmission order.

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