A multi-core processor task migration and power consumption adjustment method and architecture based on performance monitoring mechanism

Abstract

The present invention relates to a multi-core processor task migration and power consumption adjustment method and architecture based on a performance monitoring mechanism, comprising: setting the multi-core processor's operating mode to a balanced mode via an operating system; a performance monitoring module performing real-time monitoring of the decoding unit, transmitting unit, and retiring unit of each processor core; a task allocation module relying on the operating system to read the real-time monitoring results of the performance monitoring module, then calculating and analyzing the load of each processor core, and then adjusting the task allocation of each processor core and controlling the sleep and wakeup of each processor core using a pre-set task allocation strategy; and a multi-core power consumption control module receiving instructions from the task allocation module and implementing the sleep or wakeup state of the processor cores via a power management unit. The present invention not only proposes a processor core sleep and wakeup mechanism based on a priority history table, but also achieves dynamic balancing of the power consumption of the multi-core processor.

Description

Technical Field

[0001] The present invention relates to a multi-core processor task migration and power consumption adjustment method and architecture based on a performance monitoring mechanism, and belongs to the technical field of integrated circuit processor design. Background Art

[0002] With the rapid advancement of semiconductor process technology and the integrated circuit industry, the performance of single-core processors has increased dramatically, and their power consumption has also increased accordingly. The approaching performance limits of single-core processors has prompted attempts to achieve architectural breakthroughs, introducing parallel processing to improve overall processor performance. The mainstream of processor development has shifted from single-core to multi-core. The most common architecture of modern multi-core processors uses an on-chip bus to connect multiple processor cores, coupled with inter-core communication mechanisms such as shared memory and inter-core messaging to achieve thread-level parallelism. However, as the power consumption of a single core increases and the number of cores increases, the power consumption of multi-core processors increases linearly. During the operation of a multi-core processor, performance requirements decrease in low-load and idle scenarios. Running multiple cores simultaneously at high power consumption wastes performance and increases operating costs. Monitoring the operating load of a single core and dynamically adjusting task allocation across multiple cores are crucial for reducing the power consumption of multi-core processors.

[0003] A performance monitoring mechanism and power consumption dynamic balancing method specifically designed for multi-core processors are designed. Task balancing and migration are completed in the operating system, and tasks of each processor core are dynamically adjusted, which can significantly reduce the power consumption of multi-core processors. Summary of the Invention

[0004] In response to the shortcomings of the existing technology, the present invention provides a multi-core processor task migration and power consumption adjustment method and architecture based on a performance monitoring mechanism, which utilizes a multi-core interconnect bus structure for data transmission and interaction, utilizes the onboard operating system to allocate and manage processor core tasks, and utilizes sedimentation tank monitoring, hardware key signal monitoring and other methods to realize the monitoring of each processor core load.

[0005] Explanation of terms:

[0006] 1. Multi-core processor: a system composed of multiple processor cores interconnected.

[0007] The technical solution of the present invention is:

[0008] An architecture for a performance monitoring mechanism for a multi-core processor, comprising J processor cores, a performance monitoring module, a task allocation module, a multi-core power consumption control module, and a power management module, where J is a positive integer greater than or equal to 2;

[0009] Each processor core includes M decoding units, M transmitting units, and N retirement units, where M, N, and K are all positive integers;

[0010] The performance monitoring module is used to monitor the performance of the decoding unit, the transmitting unit, and the retirement unit of a single processor core;

[0011] The task allocation module is used to read the real-time monitoring results of the performance monitoring module, calculate the load of each processor core and allocate tasks according to the set task allocation strategy;

[0012] The multi-core power consumption control module is coupled with the power management module. The multi-core power consumption control module is used to receive the task assignment command from the task assignment module and then control the power management module. The power management module is used to control the switching, sleep and wake-up of the processor core; the multi-core power consumption control module realizes the sleep and wake-up of a single processor core through the power management module.

[0013] Preferably, according to the present invention, each processor core supports a multi-core interconnection bus structure, and the performance monitoring module communicates data with the task allocation module through the multi-core interconnection bus structure; the performance monitoring module collects the operating indicators of the decoding unit, the transmitting unit and the retirement unit of a single processor core through a monitor with a preset period, and the performance monitoring module supports multi-channel monitoring.

[0014] A method for multi-core processor task migration and power consumption adjustment based on a performance monitoring mechanism, based on the architecture, specifically includes:

[0015] (1) After J processor cores are powered on, they default to the J-core working mode, and the operating mode of the multi-core processor is set to the balanced mode through the operating system;

[0016] (2) The performance monitoring module monitors the decoding unit, transmitting unit, and retirement unit of each processor core in real time;

[0017] (3) The task allocation module relies on the operating system of the multi-core processor to read the real-time monitoring results of the performance monitoring module, and then calculates and analyzes the load of each processor core. It then adjusts the task allocation of each processor core and controls the sleep and wake-up of each processor core through a pre-set task allocation strategy;

[0018] (4) The multi-core power consumption control module receives instructions from the task allocation module and then controls the power management unit to realize the sleep or wake-up state of the processor core through the power management unit;

[0019] When the processor core is in the awake state, it accepts new task requests from the task allocation module and exchanges data with the shared cache through the multi-core interconnect bus;

[0020] When the task allocation module sends a sleep command to the awakened processor core, the processor core will complete all current tasks and enter the sleep state;

[0021] When a processor core is in a dormant state, it no longer accepts new task requests from the task allocation module, and the multi-core interconnect bus only transmits wake-up and sleep signals to the dormant processor core.

[0022] According to the preferred embodiment of the present invention, in step (1), the operating modes of the system include low power consumption mode, performance mode and balanced mode, specifically:

[0023] When low-power mode is enabled, the task allocation and core sleep / wake-up strategies change. To achieve lower power consumption, the multi-core processor only starts one core. The task allocation module reads the priority history table and selects the core with the highest priority to work alone. The other J-1 cores are put into sleep mode. All tasks of the operating system are handled by the active processor core, and the multi-core processor runs in extremely low-power mode.

[0024] When performance mode is enabled, all J processor cores remain awake regardless of the load on each core. The task allocation module does not intervene in the specific task allocation method, which is determined by the operating system and application programs. The simultaneous operation of all J processor cores maximizes processor performance.

[0025] When the balanced mode is turned on, the task allocation module starts working, and the multi-core processors involved share the last level cache (Last Level Cache). Therefore, when a task is migrated, all data in the current core pipeline must be processed and written to the last level cache through the intra-core bus; when the balanced mode is turned on, the task allocation module will analyze the load of each core; if the analysis result shows that J cores do not need to work simultaneously, the task allocation module will reasonably allocate tasks and wake up and sleep the cores based on the analysis result, concentrating the tasks on one or two processor cores with the highest priority, and the other processor cores will be put into sleep.

[0026] According to a preferred embodiment of the present invention, in step (2), the performance monitoring module performs real-time monitoring on the decoding unit, the transmitting unit, and the retirement unit of each processor core, specifically including:

[0027] The decoding unit includes multiple decoding modules, namely DEC0, DEC1...DECn, and can decode up to n instructions per cycle;

[0028] The launch unit includes a command sink, which serves as a temporary storage station for multiple launch commands. A performance monitoring module is set up in the command sink. There are C temporary storage stations in total, and the depth of each temporary storage station is X.

[0029] The retirement unit is mainly responsible for retiring the executed instructions to release the register renaming table. It can retire up to n instructions per cycle.

[0030] The performance monitoring module monitors the decoding results of the decoding unit, and counts the number of decodes within a certain clock cycle, the occupancy rate of each temporary storage station in the transmitting unit, and the number of retired instructions in the retirement unit.

[0031] According to a preferred embodiment of the present invention, in step (3), the priorities of the J processor cores are set through software configuration, and the processor core with the highest priority is used first, and the priorities are dynamically cyclically configured according to the software configuration; the task allocation module collects the load conditions of each of the J processor cores through the multi-core interconnection bus, and when allocating tasks, the tasks are allocated to the processor core with the highest priority first, and a sleep instruction is issued to the other processor cores that are about to sleep;

[0032] When the task load of a single processor core reaches the threshold, other dormant processor cores are awakened and tasks are dynamically scheduled to meet processor performance requirements.

[0033] According to a preferred embodiment of the present invention, in step (3), the operating system calculates and analyzes the load of the processor core, and the specific process is:

[0034] Considering the differences between different temporary storage stations, operation and jump instructions can be completed in a short cycle, so operation instructions and jump instructions are short-cycle instructions; while load instructions, write-back instructions and floating-point operation instructions are long-cycle instructions;

[0035] (1) For a certain processor core, the occupancy rates of the temporary storage stations in the emission unit corresponding to the short-cycle instructions and the long-cycle instructions within a certain clock cycle are counted, and the occupancy rates of the temporary storage stations corresponding to the long-cycle instructions are weighted. The data of the temporary storage stations corresponding to the short-cycle instructions do not need to be weighted;

[0036] Assume that the occupancy rate of the temporary storage station corresponding to the short-cycle instruction within a certain cycle is a p The occupancy rate of the temporary storage station corresponding to the long-cycle instruction in a certain cycle is b q , the weights of the temporary storage stations corresponding to the long-cycle instructions are f q , the number of detection cycles is T, then the total occupancy rate z0 of the transmitting unit satisfies:

[0037] Total occupancy z0=(a1+a2+a3+…a p)+(f1b1+f2b2+f3b3+f4b4+f5b5+…f q b q ) / X*C*T; (I)

[0038] In formula (I), X represents the depth of each temporary storage station, C represents the number of temporary storage stations; p Indicates the total number of occupied temporary stations corresponding to the p-th short-cycle instruction within a certain cycle, b q Indicates the total number of occupied temporary stations corresponding to the qth long-cycle instruction within a certain cycle, f q represents the weight of the temporary storage station corresponding to the qth long cycle instruction;

[0039] (2) The occupancy rate of the decoding unit is the occupancy rate of the decoding level. The number of detection cycles is T, the maximum number of instructions that can be decoded in a single cycle of the decoding level is n, and the number of instructions that are detected to be decoded in the detection cycle is D. Then the total occupancy rate z1 of the decoding level satisfies:

[0040] Total occupancy z1 = D / n*T (II),

[0041] (3) The method for calculating the occupancy rate of the retirement unit is the same as that of the decoding unit. The number of detection cycles is T, the maximum number of instructions that can be retired in a single cycle of the retirement level is n, and the number of instructions that are detected to be decoded in the detection cycle is R. Then the total occupancy rate z2 of the decoding level satisfies:

[0042] Total occupancy z2 = R / n*T (III),

[0043] According to the statistical occupancy of the decoding unit, the transmitting unit, and the retirement unit, the total load Z of a single core is obtained according to the empirical formula in processor design:

[0044] Z=0.25*z0+0.5*z1+0.25*z2 (IV),

[0045] In formula (IV), z0 represents the total occupancy rate of the decoding unit, z1 represents the total occupancy rate of the transmitting unit, and z2 represents the total occupancy rate of the retired unit; 0.25 and 0.5 in formula (IV) are empirical formulas;

[0046] Monitor and count the number of retired instructions within a certain clock cycle and analyze it together with the data from the decode unit and the transmit unit to obtain the execution status of the instructions and the load of a single core processor, specifically:

[0047] Assuming that the number of cores in a multi-core processor is m, the total load P of the multi-core processor is:

[0048] P=Z(0)+Z(1)+Z(2)+…Z(m) / m; (V)

[0049] In formula (V), Z(m) represents the total load of the mth processor core.

[0050] According to the preferred embodiment of the present invention, in the balanced mode, according to the total load of the multi-core processor, the multi-core wake-up and sleep modes are specifically divided into four working modes, namely:

[0051] (1) When the total load of the multi-core processor is less than 5%, the task allocation module only retains the highest priority core for task allocation, and performs pre-sleep processing on the other J-1 cores; pre-sleep processing means that the dormant processor core will no longer perform new tasks and no longer retrieve data from the shared cache during the dormant process; pre-sleep processing needs to wait until the corresponding processor core completes all instructions in the pipeline and writes them back to the shared cache; when the dormant J-1 cores send a ready signal, the task allocation module will adjust the task allocation mode, and the processor will be adjusted to a single-core working mode. At the same time, it will pass instructions to the multi-core power consumption control module to put the other J-1 low-priority processor cores to sleep, and the dormant cores will enter an extremely low power consumption mode and wait to be awakened;

[0052] (2) When the total load of the multi-core processor is greater than 5% and less than 15%, the task allocation module will issue a pre-sleep process to J-2 cores of priority 3 to priority J; the sleep strategy is as described in the first mode. When the J-2 sleeping cores send a ready signal, the task allocation module will adjust the task allocation mode, and the multi-core processor will be adjusted to a dual-core working mode. At the same time, it will pass instructions to the multi-core power consumption control module to put the J-2 low-priority processor cores to sleep. The sleeping cores will enter an extremely low power consumption mode and wait until the task allocation module wakes them up;

[0053] (3) When the total load of the multi-core processor is greater than 15% and less than 20%, the task allocation module will issue a pre-sleep process to J-3 cores of priority 4 to priority J; the sleep strategy is as described in the first mode. When the J-3 sleeping cores send a ready signal, the task allocation module will adjust the task allocation mode, and the multi-core processor will be adjusted to a three-core working mode. At the same time, it will pass instructions to the multi-core power consumption control module to put the J-3 low-priority processor cores to sleep. The sleeping cores will enter an extremely low power consumption mode and wait for the task allocation module to wake them up;

[0054] (4) When the combined load of each processor core is greater than 20%, the task allocation module does not allocate tasks to the core and does not perform sleep processing, maintaining the J core working mode to ensure the high performance operation of the multi-core processor.

[0055] According to a preferred embodiment of the present invention, after the J core processors are powered on, they default to the J core working mode, and the default priorities of the J cores are all binary code 000. When a core is put to sleep, the priority of the core is increased by one; when the core is awakened, the priority of the core is reduced by one.

[0056] Each dormant core will restart after receiving the wake-up signal and wake up in sequence according to the priority of each core. In balanced mode, the priority of each core adopts polling mode, and a three-bit status bit is used to represent the priority status of each processor core. 000 represents the lowest priority 0, 001 represents the priority 1, and so on. 111 represents the highest priority 7.

[0057] Further preferably, when the task allocation module needs to improve performance and enter a more core working mode, the processor core with the highest priority is awakened according to the priority history table;

[0058] When the task allocation module needs to reduce power consumption and enter a reduced-core operation mode, it puts the processor core with the lowest priority into sleep mode according to the priority history table. This wake-up and sleep mechanism ensures that the processor cores of the multi-core processor are in a polling state and that the performance meets the requirements of the operating system.

[0059] According to the preferred embodiment of the present invention, when the task allocation module performs task reallocation and core sleep processing, it reads the information of the priority history table of each processor core;

[0060] Each processor core is provided with six table entries for recording the priority status of the processor core and updating the value of the priority history table according to the set sampling period; the priority history table stores the priorities of the most recent six set sampling periods;

[0061] Further preferably, when processor cores with the same priority appear, the core with the largest number of high priorities closest to the current time in the priority history table of the processor core will be given priority to maintain the working state, while the current priority remains unchanged, and the priority of other cores with the same priority is reduced by one. With the help of this mechanism, the priority history table can enter a normal circulation state, ensuring the normal operation of the power consumption balance system.

[0062] This paper proposes a multi-core real-time scheduling task allocation strategy. When multiple periodic tasks are assigned to J processor cores, the cores are first put to sleep and awakened based on the load within a clock cycle as monitored by a performance monitoring module, and then tasks are allocated. This task allocation strategy follows the principle of combinatorial optimization and relies on the utilization of each core to maximize the parallel execution of tasks and fully utilize the resources of multiple cores.

[0063] The beneficial effects of the present invention are:

[0064] 1. The present invention designs three units that work together with software and hardware, namely a performance monitoring module, a task allocation module, and a multi-core power consumption control module. Based on the key signal monitoring and analysis in hardware, combined with software dynamic control, it is finally implemented in the multi-core power consumption control module to achieve the purpose of dynamically adjusting power consumption, which is of great significance for reducing the power consumption of multi-core RISC-V processors.

[0065] 2. The present invention proposes a method for analyzing the load of a single core. The architecture and working method proposed in the present invention support performance monitoring of a single high-performance RISC-V superscalar processor. Based on pipeline research and key signal analysis of the RISC-V high-performance processor, the load of a single RISC-V core is comprehensively evaluated by processing the information of the key signals of the decoding unit, the transmitting unit, and the retirement unit.

[0066] 3. Based on the single-core load analysis method proposed in the present invention, the task allocation of the multi-core processor is dynamically adjusted through software configuration, and the task allocation strategy is adjusted. At the same time, a multi-core work priority round-robin method is proposed, which can make the working status of each core dynamically adjustable and avoid the situation where a single core works for too long. BRIEF DESCRIPTION OF THE DRAWINGS

[0067] Figure 1 It is a schematic diagram of the architecture of the single-core performance monitoring module of the present invention.

[0068] Figure 2 It is a schematic diagram of the multi-core processor of the present invention performing multi-core scheduling through the task allocation module and the multi-core power consumption control module. DETAILED DESCRIPTION

[0069] The present invention will be further described below with reference to the embodiments and the accompanying drawings, but is not limited thereto.

[0070] Example 1

[0071] An architecture for a performance monitoring mechanism for multi-core processors, such as Figure 1 and Figure 2 As shown, it includes J processor cores, a performance monitoring module, a task allocation module, a multi-core power consumption control module and a power management module, where J is a positive integer greater than or equal to 2;

[0072] Each processor core includes M decoding units, M transmitting units, and N retirement units, where M, N, and K are all positive integers;

[0073] The performance monitoring module is used to monitor the performance of the decoding unit, the transmitting unit, and the retirement unit of a single processor core;

[0074] The task allocation module is used to read the real-time monitoring results of the performance monitoring module, calculate the load of each processor core and allocate tasks according to the set task allocation strategy;

[0075] The multi-core power consumption control module is coupled with the power management module. The multi-core power consumption control module is used to receive the task assignment command from the task assignment module and then control the power management module. The power management module is used to control the switching, sleep and wake-up of the processor core; the multi-core power consumption control module realizes the sleep and wake-up of a single processor core through the power management module.

[0076] Each processor core supports a multi-core interconnection bus structure, and the performance monitoring module communicates data with the task allocation module through the multi-core interconnection bus structure; the performance monitoring module collects the operating indicators of the decoding unit, transmission unit and retirement unit of a single processor core through a preset period monitor, and the performance monitoring module supports multi-channel monitoring.

[0077] Example 2

[0078] A method for multi-core processor task migration and power consumption adjustment based on a performance monitoring mechanism, based on the architecture provided in Example 1, specifically includes:

[0079] (1) After J processor cores are powered on, they default to the J-core working mode, and the operating mode of the multi-core processor system is set to the balanced mode through the operating system;

[0080] In step (1), the system's operating modes include low power mode, performance mode, and balanced mode, specifically:

[0081] When low-power mode is enabled, the task allocation and core sleep / wake-up strategies change. To achieve lower power consumption, the multi-core processor only starts one core. The task allocation module reads the priority history table and selects the core with the highest priority to work alone. The other J-1 cores are put into sleep mode. All tasks of the operating system are handled by the active processor core, and the multi-core processor runs in extremely low-power mode.

[0082] When performance mode is enabled, all J processor cores remain awake regardless of the load on each core. The task allocation module does not intervene in the specific task allocation method, which is determined by the operating system and application programs. The simultaneous operation of all J processor cores maximizes processor performance.

[0083] When the balanced mode is turned on, the task allocation module starts working, and the multi-core processors involved share the last level cache (Last Level Cache). Therefore, when a task is migrated, all data in the current core pipeline must be processed and written to the last level cache through the intra-core bus; when the balanced mode is turned on, the task allocation module will analyze the load of each core; if the analysis result shows that J cores do not need to work simultaneously, the task allocation module will reasonably allocate tasks and wake up and sleep the cores based on the analysis result, concentrating the tasks on one or two processor cores with the highest priority, and the other processor cores will be put into sleep.

[0084] (2) The performance monitoring module monitors the decoding unit, transmitting unit, and retirement unit of each processor core in real time; specifically, it includes:

[0085] like Figure 1 As shown, the decoding unit includes multiple decoding modules, namely DEC0, DEC1...DECn, and can decode up to n instructions per cycle;

[0086] The launch unit includes a command sink, which serves as a temporary storage station for multiple launch commands. A performance monitoring module is set up in the command sink. There are C temporary storage stations in total, and the depth of each temporary storage station is X.

[0087] The retirement unit is mainly responsible for retiring the executed instructions to release the register renaming table. It can retire up to n instructions per cycle.

[0088] The performance monitoring module monitors the decoding level results of the decoding unit, and counts the number of decodings within a certain clock cycle, the occupancy rate of each temporary station in the transmission unit, and the number of retired instructions in the retirement unit. (3) The task allocation module relies on the operating system on the multi-core processor to read the real-time monitoring results of the performance monitoring module, and then calculates and analyzes the load of each processor core, and then adjusts the task allocation of each processor core and controls the sleep and wake-up of each processor core through the pre-set task allocation strategy;

[0089] In step (3), the priorities of the J processor cores are set through software configuration, and the processor core with the highest priority is used first. At the same time, the priorities are dynamically configured according to the software configuration; the task allocation module collects the load conditions of each of the J processor cores through the multi-core interconnection bus, and when allocating tasks, it preferentially allocates tasks to the processor core with the highest priority, and issues sleep instructions to other processor cores that are about to sleep;

[0090] When the task load of a single processor core reaches the threshold, other dormant processor cores are awakened and tasks are dynamically scheduled to meet processor performance requirements.

[0091] In step (3), the operating system calculates and analyzes the load of the processor core. The specific process is as follows:

[0092] Considering the differences between different temporary storage stations, operation and jump instructions can be completed in a short cycle, so operation instructions and jump instructions are short-cycle instructions; while load instructions, write-back instructions and floating-point operation instructions are long-cycle instructions;

[0093] (1) For a certain processor core, the occupancy rates of the temporary storage stations in the emission unit corresponding to the short-cycle instructions and the long-cycle instructions within a certain clock cycle are counted, and the occupancy rates of the temporary storage stations corresponding to the long-cycle instructions are weighted. The data of the temporary storage stations corresponding to the short-cycle instructions do not need to be weighted;

[0094] Assume that the occupancy rate of the temporary storage station corresponding to the short-cycle instruction within a certain cycle is a p The occupancy rate of the temporary storage station corresponding to the long-cycle instruction in a certain cycle is b q , the weights of the temporary storage stations corresponding to the long-cycle instructions are f q , the number of detection cycles is T, then the total occupancy rate z0 of the transmitting unit satisfies:

[0095] Total occupancy z0=(a1+a2+a3+…a p )+(f1b1+f2b2+f3b3+f4b4+f5b5+…f q b q ) / X*C*T; (I)

[0096] In formula (I), X represents the depth of each temporary storage station, C represents the number of temporary storage stations; p Indicates the total number of occupied temporary stations corresponding to the p-th short-cycle instruction within a certain cycle, b q Indicates the total number of occupied temporary stations corresponding to the qth long-cycle instruction within a certain cycle, f q represents the weight of the temporary storage station corresponding to the qth long cycle instruction;

[0097] (2) The occupancy rate of the decoding unit is the occupancy rate of the decoding level. The number of detection cycles is T, the maximum number of instructions that can be decoded in a single cycle of the decoding level is n, and the number of instructions that are detected to be decoded in the detection cycle is D. Then the total occupancy rate z1 of the decoding level satisfies:

[0098] Total occupancy z1 = D / n*T (II),

[0099] (3) The method for calculating the occupancy rate of the retirement unit is the same as that of the decoding unit. The number of detection cycles is T, the maximum number of instructions that can be retired in a single cycle of the retirement level is n, and the number of instructions that are detected to be decoded in the detection cycle is R. Then the total occupancy rate z2 of the decoding level satisfies:

[0100] Total occupancy z2 = R / n*T (III),

[0101] According to the statistical occupancy of the decoding unit, the transmitting unit, and the retirement unit, the total load Z of a single core is obtained according to the empirical formula in processor design:

[0102] Z=0.25*z0+0.5*z1+0.25*z2 (IV),

[0103] In formula (IV), z0 represents the total occupancy rate of the decoding unit, z1 represents the total occupancy rate of the transmitting unit, and z2 represents the total occupancy rate of the retired unit; 0.25 and 0.5 in formula (IV) are empirical formulas;

[0104] Monitor and count the number of retired instructions within a certain clock cycle and analyze it together with the data from the decode unit and the transmit unit to obtain the execution status of the instructions and the load of a single core processor, specifically:

[0105] Assuming that the number of cores in a multi-core processor is m, the total load P of the multi-core processor is:

[0106] P=Z(0)+Z(1)+Z(2)+…Z(m) / m; (V)

[0107] In formula (V), Z(m) represents the total load of the mth processor core.

[0108] In balanced mode, multi-core wakeup and sleep are divided into four working modes according to the total load of the multi-core processor:

[0109] (1) When the total load of the multi-core processor is less than 5%, the task allocation module only retains the highest priority core for task allocation, and performs pre-sleep processing on the other J-1 cores; pre-sleep processing means that the dormant processor core will no longer perform new tasks and no longer retrieve data from the shared cache during the dormant process; pre-sleep processing needs to wait until the corresponding processor core completes all instructions in the pipeline and writes them back to the shared cache; when the dormant J-1 cores send a ready signal, the task allocation module will adjust the task allocation mode, and the processor will be adjusted to a single-core working mode. At the same time, it will pass instructions to the multi-core power consumption control module to put the other J-1 low-priority processor cores to sleep, and the dormant cores will enter an extremely low power consumption mode and wait to be awakened;

[0110] (2) When the total load of the multi-core processor is greater than 5% and less than 15%, the task allocation module will issue a pre-sleep process to J-2 cores of priority 3 to priority J; the sleep strategy is as described in the first mode. When the J-2 sleeping cores send a ready signal, the task allocation module will adjust the task allocation mode, and the multi-core processor will be adjusted to a dual-core working mode. At the same time, it will pass instructions to the multi-core power consumption control module to put the J-2 low-priority processor cores to sleep. The sleeping cores will enter an extremely low power consumption mode and wait until the task allocation module wakes them up;

[0111] (3) When the total load of the multi-core processor is greater than 15% and less than 20%, the task allocation module will issue a pre-sleep process to J-3 cores of priority 4 to priority J; the sleep strategy is as described in the first mode. When the J-3 sleeping cores send a ready signal, the task allocation module will adjust the task allocation mode, and the multi-core processor will be adjusted to a three-core working mode. At the same time, it will pass instructions to the multi-core power consumption control module to put the J-3 low-priority processor cores to sleep. The sleeping cores will enter an extremely low power consumption mode and wait for the task allocation module to wake them up;

[0112] (4) When the combined load of each processor core is greater than 20%, the task allocation module does not allocate tasks to the core and does not perform sleep processing, maintaining the J core working mode to ensure the high performance operation of the multi-core processor.

[0113] (4) The multi-core power consumption control module receives instructions from the task allocation module and then controls the power management unit to realize the sleep or wake-up state of the processor core through the power management unit;

[0114] When the processor core is in the awake state, it accepts new task requests from the task allocation module and exchanges data with the shared cache through the multi-core interconnect bus;

[0115] When the task allocation module sends a sleep command to the awakened processor core, the processor core will complete all current tasks and enter the sleep state;

[0116] When a processor core is in a dormant state, it no longer accepts new task requests from the task allocation module, and the multi-core interconnect bus only transmits wake-up and sleep signals to the dormant processor core.

[0117] When the task allocation module performs task redistribution and core sleep processing, it reads the information of the priority history table of each processor core;

[0118] Each processor core is provided with six table entries for recording the priority status of the processor core and updating the value of the priority history table according to the set sampling period; the priority history table stores the priorities of the most recent six set sampling periods;

[0119] Further preferably, when processor cores with the same priority appear, the core with the largest number of high priorities closest to the current time in the priority history table of the processor core will be given priority to maintain the working state, while the current priority remains unchanged, and the priority of other cores with the same priority is reduced by one. With the help of this mechanism, the priority history table can enter a normal circulation state, ensuring the normal operation of the power consumption balance system.

[0120] This paper proposes a multi-core real-time scheduling task allocation strategy. When multiple periodic tasks are assigned to J processor cores, the cores are first put to sleep and awakened based on the load within a clock cycle as monitored by a performance monitoring module, and then tasks are allocated. This task allocation strategy follows the principle of combinatorial optimization and relies on the utilization of each core to maximize the parallel execution of tasks and fully utilize the resources of multiple cores.

[0121] After the J core processors are powered on, they default to the J core working mode. The default priority of the J cores is binary code 000. When a core is put to sleep, the priority of the core increases by one; when a core is awakened, the priority of the core decreases by one.

[0122] Each dormant core will restart after receiving the wake-up signal and wake up in sequence according to the priority of each core. In balanced mode, the priority of each core adopts polling mode, and a three-bit status bit is used to represent the priority status of each processor core. 000 represents the lowest priority 0, 001 represents the priority 1, and so on. 111 represents the highest priority 7.

[0123] Further preferably, when the task allocation module needs to improve performance and enter a more core working mode, the processor core with the highest priority is awakened according to the priority history table;

[0124] When the task allocation module needs to reduce power consumption and enter a reduced-core operation mode, it puts the processor core with the lowest priority into sleep mode according to the priority history table. This wake-up and sleep mechanism ensures that the processor cores of the multi-core processor are in a polling state and that the performance meets the requirements of the operating system.

[0125] This embodiment uses the working scenario of a multi-target recognition system as an example:

[0126] The multi-core SOC in this example supports the RISC-V vector instruction set extension, so it can be used in areas that require high computing power, such as target recognition.

[0127] For ease of explanation, the four cores of the processor are respectively the first core, the second core, the third core and the fourth core.

[0128] First, after the multi-core processor is powered on, it is in quad-core working mode with an operating frequency of 1 GHz. In order to save power, the chip working mode is set to balanced mode through the operating system.

[0129] Set the performance monitoring module reporting period to 1000 clock cycles.

[0130] After receiving data from the performance monitoring module, the task allocation module analyzes and determines that the current processor load level is less than 5%. It then enters operating mode 1, leaving only the first core of the processor powered on, while the other cores enter a dormant state. Simultaneously, the priority history table is updated, and the priorities of the second, third, and fourth cores of the processor are incremented by one. The priorities of all four cores are then written to the priority table. At this point, the data in the priority table for the four cores is 00, 01, 01, and 01, respectively. The task allocation module sends instructions to the multi-core power consumption control module, which controls the dormancy of the second, third, and fourth cores of the processor.

[0131] While in operating mode 1, a car drives by, and the multi-core processor begins operating. The task allocation module, after analyzing the data from the performance monitoring module, determines that it needs to enter operating mode 2, adjusts the operating mode, and wakes up the high-priority processor. At this point, three cores of equal priority appear. The processor core wakes up the second core according to the default priority configured by the software. At this point, the priorities of the four cores are 00, 00, 10, and 10, respectively.

[0132] When multiple vehicles enter the vehicle while in operating mode 2, the task allocation module switches to operating mode 3, waking up the processor's third core. The second core wakes up according to the default priority, which is 00, 00, 00, 11.

[0133] When the system is in operating mode 3 and multiple vehicles enter the system in succession, the task allocation module switches to operating mode 4, waking up the fourth processor core. At this point, the priorities of the four cores become 00, 00, 00, and 10.

[0134] After a multi-core processor has run for a period of time, the priority history table becomes effective. Based on historical priorities, each core's sleep and wakeup time is dynamically configured. This allows for dynamic power consumption adjustment, and all parameters are configurable, allowing for dynamic policy adjustments based on operational requirements.

[0135] For example, when a multi-core processor undergoes the above working mode adjustment over a period of time, the core with the longest working time will be at the lowest priority, and the core with the shortest working time will be at the highest priority.

[0136] After the multi-core processor is configured in balanced mode, the hardware and software combined architecture proposed in the present invention can dynamically allocate tasks based on the load of the multi-core processor monitored in real time, and dynamically adjust the power consumption of each core based on the sleep and wake-up mechanism of the single core to achieve the effect of reducing power consumption.

Claims

1. A multi-core processor task migration and power consumption adjustment method based on a performance monitoring mechanism, characterized in that: Specific methods include: (1) After J processor cores are powered on, they default to the J-core working mode. The operating system sets the working mode of the multi-core processor system to the balanced mode. Each processor core includes M decoding units, M transmitting units, and N retiring units, where M, N, and K are all positive integers. The system's operating modes include low power mode, performance mode, and balanced mode, specifically: When low-power mode is enabled, the task allocation and core sleep / wake-up strategies change. To achieve lower power consumption, a multi-core processor only starts one core. The task allocation module reads the priority history table and selects the core with the highest priority to work alone. The other J-1 cores are put into sleep mode, and all tasks of the operating system are handled by the active processor core. When performance mode is enabled, all J processor cores remain awake. The task allocation module does not intervene in the specific task allocation method. Task allocation is determined by the operating system and application programs. The simultaneous operation of all J processor cores maximizes processor performance. When the balanced mode is on, the task allocation module starts working. The multi-core processors involved share the last-level cache. Therefore, when a task is migrated, all data in the current core pipeline must be processed and written to the last-level cache through the intra-core bus. When the balanced mode is on, the task allocation module will analyze the load of each core. If the analysis result shows that J cores do not need to work simultaneously, the task allocation module will allocate tasks and wake up and sleep cores based on the analysis results, concentrating tasks on one or two processor cores with the highest priority, and putting other processor cores into sleep. (2) The performance monitoring module monitors the decoding unit, transmitting unit, and retirement unit of each processor core in real time; (3) The task allocation module relies on the operating system of the multi-core processor to read the real-time monitoring results of the performance monitoring module, and then calculates and analyzes the load of each processor core. It then adjusts the task allocation of each processor core and controls the sleep and wake-up of each processor core through a pre-set task allocation strategy; (4) The multi-core power consumption control module receives instructions from the task allocation module and then controls the power management unit to realize the sleep or wake-up state of the processor core through the power management unit; When the processor core is in the awake state, it accepts new task requests from the task allocation module and exchanges data with the shared cache through the multi-core interconnect bus; When the task allocation module sends a sleep command to the awakened processor core, the processor core will complete all current tasks and enter the sleep state; When a processor core is in a dormant state, it no longer accepts new task requests from the task allocation module, and the multi-core interconnect bus only transmits wake-up and sleep signals to the dormant processor core.

2. The method for multi-core processor task migration and power consumption adjustment based on performance monitoring mechanism according to claim 1, characterized in that: Each processor core supports a multi-core interconnection bus structure, and the performance monitoring module communicates data with the task allocation module through the multi-core interconnection bus structure; the performance monitoring module collects the operating indicators of the decoding unit, transmission unit and retirement unit of a single processor core through a preset period monitor, and the performance monitoring module supports multi-channel monitoring.

3. The method for multi-core processor task migration and power consumption adjustment based on performance monitoring mechanism according to claim 1, characterized in that: In step (2), the performance monitoring module performs real-time monitoring on the decoding unit, transmitting unit, and retiring unit of each processor core, specifically including: The decoding unit includes multiple decoding modules, namely DEC0, DEC1...DECn, and can decode up to n instructions per cycle; The launch unit includes a command settling pool, which serves as a temporary storage station for multiple launch commands. There are C temporary storage stations in total, and the depth of each temporary storage station is X; The retirement unit is responsible for retiring the executed instructions to release the register renaming table. It can retire up to n instructions per cycle. The performance monitoring module monitors the decoding results of the decoding unit, and counts the number of decodes within a certain clock cycle, the occupancy rate of each temporary storage station in the transmitting unit, and the number of retired instructions in the retirement unit.

4. The method for multi-core processor task migration and power consumption adjustment based on performance monitoring mechanism according to claim 1, characterized in that: In step (3), the priorities of the J processor cores are set through software configuration, and the processor core with the highest priority is used first. At the same time, the priorities are dynamically configured according to the software configuration; the task allocation module collects the load conditions of each of the J processor cores through the multi-core interconnection bus, and when allocating tasks, it preferentially allocates tasks to the processor core with the highest priority, and issues sleep instructions to other processor cores that are about to sleep; When the task load of a single processor core reaches the threshold, other dormant processor cores are awakened and tasks are dynamically scheduled.

5. The method for multi-core processor task migration and power consumption adjustment based on performance monitoring mechanism according to claim 1, characterized in that: In step (3), the operating system calculates and analyzes the load of the processor core. The specific process is as follows: (1) For a certain processor core, the occupancy rates of the temporary storage stations in the emission unit corresponding to the short-cycle instructions and the long-cycle instructions within a certain clock cycle are counted, and the occupancy rates of the temporary storage stations corresponding to the long-cycle instructions are weighted. The data of the temporary storage stations corresponding to the short-cycle instructions do not need to be weighted; Assuming that the occupancy rate of the temporary storage station corresponding to the short-cycle instruction in a certain period is ap, the occupancy rate of the temporary storage station corresponding to the long-cycle instruction in a certain period is bq, the weights of the temporary storage stations corresponding to the long-cycle instruction are fq, and the number of detection cycles is T, then the total occupancy rate z0 of the transmitting unit satisfies: Total occupancy z0=(a1+a2+a3+…a p )+(f1b1+f2b2+f3b3+f4b4+f5b5+…f q b q ) / X*C*T (I), In formula (I), X represents the depth of each temporary storage station, C represents the number of temporary storage stations; p Indicates the total number of occupied temporary stations corresponding to the p-th short-cycle instruction within a certain cycle, b q Indicates the total number of occupied temporary stations corresponding to the qth long-cycle instruction within a certain cycle, f q represents the weight of the temporary storage station corresponding to the qth long cycle instruction; The occupancy rate of the decoding unit is the occupancy rate of the decoding level. The number of detection cycles is T. The maximum number of instructions that can be decoded in a single cycle of the decoding level is n. The number of instructions that are detected to be decoded in the detection cycle is D. Then the total occupancy rate z1 of the decoding level satisfies: total occupancy rate z1 = D / n*T (II). (3) The method for calculating the occupancy rate of the retirement unit is the same as that of the decoding unit. The number of detection cycles is T, the maximum number of instructions that can be retired in a single cycle of the retirement level is n, and the number of instructions that are detected to be decoded in the detection cycle is R. Then the total occupancy rate z2 of the decoding level satisfies: Total occupancy rate z2=R / n*T (Ⅲ), According to the statistical occupancy rates of the decoding unit, the transmitting unit, and the retirement unit, the total load Z of a single core is obtained according to the empirical formula in processor design: Z=0.25*z0+0.5*z1+0.25*z2 (Ⅳ), In formula (IV), z0 represents the total occupancy rate of the decoding unit, z1 represents the total occupancy rate of the transmitting unit, and z2 represents the total occupancy rate of the retired unit; Monitor and count the number of retired instructions within a certain clock cycle and analyze it together with the data from the decode unit and the transmit unit to obtain the execution status of the instructions and the load of a single core processor, specifically: Assuming that the number of cores in a multi-core processor is m, the total load P of the multi-core processor is: P=Z(0)+Z(1)+Z(2)+…Z(m) / m (V), In formula (V), Z(m) represents the total load of the mth processor core.

6. The method for multi-core processor task migration and power consumption adjustment based on performance monitoring mechanism according to claim 1, characterized in that: In balanced mode, multi-core wakeup and sleep are divided into four working modes according to the total load of the multi-core processor: (1) When the total load of the multi-core processor is less than 5%, the task allocation module only reserves the highest priority core for task allocation, and at the same time performs pre-sleep processing on the other J-1 cores; when the dormant J-1 cores send a ready signal, the task allocation module adjusts the task allocation mode, adjusts the processor to single-core working mode, and at the same time transmits instructions to the multi-core power consumption control module to put the other J-1 low-priority processor cores into sleep mode and wait for wake-up; (2) When the total load of the multi-core processor is greater than 5% and less than 15%, the task allocation module will issue a pre-sleep process to J-2 cores with priority levels 3 to J; when the J-2 cores in sleep mode send a ready signal, the task allocation module will adjust the task allocation mode, and the multi-core processor will be adjusted to a dual-core working mode. At the same time, it will pass instructions to the multi-core power consumption control module to put J-2 low-priority processor cores into sleep mode until the task allocation module wakes them up; (3) When the total load of the multi-core processor is greater than 15% and less than 20%, the task allocation module will issue a pre-sleep process to J-3 cores with priority levels 4 to J; when the J-3 cores in sleep mode send a ready signal, the task allocation module will adjust the task allocation mode, and the multi-core processor will be adjusted to a three-core working mode. At the same time, it will pass instructions to the multi-core power consumption control module to put J-3 low-priority processor cores into sleep mode, waiting for the task allocation module to wake up; (4) When the combined load of each processor core is greater than 20%, the J core working mode is maintained.

7. The method for multi-core processor task migration and power consumption adjustment based on performance monitoring mechanism according to claim 1, characterized in that: After the J core processors are powered on, they default to the J core working mode. The default priority of the J cores is binary code 000. When a core is put to sleep, the priority of the core increases by one; when a core is awakened, the priority of the core decreases by one. Each dormant core will restart after receiving the wake-up signal and wake up in sequence according to the priority of each core. In balanced mode, the priority of each core adopts polling mode, and a three-bit status bit is used to indicate the priority status of each processor core.

8. The method for multi-core processor task migration and power consumption adjustment based on performance monitoring mechanism according to claim 7, characterized in that: When the task allocation module needs to improve performance and enter the multi-core working mode, it wakes up the processor core with the highest priority according to the priority history table; When the task allocation module needs to reduce power consumption and enter a fewer cores working mode, it puts the processor core with the lowest priority to sleep according to the priority history table.

9. The method for multi-core processor task migration and power consumption adjustment based on performance monitoring mechanism according to claim 1, characterized in that: When the task allocation module performs task redistribution and core sleep processing, it reads the information of the priority history table of each processor core; Each processor core is provided with six table entries for recording the priority status of the processor core and updating the value of the priority history table according to the set sampling period; the priority history table stores the priorities of the latest six set sampling periods.

10. The method for multi-core processor task migration and power consumption adjustment based on performance monitoring mechanism according to claim 9, characterized in that: When processor cores with the same priority appear, the core with the highest priority closest to the current time in the processor core priority history table will be given priority to remain in working state, while the current priority remains unchanged, and the priority of other cores with the same priority is reduced by one.

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