Packaging structure, packaging substrate and its manufacturing method

Abstract

This application discloses a packaging substrate, including a circuit layer, a solder resist layer, and a barrier structure. The circuit layer has a packaging area, the solder resist layer is disposed on the circuit layer, and the solder resist layer corresponding to the packaging area has multiple openings. A portion of the circuit layer is exposed at the bottom of the openings. The barrier structure is disposed on the solder resist layer and avoids the packaging area. The packaging substrate provided by this application forms the barrier structure by electroplating an electroplated layer on the solder resist layer and electroplating a first barrier portion on the electroplated layer. This barrier structure has a strong bond with the solder resist layer, which helps to reduce the cross-sectional width of the barrier structure, thereby reserving more space for the placement of other electronic components. In addition, this application also provides a method for manufacturing the packaging substrate. Furthermore, this application also provides a packaging structure.

Description

Technical Field

[0001] This application relates to a packaging structure, a packaging substrate, and a method for manufacturing the same. Background Technology

[0002] In existing chip packaging processes, two solder resist layers are typically fabricated on the surface of the packaging substrate. The first solder resist layer defines the contact pads on the packaging substrate, and the second solder resist layer is formed on the first solder resist layer and surrounds the chip packaging area to act as a dam during chip packaging, preventing solder from overflowing between the chip and the first solder resist layer. However, since the second solder resist layer is formed on the first solder resist layer, its adhesion is relatively weak. Therefore, the second solder resist layer often requires a large linewidth (e.g., greater than 100 micrometers) to achieve effective adhesion, but a large linewidth is not conducive to the placement of other electronic components. Summary of the Invention

[0003] To address the problems involved in the prior art, this application provides a packaging substrate.

[0004] In addition, it is necessary to provide a manufacturing method for forming the above-mentioned packaging substrate.

[0005] In addition, it is necessary to provide a packaging structure having the above-mentioned packaging substrate.

[0006] A method for manufacturing a packaging substrate includes the following steps: providing a circuit substrate, the circuit substrate including a circuit layer and a first solder resist layer disposed on the circuit layer, the circuit layer having a packaging region, and the first solder resist layer corresponding to the packaging region having a plurality of first openings through it, with a portion of the circuit layer exposed at the bottom of the first openings; electroplating to form an electroplated layer on the first solder resist layer; disposing a second solder resist layer on the electroplated layer, the second solder resist layer having a plurality of second openings through it, the projection of the second openings not coinciding with the projection of the packaging region along the thickness direction of the circuit substrate, and a portion of the electroplated layer exposed at the bottom of the second openings; disposing a first blocking portion within the second openings, the electroplated layer including a second blocking portion covered by the first blocking portion and a portion to be removed excluding the second blocking portion; removing the second solder resist layer and the portion to be removed, the first blocking portion and the second blocking portion together forming a blocking structure, thereby obtaining the packaging substrate.

[0007] Furthermore, the electroplated layer is also disposed on the inner periphery of the first opening, and the manufacturing method further includes:

[0008] Remove the electroplated layer disposed on the inner periphery of the first opening.

[0009] Further, the method for manufacturing the circuit board includes: providing a circuit layer; depositing a first photosensitive resin layer on the circuit layer; removing the first photosensitive resin layer corresponding to the first opening to form the first solder resist layer, thereby obtaining the circuit board.

[0010] Further, the step of "depositing a second solder resist layer on the electroplated layer" includes: depositing a second photosensitive resin layer on the electroplated layer; and removing the second photosensitive resin layer corresponding to the second opening to form the second solder resist layer.

[0011] A packaging substrate includes a circuit layer, a solder resist layer, and a barrier structure. The circuit layer has a packaging area. The solder resist layer is disposed on the circuit layer and has a plurality of openings corresponding to the packaging area. A portion of the circuit layer is exposed at the bottom of the openings. The barrier structure is disposed on the solder resist layer. Along the thickness direction of the packaging substrate, the projection of the barrier structure does not coincide with the projection of the packaging area. The barrier structure includes a first blocking portion and a second blocking portion, with the second blocking portion connected between the solder resist layer and the first blocking portion.

[0012] Furthermore, the materials of the first blocking part and the second blocking part include any one of gold, silver, copper, and aluminum.

[0013] Furthermore, the barrier structure is disposed around the encapsulation area.

[0014] Furthermore, the cross-sectional width of the barrier structure is 10 to 20 micrometers.

[0015] A packaging structure includes a chip, a conductor, a filler, and a packaging substrate as described above. The chip is disposed on the solder resist layer corresponding to the packaging area. The conductor is disposed within the opening. The conductor includes a first end and a second end opposite to the first end. The first end is electrically connected to the chip, and the second end is electrically connected to the circuit layer. The filler is disposed in the gap between the chip and the solder resist layer. A blocking structure is used to prevent the filler from flowing out of the packaging area.

[0016] Furthermore, the height of the blocking structure is greater than or equal to the thickness of the filler.

[0017] The packaging substrate provided in this application forms the barrier structure by electroplating an electroplated layer on the solder resist layer and electroplating a first barrier portion on the electroplated layer. The barrier structure has a strong bond with the solder resist layer, which helps to reduce the cross-sectional width of the barrier structure, thereby reserving more space for the layout of other electronic components. Attached Figure Description

[0018] Figure 1This is a schematic diagram of a circuit layer and a first photosensitive resin layer provided in an embodiment of this application.

[0019] Figure 2 In order to be in Figure 1 The diagram shown is a schematic of the circuit layer after the first solder mask layer has been applied.

[0020] Figure 3 In order to be in Figure 2 The diagram shown is a schematic of the first solder resist layer after electroplating.

[0021] Figure 4 In order to be in Figure 3 The diagram shown illustrates the electroplated layer after the second solder resist layer has been applied.

[0022] Figure 5 In order to be in Figure 4 The diagram shows a first blocking part provided in the second solder resist layer.

[0023] Figure 6 This is a schematic diagram of a packaging substrate provided in an embodiment of this application.

[0024] Figure 7 This is a schematic diagram of a packaging structure provided in an embodiment of this application.

[0025] Explanation of main component symbols

[0026] Packaging substrate 100

[0027] Circuit board 101

[0028] Line layer 10

[0029] Package area 11

[0030] First photosensitive resin layer 20

[0031] First opening 21

[0032] First weld shielding layer 22

[0033] Electroplating layer 30

[0034] Second blocking section 31

[0035] Part 32 to be removed

[0036] Second weld shielding layer 40

[0037] Second opening 41

[0038] First blocking section 50

[0039] Blocking structure 60

[0040] Package structure 200

[0041] Chip 201

[0042] Conductor 202

[0043] First end 202a

[0044] Second end 202b

[0045] Filler 203

[0046] Width S

[0047] Altitude D1

[0048] Thickness D2

[0049] Thickness direction A

[0050] The following detailed description, in conjunction with the accompanying drawings, will further illustrate this application. Detailed Implementation

[0051] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0052] It should be noted that when a component is said to be "fixed to" another component, it can be directly on the other component or there may be an intervening component. When a component is said to be "connected to" another component, it can be directly connected to the other component or there may be an intervening component. When a component is said to be "set on" another component, it can be directly set on the other component or there may be an intervening component.

[0053] Please see Figures 1 to 7 A method for manufacturing a packaging substrate 100 according to an embodiment of this application includes the following steps:

[0054] S1: Please see Figure 2 A circuit board 101 is provided, the circuit board 101 includes a circuit layer 10 and a first solder resist layer 22 disposed on the circuit layer 10. The circuit layer 10 has a packaging area 11. The first solder resist layer 22 corresponding to the packaging area 11 is provided with a plurality of first openings 21. Part of the circuit layer 10 is exposed at the bottom of the first openings 21.

[0055] In this embodiment, step S1, the method for manufacturing the circuit board 101 includes:

[0056] S10: Please refer to Figure 1A circuit layer 10 is provided, the circuit layer 10 having a packaging region 11, the packaging region 11 being located approximately in the central region of the circuit layer 10, the packaging region being used to house a chip 201 (see [link]). Figure 7 ).

[0057] S11: A first photosensitive resin layer 20 is provided on the circuit layer 10.

[0058] S12: Expose the first photosensitive resin layer 20 corresponding to the first opening 21, so that the first photosensitive resin layer 20 not corresponding to the first opening 21 undergoes a photochemical reaction.

[0059] S13: Please see Figure 2 Remove the first photosensitive resin layer 20 that has not undergone photochemical reaction (i.e., the first photosensitive resin layer 20 corresponding to the first opening 21), bake it to obtain the first solder resist layer 22, and obtain the circuit board 101.

[0060] S2: Please see Figure 3 An electroplated layer 30 is formed on the first solder resist layer 22 by electroplating. The thickness of the electroplated layer 30 is 10-50 micrometers. The electroplated layer 30 includes a second blocking portion 31 and a removable portion 32 excluding the second blocking portion 31. Part of the removable portion 32 is attached to the inner periphery of the first opening 21. The material of the electroplated layer 30 includes metals such as gold, silver, copper, and aluminum.

[0061] S3: Please see Figure 4 A second solder resist layer 40 is provided on the electroplated layer 30, and a plurality of second openings 41 are provided through the second solder resist layer 40, avoiding the encapsulation area 11 (that is, along the thickness direction A of the circuit board 101, the projection of the second opening 41 does not coincide with the projection of the encapsulation area 11), and the second blocking part 31 is exposed at the bottom of the second opening 41.

[0062] In this embodiment, step S3, specifically the step of "setting the second solder resist layer 40", includes:

[0063] S30: A second photosensitive resin layer (not shown) is laminated onto the electroplated layer 30;

[0064] S31: Expose the second photosensitive resin layer corresponding to the second opening 41, so that the second photosensitive resin layer not corresponding to the second opening 41 undergoes a photochemical reaction.

[0065] S32: Remove the unreacted second photosensitive resin layer (i.e., the second photosensitive resin layer corresponding to the second opening 41), and obtain the second solder resist layer 40 after baking.

[0066] In this embodiment, a plurality of second openings 41 are disposed on the outer side of the encapsulation area 11.

[0067] S4: Please see Figure 5 and Figure 6 A first blocking portion 50 is formed by electroplating within the second opening 41. The first blocking portion 50 is disposed on the second blocking portion 31. The first blocking portion 50 and the second blocking portion 31 form a blocking structure 60. The portion to be removed 32 and the second solder resist layer 40 are then removed to obtain the encapsulation substrate 100. The material of the first blocking portion 50 is the same as the material of the second blocking portion 31. In other embodiments of this application, the materials of the first blocking portion 50 and the second blocking portion 31 may be different.

[0068] Please see Figure 6 This application provides a packaging substrate 100, which includes a circuit layer 10, a first solder resist layer 22, and a barrier structure 60. The circuit layer 10 has a packaging area 11. The first solder resist layer 22 is disposed on the circuit layer 10. The first solder resist layer 22 corresponding to the packaging area 11 is provided with a plurality of first openings 21. Part of the circuit layer 10 is exposed at the bottom of the first openings 21. The barrier structure 60 is disposed on the first solder resist layer 22 and avoids the packaging area 11.

[0069] In this embodiment, the barrier structure 60 is disposed around the encapsulation area 11, and the cross-sectional width S of the barrier structure 60 is 10 to 20 micrometers.

[0070] The packaging substrate 100 provided in this application forms the barrier structure 60 by electroplating an electroplated layer 30 on the first solder resist layer 22 and electroplating a first barrier portion 50 on the electroplated layer 30. The barrier structure 60 has a strong bond with the first solder resist layer 22, which is beneficial to reducing the cross-sectional width S of the barrier structure 60, thereby reserving more space for the layout of other electronic components.

[0071] Please see Figure 7This application embodiment also provides a packaging structure 200, which includes a chip 201, a conductor 202, a filler 203, and a packaging substrate 100. The chip 201 is disposed on the first solder resist layer 22 corresponding to the packaging area 11. The conductor 202 is disposed in the first opening 21. The conductor 202 includes a first end 202a and a second end 202b opposite to the first end 202a. The first end 202a is electrically connected to the chip 201, and the second end 202b is electrically connected to the circuit layer 10. The filler 203 is disposed in the gap between the chip 201 and the first solder resist layer 22. The blocking structure 60 prevents the filler 203 from flowing out of the packaging area 11.

[0072] In this embodiment, the height D1 of the blocking structure 60 is greater than or equal to the thickness D2 of the filler 203.

[0073] The above description is merely an optimized implementation of this application, and its application should not be limited to this specific implementation. Other modifications and alterations made by those skilled in the art based on the technical concept of this application should fall within the protection scope of this application.

Claims

1. A method for manufacturing a packaging substrate, characterized in that, Including the following steps: A circuit board is provided, the circuit board including a circuit layer and a first solder resist layer disposed on the circuit layer, the circuit layer having a packaging area, and the first solder resist layer corresponding to the packaging area having a plurality of first openings through it, and a portion of the circuit layer being exposed at the bottom of the first openings; An electroplating layer is formed on the first solder resist layer, and the electroplating layer is also disposed on the inner periphery of the first opening; a second solder resist layer is disposed on the electroplating layer, and the second solder resist layer is provided with a plurality of second openings through it. Along the thickness direction of the circuit board, the projection of the second opening does not coincide with the projection of the packaging area, and part of the electroplating layer is exposed at the bottom of the second opening. A first blocking portion is provided in the second opening, and the electroplated layer includes a second blocking portion covered by the first blocking portion and a portion to be removed excluding the second blocking portion; The second solder resist layer and the part to be removed are removed, and the first blocking part and the second blocking part together form a blocking structure to obtain the packaging substrate. The removal step further includes: removing the electroplated layer disposed on the inner periphery of the first opening. The first solder resist layer and the second solder resist layer are respectively formed by photosensitive resin, and the first opening and the second opening are formed by exposure and development.

2. A packaging substrate manufactured by the method for manufacturing a packaging substrate according to claim 1, characterized in that, The package includes a circuit layer, a solder resist layer, and a barrier structure. The circuit layer has a packaging area. The solder resist layer is disposed on the circuit layer and has multiple openings corresponding to the packaging area. Part of the circuit layer is exposed at the bottom of the openings. The barrier structure is disposed on the solder resist layer. Along the thickness direction of the packaging substrate, the projection of the barrier structure does not coincide with the projection of the packaging area. The barrier structure includes a first barrier portion and a second barrier portion, with the second barrier portion connected between the solder resist layer and the first barrier portion.

3. The packaging substrate as described in claim 2, wherein the material of the first blocking portion and the second blocking portion includes any one of gold, silver, copper, and aluminum.

4. The packaging substrate as described in claim 2, characterized in that, The barrier structure is disposed around the encapsulation area.

5. The packaging substrate as described in claim 2, characterized in that, The cross-sectional width of the barrier structure is 10-20 micrometers.

6. A packaging structure, characterized in that, The package includes a chip, a conductor, a filler, and a packaging substrate as described in any one of claims 2 to 5. The chip is disposed on the solder resist layer corresponding to the packaging area. The conductor is disposed within the opening. The conductor includes a first end and a second end opposite to the first end. The first end is electrically connected to the chip, and the second end is electrically connected to the circuit layer. The filler is disposed in the gap between the chip and the solder resist layer. The blocking structure is used to prevent the filler from flowing out of the packaging area.

7. The packaging structure as described in claim 6, characterized in that, The height of the barrier structure is greater than or equal to the thickness of the filler.

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