Semiconductor package device and method of manufacturing the same

Abstract

The present disclosure relates to a semiconductor packaging device and a manufacturing method thereof. The semiconductor packaging device comprises a first circuit layer, a second circuit layer located at a different horizontal plane from the first circuit layer, and a chip disposed between the first circuit layer and the second circuit layer, wherein a passive surface of the chip is fixedly connected to the second circuit layer, an active surface of the chip is electrically connected to the first circuit layer, the passive surface of the chip and the second circuit layer are fixedly connected through an adhesive layer, and a bottom filler is disposed between the active surface of the chip and the first circuit layer. The semiconductor packaging device can reduce the inconsistency of the overall structure thermal expansion coefficient, and the corners of the chip are located in the compressive stress zone, thereby reducing the risk of structural fracture.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor packaging, and in particular, to a semiconductor packaging device and a manufacturing method thereof. BACKGROUND

[0002] In the existing fan-out substrate (FOSub) structure, due to the inconsistency of the coefficient of thermal expansion (CTE) of the overall structure, warpage occurs in the heating process, and the chip corner is in the tension stress region below the stress neutral axis, thereby causing cracks in the packaging structure.

[0003] Therefore, it is necessary to propose a new technical solution to solve at least one of the above technical problems. SUMMARY

[0004] The present disclosure provides a semiconductor packaging device and a manufacturing method thereof.

[0005] In a first aspect, the present disclosure provides a semiconductor packaging device, comprising:

[0006] a first circuit layer;

[0007] a second circuit layer, located at a different horizontal plane from the first circuit layer;

[0008] a chip, disposed between the first circuit layer and the second circuit layer, a passive surface of the chip being fixedly connected to the second circuit layer, and an active surface of the chip being electrically connected to the first circuit layer.

[0009] In some optional embodiments, the passive surface of the chip and the second circuit layer are fixedly connected through an adhesive layer.

[0010] In some optional embodiments, a bottom filler is disposed between the active surface of the chip and the first circuit layer.

[0011] In some optional embodiments, a dielectric material is disposed between the first circuit layer and the second circuit layer, and the dielectric material covers the chip.

[0012] In some optional embodiments, the first circuit layer and the second circuit layer are electrically connected through a conductive hole, and the conductive hole penetrates through the first circuit layer and the dielectric material.

[0013] In some alternative embodiments, the corner of the chip covered by the underfill material is located in a compressive stress region of the semiconductor package device.

[0014] In some alternative embodiments, a line spacing of the second line layer is greater than a line spacing of the first line layer.

[0015] In some alternative embodiments, the chip comprises a first chip and a second chip, and the first chip and the second chip are electrically connected through the first line layer.

[0016] In some alternative embodiments, the first line layer is a redistribution line layer, and the second line layer is a substrate line layer.

[0017] In some alternative embodiments, a surface of the first line layer facing away from the chip is provided with an isolation layer, and the isolation layer is provided with a heat dissipation structure.

[0018] In some alternative embodiments, a surface of the second line layer facing away from the chip is provided with an electrical connector.

[0019] In a second aspect, the present disclosure provides a manufacturing method of a semiconductor package device, comprising:

[0020] forming a first line layer on a carrier;

[0021] disposing a chip on the first line layer, wherein an active surface of the chip is electrically connected to the first line layer;

[0022] fixedly connecting a passive surface of the chip to a second line layer;

[0023] removing the carrier.

[0024] In some alternative embodiments, the passive surface of the chip is provided with an adhesive layer; and

[0025] The fixedly connecting the passive surface of the chip to the second line layer comprises:

[0026] disposing a dielectric material between the first line layer and the second line layer;

[0027] embedding the passive surface of the chip into the dielectric material, so that the passive surface of the chip and the second line layer are fixedly connected through the adhesive layer, and the dielectric material covers the chip.

[0028] In some alternative embodiments, the chip comprises a first chip and a second chip; and

[0029] The disposing the chip on the first line layer comprises:

[0030] The first chip and the second chip are disposed on the first circuit layer, and the first chip and the second chip are electrically connected by the first circuit layer.

[0031] In some optional embodiments, after the passive surface of the chip is fixedly connected to the second circuit layer, the method further comprises:

[0032] A conductive hole is formed between the first circuit layer and the second circuit layer to electrically connect the first circuit layer and the second circuit layer.

[0033] In some optional embodiments, after the passive surface of the chip is fixedly connected to the second circuit layer, the method further comprises:

[0034] A heat dissipation structure is disposed on the surface of the first circuit layer facing away from the chip.

[0035] In the semiconductor packaging device and the manufacturing method thereof provided by the present disclosure, by disposing the chip between the first circuit layer and the second circuit layer, and fixedly connecting the passive surface of the chip to the second circuit layer, and electrically connecting the active surface of the chip to the first circuit layer, the inconsistency degree of the overall structure thermal expansion coefficient can be reduced, and the corner of the chip is located in the compressive stress area, thereby reducing the risk of structural fracture. BRIEF DESCRIPTION OF DRAWINGS

[0036] Other features, objects, and advantages of the present disclosure will become more apparent from the following detailed description of non-limiting embodiments made with reference to the following drawings:

[0037] Figure 1 is a schematic diagram of a semiconductor packaging device in the prior art;

[0038] Figures 2-4 is a first schematic diagram to a third schematic diagram of a semiconductor packaging device according to an embodiment of the present disclosure;

[0039] Figures 5-10 is a schematic diagram of a manufacturing method of a semiconductor packaging device according to an embodiment of the present disclosure.

[0040] SYMBOL DESCRIPTION:

[0041] 11, substrate; 12, left chip; 13, right chip; 100, first circuit layer; 200, second circuit layer; 210, electrical connector; 310, first chip; 320, second chip; 330, adhesive layer; 400, underfill material; 500, dielectric material; 600, conductive hole; 700, isolation layer; 800, heat dissipation structure; 810, heat dissipation film; 820, heat dissipation piece; 910, carrier; 920, bonding head; 1101, first unit; 1102, second unit. DETAILED DESCRIPTION

[0042] The technical problems solved by the present application and the technical effects generated by the present application can be easily understood by those skilled in the art through the content described in the specification. It should be understood that the specific embodiments described herein are only used to explain the related application, and not to limit the application. In addition, only the parts related to the application are shown in the drawings for ease of description.

[0043] It should be noted that the structures, proportions, sizes, etc. shown in the drawings of the specification are only used to cooperate with the content described in the specification for the understanding and reading of those skilled in the art, and are not used to limit the implementation conditions of the present application, so they do not have technical significance. Any modification of the structure, change of the proportion relationship or adjustment of the size, without affecting the effects and purposes that can be generated by the present application, should still fall within the scope of the technical content disclosed by the present application. At the same time, the terms such as "upper", "first", "second" and "one" used in the specification are only for the convenience of clear description, and not to limit the scope of the application, and the change or adjustment of the relative relationship without substantial change of the technical content is also considered as the implementation of the application.

[0044] It should also be noted that the embodiments of the present disclosure correspond to the longitudinal section in the front view direction, the transverse section in the right view direction, and the horizontal section in the upper view direction.

[0045] In addition, the embodiments in the present disclosure and the features in the embodiments can be combined with each other without conflict. The present disclosure will be described in detail below with reference to the drawings and in combination with the embodiments.

[0046] Figure 1 is a schematic diagram of a semiconductor packaging device in the prior art. As shown in Figure 1 , the semiconductor packaging device in the prior art includes a substrate 11, a left chip 12 and a right chip 13. Due to the inconsistent thermal expansion coefficients of the parts in the structure, warping will occur in the heating process. The stress neutral axis of the semiconductor packaging device is shown by the dashed line in Figure 1 , where the area above the stress neutral axis is subjected to compressive stress, and the area below the stress neutral axis is subjected to tensile stress. The lower corner of the right chip 13 is located in the tensile stress zone and is far away from the stress neutral axis, so the stress value is large. In addition, the stress concentration effect at the corner will further amplify the stress at the corner of the chip. Therefore, the lower corner of the right chip 13 is prone to cracking, as shown by the dashed circle in Figure 1 .

[0047] Figures 2-4Fig. 1 is a first schematic view of a semiconductor package device according to an embodiment of the present application.

[0048] As shown in Fig. 1, the semiconductor package device in the present embodiment includes a first circuit layer 100, a second circuit layer 200, a first chip 310, and a second chip 320. Figure 2

[0049] In the present embodiment, the first circuit layer 100 and the second circuit layer 200 are located at different horizontal planes. Specifically, the first circuit layer 100 is located above the second circuit layer 200. The first circuit layer 100 is, for example, a redistribution circuit layer, and the second circuit layer 200 is, for example, an organic substrate circuit layer.

[0050] In the present embodiment, the first chip 310 and the second chip 320 are disposed between the first circuit layer 100 and the second circuit layer 200. The passive surface of the first chip 310 is fixedly connected to the second circuit layer 200, and the active surface of the first chip 310 is electrically connected to the first circuit layer 100. Similarly, the passive surface of the second chip 320 is fixedly connected to the second circuit layer 200, and the active surface of the second chip 320 is electrically connected to the first circuit layer 100. The first chip 310 and the second chip 320 can be directly mounted on the first circuit layer 100 by means of Flip Chip.

[0051] In the present embodiment, the "active surface" refers to the surface of a chip used for external connection (e.g., the upper surface of the first chip 310 in Fig. 1), and the "passive surface" refers to the surface of the chip opposite to the active surface (e.g., the lower surface of the first chip 310 in Fig. 1). Figure 2 Figure 2

[0052] In the present embodiment, by mounting the active surface of the chip on the first circuit layer 100 and fixedly connecting the passive surface of the chip to the second circuit layer 200, both sides of the chip can be supported, which is conducive to improving the strength of the overall structure.

[0053] In the present embodiment, the passive surface of the first chip 310 is fixedly connected to the second circuit layer 200 by means of an adhesive layer 330 (Die Attach Film, DAF). Similarly, the passive surface of the second chip 320 is fixedly connected to the second circuit layer 200 by means of the adhesive layer 330. The adhesive layer 330 can abut against the underlying circuit, thereby relieving the degree of stress concentration at the corners below the chip.

[0054] ​​​In this embodiment, an underfill material 400 is provided between the active surface of the first chip 310 and the first circuit layer 100. Similarly, an underfill material 400 is provided between the active surface of the second chip 320 and the first circuit layer 100. Furthermore, a portion of the space between the first chip 310 and the second chip 320 is also provided with an underfill material 400. The aforementioned underfill material 400 can fill gaps in the structure, thereby improving structural strength.

[0055] In this embodiment, a dielectric material 500 is disposed between the first circuit layer 100 and the second circuit layer 200. The dielectric material 500 covers the first chip 310 and the second chip 320, thereby protecting the first chip 310 and the second chip 320.

[0056] In this embodiment, the first circuit layer 100 and the second circuit layer 200 are electrically connected through a conductive hole 600, which penetrates the first circuit layer 100 and the dielectric material 500.

[0057] In this embodiment, the corner of the first chip 310 covered by the bottom filler 400 is located in the compressive stress region of the semiconductor packaging device. In this embodiment, the stress neutral axis of the semiconductor packaging device is as follows: Figure 3 As shown by the dashed straight line, the area above the stress neutral axis is the compressive stress region, and the area below the stress neutral axis is the tensile stress region. The corners of the first chip 310 covered by the bottom filler 400 (e.g.) Figure 3 The area (shown by the dashed circle) is located above the stress neutral axis, i.e., in the compressive stress region. Furthermore, the distance from the aforementioned corner to the stress neutral axis is small, resulting in a correspondingly smaller force value. Therefore, the risk of fracture at the corner in this embodiment is relatively low.

[0058] In this embodiment, the line spacing of the second line layer 200 (e.g.) Figure 3 As shown in d2, the line spacing is greater than that of the first line layer 100 (e.g., ...). Figure 3 (As shown in d1). Here, the spacing between the lines in the circuit layer can be an average spacing or a maximum spacing, etc., and this embodiment does not limit this. The first chip 310 and the second chip 320 can be electrically connected through the fine-pitch first circuit layer 100 without the need for an additional bridge die.

[0059] In this embodiment, an isolation layer 700 is disposed on the surface of the first circuit layer 100 facing away from the chip, and a heat dissipation structure 800 is disposed on the isolation layer 700. The heat dissipation structure 800 further includes a heat dissipation film 810 and a heat sink 820. The isolation layer 700 and the heat dissipation structure 800 improve the heat dissipation performance of the semiconductor packaging device.

[0060] In the embodiment, the back-chip surface of the second circuit layer 200 is provided with the electrical connection 210, so as to realize the external connection of the semiconductor packaging device.

[0061] In one example, as shown in Figure 4 , the semiconductor packaging device can further include a plurality of structural units, such as the first unit 1101 and the second unit 1102. Each structural unit can include two or more single chips. In this way, the diversity of the functions of the semiconductor packaging device can be realized.

[0062] In the semiconductor packaging device of the embodiment, by arranging the chips between the first circuit layer 100 and the second circuit layer 200, and fixing the passive surface of the chip to the second circuit layer 200 and electrically connecting the active surface of the chip to the first circuit layer 100, the inconsistency of the overall structure thermal expansion coefficient can be reduced, and the corner of the chip is located in the compressive stress area, thereby reducing the risk of structure fracture and improving the product yield.

[0063] The embodiment further provides a manufacturing method of a semiconductor packaging device. As shown in Figures 5-10 , the method includes the following steps.

[0064] Firstly, as shown in Figure 5 , the first circuit layer 100 is formed on the carrier 910.

[0065] Secondly, the chip is arranged on the first circuit layer 100, wherein the active surface of the chip is electrically connected to the first circuit layer 100.

[0066] As shown in Figure 6 and Figure 7 , the first chip 310 can be arranged on the first circuit layer 100 by the bonding head 920 first, and then the second chip 320 is arranged on the first circuit layer 100 by the bonding head 920. The first chip 310 and the second chip 320 are electrically connected by the first circuit layer 100. In addition, as shown in Figure 8 , the underfill material 400 can be arranged between the first chip 310 and the first circuit layer 100, and between the second chip 320 and the first circuit layer 100.

[0067] Thirdly, the passive surface of the chip is fixedly connected to the second circuit layer 200. As shown in Figure 9 and Figure 10 , the dielectric material 500 can be arranged between the first circuit layer 100 and the second circuit layer 200 first, and then the passive surface of the chip is embedded in the dielectric material 500, so that the passive surface of the chip and the second circuit layer 200 are fixedly connected by the adhesive layer 330, and the dielectric material 500 covers the chip.

[0068] Fourthly, as shown in Figure 10As shown, a conductive hole 600 is formed between the first circuit layer 100 and the second circuit layer 200 to electrically connect the first circuit layer 100 and the second circuit layer 200.

[0069] In the fifth step, the carrier 910 is removed and the heat dissipation structure 800 is arranged on the back-chip surface of the first circuit layer 100, obtaining a structure as shown. Figure 2

[0070] The manufacturing method of the semiconductor packaging device in the embodiment can achieve the technical effects of the semiconductor packaging device described above, which will not be repeated here.

[0071] Although the disclosure has been described and illustrated with reference to specific embodiments, the descriptions and illustrations have been made by way of example only. From the preceding description, one skilled in the art will readily ascertain variations and modifications without departing from the true spirit and scope of the disclosure as defined by the following claims. The figures may not be drawn to scale. There can be distinctions between the technical reproduction and the actual devices in the disclosure due to variables in the manufacturing process, etc. There can be other embodiments of the disclosure that are not specifically described. The specification and drawings should be considered illustrative only and not restrictive. Modifications can be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the disclosure. All such modifications are intended to be within the scope of the claims appended hereto. Although the methods disclosed herein have been described with reference to particular operations performed in a particular order, it can be appreciated that these operations can be combined, subdivided, or re-ordered to form equivalent methods without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of operations are not a limitation of the disclosure.​

Claims

1.A semiconductor packaging device, comprising: a first circuit layer, the first circuit layer being a redistribution circuit layer; a second circuit layer, the second circuit layer being a substrate circuit layer, and the second circuit layer being located at a different horizontal plane from the first circuit layer; a chip, the chip being disposed between the first circuit layer and the second circuit layer, a passive surface of the chip being fixedly connected to the second circuit layer, an active surface of the chip being electrically connected to the first circuit layer, and both sides of the chip being supported; the passive surface of the chip and the second circuit layer being fixedly connected through an adhesive layer, the adhesive layer abutting against the second circuit layer, so as to alleviate the stress concentration degree at the corners below the chip; a bottom filler being disposed between the active surface of the chip and the first circuit layer; a stress neutral axis of the semiconductor packaging device being located between the first circuit layer and the second circuit layer and passing through the chip, the stress neutral axis dividing the semiconductor packaging device into a compressive stress region and a tensile stress region, and the corners of the chip covered by the bottom filler being located in the compressive stress region of the semiconductor packaging device; a dielectric material being disposed between the first circuit layer and the second circuit layer, and the dielectric material covering the chip; the first circuit layer and the second circuit layer being electrically connected through a conductive hole, the conductive hole penetrating through the first circuit layer and the dielectric material; a circuit pitch of the second circuit layer being greater than a circuit pitch of the first circuit layer; the chip comprising a first chip and a second chip, and the first chip and the second chip being electrically connected through the first circuit layer; a surface of the first circuit layer facing away from the chip being provided with an isolation layer, and a heat dissipation structure being disposed on the isolation layer. 6.A manufacturing method of a semiconductor packaging device, for manufacturing the semiconductor packaging device of claim 1, the method comprising: forming a first circuit layer on a carrier, the first circuit layer being a redistribution circuit layer; disposing a chip on the first circuit layer, wherein an active surface of the chip is electrically connected to the first circuit layer, and a bottom filler is disposed between the active surface of the chip and the first circuit layer; fixedly connecting a passive surface of the chip to a second circuit layer, so that both sides of the chip are supported, the second circuit layer being a substrate circuit layer, and the second circuit layer being located at a different horizontal plane from the first circuit layer; removing the carrier; wherein the passive surface of the chip is provided with an adhesive layer; and the fixedly connecting the passive surface of the chip to the second circuit layer comprises: disposing a dielectric material between the first circuit layer and the second circuit layer; embedding the passive surface of the chip into the dielectric material, so that the passive surface of the chip and the second circuit layer are fixedly connected through the adhesive layer, and the dielectric material covers the chip; a stress neutral axis of the semiconductor packaging device being located between the first circuit layer and the second circuit layer and passing through the chip, the stress neutral axis dividing the semiconductor packaging device into a compressive stress region and a tensile stress region, and the corners of the chip covered by the bottom filler being located in the compressive stress region of the semiconductor packaging device. ​ ​ ​ ​ ​ ​ 2. The semiconductor package device of claim 1, wherein, ​ 3. The semiconductor package device of claim 1, wherein, ​ 4. The semiconductor package device of claim 3, wherein, ​ 5. The semiconductor package device of claim 1, wherein, ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​

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