Array substrate, display panel and display device

Abstract

The embodiment of the present invention discloses an array substrate, a display panel and a display device. The array substrate includes: a base substrate, the base substrate includes a display area and a non-display area; the display area includes a plurality of pixel circuits and a plurality of data signal lines arranged in an array, the pixel circuit includes a plurality of transistors; a light-shielding metal layer, along a direction perpendicular to the base substrate, the light-shielding metal layer covers the active area of ​​at least one transistor; the non-display area includes a first fan-out area, the first fan-out area includes a plurality of first fan-out lines; the display area includes a second fan-out area, the second fan-out area includes a plurality of second fan-out lines, the first end of the second fan-out line is electrically connected to the data signal line, and the second end is electrically connected to the first fan-out line; the second fan-out line is arranged on the same layer as the light-shielding metal layer. The technical solution of the embodiment of the present invention realizes FIAA technology by optimizing the routing method and pixel design on the basis of not significantly increasing the process cost, so as to achieve the effect of a narrow frame.

Description

Technical Field

[0001] Embodiments of the present invention relate to display technology, and more particularly to an array substrate, a display panel, and a display device. Background Art

[0002] With the development of display technology, the screen-to-body ratio of display panels is getting larger and larger, and narrow-border technology is attracting more and more attention.

[0003] To meet customer requirements, a new narrow-border technology is emerging in the industry. The related technology uses the technology of placing some fan-out lines in the display area (Fanout in AA, FIAA). The core of this technology is to achieve a narrow border of the product by adding two mask processes and a layer of metal routing. However, the use of this technology will significantly increase the preparation cost of the display panel, which is bound to cause production capacity loss. Summary of the Invention

[0004] Embodiments of the present invention provide an array substrate, a display panel, and a display device. The array substrate can implement FIAA technology to achieve a narrow bezel effect by optimizing wiring and pixel design without significantly increasing process costs.

[0005] In a first aspect, an embodiment of the present invention provides an array substrate, comprising:

[0006] A base substrate, the base substrate comprising a display area and a non-display area;

[0007] The display area includes a plurality of pixel circuits arranged in an array and a plurality of data signal lines located on one side of the base substrate, wherein the data signal lines are electrically connected to the plurality of pixel circuits, and the pixel circuits include a plurality of transistors;

[0008] a light-shielding metal layer, located on a side of the base substrate close to the pixel circuit, and covering an active area of ​​at least one of the transistors in a direction perpendicular to the base substrate;

[0009] The non-display area includes a first fan-out area, and the first fan-out area includes a plurality of first fan-out lines;

[0010] The display area includes a second fan-out area, the second fan-out area includes a plurality of second fan-out lines, a first end of the second fan-out line is electrically connected to the data signal line, and a second end of the second fan-out line is electrically connected to the first fan-out line;

[0011] Wherein, the second fan-out wiring is arranged on the same layer as the light-shielding metal layer.

[0012] In a second aspect, an embodiment of the present invention further provides an array substrate, comprising:

[0013] A base substrate, the base substrate comprising a display area and a non-display area;

[0014] The display area includes a plurality of pixel circuits arranged in an array and a plurality of data signal lines located on one side of the substrate, the data signal lines being electrically connected to the plurality of pixel circuits, the pixel circuits including N-type transistors and P-type transistors, the N-type transistors including a metal oxide active layer, and the P-type transistors including a low-temperature polysilicon active layer;

[0015] The non-display area includes a first fan-out area, and the first fan-out area includes a plurality of first fan-out lines;

[0016] The display area includes a second fan-out area, the second fan-out area includes a plurality of second fan-out lines, a first end of the second fan-out line is electrically connected to the data signal line, and a second end of the second fan-out line is electrically connected to the first fan-out line;

[0017] The second fan-out wiring is arranged on the same layer as the gate layer of the N-type transistor.

[0018] In a third aspect, an embodiment of the present invention further provides a display panel comprising the above-mentioned array substrate.

[0019] In a fourth aspect, an embodiment of the present invention further provides a display device comprising the above-mentioned display panel.

[0020] An array substrate provided by an embodiment of the present invention includes: a base substrate, the base substrate including a display area and a non-display area; the display area includes a plurality of array-arranged pixel circuits and a plurality of data signal lines located on one side of the base substrate, the data signal lines are electrically connected to the plurality of pixel circuits, and the pixel circuits include a plurality of transistors; a light-shielding metal layer, located on a side of the base substrate close to the pixel circuits, and the light-shielding metal layer covers the active area of ​​at least one transistor along a direction perpendicular to the base substrate; the non-display area includes a first fan-out area, the first fan-out area includes a plurality of first fan-out lines; the display area includes a second fan-out area, the second fan-out area includes a plurality of second fan-out lines, the first ends of the second fan-out lines are electrically connected to the data signal lines, and the second ends of the second fan-out lines are electrically connected to the first fan-out lines; wherein the second fan-out lines are arranged on the same layer as the light-shielding metal layer. By setting a light-shielding metal layer to block at least one transistor, the performance of the pixel circuit can be improved; by setting part of the fan-out area in the display area, a narrow frame effect can be achieved; by setting the second fan-out line on the same layer as the light-shielding metal layer, FIAA technology can be implemented without increasing the process flow, which is beneficial to reducing the cost of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 A schematic structural diagram of an array substrate provided by an embodiment of the present invention;

[0022] Figure 2 A schematic diagram of a partial structure of an array substrate provided by an embodiment of the present invention;

[0023] Figure 3 A schematic diagram of a partial structure of another array substrate provided by an embodiment of the present invention;

[0024] Figure 4 A schematic structural diagram of a second fan-out routing provided by an embodiment of the present invention;

[0025] Figure 5 A schematic structural diagram of a pixel circuit provided by an embodiment of the present invention;

[0026] Figure 6 A schematic diagram of the specific structure of a pixel circuit provided by an embodiment of the present invention;

[0027] Figure 7 A schematic cross-sectional structure diagram of an array substrate provided in an embodiment of the present invention;

[0028] Figure 8 A schematic diagram of a partial structure of another array substrate provided by an embodiment of the present invention;

[0029] Figure 9 A schematic structural diagram of another array substrate provided by an embodiment of the present invention;

[0030] Figure 10 A schematic structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0031] Figure 11 A schematic cross-sectional view of another array substrate provided by an embodiment of the present invention;

[0032] Figure 12 A schematic structural diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0033] The present invention will be further described in detail below with reference to the accompanying drawings and examples. It will be understood that the specific embodiments described herein are intended only to illustrate the present invention and are not intended to limit the present invention. It should also be noted that, for ease of description, the accompanying drawings only illustrate portions relevant to the present invention, not all structures.

[0034] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. It should be noted that the directional words such as "upper", "lower", "left", and "right" described in the embodiments of the present invention are described based on the angles shown in the accompanying drawings and should not be understood as limitations on the embodiments of the present invention. In addition, in the context, it is also necessary to understand that when it is mentioned that an element is formed "on" or "under" another element, it can not only be formed directly "on" or "under" another element, but can also be formed indirectly "on" or "under" another element through an intermediate element. The terms "first", "second", etc. are only used for descriptive purposes and do not indicate any order, quantity or importance, but are only used to distinguish different components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to the specific circumstances.

[0035] Figure 1 This is a structural diagram of an array substrate provided by an embodiment of the present invention. Figure 1 The array substrate includes a base substrate 100, which includes a display area AA and a non-display area NA; the display area AA includes a plurality of pixel circuits 10 arranged in an array and a plurality of data signal lines 20 located on one side of the base substrate 100, the data signal lines 20 are electrically connected to the plurality of pixel circuits 10, and the pixel circuits 10 include a plurality of transistors ( Figure 1 light-shielding metal layer 30, located on one side of the base substrate 100 close to the pixel circuit 10, along a direction perpendicular to the base substrate 100, the light-shielding metal layer 30 covers the active area of ​​at least one transistor. Figure 2 A schematic diagram of a partial structure of an array substrate provided by an embodiment of the present invention. Figure 2 The non-display area NA includes a first fan-out area 40, which includes a plurality of first fan-out traces 41; the display area AA includes a second fan-out area 50, which includes a plurality of second fan-out traces 51, wherein a first end of the second fan-out trace 51 is electrically connected to the data signal line 20, and a second end of the second fan-out trace 51 is electrically connected to the first fan-out trace 41; wherein the second fan-out trace 51 is arranged on the same layer as the light-shielding metal layer 30.

[0036] Among them, the array substrate provided in this embodiment can be used in a display panel, and the display panel can be an organic light-emitting diode (OLED) or micro light-emitting diode (Micro LED) display panel, or other types of display panels, which are not limited in this embodiment of the present invention. The base substrate 100 can be a rigid substrate, such as a glass substrate, or a flexible substrate, such as a polyimide (PI) substrate, and can be selected according to actual conditions during specific implementation. The display area AA of the base substrate 100 includes a plurality of pixel circuits 10 arranged in an array, wherein the structure of the pixel circuit 10 can be designed according to actual conditions, such as a 7T1C structure including 7 transistors and 1 capacitor. For example, refer to Figure 1 , the pixel circuits 10 are arranged in an array of multiple rows and columns, and a data signal line 20 is electrically connected to a column of pixel circuits 10 to provide data signals to the corresponding pixel circuits 10. Figure 1 The top view of the array substrate is shown, so the positional relationship of the film layers is not shown. In a specific implementation, the light-shielding metal layer 30 is located below the pixel circuit 10 and is used to shield the active area of ​​part of the transistor. This arrangement can improve transistor performance. For example, the light-shielding metal layer 30 shields the driving transistor, which can improve the threshold stability and subthreshold swing stability of the driving transistor. It also helps to improve the anti-static interference capability of the array substrate and protect key components. Figure 2 , the first fan-out line 41 of the first fan-out area 40 can be used to connect to the driver chip ( Figure 2 (not shown), in this embodiment, by setting a second fan-out area 50 in the display area AA, the width of the non-display area NA can be effectively reduced, and the narrow frame effect of the display panel can be achieved. Moreover, in this embodiment, by reusing the light-shielding metal layer 30 to form a second fan-out wiring 51, it is possible to meet product requirements without increasing the Mask, which is beneficial to significantly reduce costs. The existing FIAA technology adds a layer of metal wiring above the film layer of the pixel circuit 10. Since the wiring is pulled in the display area AA, it has a great impact on the uniformity of the display. In this embodiment, by reusing the light-shielding metal layer 30 located below the film layer of the pixel circuit 10, the uniformity of the display is less affected.

[0037] Continue to refer Figure 2 Optionally, the second fan-out area 50 is located in a corner area of ​​the display area AA close to the non-display area NA.

[0038] It is understood that in the structure of a display panel, the corners of the display area AA are generally rounded, commonly referred to as "R-corners," and the width of the non-display area NA adjacent to the display area AA is designed to be narrower. For example, in one embodiment, the lower border of the non-display area NA is designed to be 9 mm less than the edge of the display area AA. To ensure the narrow border effect of the display panel, the FIAA technology provided in this embodiment is adopted, and the second fan-out area 50 is located in the corner area of ​​the display area AA on the side close to the non-display area NA, thereby achieving a narrow border effect.

[0039] The technical solution of the embodiment of the present invention can improve the performance of the pixel circuit by setting a light-shielding metal layer to block at least one transistor; by setting part of the fan-out area in the display area, a narrow frame effect can be achieved; by setting the second fan-out line and the light-shielding metal layer on the same layer, FIAA technology can be implemented without increasing the process, which is beneficial to reducing the cost of the display panel.

[0040] Figure 3 A schematic diagram of the partial structure of another array substrate provided by an embodiment of the present invention. Figure 3 Optionally, the light-shielding metal layer 30 includes a plurality of light-shielding blocks 31, and the light-shielding blocks 31 cover the active area ( Figure 3 The second fan-out wiring 51 is electrically connected to at least one light shielding block 31.

[0041] It can be understood that since the second fan-out line 51 is set on the same layer as the shading metal layer 30, by setting the second fan-out line 51 to be connected to at least one shading block 31, the resistance of the second fan-out line 51 can be effectively reduced by utilizing the principle of parallel resistance reduction, thereby reducing the power consumption of the panel.

[0042] In another embodiment, Figure 4 This is a schematic diagram of the structure of a second fan-out routing provided by an embodiment of the present invention. Figure 4 Optionally, the second fan-out routing 51 includes a plurality of first routings 511 extending along a first direction x and a plurality of second routings 512 extending along a second direction y. The first routings 511 and the second routings 512 are electrically connected to form a mesh structure, and the first direction x and the second direction y intersect.

[0043] Since the light-shielding metal layer 30 is located on the side of the pixel circuit 10 close to the base substrate 100 (below the pixel circuit 10), it is not electrically connected to the pixel circuit 10. Therefore, in order to reduce the resistance of the second fan-out trace 51, a mesh structure of the second fan-out trace 51 can be designed. In a specific implementation, the first direction x can be designed to be parallel to the row direction of the pixel circuit array, and the second direction y can be designed to be parallel to the column direction of the pixel circuit array. In other embodiments, the first direction x and the second direction y can also be designed according to actual conditions. In a specific implementation, the design can be based on actual conditions.

[0044] Figure 5 A schematic diagram of the structure of a pixel circuit provided by an embodiment of the present invention. Figure 5 , optionally, the pixel circuit includes a first light-emitting control module 11, a second light-emitting control module 12, a first initialization module 13, a second initialization module 14, a driving module 15, a data writing module 16, a threshold compensation module 17 and a storage module 18; the control end of the first light-emitting control module 11 is electrically connected to the enable signal line Emit, the first end of the first light-emitting control module 11 is electrically connected to the first power supply voltage signal line PVDD, and the second end of the first light-emitting control module 11 is electrically connected to the first end of the driving module 15; the control end of the driving module 15 is electrically connected to the first node N1, and the second end of the driving module 15 is electrically connected to the first end of the second light-emitting control module 12; the control end of the second light-emitting control module 12 is electrically connected to the enable signal line Emit, and the second end of the second light-emitting control module 12 is electrically connected to the first electrode of the light-emitting element D; the control end of the first initialization module 13 is connected to the first scanning signal line S1, the first end of the first initialization module 13 is electrically connected to the first reference signal line Vref1, and the first The second end of the initialization module 13 is electrically connected to the first node N1; the control end of the data writing module 16 is electrically connected to the second scanning signal line S2, the first end of the data writing module 16 is electrically connected to the data signal line Data, and the second end of the data writing module 16 is electrically connected to the first end of the driving module 15; the control end of the threshold compensation module 17 is electrically connected to the third scanning signal line S3, the first end of the threshold compensation module 17 is electrically connected to the second end of the driving module 15, and the second end of the threshold compensation module 17 is electrically connected to the first node N1; the control end of the second initialization module 14 is electrically connected to the fourth scanning signal line S4, the first end of the second initialization module 14 is electrically connected to the second reference signal line Vref2, the second end of the second initialization module 14 is electrically connected to the first electrode of the light-emitting element D, and the second electrode of the light-emitting element D is electrically connected to the second power supply voltage signal line PVEE; the first end of the storage module 18 is electrically connected to the first node N1, and the second end of the storage module 18 is electrically connected to the first power supply voltage signal line PVDD.

[0045] Specifically, refer to Figure 5The pixel circuit is provided with a first light emission control module 11, a second light emission control module 12, a first initialization module 13, a second initialization module 14, a driver module 15, a data writing module 16, a threshold compensation module 17, and a storage module 18. The control terminal of the first initialization module 13 is electrically connected to the first scan signal line S1, the first terminal of the first initialization module 13 is electrically connected to the first reference signal line Vref1, and the second terminal of the first initialization module 13 is electrically connected to the first node N1. During the initialization phase, the first initialization module 13 is turned on in response to the first scan signal transmitted by the first scan signal line S1, and the first reference signal is written to the first node N1. The control terminal of the driver module 15 is connected to the first node N1, and the first reference signal is written to the control terminal of the driver module 15, thereby completing the initialization of the driver module 15.

[0046] The control terminal of the data writing module 16 is electrically connected to the second scan signal line S2, the first terminal of the data writing module 16 is electrically connected to the data signal line Data, and the second terminal of the data writing module 16 is electrically connected to the first terminal of the driving module 15. The control terminal of the threshold compensation module 17 is electrically connected to the third scan signal line S3, the first terminal of the threshold compensation module 17 is electrically connected to the second terminal of the driving module 15, and the second terminal of the threshold compensation module 17 is electrically connected to the first node N1. The first terminal of the storage module 18 is electrically connected to the first node N1, and the second terminal of the storage module 18 is electrically connected to the first power supply voltage signal line PVDD. During the data writing phase, the data writing module 16 is turned on in response to the second scan signal transmitted by the second scan signal line S2, the threshold compensation module 17 is turned on in response to the third scan signal transmitted by the third scan signal line S3, and the driving module 15 is turned on at the same time. The data voltage signal is sequentially written to the control terminal of the driving module 15 (i.e., the first node N1) through the data writing module 16, the driving module 15, and the threshold compensation module 17. The storage module 18 stores the voltage of the first node N1.

[0047] The control end of the second initialization module 14 is electrically connected to the fourth scan signal line S4, the first end of the second initialization module 14 is electrically connected to the second reference signal line Vref2, and the second end of the second initialization module 14 is electrically connected to the first electrode of the light-emitting element D. In the data writing stage, the second initialization module 14 is turned on according to the fourth scan signal transmitted by the fourth scan signal line S4, and the second reference signal is written into the first electrode of the light-emitting element D to initialize the first electrode of the light-emitting element D.

[0048] The control terminal of the first light-emitting control module 11 is electrically connected to the enable signal line Emit, the first terminal of the first light-emitting control module 11 is electrically connected to the first power supply voltage signal line PVDD, and the second terminal of the first light-emitting control module 11 is electrically connected to the first terminal of the driver module 15; the second terminal of the driver module 15 is electrically connected to the first terminal of the second light-emitting control module 12; the control terminal of the second light-emitting control module 12 is electrically connected to the enable signal line Emit, and the second terminal of the second light-emitting control module 12 is electrically connected to the first electrode of the light-emitting element D. During the light-emitting phase, the first and second light-emitting control modules 11 and 12 are turned on according to the enable signal transmitted by the enable signal line Emit, the driver module 15 is turned on, and the power supply voltage signal passes through the first light-emitting control module 11, the driver module 15, and the second light-emitting control module 12, thereby generating a drive current to drive the light-emitting element D to emit light.

[0049] Among them, optionally, the first light-emitting control module 11 includes a first transistor M1, the data writing module 16 includes a second transistor M2, the driving module 15 includes a third transistor M3, the threshold compensation module 17 includes a fourth transistor M4, the first initialization module 13 includes a fifth transistor M5, the second light-emitting control module 12 includes a sixth transistor M6, the second initialization module 14 includes a seventh transistor M7, and the storage module 18 includes a storage capacitor C; the first electrode can be the anode of the light-emitting element D.

[0050] Figure 5 The connection structure diagram of a 7T1C pixel circuit is only shown as an example. The connection method of each component in the above pixel circuit is optional. In actual application, those skilled in the art can adjust the design method of the pixel circuit according to actual needs. For example, in one embodiment, the first initialization module 13 can be electrically connected to the second end of the driving module 15, and at least two scanning signal lines can be multiplexed. Figure 5 The circuit structure shown in the figure takes the transistors as P-type transistors as an example. Optionally, the transistors in the pixel circuit are all P-type transistors or all N-type transistors. The specific implementation can be designed according to actual conditions.

[0051] Figure 6 A schematic diagram of a specific structure of a pixel circuit provided by an embodiment of the present invention. Figure 6 Optionally, the pixel circuit includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7 and a storage capacitor C; along a direction perpendicular to the base substrate 100, the light-shielding metal layer 30 covers the active areas of the third transistor M3, the fourth transistor M4 and the fifth transistor M5.

[0052] By providing a light-shielding metal layer 30 to shield the M3 / M4 / M5 devices of the 7T1C pixel circuit, the signal stability of the first node N1 can be improved, the uniformity of the threshold and subthreshold swing of the third transistor M3 can be improved, and the overall copper rod friction and plate ESD resistance can be improved, thereby protecting key components.

[0053] Figure 7 A schematic cross-sectional view of an array substrate provided by an embodiment of the present invention. Figure 7 Optionally, the pixel circuit includes a first metal layer 101, a second metal layer 102, a third metal layer 103 and a fourth metal layer 104; the enable signal line, the first scan signal line, the second scan signal line, the third scan signal line, the fourth scan signal line and the first electrode of the storage capacitor are all located in the first metal layer 101 ( Figure 7 The first reference signal line, the second reference signal line and the second plate of the storage capacitor are all located in the second metal layer 102; the data signal line is located in the third metal layer 103; the first power supply voltage signal line is located in the third metal layer 103 and the fourth metal layer 104.

[0054] In specific implementation, an insulating layer is set between two adjacent metal layers. When the wiring of different metal layers needs to be connected, electrical connection can be achieved through vias set in the insulating layer. When the wiring of the same layer does not need to be electrically connected but may cross during design, crossing can be avoided by changing the line. Figure 7 Schematically shows a transistor 200 , which includes an active layer 201 , a gate layer 202 and a source-drain layer 203 , wherein the gate layer 202 is located in the first metal layer 101 , and the source-drain layer 203 is located in the third metal layer 103 .

[0055] The array substrate in the embodiment of the present invention may also include other conventionally set film layers, such as a light-emitting layer, a planarization layer, and a pixel definition layer. The setting method of the above-mentioned conventional film layers can be set by technical personnel in this field according to actual needs, and the embodiment of the present invention does not elaborate on this and does not limit it.

[0056] Figure 8 A schematic diagram of a partial structure of another array substrate provided by an embodiment of the present invention. Figure 8 Optionally, the first fan-out area 40 includes a first sub-fan-out area 410 and a second sub-fan-out area 420, and the first sub-fan-out area 410 is located on the side of the second sub-fan-out area 420 close to the display area AA; the first sub-fan-out area 410 includes a first sub-fan-out routing 411, and the second sub-fan-out area 420 includes a second sub-fan-out routing 421, the first sub-fan-out routing 411 is located in the second metal layer and / or the third metal layer, and the second sub-fan-out routing 421 is located in the fourth metal layer.

[0057] In this embodiment, in the AA area, the data signal line is switched using metal routing on the same layer as the light-shielding metal layer. The data signal line is routed to the first sub-fan-out area 410, and then the second metal layer and / or the third metal layer are used to switch the line to avoid crossing of different signal lines on the same layer. The data signal line is then routed to the second sub-fan-out area 420 and switched to the fourth metal layer. Optionally, the second sub-fan-out area 420 is a bending area. By setting the second sub-fan-out area 420 as a bending area, it is possible to achieve bending of part of the non-display area, further reducing the width of the frame and achieving a narrow frame effect. In addition, the fourth metal layer generally adopts a multi-layer metal stacked structure, which has good bending performance and can avoid breakage during bending.

[0058] In some embodiments, the display panel may be provided with a hole-punch area for placing devices such as a camera, and the narrow frame design of the hole-punch area is also a problem that technicians need to solve. The design concept of the embodiment of the present invention can also be extended to the hole-punch area to achieve a narrower frame of the hole-punch area. For example, Figure 9 This is a schematic diagram of the structure of another array substrate provided by an embodiment of the present invention. Figure 9 Optionally, the display area AA includes at least one hole area A1, and the data signal lines around the edge of the hole area A1 are arranged on the same layer as the light shielding metal layer ( Figure 9 The specific structure is not shown in the figure), thereby realizing a narrow frame design of the hole area.

[0059] When designing a pixel circuit, in addition to using transistors of the same type, two types of transistors can also be used, that is, the pixel circuit includes both P-type transistors and N-type transistors. For example, Figure 10 A schematic diagram of another pixel circuit structure provided by an embodiment of the present invention, Figure 5 The difference is that in this embodiment, the fourth transistor M4 and the fifth transistor M5 are N-type transistors, and the other transistors are P-type transistors. The N-type transistors are based on metal oxide (such as IGZO) and the P-type transistors are based on low-temperature polysilicon. Compared with low-temperature polysilicon transistors, metal oxide has advantages such as high transmittance, low electron mobility, large on-off ratio, and low power consumption. The pixel circuit formed by using these two transistors has better performance.

[0060] Based on this, an embodiment of the present invention also provides an array substrate, including: a base substrate, the base substrate including a display area and a non-display area; the display area including a plurality of array-arranged pixel circuits and a plurality of data signal lines located on one side of the base substrate, the data signal lines being electrically connected to the plurality of pixel circuits, the pixel circuits including N-type transistors and P-type transistors, the N-type transistor including a metal oxide active layer, the P-type transistor including a low-temperature polysilicon active layer; the non-display area including a first fan-out area, the first fan-out area including a plurality of first fan-out lines; the display area including a second fan-out area, the second fan-out area including a plurality of second fan-out lines, the first end of the second fan-out line being electrically connected to the data signal line, and the second end of the second fan-out line being electrically connected to the first fan-out line; wherein the second fan-out line is arranged on the same layer as the gate layer of the N-type transistor.

[0061] Figure 11 This is a schematic cross-sectional view of another array substrate provided by an embodiment of the present invention. Figure 11 The array substrate includes an N-type transistor 200N and a P-type transistor 200P, wherein the P-type transistor includes a first active layer 201P, a first gate layer 202P and a first source-drain layer 203P, and the N-type transistor includes a second active layer 201N, a second gate layer 202N and a second source-drain layer 203N, wherein the second gate layer 202N is located in the fifth metal layer 105. In this embodiment, the second fan-out line is arranged on the same layer as the fifth metal layer.

[0062] Continue to refer Figure 11 Optionally, the array substrate further includes a light-shielding metal layer 30, which is located on a side of the base substrate 100 close to the pixel circuit. Along a direction z perpendicular to the base substrate 100, the light-shielding metal layer 30 covers the active area of ​​at least one N-type transistor and a P-type transistor.

[0063] During specific implementation, the light shielding metal layer 30 is disposed in a manner similar to that of the aforementioned embodiment, and may also cover the third transistor M3 , the fourth transistor M4 , and the fifth transistor M5 .

[0064] Based on the same concept, an embodiment of the present invention further provides a display panel, which includes any of the array substrates provided in the above embodiments. The display panel provided by the embodiment of the present invention includes all the technical features and corresponding beneficial effects of the array substrate provided by any embodiment of the present invention, which will not be repeated here.

[0065] Figure 12 A schematic diagram of the structure of a display device provided by an embodiment of the present invention. Figure 12 The display device 1 includes any one of the display panels 2 provided in the embodiments of the present invention. The display device 1 can be a mobile phone, a computer, a smart wearable device, etc.

[0066] Note that the above are only preferred embodiments of the present invention and the technical principles employed. Those skilled in the art will appreciate that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, combinations, and substitutions are possible for those skilled in the art without departing from the scope of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments and may include many other equivalent embodiments without departing from the scope of the present invention. The scope of the present invention is determined by the scope of the appended claims.

Claims

1. An array substrate, characterized in that: include: A base substrate, the base substrate comprising a display area and a non-display area; The display area includes a plurality of pixel circuits arranged in an array and a plurality of data signal lines located on one side of the base substrate, wherein the data signal lines are electrically connected to the plurality of pixel circuits, and the pixel circuits include a plurality of transistors; a light-shielding metal layer, located on a side of the base substrate close to the pixel circuit, and covering an active area of ​​at least one of the transistors in a direction perpendicular to the base substrate; The non-display area includes a first fan-out area, and the first fan-out area includes a plurality of first fan-out lines; The display area includes a second fan-out area, the second fan-out area includes a plurality of second fan-out lines, a first end of the second fan-out line is electrically connected to the data signal line, and a second end of the second fan-out line is electrically connected to the first fan-out line; Wherein, the second fan-out wiring is arranged on the same layer as the light-shielding metal layer; The light-shielding metal layer includes a plurality of light-shielding blocks, and the second fan-out line is electrically connected to at least one of the light-shielding blocks; The second fan-out area is located in a corner area of ​​the display area on a side close to the non-display area.

2. The array substrate according to claim 1, wherein: Along a direction perpendicular to the substrate, the light shielding block covers an active area of ​​at least one of the transistors.

3. The array substrate according to claim 1, wherein: The second fan-out routing includes a plurality of first routings extending along a first direction and a plurality of second routings extending along a second direction. The first routings and the second routings are electrically connected to form a mesh structure. The first direction and the second direction intersect.

4. The array substrate according to claim 1, wherein: The pixel circuit includes a first light emitting control module, a second light emitting control module, a first initialization module, a second initialization module, a driving module, a data writing module, a threshold compensation module and a storage module; The control end of the first light emitting control module is electrically connected to the enable signal line, the first end of the first light emitting control module is electrically connected to the first power supply voltage signal line, and the second end of the first light emitting control module is electrically connected to the first end of the driving module; The control end of the driving module is electrically connected to the first node, and the second end of the driving module is electrically connected to the first end of the second light-emitting control module; The control end of the second light emitting control module is electrically connected to the enable signal line, and the second end of the second light emitting control module is electrically connected to the first electrode of the light emitting element; The control end of the first initialization module is connected to the first scan signal line, the first end of the first initialization module is electrically connected to the first reference signal line, and the second end of the first initialization module is electrically connected to the first node; The control end of the data writing module is electrically connected to the second scanning signal line, the first end of the data writing module is electrically connected to the data signal line, and the second end of the data writing module is electrically connected to the first end of the driving module; The control end of the threshold compensation module is electrically connected to the third scan signal line, the first end of the threshold compensation module is electrically connected to the second end of the driving module, and the second end of the threshold compensation module is electrically connected to the first node; The control end of the second initialization module is electrically connected to the fourth scan signal line, the first end of the second initialization module is electrically connected to the second reference signal line, and the second end of the second initialization module is electrically connected to the first electrode of the light-emitting element; A first end of the storage module is electrically connected to the first node, and a second end of the storage module is electrically connected to the first power supply voltage signal line.

5. The array substrate according to claim 4, wherein: The first light emitting control module includes a first transistor, the data writing module includes a second transistor, the driving module includes a third transistor, the threshold compensation module includes a fourth transistor, the first initialization module includes a fifth transistor, the second light emitting control module includes a sixth transistor, the second initialization module includes a seventh transistor, and the storage module includes a storage capacitor; Along a direction perpendicular to the substrate, the light-shielding metal layer covers active regions of the third transistor, the fourth transistor, and the fifth transistor.

6. The array substrate according to claim 5, wherein: The pixel circuit includes a first metal layer, a second metal layer, a third metal layer and a fourth metal layer; The enable signal line, the first scan signal line, the second scan signal line, the third scan signal line, the fourth scan signal line and the first electrode plate of the storage capacitor are all located in the first metal layer; The first reference signal line, the second reference signal line and the second plate of the storage capacitor are all located in the second metal layer; The data signal line is located in the third metal layer; The first power supply voltage signal line is located in the third metal layer and the fourth metal layer.

7. The array substrate according to claim 6, wherein: The first fan-out area includes a first sub-fan-out area and a second sub-fan-out area, and the first sub-fan-out area is located on a side of the second sub-fan-out area close to the display area; The first sub-fan-out area includes a first sub-fan-out routing, the second sub-fan-out area includes a second sub-fan-out routing, the first sub-fan-out routing is located in the second metal layer and / or the third metal layer, and the second sub-fan-out routing is located in the fourth metal layer.

8. The array substrate according to claim 7, wherein: The second sub-fan-out area is a bending area.

9. The array substrate according to claim 1, wherein: The display area includes at least one hole-punching area, and the data signal lines surrounding the edge of the hole-punching area are arranged in the same layer as the light-shielding metal layer.

10. The array substrate according to claim 1, wherein: The transistors in the pixel circuit are all P-type transistors or all N-type transistors.

11. A display panel, characterized in that: The invention comprises the array substrate according to any one of claims 1 to 10.

12. A display device, characterized in that: The display panel according to claim 11 is included.

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