Voltage controlled oscillation device and power supply stabilization circuit therefor

Abstract

The present application relates to a power stabilizing circuit with a noise suppression mechanism configured to drive a voltage-controlled oscillator circuit. The power stabilizing circuit includes a current-regulating N-type transistor and a regulating voltage generating circuit. The current-regulating N-type transistor includes a drain, a source and a gate. The drain receives a first operating voltage. The source generates a power signal to the voltage-controlled oscillator circuit to cause the voltage-controlled oscillator circuit to operate according to the power signal. The gate receives a regulating voltage. The regulating voltage generating circuit operates according to a second operating voltage higher than the first operating voltage and generates the regulating voltage according to a reference voltage generated by voltage division according to the first operating voltage. The regulating voltage is a sum of the reference voltage and a threshold voltage of the current-regulating N-type transistor, causing the current-regulating N-type transistor to operate in a saturation region and causing a current variation of the power signal to be less than a predetermined value.

Description

Technical Field

[0001] This invention relates to voltage-controlled oscillator (VCO) circuit technology, and more particularly to a VCO device and its power supply stabilization circuit. Background Technology

[0002] In phase-locked loops (PLLs) and clock and data recovery (CDR) circuits, voltage-controlled oscillators (VCOs) are often used to provide an oscillation signal with a specific frequency, enabling phase or frequency locking through a feedback mechanism. The oscillation frequency of the VCO signal can be changed by adjusting the control voltage.

[0003] Voltage-controlled oscillators (VCOs) are susceptible to jitter due to power supply signal noise. A common technique is to use low-dropout regulators (LDOs) for voltage regulation. However, with the evolution of manufacturing processes, component voltage ratings have become increasingly smaller, resulting in insufficient voltage margin. Furthermore, LDOs use operational amplifiers for filtering via a feedback mechanism, which not only results in large area and power consumption, but the noise of the operational amplifiers themselves can also easily affect the VCO. Summary of the Invention

[0004] In view of the problems of the prior art, one object of the present invention is to provide a voltage-controlled oscillator and its power supply stabilization circuit to improve the prior art.

[0005] This invention includes a power supply stabilization circuit with a noise suppression mechanism, configured to drive a voltage-controlled oscillator (VCO) circuit. The power supply stabilization circuit includes a current-regulating N-type transistor and a regulating voltage generation circuit. The current-regulating N-type transistor includes a drain, a source, and a gate. The drain is configured to receive a first operating voltage. The source is configured to generate a power supply signal to the VCO circuit, causing the VCO circuit to operate according to the power supply signal. The gate is configured to receive the regulating voltage. The regulating voltage generation circuit is configured to operate according to a second operating voltage higher than the first operating voltage, and receives a reference voltage generated by dividing the first operating voltage to generate the regulating voltage, wherein the regulating voltage is the sum of the reference voltage and the threshold voltage of the current-regulating N-type transistor, so that the current-regulating N-type transistor operates in the saturation region, thereby making the current variation of the power supply signal less than a preset current variation value.

[0006] The present invention also includes a voltage-controlled oscillator (VCO) device, comprising: a VCO circuit and a power supply stabilization circuit. The VCO circuit operates according to a power supply signal. The power supply stabilization circuit includes: a current-regulating N-type transistor and a regulating voltage generation circuit. The current-regulating N-type transistor includes: a drain, a source, and a gate. The drain is configured to receive a first operating voltage. The source is configured to generate a power supply signal to the VCO circuit. The gate is configured to receive a regulating voltage. The regulating voltage generation circuit is configured to operate according to a second operating voltage higher than the first operating voltage, and receives a reference voltage generated by voltage division of the first operating voltage to generate a regulating voltage, wherein the regulating voltage is the sum of the reference voltage and the threshold voltage of the current-regulating N-type transistor, so that the current-regulating N-type transistor operates in the saturation region, thereby making the current variation of the power supply signal less than a preset current variation value.

[0007] The features, implementation, and effects of the present invention will be described in detail below with reference to the accompanying drawings, focusing on preferred embodiments. Attached Figure Description

[0008] Figure 1 A block diagram of a voltage-controlled oscillator device according to an embodiment of the present invention is shown; and

[0009] Figure 2 A circuit diagram of a power stabilization circuit according to an embodiment of the present invention is shown. Detailed Implementation

[0010] One objective of this invention is to provide a voltage-controlled oscillator and its power supply stabilization circuit, which generates a stable, undisturbed power signal with sufficient margin to the voltage-controlled oscillator circuit, so that the voltage-controlled oscillator circuit can stably output an oscillation signal with an oscillation frequency.

[0011] Please refer to Figure 1 . Figure 1 A block diagram of a voltage-controlled oscillator 100 according to an embodiment of the present invention is shown. The voltage-controlled oscillator 100 includes a voltage-controlled oscillator circuit 110 and a power supply stabilization circuit 120.

[0012] The voltage-controlled oscillator circuit 110 is configured to receive a power supply signal CS and operate according to the power supply signal CS. In one embodiment, the voltage-controlled oscillator circuit 110 includes a control voltage receiving circuit 140 and an oscillator 150. The control voltage receiving circuit 140 is configured to receive a control voltage VCTL, thereby causing the oscillator 150 to generate oscillation signals (not shown) with different oscillation frequencies according to changes in the control voltage VCTL.

[0013] In one embodiment, the voltage-controlled oscillator circuit 110 can be applied to, for example, but not limited to, phase-locked loops (PLLs), clock and data recovery (CDR) circuits, or other circuits that perform phase-locking or frequency-locking based on a feedback mechanism. The voltage-controlled oscillator circuit 110 can determine the oscillation frequency of the oscillation signal based on the control voltage VCTL received from other circuit modules in these circuits.

[0014] It should be noted that, Figure 1 The control voltage receiving circuit 140 and oscillator 150 shown are merely an example. In other embodiments, the control voltage receiving circuit 140 and oscillator 150 may be implemented with other circuit structures.

[0015] The power stabilization circuit 120 includes a current-regulating N-type transistor MNA and a voltage-regulating generation circuit 130.

[0016] The current-regulated N-type transistor MNA includes a drain DA, a source SA, and a gate GA. The drain DA is configured to receive a first operating voltage VDD1. In one embodiment, the first operating voltage VDD1 is 1.8 volts. The source SA is configured to generate a power supply signal CS to the voltage-controlled oscillator circuit 110, wherein the power supply signal CS has a corresponding current IC and voltage VC. The gate GA is configured to receive a regulated voltage VA.

[0017] The regulating voltage generating circuit 130 is configured to generate a regulating voltage VA. In one embodiment, the power stabilizing circuit 120 may optionally include a filter circuit 160 disposed on the path from the regulating voltage generating circuit 130 generating the regulating voltage VA to the gate GA of the current-regulating N-type transistor MNA, to provide filtering and stabilizing of the regulating voltage VA. In one embodiment, the filter circuit 160 may be as follows: Figure 1 The diagram shows a capacitive-resistive circuit including a resistor RF and a capacitor CF. However, this invention is not limited thereto.

[0018] The regulating voltage generating circuit 130 operates based on a second operating voltage VDD2, which is higher than the first operating voltage VDD1. In one embodiment, the second operating voltage VDD2 is 3.3 volts. Further, the regulating voltage generating circuit 130 receives a reference voltage VREF generated by dividing the first operating voltage VDD1 to generate a regulating voltage VA.

[0019] The regulating voltage VA is the sum of the reference voltage VREF and the threshold voltage VTHA of the current-regulating N-type transistor MNA, i.e., VA = VREF + VTHA. Therefore, the current-regulating N-type transistor MNA operates in the saturation region, thereby making the current fluctuation of the current IC corresponding to the power supply signal CS less than the preset current fluctuation value.

[0020] In one embodiment, the current-regulated N-type transistor MNA has a high impedance relative to the first operating voltage VDD1. In this case, the current IC corresponding to the power supply signal CS is defined by the aforementioned control voltage VCTL. However, under the control of the current-regulated N-type transistor MNA by a stable ground-based voltage regulation voltage VA, the voltage VC of the power supply signal CS is defined by the current IC and the gate-source voltage difference of the current-regulated N-type transistor MNA.

[0021] Therefore, since the current-regulating N-type transistor MNA has a high impedance when viewed from the drain DA end, it can effectively suppress the disturbance caused by noise due to process, voltage, and temperature (PVT) variations in the first operating voltage VDD1, making the current fluctuation of the current IC less than the current fluctuation preset value, and thus making the voltage fluctuation of the voltage VC less than the voltage fluctuation preset value.

[0022] Please refer to Figure 2 . Figure 2 A circuit diagram of a voltage regulation generating circuit 130 according to an embodiment of the present invention is shown. The voltage regulation generating circuit 130 includes: a first resistor R1, a second resistor R2, a first N-type transistor MN1, a second N-type transistor MN2, and a third N-type transistor MN3.

[0023] The first N-type transistor MN1 includes a drain D1, a source S1, and a gate G1. The drain D1 is configured to receive a first operating voltage VDD1. The source S1 is electrically coupled to ground GND through the first resistor R1. The gate G1 is configured to receive a reference voltage VREF.

[0024] The reference voltage VREF is generated by dividing the first operating voltage VDD1. In one embodiment, the magnitude of the reference voltage VREF can be 80% to 90% of the magnitude of the first operating voltage VDD1. Taking a first operating voltage VDD1 of 1.8 volts as an example, the reference voltage VREF can be about 200 to 300 millivolts less than the first operating voltage VDD1, and is 1.5 to 1.6 volts. This size configuration will help the current-regulated N-type transistor MNA remain in the saturation region when disturbed by the first operating voltage VDD1, thus effectively suppressing power supply noise.

[0025] In one embodiment, the reference voltage VREF is generated by dividing the first operating voltage VDD1 using a variable resistor RVA, and the variable resistor RVA can be located within the regulating voltage generation circuit 130 or independently of the regulating voltage generation circuit 130. In other embodiments, the reference voltage VREF can also be generated by other types of voltage divider circuits.

[0026] The second N-type transistor MN2 includes a drain D2, a source S2, and a gate G2. The source S2 is electrically coupled to ground GND through a first resistor R1. The gate G2 is electrically coupled to the drain D2 to form a diode-connected configuration.

[0027] The third N-type transistor MN3 includes a drain D3, a source S3, and a gate G3. The drain D3 receives a second operating voltage VDD2 through a second resistor R2. In one embodiment, the second operating voltage VDD2 is 3.3 volts. The source S3 is electrically coupled to the drain D2 of the second N-type transistor MN2. The gate G3 is electrically coupled to the drain D3 to form a diode connection.

[0028] Furthermore, gate G3 and Figure 1 The gate GA of the current-regulating N-type transistor MNA is electrically coupled to output a regulated voltage VA.

[0029] In operation, the resistance values ​​of the first resistor R1 and the second resistor R2 are such that the first N-type transistor MN1, the second N-type transistor MN2, and the third N-type transistor MN3 all operate in the weak inversion region.

[0030] Because it operates in the weak inversion region, the first N-type transistor MN1 will generate a very small current, making the voltage difference between its gate G1 and source S1 substantially equal to the threshold voltage VTH1 of the first N-type transistor MN1. In this condition, the voltage at the source S1 will be VREF - VTH1. It should be noted that the phrase "substantially" means that the voltage difference does not necessarily have to be exactly equal to the threshold voltage VTH1, but can have a reasonable margin of error.

[0031] The source voltage S2 of the second N-type transistor MN2 is the same as the source voltage S1, which is VREF-VTH1. Because it operates in the weak inversion region, the second N-type transistor MN2 will generate a very small current, and the voltage difference between the gate G2 and source S2 of the second N-type transistor MN2 will be substantially equal to the threshold voltage VTH2 of the second N-type transistor MN2. It should be noted that the phrase "substantially" means that the voltage difference between the two does not necessarily have to be exactly equal to the threshold voltage VTH2, but can have a reasonable range of error.

[0032] In one embodiment, the second N-type transistor MN2 is matched with the first N-type transistor MN1, such that the threshold voltage VTH2 of the second N-type transistor MN2 is the same as the threshold voltage VTH1 of the first N-type transistor MN1, i.e., VTH1 = VTH2. Therefore, the voltage at the gate G2 of the second N-type transistor MN2 will be VREF - VTH1 + VTH2 = VREF. Furthermore, since the gate G2 of the second N-type transistor MN2 is electrically coupled to the drain D2, the voltage at the drain D2 is also VREF.

[0033] Because it operates in the weak inversion region, the third N-type transistor MN3 will generate a very small current, and the voltage difference between the gate G3 and source S3 of the third N-type transistor MN3 will be substantially equal to the threshold voltage VTH3 of the third N-type transistor MN3. It should be noted that the word "substantially" means that the voltage difference between the two does not necessarily have to be exactly equal to the threshold voltage VTH3, but can have an error within a reasonable range.

[0034] The threshold voltage VTH3 does not necessarily have to be the same as the threshold voltages VTH1 and VTH2. Therefore, the voltage at the gate G3 of the third N-type transistor MN3 will be VREF + VTH3. Furthermore, since the gate G3 of the third N-type transistor MN3 is electrically coupled to the drain D3, the voltage at the drain D3 is also VREF + VTH3.

[0035] Since the voltage generated by the gate G3 of the third N-type transistor MN3 is the adjustment voltage VA, the adjustment voltage VA will be VREF + VTH3. In one embodiment, the third N-type transistor MN3 is matched with the current-regulating N-type transistor MNA, so that the threshold voltage VTH3 of the third N-type transistor MN3 is the same as the threshold voltage VTHA of the current-regulating N-type transistor MNA, that is, VTH3 = VTHA. Therefore, the adjustment voltage VA can also be expressed as VREF + VTHA. Further, in Figure 1 The voltage VC of the power supply signal CS generated by the source SA of the current-regulated N-type transistor MNA will be VREF + VTHA - VTHA = VREF.

[0036] Since the regulating voltage generating circuit 130, which generates the regulating voltage VA, uses a second operating voltage VDD2 that is higher than the first operating voltage VDD1, the voltage VC of the power supply signal CS is indirectly given sufficient headroom. Furthermore, none of the transistors in the power supply stabilization circuit 120 exceed a voltage rating of 1.8 volts.

[0037] Therefore, the power stabilization circuit 120 of the present invention can stably provide the regulating voltage VA by using an architecture of all N-type transistors, and control the current regulating N-type transistor MNA with high impedance relative to the first operating voltage VDD1 to generate a power signal CS with a stable current IC, thereby making the voltage VC of the power signal CS not affected by the noise fluctuation of the first operating voltage VDD1, and having sufficient margin.

[0038] In one embodiment, Figure 2 The third N-type transistor MN3 and Figure 1 The current-regulated N-type transistor MNA can be a general transistor device. However, when the device has a voltage withstand limit, the third N-type transistor MN3 and the current-regulated N-type transistor MNA can each include a deep N-well to prevent overvoltage problems when the circuit is to be turned off.

[0039] It should be noted that the above-described implementation is merely an example. In other embodiments, those skilled in the art can make modifications without departing from the spirit of the invention. It should be understood that, unless otherwise specified, the order of the steps mentioned in the above embodiments can be adjusted as needed, and they can even be performed simultaneously or partially simultaneously.

[0040] In summary, the voltage-controlled oscillator and its power supply stabilization circuit in this invention can generate a stable, undisturbed power signal with sufficient margin to the voltage-controlled oscillator circuit, so that the voltage-controlled oscillator circuit can stably output an oscillation signal with an oscillation frequency.

[0041] While the embodiments of the present invention have been described above, these embodiments are not intended to limit the present invention. Those skilled in the art can make changes to the technical features of the present invention based on the explicit or implicit content of the present invention. All such changes fall within the scope of patent protection sought by the present invention. In other words, the scope of patent protection of the present invention shall be defined by the claims of the present invention.

[0042] Explanation of reference numerals in the attached figures:

[0043] 100: Voltage-controlled oscillation device

[0044] 110: Voltage-controlled oscillator circuit

[0045] 120: Power supply stabilization circuit

[0046] 130: Regulating voltage generation circuit

[0047] 140: Control voltage receiving circuit

[0048] 150: Oscillator

[0049] 160: Filtering circuit

[0050] CF: Capacitor

[0051] CS: Power signal

[0052] D1, D2, D3, DA: Drain

[0053] G1, G2, G3, GA: Gate

[0054] GND: Ground terminal

[0055] IC: Current

[0056] MN1: First N-type transistor

[0057] MN2: Second N-type transistor

[0058] MN3: Third N-type transistor

[0059] MNA: Current-regulating N-type transistor

[0060] R1: First resistor

[0061] R2: Second resistor

[0062] RF: Resistance

[0063] RVA: Variable Resistance

[0064] S1, S2, S3, SA: Source

[0065] VA: Regulate voltage

[0066] VC: Voltage

[0067] VCTL: Control Voltage

[0068] VDD1: First operating voltage

[0069] VDD2: Second operating voltage

[0070] VREF: Reference Voltage

[0071] VTH1, VTH2, VTH3, VTHA: Threshold voltage

Claims

1. A power supply stabilization circuit with a noise suppression mechanism, configured to drive a voltage-controlled oscillator circuit, the power supply stabilization circuit comprising: A current-regulating N-type transistor, comprising: One drain is configured to receive a first operating voltage; One source is configured to generate a power signal to the voltage-controlled oscillator circuit, so that the voltage-controlled oscillator circuit operates according to the power signal; and A gate, configured to receive a regulated voltage; and An adjustable voltage generating circuit is configured to operate based on a second operating voltage higher than the first operating voltage, and to receive a reference voltage generated by voltage division based on the first operating voltage to generate the adjustable voltage, wherein the adjustable voltage is the sum of the reference voltage and a threshold voltage of the current-regulating N-type transistor, so that the current-regulating N-type transistor operates in a saturation region, thereby making a current variation of the power supply signal less than a current variation preset value.

2. The power supply stabilizing circuit according to claim 1, characterized by The voltage regulation generating circuit further includes: A first resistor and a second resistor; A first N-type transistor, comprising: One drain is configured to receive the first operating voltage; A source electrode is electrically coupled to a ground terminal through the first resistor; and A gate configured to receive the reference voltage; A second N-type transistor, matched with the first N-type transistor, and comprising: One leak pole; One source electrode is electrically coupled to the ground terminal through the first resistor; and A gate, electrically coupled to the drain of the second N-type transistor; and A third N-type transistor, matched with the current-regulating N-type transistor, includes: One drain receives the second operating voltage through the second resistor; A source, electrically coupled to the drain of the second N-type transistor; and A gate is electrically coupled to the drain of the third N-type transistor and electrically coupled to the gate of the current-regulating N-type transistor to output the regulating voltage; The resistance values ​​of the first resistor and the second resistor are such that the first N-type transistor, the second N-type transistor, and the third N-type transistor all operate in a weak inversion region.

3. The power supply stabilization circuit according to claim 2, characterized in that, A first voltage at the source of the first N-type transistor and the second N-type transistor is the difference between the reference voltage and a threshold voltage of the first N-type transistor; a second voltage at the drain of the second N-type transistor is the reference voltage; a third voltage at the gate and drain of the third N-type transistor is the sum of the reference voltage and a threshold voltage of the third N-type transistor; and a fourth voltage at the source of the current-regulating N-type transistor corresponding to the power supply signal is the reference voltage.

4. The power supply stabilization circuit according to claim 2, characterized in that, It also includes a variable resistor circuit configured to receive the first operating voltage and divide it to output the reference voltage to the gate of the first N-type transistor.

5. The power supply stabilization circuit according to claim 2, characterized in that, The magnitude of the reference voltage is 80% to 90% of the magnitude of the first operating voltage.

6. The power supply stabilization circuit according to claim 2, characterized in that, The third N-type transistor and the current-regulating N-type transistor each include a deep N-well.

7. The power supply stabilization circuit according to claim 1, characterized in that, It also includes a filter circuit disposed on a path whereby the regulating voltage generated by the regulating voltage generation circuit is applied to the gate of the current-regulating N-type transistor.

8. The power supply stabilization circuit according to claim 1, characterized in that, The voltage variation of the power signal is less than a preset voltage variation value.

9. The power supply stabilization circuit according to claim 1, characterized in that, The current-regulated N-type transistor has a high impedance relative to the first operating voltage.

10. A voltage-controlled oscillation device, comprising: A voltage-controlled oscillator circuit that operates based on a power supply signal; as well as A power supply stabilization circuit, including: A current-regulating N-type transistor, comprising: One drain is configured to receive a first operating voltage; One source, configured to generate the power signal to the voltage-controlled oscillator circuit; and A gate, configured to receive a regulated voltage; and An adjustable voltage generating circuit is configured to operate based on a second operating voltage higher than the first operating voltage, and to receive a reference voltage generated by voltage division based on the first operating voltage to generate the adjustable voltage, wherein the adjustable voltage is the sum of the reference voltage and a threshold voltage of the current-regulating N-type transistor, so that the current-regulating N-type transistor operates in a saturation region, thereby making a current variation of the power supply signal less than a current variation preset value.

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