A clock signal transmission method, device, equipment and medium

Abstract

The present application discloses a clock signal transmission method, apparatus, device and medium, relating to the field of chip applications. The method includes: setting a crystal oscillator, a clock generator and a first clock buffer on a retimer main board; generating a clock signal by using the crystal oscillator and the clock generator on the retimer main board; transmitting the clock signal to a second clock buffer on a target retimer board through a series line by using the first clock buffer on the retimer main board, so that the second clock buffer transmits the clock signal to a hard disk backplane and a retimer chip on the target retimer board. By using the newly added crystal oscillator, clock generator and first clock buffer, the present invention realizes the application of local non-homogeneous clocks, can solve the problem that the transmission quality of the homogeneous clock signal fails to meet the requirements in the traditional clock signal transmission process, has the advantages of short wiring and high clock signal quality, eliminates problems such as clock monotonicity, overshoot ringing, and jitter, and ensures the effectiveness of the Retimer card clock signal.

Description

Technical Field

[0001] The present invention relates to the field of chip applications, and particularly to a clock signal transmission method, device, equipment and medium. Background Art

[0002] With the continuous expansion of scale, the traditional way of simply stacking servers and storage devices in a data center, connecting them with switches, and supplementing with virtualization software for resource scheduling and management can no longer meet the requirements. It is necessary to carry out technological innovation at all levels and transform the data center architecture, that is, the converged architecture.

[0003] The third-generation converged architecture, an IO Fabric system developed based on PCIe5.0 Switch, can achieve dynamic allocation of PCIe (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus) channels within the resource pool system for different application requirements, with high bandwidth, low latency, and maximizing the utilization rate of PCIe resources. Microchip (Microchip Technology Incorporated, USA) has officially released the Switchtec PCIe Switch chip that supports the PCIe 5.0 rate. When used in conjunction with its own PCIe 5.0 Retimer chip, it can obtain a latency 80% lower than the PCIe 5.0 specification, greatly improving the system performance.

[0004] In a low-speed system, the interconnect delay and ringing phenomenon of the clock can be ignored because the signal has enough time to reach a stable state. For a PCIe Fabric high-performance network, due to its requirements of multi-host sharing and dynamic allocation, the requirements for clock signals are very high. In a converged architecture system, the CPU (Central Processing Unit) and the hard disk belong to different chassis, and the Retimer board is directly connected to the hard disk backplane. Therefore, it is necessary to fully consider whether there are possible clock delays, abnormal jitters, etc. in the clock signals transmitted by the cable from other chassis on the Retimer board. Once the clock signal is mismatched and distorted, the Retimer chip cannot correctly receive and transmit data, resulting in the hard disk of the system being unable to work properly.

[0005] As can be seen from the above, in the process of applying the converged architecture, how to avoid the situation of clock delay and jitter that may occur due to too long clock line routing is a problem to be solved in this field. Summary of the Invention

[0006] In view of this, the purpose of the present invention is to provide a clock signal transmission method, device, equipment and medium, which can solve the risk of abnormal delay and jitter of the same-source clock of the Retimer card under the fusion architecture and ensure the normal operation of the PCIe IO Fabric system. The specific solution is as follows:

[0007] In a first aspect, the present application discloses a clock signal transmission method, including:

[0008] Setting a crystal oscillator, a clock generator and a first clock buffer on the retimer motherboard;

[0009] Generating a clock signal by using the crystal oscillator and the clock generator on the retimer motherboard;

[0010] Using the first clock buffer on the retimer motherboard to transmit the clock signal to the second clock buffer on the target retimer board through a series circuit, so that the second clock buffer transmits the clock signal to the hard disk backplane and the retimer chip on the target retimer board; the series circuit is a circuit connected by connecting the first clock buffer on the retimer motherboard and the second clock buffer on the target retimer board in series through a series resistor.

[0011] Optionally, the setting of the crystal oscillator, the clock generator and the first clock buffer on the retimer motherboard includes:

[0012] Setting a 25MHz crystal oscillator, a clock generator and a 9QXL2001 Gen 5 clock buffer on the motherboard.

[0013] Optionally, after setting the crystal oscillator, the clock generator and the first clock buffer on the retimer motherboard, it further includes:

[0014] Connecting the crystal oscillator, the clock generator and the first clock buffer by using a preset connection relationship;

[0015] Connecting the first clock buffer on the retimer motherboard and the second clock buffer on the target retimer card in series through a series resistor.

[0016] Optionally, the connecting the crystal oscillator, the clock generator and the first clock buffer by using a preset connection relationship includes:

[0017] Connecting the XTAL_IN pin and the XTAL_OUT pin of the clock generator to the crystal oscillator, and connecting the output pin of the clock generator to the input pin of the clock buffer.

[0018] Optionally, connecting the first clock buffer on the retimer main board to the second clock buffer on the retimer card in the way of connecting through a series resistor includes:

[0019] Connecting the output pin of the first clock buffer on the retimer main board to the input pin of the second clock buffer on the target retimer card in the way of connecting through a series resistor.

[0020] Optionally, after using the first clock buffer on the retimer main board to transmit the clock signal to the second clock buffer on the target retimer board through a series circuit, so that the second clock buffer transmits the clock signal to the hard disk backplane and the retimer chip on the target retimer board, it further includes:

[0021] When a quality monitoring instruction is obtained, use a preset clock signal quality monitoring method to monitor the clock signal transmission quality, then generate a quality monitoring result in a preset format, and wait for a line switching instruction;

[0022] When a line switching instruction is obtained, switch the clock transmission line through the series resistor reserved in the series circuit.

[0023] Optionally, after switching the clock transmission line through the series resistor reserved in the series circuit, it further includes:

[0024] Use the second clock buffer on the target retimer board to receive the clock signal sent by the upper chassis, so that the second clock buffer transmits the clock signal to the hard disk backplane and the retimer chip on the target retimer board.

[0025] In a second aspect, the present application discloses a clock signal transmission device, including:

[0026] A device setting module, configured to set a crystal oscillator, a clock generator, and a first clock buffer on the retimer main board;

[0027] A clock signal generation module, configured to generate a clock signal by using the crystal oscillator and the clock generator on the retimer main board;

[0028] A clock signal transmission module is used to transmit the clock signal to a second clock buffer on a target retimer board through a series line by using a first clock buffer on the retimer main board, so that the second clock buffer transmits the clock signal to a hard disk backplane and a retimer chip on the target retimer board; the series line is a line connecting a first clock buffer on the retimer main board and a second clock buffer on the target retimer board in a series resistance connection manner.

[0029] In a third aspect, the present application discloses an electronic device, including:

[0030] A memory for storing a computer program;

[0031] A processor for executing the computer program to implement the foregoing clock signal transmission method.

[0032] In a fourth aspect, the present application discloses a computer storage medium for storing a computer program; wherein, when the computer program is executed by a processor, the steps of the foregoing disclosed clock signal transmission method are implemented.

[0033] In the present application, a crystal oscillator, a clock generator, and a first clock buffer are arranged on the retimer main board; a clock signal is generated by using the crystal oscillator and the clock generator on the retimer main board; the clock signal is transmitted to a second clock buffer on a target retimer board through a series line by using the first clock buffer on the retimer main board, so that the second clock buffer transmits the clock signal to a hard disk backplane and a retimer chip on the target retimer board; the series line is a line connecting a first clock buffer on the retimer main board and a second clock buffer on the target retimer board in a series resistance connection manner. In this way, the problem that the transmission quality of the same-source clock signal fails to meet the requirements in the traditional clock signal transmission process can be solved, and the application of non-homogeneous clocks can be realized by using the newly added crystal oscillator, clock generator, and first clock buffer. Moreover, in the present application, the local clock source and the clock buffer have the advantages of short wiring and high clock signal quality, eliminating problems such as clock monotonicity, overshoot ringing, and jitter, and at the same time ensuring a point-to-point topology and the effectiveness of the Retimer card clock signal. Description of the Drawings

[0034] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the accompanying drawings required in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only the embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can also be obtained based on the provided drawings.

[0035] Figure 1 It is a flowchart of a clock signal transmission method provided by this application;

[0036] Figure 2 It is a structural diagram of clock signal transmission of an existing Retimer card;

[0037] Figure 3 It is a structural diagram of a clock signal transmission provided by this application;

[0038] Figure 4 It is a specific flowchart of a clock signal transmission method provided by this application;

[0039] Figure 5 It is a schematic structural diagram of a clock signal transmission device provided by this application;

[0040] Figure 6 It is a structural diagram of an electronic device provided by this application. Specific Embodiments

[0041] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0042] In the prior art, on the Retimer board, it is necessary to fully consider whether there are possible clock delays, abnormal jitters, etc. in the clock signals transmitted from other chassis by cables. Once the clock signals are mismatched and distorted, the Retimer chip cannot correctly transmit and receive data, resulting in the system hard disk being unable to work properly. The present invention can solve the problem of poor clock signal quality of the Retimer board due to too long clock line routing in the fusion architecture.

[0043] An embodiment of the present invention discloses a clock signal transmission method. Refer to Figure 1 As described, the method includes:

[0044] Step S11: Set a crystal oscillator, a clock generator, and a first clock buffer on the retimer main board.

[0045] As shown Figure 2 in the existing Retimer card clock signal transmission structure diagram taking three Retimer cards as an example, when the Retimer card clock signal is transmitted from the upper chassis to the local retimer board through the CDPF connector, it is used after passing through the clock buffer set in the retimer board, enhancing and replicating the same-source clock signal sent from the bus driver end of other chassis. Subsequently, the clock buffer sends the clock signal to the retimer chip set in the retimer board and the hard disk backplane directly connected to the retimer board for use by the Retimer chip and the hard disk backplane. Specifically, when the clock signal is transmitted to the hard disk backplane, it will be transmitted to the connector preset in the hard disk backplane. The same-source transmission method is adopted during the entire clock signal transmission process. It can be understood that the clock buffer in the retimer board can use the DB800ZL clock buffer, and the connector preset in the hard disk backplane can be the Gen 5 MCIO connector.

[0046] As shown Figure 3 in the clock signal transmission structure diagram taking three Retimer cards as an example proposed in this application, that is, by adding a crystal oscillator, a clock generator, and a clock buffer on the main board of the Retimer card, a local non-same-source clock can be provided for multiple Retimer cards.

[0047] In the embodiment of this application, the setting of the crystal oscillator, the clock generator, and the first clock buffer on the retimer main board may include: setting a 25 MHz crystal oscillator, a clock generator, and a 9QXL2001 Gen 5 clock buffer on the main board. That is, in the embodiment of this application, the crystal oscillator is preferably a 25 MHz crystal oscillator, and the clock buffer is preferably a 9QXL2001 Gen 5 clock buffer.

[0048] In the embodiment of this application, after setting the crystal oscillator, the clock generator, and the first clock buffer on the retimer main board, it may further include: connecting the crystal oscillator, the clock generator, and the first clock buffer using a preset connection relationship; connecting the first clock buffer on the retimer main board to the second clock buffer on the target retimer card in a series resistance connection manner. It can be understood that in the embodiment of this application, the clock buffer set on the retimer main board is called the first clock buffer, and the clock buffer set on the retimer board is called the second clock buffer.

[0049] In the embodiment of the present application, the connection of the crystal oscillator, the clock generator, and the first clock buffer using the preset connection relationship may include: connecting the XTAL_IN pin and the XTAL_OUT pin of the clock generator to the crystal oscillator, and connecting the output pin of the clock generator to the input pin of the clock buffer.

[0050] It can be understood that after the crystal oscillator, the clock generator, and the first clock buffer are arranged on the retimer main board, the crystal oscillator, the clock generator, and the first clock buffer will also be connected. In a specific embodiment, when the crystal oscillator is a 25 MHz crystal oscillator and the first clock buffer is a 9QXL2001 Gen 5 clock buffer, the XTAL_OUT pin and the XTAL_IN pin of the clock generator can be connected to the 25 MHz crystal oscillator. The output pin DIF0_P / N of the clock generator is connected to the input pin DIF_IN_P / N of the 9QXL2001 Gen 5 clock buffer.

[0051] In the embodiment of the present application, the connection of the first clock buffer on the retimer main board to the second clock buffer on the retimer card by means of series resistance connection may include: connecting the output pin of the first clock buffer on the retimer main board to the input pin of the second clock buffer on the target retimer card by means of series resistance connection. That is, in the embodiment of the present application, the first clock buffer is also used to connect the second clock buffer on the target retimer card, so as to provide a clock signal to the target retimer card by using the crystal oscillator, the clock generator, and the first clock buffer arranged on the retimer main board.

[0052] In a specific embodiment, when the crystal oscillator is a 25 MHz crystal oscillator, the first clock buffer is a 9QXL2001 Gen 5 clock buffer, and the second clock buffer is a DB800ZL clock buffer, if multiple retimer boards are connected to the retimer main board, each output pin of the 9QXL2001 clock buffer will be respectively connected to the input pin DIF_IN_P / N of the DB800ZL clock buffer on the Retimer board through a CN series resistance. As Figure 3 shown, when the retimer main board is connected to three Retimer boards at the same time, the output pins DIF0_P / N, DIF1_P / N, and DIF2_P / N of the 9QXL2001 clock buffer can be respectively connected to the input pin DIF_IN_P / N of the DB800ZL clock buffer on the three Retimer cards through a CN series resistance.

[0053] Step S12: Generate a clock signal using the crystal oscillator and the clock generator on the retimer main board.

[0054] Specifically, in the embodiment of the present application, the clock signal is generated by the clock generator.

[0055] Step S13: Use the first clock buffer on the retimer main board to transmit the clock signal to the second clock buffer on the target retimer board through a series line, so that the second clock buffer transmits the clock signal to the hard disk backplane and the retimer chip on the target retimer board; the series line is a line connecting the first clock buffer on the retimer main board and the second clock buffer on the target retimer board in a series resistance connection manner.

[0056] It should be noted that the connection line between the first clock buffer and the second clock buffer in the embodiment of the present application is a series line, and a series resistance is reserved in the series line.

[0057] In the embodiment of the present application, with reference to Figure 3 As shown, after the clock generator on the retimer main board generates a clock signal, it will send the clock signal to each second clock buffer on each retimer board through the clock buffer on the retimer main board, and each second clock buffer will send the clock signal to the retimer chip on the corresponding retimer board and the hard disk backplane directly connected to the retimer board for the retimer chip and the hard disk backplane to use the clock signal.

[0058] In the embodiment of the present application, a crystal oscillator, a clock generator, and a first clock buffer are arranged on the retimer main board. Then, a clock signal is generated by using the crystal oscillator and the clock generator on the retimer main board. Next, the first clock buffer on the retimer main board is used to transmit the clock signal to the second clock buffer on the target retimer board card through a series line, so that the second clock buffer can transmit the clock signal to the hard disk backplane and the retimer chip on the target retimer board card. Among them, the series line is a line connecting the first clock buffer on the retimer main board and the second clock buffer on the target retimer board card in a series resistance connection manner. In this way, the problem that the transmission quality of the same-source clock signal cannot meet the requirements in the traditional clock signal transmission process can be solved, and the application of non-homogeneous clocks can be realized by using the newly added crystal oscillator, clock generator, and first clock buffer. Moreover, in the present application, the local clock source and the clock buffer have the advantages of short wiring and high clock signal quality, eliminating problems such as clock monotonicity, overshoot ringing, and jitter. At the same time, the point-to-point topology is also ensured, ensuring the effectiveness of the clock signal of the Retimer card.

[0059] Figure 4 It is a flowchart of a specific clock signal transmission method provided by the embodiment of the present application. Refer to Figure 4 As shown, the method includes:

[0060] Step S21: Set a crystal oscillator, a clock generator, and a first clock buffer on the retimer main board.

[0061] Among them, for a more specific processing process of step S21, reference can be made to the corresponding content disclosed in the foregoing embodiments, and details will not be elaborated here.

[0062] Step S22: Generate a clock signal by using the crystal oscillator and the clock generator on the retimer main board.

[0063] Among them, for a more specific processing process of step S22, reference can be made to the corresponding content disclosed in the foregoing embodiments, and details will not be elaborated here.

[0064] Step S23: Use the first clock buffer on the retimer main board to transmit the clock signal to the second clock buffer on the target retimer board card through a series line, so that the second clock buffer can transmit the clock signal to the hard disk backplane and the retimer chip on the target retimer board card; the series line is a line connecting the first clock buffer on the retimer main board and the second clock buffer on the target retimer board card in a series resistance connection manner.

[0065] Among them, for a more specific processing procedure regarding step S23, reference can be made to the corresponding content disclosed in the foregoing embodiments, and details are not described herein again.

[0066] Step S24: When a quality monitoring instruction is obtained, use a preset clock signal quality monitoring method to monitor the clock signal transmission quality, then generate a quality monitoring result in a preset format, and wait for a line switching instruction; when a line switching instruction is obtained, switch the clock transmission line through the series resistor reserved in the series line.

[0067] In the embodiment of the present application, after switching the clock transmission line through the series resistor reserved in the series line, it may include: using the second clock buffer on the target retimer board to receive the clock signal sent by the upper chassis, so that the second clock buffer transmits the clock signal to the hard disk backplane and the retimer chip on the target retimer board. That is, in the embodiment of the present application, a crystal oscillator, a clock generator, and a clock buffer are added to the Retimer card main board, so that the Retimer card can use both the same-source long-distance transmission clock and the local clock, and the two clock signals can be switched to eliminate the risk of abnormal operation caused by clock delay and jitter anomalies. In a specific implementation, the user can switch the clock transmission line provided by the current local non-same-source clock to the clock transmission line that sends the clock signal through the upper chassis through a line switching instruction to switch the local non-same-source clock to the same-source clock, or can also receive a line switching instruction when using the clock transmission line that sends the clock signal through the upper chassis and switch back to the local non-same-source clock.

[0068] It should be noted that in the embodiment of the present application, the connection line between the first clock buffer and the second clock buffer is a series line, and a series resistor is reserved in the series line. In the embodiment of the present application, the user can obtain the current clock signal transmission quality through a quality monitoring instruction, and when the user wants to switch the clock transmission line, the purpose of switching between the same-source and non-same-source clocks can be achieved by reserving the series resistor CN.

[0069] In the embodiment of the present application, a crystal oscillator, a clock generator, and a first clock buffer are provided on the retimer main board; a clock signal is generated by using the crystal oscillator and the clock generator on the retimer main board; the first clock buffer on the retimer main board is used to transmit the clock signal to the second clock buffer on the target retimer board card through a series line, so that the second clock buffer transmits the clock signal to the hard disk backplane and the retimer chip on the target retimer board card; the series line is a line connecting the first clock buffer on the retimer main board and the second clock buffer on the target retimer board card in a series resistance connection manner; when a quality monitoring instruction is obtained, the transmission quality of the clock signal is monitored by using a preset clock signal quality monitoring method, and then a quality monitoring result is generated in a preset format, and a line switching instruction is waited for; when a line switching instruction is obtained, the clock transmission line is switched through the series resistance reserved in the series line. In this way, the present invention can solve the problem that the transmission quality of the same-source clock signal fails to meet the requirements in the traditional clock signal transmission process, and realizes the application of non-same-source clocks by using the newly added crystal oscillator, clock generator, and first clock buffer. In addition, the local clock source and the clock buffer in the present application have the advantages of short wiring and high clock signal quality, eliminating problems such as clock monotonicity, overshoot ringing, and jitter, and at the same time ensuring a point-to-point topology and the effectiveness of the Retimer card clock signal. Moreover, the user can achieve the purpose of switching between the same-source and non-same-source clocks through the line switching instruction to meet the application requirements of the clock signal under certain conditions.

[0070] See Figure 5 As shown, the embodiment of the present application discloses a clock signal transmission device, which specifically may include:

[0071] A device setting module 11, configured to set a crystal oscillator, a clock generator, and a first clock buffer on the retimer main board;

[0072] A clock signal generation module 12, configured to generate a clock signal by using the crystal oscillator and the clock generator on the retimer main board;

[0073] A clock signal transmission module 13, configured to transmit the clock signal to the second clock buffer on the target retimer board card through a series line by using the first clock buffer on the retimer main board, so that the second clock buffer transmits the clock signal to the hard disk backplane and the retimer chip on the target retimer board card; the series line is a line connecting the first clock buffer on the retimer main board and the second clock buffer on the target retimer board card in a series resistance connection manner.

[0074] In this application, a crystal oscillator, a clock generator, and a first clock buffer are provided on the retimer main board. Then, the crystal oscillator and the clock generator on the retimer main board are used to generate a clock signal. Next, the first clock buffer on the retimer main board is used to transmit the clock signal to the second clock buffer on the target retimer board card through a series line, so that the second clock buffer can transmit the clock signal to the hard disk backplane and the retimer chip on the target retimer board card. Among them, the series line is a line connecting the first clock buffer on the retimer main board and the second clock buffer on the target retimer board card in a series resistance connection manner. In this way, the problem that the transmission quality of the same-source clock signal cannot meet the requirements in the traditional clock signal transmission process can be solved, and the application of non-homogeneous clocks can be realized by using the newly added crystal oscillator, clock generator, and first clock buffer. Moreover, in this application, the local clock source and the clock buffer have the advantages of short wiring and high clock signal quality, eliminating problems such as clock monotonicity, overshoot ringing, and jitter, and at the same time ensuring a point-to-point topology and the effectiveness of the Retimer card clock signal.

[0075] In some specific embodiments, the device setting module 11 may specifically include:

[0076] A device setting unit for setting a 25MHz crystal oscillator, a clock generator, and a 9QXL2001 Gen 5 clock buffer on the main board.

[0077] In some specific embodiments, the clock signal transmission device may specifically further include:

[0078] A first connection module for connecting the crystal oscillator, the clock generator, and the first clock buffer by using a preset connection relationship;

[0079] A second connection module for connecting the first clock buffer on the retimer main board and the second clock buffer on the target retimer card in a series resistance connection manner.

[0080] In some specific embodiments, the first connection module may specifically include:

[0081] A first connection unit for connecting the XTAL_IN pin and the XTAL_OUT pin of the clock generator to the crystal oscillator, and connecting the output pin of the clock generator to the input pin of the clock buffer.

[0082] In some specific embodiments, the second connection module may specifically include:

[0083] A second connection unit for connecting an output pin of a first clock buffer on the retimer main board to an input pin of a second clock buffer on a target retimer card in a series resistor connection manner.

[0084] In some specific embodiments, the clock signal transmission device may further specifically include:

[0085] A quality monitoring module for, when a quality monitoring instruction is obtained, monitoring the clock signal transmission quality using a preset clock signal quality monitoring method, then generating a quality monitoring result in a preset format, and waiting for a line switching instruction;

[0086] A line switching module for, when a line switching instruction is obtained, switching the clock transmission line through a series resistor reserved in the series line.

[0087] In some specific embodiments, the clock signal transmission device may further specifically include:

[0088] A second clock signal transmission module for receiving a clock signal sent by an upper chassis using a second clock buffer on the target retimer board for clock signal transmission, so that the second clock buffer transmits the clock signal to a hard disk backplane and a retimer chip on the target retimer board.

[0089] Furthermore, an embodiment of the present application also discloses an electronic device. Figure 6 It is a structural diagram of an electronic device 20 shown according to an exemplary embodiment, and the content in the figure cannot be considered as any limitation to the scope of use of the present application.

[0090] Figure 6 It is a schematic structural diagram of an electronic device 20 provided by an embodiment of the present application. The electronic device 20 may specifically include: at least one processor 21, at least one memory 22, a power supply 23, a display screen 24, an input / output interface 25, a communication interface 26, and a communication bus 27. Among them, the memory 22 is used to store a computer program, and the computer program is loaded and executed by the processor 21 to implement the following steps:

[0091] Set a crystal oscillator, a clock generator, and a first clock buffer on the retimer main board;

[0092] Generate a clock signal using the crystal oscillator and the clock generator on the retimer main board;

[0093] Use the first clock buffer on the retimer main board to transmit the clock signal to the second clock buffer on the target retimer board card through a series connection line, so that the second clock buffer transmits the clock signal to the hard disk backplane and the retimer chip on the target retimer board card; the series connection line is a line connecting the first clock buffer on the retimer main board and the second clock buffer on the target retimer board card in a series resistance connection manner.

[0094] In some specific embodiments, the processor can specifically implement the following steps by executing the computer program stored in the memory:

[0095] Set a 25 MHz crystal oscillator, a clock generator, and a 9QXL2001 Gen 5 clock buffer on the main board.

[0096] In some specific embodiments, the processor can further include the following steps by executing the computer program stored in the memory:

[0097] Connect the crystal oscillator, the clock generator, and the first clock buffer using a preset connection relationship;

[0098] Connect the first clock buffer on the retimer main board and the second clock buffer on the target retimer card in a series resistance connection manner.

[0099] In some specific embodiments, the processor can specifically implement the following steps by executing the computer program stored in the memory:

[0100] Connect the XTAL_IN pin and the XTAL_OUT pin of the clock generator to the crystal oscillator, and connect the output pin of the clock generator to the input pin of the clock buffer.

[0101] In some specific embodiments, the processor can specifically implement the following steps by executing the computer program stored in the memory:

[0102] Connect the output pin of the first clock buffer on the retimer main board and the input pin of the second clock buffer on the target retimer card in a series resistance connection manner.

[0103] In some specific embodiments, the processor can further include the following steps by executing the computer program stored in the memory:

[0104] When a quality monitoring instruction is obtained, the clock signal transmission quality is monitored by using a preset clock signal quality monitoring method, and then the quality monitoring result is generated in a preset format, and the line switching instruction is waited for;

[0105] When a line switching instruction is obtained, the clock transmission line is switched through the series resistance reserved in the series line.

[0106] In some specific embodiments, when the processor executes the computer program stored in the memory, the following steps may further be included:

[0107] The second clock buffer on the target retimer board is used to receive the clock signal sent by the upper chassis, so that the second clock buffer transmits the clock signal to the hard disk backplane and the retimer chip on the target retimer board.

[0108] In addition, the electronic device 20 in the embodiment of the present application may specifically be an electronic computer. In the embodiment of the present application, the power supply 23 is used to provide working voltage for each hardware device on the electronic device 20; the communication interface 26 can create a data transmission channel between the electronic device 20 and external devices, and the communication protocol it follows is any communication protocol applicable to the technical solution of the present application, and no specific limitation is made here; the input / output interface 25 is used to obtain external input data or output data to the outside, and its specific interface type can be selected according to specific application needs, and no specific limitation is made here.

[0109] In addition, the memory 22 as a carrier for resource storage may be a read-only memory, a random access memory, a disk, or an optical disc, etc., and the resources stored thereon may include an operating system 221, a computer program 222, and virtual machine data 223, etc. The virtual machine data 223 may include various kinds of data. The storage method may be short-term storage or permanent storage.

[0110] Among them, the operating system 221 is used to manage and control each hardware device and the computer program 222 on the electronic device 20, and it may be Windows Server, Netware, Unix, Linux, etc. In addition to the computer program that can be used to complete the clock signal transmission method executed by the electronic device 20 disclosed in any of the foregoing embodiments, the computer program 222 may further include a computer program that can be used to complete other specific tasks.

[0111] Furthermore, the present application also discloses a computer-readable storage medium, which includes a random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disks, magnetic disks, or optical disks, or any other form of storage medium known in the art. Among them, when the computer program is executed by the processor, it implements the clock signal transmission method disclosed above. For the specific steps of this method, reference can be made to the corresponding content disclosed in the foregoing embodiments, and details will not be repeated here.

[0112] The various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same or similar parts among the embodiments, reference can be made to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple. For the relevant parts, reference can be made to the description in the method part. Professionals can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed in this article can be implemented by electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been generally described according to their functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Professionals can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present application.

[0113] The steps of the method or algorithm described in combination with the embodiments disclosed in this article can be directly implemented by hardware, a software module executed by a processor, or a combination of both. The software module can be placed in a random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disks, removable disks, CD-ROMs, or any other form of storage medium known in the art.

[0114] Finally, it should also be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the said element.

[0115] The above has introduced in detail the clock signal transmission method, apparatus, device, and storage medium provided by the present invention. Specific examples are used in this text to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. A clock signal transmission method, characterized in that, Including: A crystal oscillator, a clock generator, and a first clock buffer are arranged on the retimer main board; The crystal oscillator and the clock generator on the retimer main board are used to generate a clock signal; The first clock buffer on the retimer main board is used to transmit the clock signal to the second clock buffer on the target retimer board card through a series connection line, so that the second clock buffer transmits the clock signal to the hard disk backplane and the retimer chip on the target retimer board card; the series connection line is a line connecting the first clock buffer on the retimer main board and the second clock buffer on the target retimer board card in a series resistance connection manner.

2. The clock signal transmission method according to claim 1, characterized in that The step of arranging a crystal oscillator, a clock generator, and a first clock buffer on the retimer main board includes: A 25MHz crystal oscillator, a clock generator, and a 9QXL2001 Gen 5 clock buffer are arranged on the main board.

3. The clock signal transmission method according to claim 1, wherein After arranging the crystal oscillator, the clock generator, and the first clock buffer on the retimer main board, it further includes: Connecting the crystal oscillator, the clock generator, and the first clock buffer by using a preset connection relationship; Connecting the first clock buffer on the retimer main board and the second clock buffer on the target retimer card in a series resistance connection manner.

4. The clock signal transmission method according to claim 3, wherein The step of connecting the crystal oscillator, the clock generator, and the first clock buffer by using a preset connection relationship includes:

5. The clock signal transmission method according to claim 3, wherein Connecting the XTAL_IN pin and the XTAL_OUT pin of the clock generator to the crystal oscillator, and connecting the output pin of the clock generator to the input pin of the clock buffer. The step of connecting the first clock buffer on the retimer main board and the second clock buffer on the retimer card in a series resistance connection manner includes:

6. The clock signal transmission method according to any one of claims 1 to 5, characterized in that Connecting the output pin of the first clock buffer on the retimer main board and the input pin of the second clock buffer on the target retimer card in a series resistance connection manner. After the first clock buffer on the retimer main board is used to transmit the clock signal to the second clock buffer on the target retimer board card through the series connection line, so that the second clock buffer transmits the clock signal to the hard disk backplane and the retimer chip on the target retimer board card, it further includes: When a quality monitoring instruction is obtained, a preset clock signal quality monitoring method is used to monitor the clock signal transmission quality, and then a quality monitoring result is generated in a preset format, and a line switching instruction is awaited; 7. The clock signal transmission method according to claim 6, wherein When a line switching instruction is obtained, the clock transmission line is switched through the series resistance reserved in the series connection line. After switching the clock transmission line through the series resistance reserved in the series connection line, it further includes: The second clock buffer on the target retimer board card is used to receive the clock signal sent by the upper chassis, so that the second clock buffer transmits the clock signal to the hard disk backplane and the retimer chip on the target retimer board card.

8. A clock signal transmission device, characterized in that, Comprising: A device setting module, configured to set a crystal oscillator, a clock generator, and a first clock buffer on a retimer main board; A clock signal generation module, configured to generate a clock signal by using the crystal oscillator and the clock generator on the retimer main board; A clock signal transmission module, configured to transmit the clock signal to a second clock buffer on a target retimer board through a series line by using the first clock buffer on the retimer main board, so that the second clock buffer transmits the clock signal to a hard disk backplane and a retimer chip on the target retimer board; the series line is a line connecting the first clock buffer on the retimer main board and the second clock buffer on the target retimer board in a series resistance connection manner.

9. An electronic device, characterized in that, Comprising a processor and a memory; wherein, when the processor executes a computer program stored in the memory, the clock signal transmission method according to any one of claims 1 to 7 is implemented.

10. A computer-readable storage medium, characterized in that, For storing a computer program; wherein, when the computer program is executed by a processor, the clock signal transmission method according to any one of claims 1 to 7 is implemented.

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