A load balancing method, computing device, and storage medium

Abstract

The application relates to the field of operating systems, in particular to a load balancing method, a computing device and a storage medium, and comprises the following steps: determining a scheduling domain in the computing device which needs to be subjected to load balancing, and determining a plurality of scheduling groups according to the scheduling domain, each scheduling group comprising one or more processors; when the load of a processor is changed from a first load to a second load, determining the load of the scheduling group to which the processor belongs at a first time according to the second load; determining a first scheduling group load list of the scheduling domain according to the load of the scheduling group to which the processor belongs at the first time, the first scheduling group load list comprising the loads of the plurality of scheduling groups; and performing load balancing on the processors in the scheduling domain according to the first scheduling group load list. According to the application, the load is statistically calculated again when the load of the processor is changed, and then the load balancing is performed according to the load, so that the centralized and unified load of all scheduling group load information is decomposed, and the efficiency of the load balancing is improved.

Description

Technical Field

[0001] This invention relates to the field of operating systems, and in particular to a load balancing method, computing device, and storage medium. Background Technology

[0002] With the development of computer technology, the architecture of the processor chip (SoC) in a computer has become more demanding, including an increasing number of processing cores. When these processor cores process tasks, some cores have more tasks than others. Therefore, some cores have a heavier load than others, necessitating load balancing for the processor.

[0003] In existing technologies, load balancing requires statistical analysis of the load on different parts of the processor to determine which parts have a high load and which have a low load; load balancing is then performed based on the statistical results. However, this load statistical analysis is not only time-consuming each time, but also occurs frequently, consuming significant computer resources.

[0004] Therefore, a new load balancing method is needed. Summary of the Invention

[0005] Therefore, the present invention provides a load balancing method in an attempt to solve or at least alleviate the problems mentioned above.

[0006] According to one aspect of the present invention, a load balancing method is provided, suitable for execution in a computing device. The method includes: determining a scheduling domain in the computing device that requires load balancing, and determining multiple scheduling groups according to the scheduling domain, each scheduling group including one or more processors; when the load of a processor changes from a first load to a second load, determining the load of the scheduling group to which the processor belongs at a first moment according to the second load; determining a first scheduling group load list of the scheduling domain according to the load of the scheduling group to which the processor belongs at the first moment, the first scheduling group load list including the loads of multiple scheduling groups; and performing load balancing on the processors in the scheduling domain according to the first scheduling group load list.

[0007] Optionally, in the method according to the present invention, the processor load includes processor states, which include idle states and busy states. Determining the load of the scheduling group to which the processor belongs at a first moment based on the second load includes: when the processor state of the first load is busy and the processor state of the second load is idle, modifying the status identifier of the processor in the scheduling group to the second identifier; and determining the load of the scheduling group to which the processor belongs at a first moment based on the status identifier of the processors included in the scheduling group.

[0008] Optionally, the method according to the present invention further includes: when the processor state of the first load is idle and the processor state of the second load is busy, modifying the status identifier of the processor in the scheduling group to the first identifier; and determining the load of the scheduling group to which the processor belongs at the first moment based on the status identifier of the processors included in the scheduling group.

[0009] Optionally, in the method according to the invention, determining the load of the scheduling group based on the status identifiers of the processors included in the scheduling group includes: determining the number of processors in the scheduling group that are in an idle state based on the status identifiers of the processors included in the scheduling group; and determining the load of the scheduling group based on the number of processors in the scheduling group that are in an idle state.

[0010] Optionally, the method according to the present invention further includes: pre-obtaining the load of each scheduling group in the scheduling domain at a second time; sorting the scheduling groups according to the load of each scheduling group to obtain a sorted scheduling group sequence; and constructing a second scheduling group list according to the scheduling group sequence, the second scheduling group list including multiple scheduling groups and their corresponding loads.

[0011] Optionally, in the method according to the present invention, determining the first scheduling group load list of the scheduling domain based on the load of the scheduling group to which the processor belongs at a first moment includes: modifying the load of the scheduling group in the second scheduling group list at a second moment to the load of the scheduling group at the first moment, thereby obtaining the first scheduling group load list of the scheduling domain.

[0012] Optionally, in the method according to the present invention, load balancing of processors in the scheduling domain according to the first scheduling group load list includes: determining the scheduling group with the largest load in the scheduling domain according to the first scheduling group load list; and load balancing of processors in the scheduling group with the largest load according to a preset load balancing strategy.

[0013] Optionally, in the method according to the invention, the processor load includes a processor load value, and determining the load of the scheduling group to which the processor belongs based on the second load further includes: modifying the processor load value of the processor in the scheduling group at a second time to the processor load value of the processor at a first time; and determining the load of the scheduling group based on the processor load value of the processor at the first time.

[0014] According to another aspect of the present invention, a computing device is provided, comprising: one or more processors; a memory; and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, and the one or more programs include instructions for performing the load balancing method according to the present invention.

[0015] According to another aspect of the invention, a computer-readable storage medium is provided for storing one or more programs, the one or more programs including instructions that, when executed by a computing device, cause the computing device to perform the load balancing method according to the invention.

[0016] This invention discloses a load balancing method suitable for execution in computing devices. The method includes: determining a scheduling domain in the computing device that requires load balancing, and determining multiple scheduling groups based on the scheduling domain, each scheduling group including one or more processors; when the load of a processor changes from a first load to a second load, determining the load of the scheduling group to which the processor belongs at a first moment based on the second load; determining a first scheduling group load list for the scheduling domain based on the load of the scheduling group to which the processor belongs at the first moment, the first scheduling group load list including the loads of multiple scheduling groups; and performing load balancing on the processors in the scheduling domain based on the first scheduling group load list. This invention reduces the frequency and number of load statistics when the processor load changes, improves the efficiency of load balancing, and saves computer resources. Attached Figure Description

[0017] To achieve the foregoing and related objectives, certain illustrative aspects are described herein in conjunction with the following description and accompanying drawings. These aspects indicate various ways in which the principles disclosed herein may be practiced, and all aspects and their equivalents are intended to fall within the scope of the claimed subject matter. The foregoing and other objectives, features, and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Throughout this disclosure, the same reference numerals generally refer to the same parts or elements.

[0018] Figure 1 A schematic diagram of a load balancing method 100 according to an exemplary embodiment of the present invention is shown;

[0019] Figure 2 A structural block diagram of a computing device 200 according to an exemplary embodiment of the present invention is shown;

[0020] Figure 3 A schematic diagram of a scheduling domain and scheduling group according to an exemplary embodiment of the present invention is shown. Detailed Implementation

[0021] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. The same reference numerals generally refer to the same parts or elements.

[0022] One load balancing method in this invention is suitable for execution in computing devices. Figure 2 A structural block diagram of a computing device according to an exemplary embodiment of the present invention is shown.

[0023] In a basic configuration, computing device 200 includes at least one processing unit 220 and system memory 210. According to one aspect, depending on the configuration and type of the computing device, system memory 210 includes, but is not limited to, volatile memory (e.g., random access memory), non-volatile memory (e.g., read-only memory), flash memory, or any combination of such memory. According to one aspect, system memory 210 includes an operating system 211.

[0024] According to one aspect, operating system 211, for example, is suitable for controlling the operation of computing device 200. Furthermore, the example is practiced in conjunction with graphics libraries, other operating systems, or any other applications, and is not limited to any particular application or system. Figure 2 The basic configuration is illustrated by the components within the dashed line 215. According to one aspect, the computing device 200 has additional features or functions. For example, according to one aspect, the computing device 200 includes additional data storage devices (removable and / or non-removable), such as disks, optical discs, or magnetic tapes.

[0025] As stated above, according to one aspect, program module 212 is stored in system memory 210. According to one aspect, program module 212 may include one or more applications. The invention does not limit the type of application; for example, applications also include: email and contact applications, word processing applications, spreadsheet applications, database applications, slideshow applications, drawing or computer-aided applications, web browser applications, etc.

[0026] According to one aspect, examples can be practiced on circuits including discrete electronic components, packaged or integrated electronic chips containing logic gates, circuits utilizing microprocessors, or on a single chip containing electronic components or a microprocessor. For example, it can be practiced via wherein... Figure 2Each or many of the components shown can be implemented as an example by integrating a System-on-a-Chip (SOC) on a single integrated circuit. According to one aspect, such an SOC device may include one or more processing units, graphics units, communication units, system virtualization units, and various application functions, all integrated (or “burned in”) as a single integrated circuit onto a chip substrate. When operating via the SOC, the functions described herein can be operated via dedicated logic integrated on a single integrated circuit (chip) with other components of the computing device 200. Embodiments of the invention can also be implemented using other techniques capable of performing logical operations (e.g., AND, OR, and NOT), including but not limited to mechanical, optical, fluid, and quantum technologies. Additionally, embodiments of the invention can be implemented within a general-purpose computer or in any other circuit or system.

[0027] According to one aspect, computing device 200 may also connect to one or more input devices 231, such as a keyboard, mouse, pen, voice input device, touch input device, etc. It may also connect to output devices 232, such as a monitor, speaker, printer, etc. The foregoing devices are examples and other devices may also be used. Computing device 200 may include one or more communication connections 233 that allow communication with other computing devices 240. Examples of suitable communication connections 233 include, but are not limited to: RF transmitters, receivers and / or transceiver circuitry; Universal Serial Bus (USB), parallel and / or serial ports. Computing device 200 may communicate with other computing devices 240 via communication connections 233.

[0028] This invention also provides a non-transitory readable storage medium storing instructions for causing a computing device to execute a method according to an embodiment of the invention. The readable medium in this embodiment includes both permanent and non-permanent, removable and non-removable media, and information storage can be implemented by any method or technology. The information can be computer-readable instructions, data structures, program modules, or other data. Examples of readable storage media include, but are not limited to: phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transitory readable storage medium.

[0029] According to one aspect, a communication medium is implemented by computer-readable instructions, data structures, program modules, or other data in a modulated data signal (e.g., a carrier wave or other transmission mechanism), and includes any information transmission medium. According to one aspect, the term "modulated data signal" describes a signal having one or more sets of characteristics or altered in a manner that encodes information in the signal. By way of example and not limitation, a communication medium includes wired media such as wired networks or direct wired connections, and wireless media such as acoustic, radio frequency (RF), infrared, and other wireless media.

[0030] It should be noted that although the above-described computing device only shows the processing unit 220, system memory 210, input device 231, output device 232, and communication connection 233, in specific implementations, the device may also include other components necessary for normal operation. Furthermore, those skilled in the art will understand that the above-described device may only include the components necessary for implementing the embodiments of this specification, and not necessarily all the components shown in the figures.

[0031] Figure 1 A schematic flowchart of a load balancing method 100 according to an exemplary embodiment of the present invention is shown. Figure 1 As shown, step 110 is executed first to determine the scheduling domains in the computing device that need to be load balanced, and multiple scheduling groups are determined according to the scheduling domains, each scheduling group including one or more processors.

[0032] According to one embodiment of the present invention, a computing device may include one or more central processing units (or processor chips, SoCs). The present invention does not limit the type or number of central processing units included in a computing device.

[0033] Each central processing unit (CPU) comprises multiple cores (or simply cores), and this invention does not limit the number of cores a CPU may contain. Multiple cores sharing a common cache form a cluster, and this invention does not limit the number of cores included in a cluster.

[0034] According to one embodiment of the present invention, each core can be virtually equipped with multiple processors (logical CPUs). The present invention does not limit the number of processors included in each core.

[0035] According to one embodiment of the present invention, the processors included in each core can form a scheduling domain (SMT scheduling domain). The multiple processors included in the SMT scheduling domain are divided into multiple scheduling groups. The SMT scheduling domain includes multiple scheduling groups, and each scheduling group includes one processor.

[0036] According to one embodiment of the present invention, the processors included in each cluster can form a scheduling domain (MC scheduling domain). One or more processors included in an MC scheduling domain are divided into multiple scheduling groups based on the sibling relationship of the processors in the sub-scheduling domains. An MC scheduling domain includes multiple scheduling groups, each scheduling group includes one core, and each core includes one or more processors; that is, each scheduling group in an MC scheduling domain includes one or more processors.

[0037] According to one embodiment of the present invention, the processors included in each central processing unit can form a scheduling domain (DIE scheduling domain). The multiple processors included in the DIE scheduling domain are divided into multiple scheduling groups according to the sibling relationship of the sub-scheduling domains. The DIE scheduling domain includes multiple scheduling groups, each scheduling group includes a cluster, each cluster includes one or more cores, and each core includes one or more processors.

[0038] According to one embodiment of the present invention, all processors included in the central processing unit of the computing device can be grouped into a scheduling domain (physical processor scheduling domain). The physical processor scheduling domain includes multiple scheduling groups, each scheduling group includes one or more central processing units, each central processing unit includes one or more clusters, each cluster includes one or more cores, and each core includes one or more processors.

[0039] In this invention, when determining the scheduling domain in a computing device that requires load balancing, one or more of the above-mentioned SMT scheduling domain, MC scheduling domain, SoC scheduling domain or physical processor scheduling domain can be used as the scheduling domain that requires load balancing, and then the multiple scheduling groups under the jurisdiction of the scheduling domain can be determined.

[0040] According to one embodiment of the present invention, multi-level scheduling domains can be obtained based on the above-described partitioning rules. Two adjacent scheduling domains can serve as a parent scheduling domain and a child scheduling domain. A parent scheduling domain includes a child scheduling domain.

[0041] According to one embodiment of the present invention, when determining a scheduling group based on a scheduling domain, a tree structure diagram can be drawn based on the scheduling domain, where each node in the tree structure diagram is a scheduling group, and the scheduling group is determined based on the tree structure diagram.

[0042] According to one embodiment of the present invention, the scheduling domain and scheduling group, as well as the hierarchical relationship between the scheduling group and the scheduling domain, can be determined by executing the following code:

[0043]

[0044] Subsequently, step 120 is executed, whereby when the processor's load changes from the first load to the second load, the load of the scheduling group to which the processor belongs at the first moment is determined based on the second load.

[0045] According to one embodiment of the present invention, the time when the processor load changes from other load conditions to a first load is designated as the second moment, and the time when the processor load changes from the first load to the second load is designated as the first moment. In terms of time sequence, the second moment precedes the first moment.

[0046] According to one embodiment of the present invention, the time when the processor load changes from a first load to a second load includes the time for changes in the processor's ready queue, the time for changes in the processor state, and the time for the computing device to start up. When the computing device starts up, the processor begins to execute tasks and is under load.

[0047] According to one embodiment of the present invention, the processor load includes processor state, which includes idle state and busy state. When determining the load of the scheduling group to which the processor belongs at a first moment based on the second load, if the processor state of the first load is busy and the processor state of the second load is idle, the status identifier of the processor in the scheduling group is modified to the second identifier; then the load of the scheduling group to which the processor belongs at a first moment is determined based on the status identifier of the processors included in the scheduling group.

[0048] According to one embodiment of the present invention, the following code can be executed to modify the status identifier from a first identifier to a second identifier:

[0049] cpumask_set_cpu(cpu,sg->cpumask+BITS_TO_LONGS(nr_cpumask_bits);

[0050] According to one embodiment of the present invention, the scheduling group includes multiple attributes, one of which is the processor state. The processor state is used as one of the data points related to the processor's load. In the processor state, an idle state indicates that the processor has entered an idle process, meaning its resources are not being used by the system and it is not performing other tasks. In the processor state, a busy state indicates that the processor's resources are being used by the system and it is performing other tasks.

[0051] According to one embodiment of the present invention, the processor status of the scheduling group can be stored in the cpumask attribute value, and the status identifier of the processor in the scheduling group is set in the storage space of the cpumask attribute value.

[0052] According to one embodiment of the present invention, when the processor is in an idle state, its status identifier can be implemented as a second identifier; when the processor is in a busy state, its status identifier can be set to a first identifier. The present invention does not limit the specific identifier style of the first and second identifiers; the first identifier can specifically be implemented as 1, and the second identifier can specifically be implemented as 0.

[0053] When the processor state of the first load is different from that of the second load, the processor state flag is modified accordingly based on the change in processor state.

[0054] According to one embodiment of the present invention, when the processor of the first load is in an idle state and the processor of the second load is in a busy state, the status identifier of the processor in the scheduling group is modified to the first identifier; then the load of the scheduling group to which the processor belongs at the first moment is determined according to the status identifier of the processors included in the scheduling group.

[0055] According to one embodiment of the present invention, the following code can be executed to modify the status identifier from the second identifier to the first identifier:

[0056] cpumask_clear_cpu(cpu,sg->cpumask+BITS_TO_LONGS(nr_cpumask_bits));

[0057] According to one embodiment of the present invention, when determining the load of a scheduling group based on the status identifiers of the processors included in the scheduling group, the number of processors in the scheduling group that are in an idle state is determined based on the status identifiers of the processors included in the scheduling group; then, the load of the scheduling group is determined based on the number of processors in the scheduling group that are in an idle state. The load of the scheduling group includes the number of processors in the scheduling group that are processing idle states.

[0058] According to one embodiment of the present invention, the number of processors in an idle state in a scheduling group can be determined by executing the following code:

[0059] sg->idle_cpus=cpumask_weight(sg->cpumask+BITS_TO_LONGS(nr_cpumask_bits));

[0060] According to one embodiment of the present invention, the processor load further includes a processor load value. When determining the load of the scheduling group to which the processor belongs at the first moment based on the second load, the processor load value of the processor in the scheduling group at the second moment is also modified to the processor load value of the processor at the second moment. The second load includes the processor load value of the processor at the second moment; the first load includes the processor load value of the processor at the first moment.

[0061] When determining the load of a scheduling group, the load of the scheduling group is determined based on the processor load value at the first moment. Specifically, the load of the scheduling group includes the average load and the total load of the scheduling group. When determining the load of the scheduling group, the load value of the processor at the second moment is replaced with the load value at the first moment, and the average load and total load of each processor in the scheduling group are calculated by comparing it with the load values ​​of other processors in other scheduling groups.

[0062] According to one embodiment of the present invention, the load of a scheduling group can be determined by setting enqueue_task_fair and dequeue_task_fair, adding parameter statistics logic to them, and executing the function to obtain the load of the scheduling group.

[0063] Figure 3 A schematic diagram of a scheduling domain and scheduling group according to an exemplary embodiment of the present invention is shown. Figure 3 As shown: Scheduling domain 310 includes a first scheduling group 311 and a second scheduling group 312. The first scheduling group 311 includes processors 321 and 322. The second scheduling group 312 includes processors 323 and 324.

[0064] The first scheduling group 311 has a load at the second time point, wherein the processor 321 has a first load at the second time point. In the first load, the processor state is busy and the load value is 10. The load of processor 321 changes from the first load to the second load at the first time point, in which the processor state is idle and the load value is 0.

[0065] When the load of processor 321 changes from the first load to the second load at the first moment, the load of the first scheduling group 311 at the first moment is determined according to the second load.

[0066] Since the processor state of processor 321 changes from busy to idle, the status identifier of processor 321 in the first scheduling group 311 is changed from the first identifier to the second identifier.

[0067] The load value of processor 321 is changed from 10 to 0, and the processor load value of processor 321 in the scheduling group is modified from 10 to 0.

[0068] The load of the first scheduling group 311 is then determined based on the processor state and processor load value of processor 321 (i.e., the second load of processor 321).

[0069] According to one embodiment of the present invention, a list of scheduling groups is pre-generated in the scheduling domain. The present invention does not limit the specific time for generating the scheduling group list; for example, the scheduling group list of the scheduling domain can be generated when the computing device starts up. The scheduling group list is regenerated each time the processor load changes.

[0070] According to one embodiment of the present invention, at the second time moment, a list of scheduling groups is also generated in the scheduling domain. Specifically, the load of each scheduling group in the scheduling domain at the second time moment is obtained; the scheduling groups are sorted according to the load of each scheduling group to obtain a sorted sequence of scheduling groups; a second list of scheduling groups is constructed based on the sequence of scheduling groups, the second list of scheduling groups including multiple scheduling groups and their corresponding loads.

[0071] According to one embodiment of the present invention, when sorting scheduling groups based on their load, the scheduling groups can be sorted from high to low load. The present invention does not limit the specific sorting method; the scheduling groups can also be sorted from low to high load. When sorting scheduling groups based on their load, the sorting can be based on one or more parameters of the load of the scheduling group, or the load characteristic value can be calculated based on each parameter according to preset rules. The present invention does not limit the specific method of calculating the load characteristic value of the scheduling group.

[0072] Subsequently, step 130 is executed. Based on the load of the scheduling group to which the processor belongs at the first moment, a first scheduling group load list for the scheduling domain is determined. The first scheduling group load list includes the loads of multiple scheduling groups. Specifically, the loads of the scheduling groups in the second scheduling group list at the second moment are modified to match their loads at the first moment, thus obtaining the first scheduling group load list for the scheduling domain. After modifying the loads of the scheduling groups in the second scheduling group list at the second moment to match their loads at the first moment, if the resulting scheduling group sequence needs to change, it is re-sorted according to the loads of each scheduling group, resulting in a sorted scheduling group sequence. The first scheduling group list is then constructed based on the scheduling group sequence.

[0073] Finally, step 140 is executed, which performs load balancing on the processors in the scheduling domain according to the first scheduling group load list. Specifically: the scheduling group with the highest load in the scheduling domain is determined based on the first scheduling group load list; and process migration is performed on the processors in the scheduling group with the highest load according to a preset load balancing strategy. Load balancing refers to distributing running processes evenly across the processors in the scheduling domain according to processor usage.

[0074] According to one embodiment of the present invention, in the first scheduling group load list, each scheduling group is sorted from high to low according to its load. The scheduling group ranked first is the scheduling group with the highest load. The present invention does not limit the specific content of the load balancing strategy and can be set according to specific needs. Processes are selected from the scheduling groups with high loads and migrated to the scheduling groups with low loads, thereby improving the operating efficiency of computing devices and making full use of computer resources.

[0075] According to one embodiment of the present invention, the scheduling domain 310 generates a second scheduling group load list at a second time, which includes scheduling groups with loads ranked from high to low. The first scheduling group 311 and the second scheduling group 312 are the first and second positions in the second scheduling group load list, respectively. At a first time, the load of the processor 321 changes. The scheduling domain 310 generates the first scheduling group load list at the first time. Specifically: the load of the first scheduling group 311 is calculated, and the load of the first scheduling group 311 is less than the load of the second scheduling group 312. The scheduling groups are then re-sorted according to their loads to obtain a sorted sequence of scheduling groups; a second scheduling group list is constructed based on this sequence. In the second scheduling group list, the second scheduling group 312 is the first position, and the first scheduling group 311 is the second position. Subsequently, the processes running on the processors in the second scheduling group 312 are migrated to implement load balancing.

[0076] This invention discloses a load balancing method suitable for execution in computing devices. The method includes: determining a scheduling domain in the computing device that requires load balancing, and determining multiple scheduling groups based on the scheduling domain, each scheduling group including one or more processors; when the load of a processor changes from a first load to a second load, determining the load of the scheduling group to which the processor belongs at a first moment based on the second load; determining a first scheduling group load list for the scheduling domain based on the load of the scheduling group to which the processor belongs at the first moment, the first scheduling group load list including the loads of multiple scheduling groups; and performing load balancing on the processors in the scheduling domain based on the first scheduling group load list. This invention reduces the frequency and number of load statistics by statistically analyzing the load situation when the processor load changes, thereby improving the efficiency of load balancing, decomposing the burden of centrally and uniformly statistically analyzing the load information of all scheduling groups, and saving computer resources.

[0077] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0078] Similarly, it should be understood that, in order to streamline this disclosure and aid in understanding one or more of the various aspects of the invention, in the above description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof.

[0079] Those skilled in the art will understand that the modules, units, or groups of devices in the examples disclosed herein can be arranged in the device as described in this embodiment, or alternatively, can be located in one or more devices different from the device in this example. The modules in the foregoing examples can be combined into a single module or, in addition, can be divided into multiple sub-modules.

[0080] Those skilled in the art will understand that modules in the apparatus of the embodiments can be adaptively changed and placed in one or more devices different from that embodiment. Modules, units, or groups in the embodiments can be combined into a single module, unit, or group, and further, they can be divided into multiple sub-modules, sub-units, or sub-groups. Except where at least some of such features and / or processes or units are mutually exclusive, any combination can be used to combine all features disclosed herein and all processes or units of any method or apparatus so disclosed. Unless expressly stated otherwise, each feature disclosed herein may be replaced by an alternative feature that serves the same, equivalent, or similar purpose.

[0081] Furthermore, those skilled in the art will understand that although some embodiments described herein include certain features included in other embodiments but not others, combinations of features from different embodiments are meant to be within the scope of the invention and form different embodiments.

[0082] Furthermore, some of the embodiments described herein are methods or combinations of method elements that can be implemented by a processor of a computer system or by other means of performing the functions. Therefore, a processor having the necessary instructions for implementing the methods or method elements forms means for implementing the methods or method elements. Furthermore, the elements described herein in the apparatus embodiments are examples of means for implementing the functions performed by elements for the purposes of carrying out the invention.

[0083] The various techniques described herein can be implemented in combination with hardware or software, or a combination thereof. Thus, the methods and apparatus of the present invention, or certain aspects or portions thereof, can take the form of program code (i.e., instructions) embedded in a tangible medium, such as a floppy disk, CD-ROM, hard disk, or any other machine-readable storage medium, wherein when the program is loaded into and executed by a machine such as a computer, the machine becomes an apparatus for practicing the present invention.

[0084] When the program code is executed on a programmable computer, the computing device generally includes a processor, a processor-readable storage medium (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device. The memory is configured to store program code; the processor is configured to execute the load balancing method of the present invention according to instructions in the program code stored in the memory.

[0085] By way of example, and not limitation, computer-readable media include computer storage media and communication media. Computer storage media stores information such as computer-readable instructions, data structures, program modules, or other data. Communication media generally embodies computer-readable instructions, data structures, program modules, or other data in the form of modulated data signals such as carrier waves or other transmission mechanisms, and includes any information delivery medium. Any combination of the above is also included within the scope of computer-readable media.

[0086] As used herein, unless otherwise specified, the use of ordinal numbers such as “first,” “second,” “third,” etc., to describe ordinary objects merely indicates different instances of similar objects and is not intended to imply that the objects being described must have a given order in time, space, ordering, or any other manner.

[0087] Although the invention has been described with reference to a limited number of embodiments, those skilled in the art will understand from the foregoing description that other embodiments are conceivable within the scope of the invention described herein. Furthermore, it should be noted that the language used in this specification has been chosen primarily for readability and edibility purposes, and not for the purpose of explaining or limiting the subject matter of the invention. Therefore, many modifications and variations will be apparent to those skilled in the art. The disclosure of the invention regarding its scope is illustrative and not restrictive.

Claims

1. A load balancing method, suitable for execution in a computing device, the method comprising: The scheduling domains in the computing device that require load balancing are determined, and multiple scheduling groups are determined based on the scheduling domains, each scheduling group including one or more processors; The load of each scheduling group in the scheduling domain at the second time point is obtained in advance; The scheduling groups are sorted according to their load to obtain a sorted sequence of scheduling groups; A second scheduling group list is constructed based on the scheduling group sequence. The second scheduling group list includes multiple scheduling groups and their corresponding loads. When the processor's load changes from a first load to a second load, the load of the scheduling group to which the processor belongs at the first moment is determined based on the second load; Based on the load of the scheduling group to which the processor belongs at the first moment, determine the first scheduling group load list of the scheduling domain, including modifying the load of the scheduling group in the second scheduling group list at the second moment to the load of the scheduling group at the first moment, to obtain the first scheduling group load list of the scheduling domain, wherein the first scheduling group load list includes the load of multiple scheduling groups. Process migration is performed on processors in the scheduling domain based on the load list of the first scheduling group.

2. The method as described in claim 1, wherein, The processor load includes processor states, which include idle and busy states. Determining the load of the scheduling group to which the processor belongs at a first moment based on the second load includes: When the processor of the first load is in a busy state and the processor of the second load is in an idle state, the status identifier of the processor in the scheduling group is modified to the second identifier; The load of the scheduling group to which the processor belongs at the first moment is determined based on the status identifier of the processors included in the scheduling group.

3. The method as described in claim 2, wherein, The method further includes: When the processor of the first load is in an idle state and the processor of the second load is in a busy state, the status identifier of the processor in the scheduling group is modified to the first identifier; The load of the scheduling group to which the processor belongs at the first moment is determined based on the status identifier of the processors included in the scheduling group.

4. The method as described in claim 2 or 3, wherein, Determining the load of the scheduling group based on the status identifiers of the processors included in the scheduling group includes: The number of processors in the scheduling group that are in an idle state is determined based on the status identifiers of the processors included in the scheduling group; The load of the scheduling group is determined based on the number of processors in the scheduling group that are in an idle state.

5. The method of claim 1, wherein, The step of load balancing the processors in the scheduling domain according to the first scheduling group load list includes: The scheduling group with the highest load in the scheduling domain is determined based on the first scheduling group load list; Process migration is performed on the processors in the scheduling group with the highest load according to the preset load balancing strategy.

6. The method as described in claim 1 or 5, wherein, The processor load also includes a processor load value. Determining the load of the scheduling group to which the processor belongs at the first moment based on the second load also includes: Modify the processor load value of the processor in the scheduling group at the second time to the processor load value of the processor at the first time; The load of the scheduling group is determined based on the processor load value of the processor at the first moment.

7. A computing device, comprising: One or more processors; Memory; as well as One or more programs, wherein the programs are stored in memory and configured to be executed by one or more processors, and the programs include instructions for performing the method according to any one of claims 1-6.

8. A computer-readable storage medium storing one or more programs, said one or more programs including instructions that, when executed by a computing device, cause the computing device to perform the method according to any one of claims 1-6.

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