Semiconductor structure and method of forming a capacitor structure

Abstract

The embodiment of the present disclosure provides a semiconductor structure and a forming method of a capacitor structure, and the method comprises the following steps: providing a first substrate; wherein the first substrate comprises a bottom support layer, a first sacrificial layer with a lower electrode penetrating through and a mask layer in sequence; the surface of the lower electrode is flush with the mask layer and is connected with a capacitor contact pad in the bottom support layer; etching the first sacrificial layer to a preset first thickness to form a second sacrificial layer; forming an intermediate support layer and a top support layer on the second sacrificial layer to form a capacitor structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and to, but is not limited to, a method for forming a semiconductor structure and a capacitor structure. Background Technology

[0002] Dynamic Random Access Memory (DRAM) consists of transistors and capacitors. To increase the capacitance of the capacitor structure, capacitors often have a high aspect ratio. This requires a capacitor structure design with two sacrificial layers and three support layers to achieve stability. However, current manufacturing processes struggle to achieve the required verticality of the capacitor profile and smoothness of the sidewalls, which can negatively impact the stability of the capacitor structure. Summary of the Invention

[0003] This disclosure provides a method for forming a semiconductor structure and a capacitor structure.

[0004] In a first aspect, embodiments of this disclosure provide a method for forming a capacitor structure, the method comprising: providing a first substrate; wherein the first substrate sequentially comprises: a bottom support layer, a first sacrificial layer having a lower electrode penetrating through it, and a mask layer; the surface of the lower electrode is flush with the mask layer and connected to a capacitor contact pad in the bottom support layer; etching the first sacrificial layer to a predetermined first thickness to form a second sacrificial layer; and forming an intermediate support layer and a top support layer on the second sacrificial layer to form a capacitor structure.

[0005] In some embodiments, providing the first substrate includes: providing a second substrate; wherein the second substrate sequentially includes: the bottom support layer, an initial first sacrificial layer, and an initial mask layer; etching the initial mask layer and the initial first sacrificial layer with a first pattern identical to the capacitor hole pattern to form a mask layer and a first sacrificial layer having capacitor holes; and depositing electrode material in the capacitor holes to form the lower electrode.

[0006] In some embodiments, etching the initial mask layer and the initial first sacrificial layer with a first pattern identical to the capacitor hole pattern to form a mask layer and a first sacrificial layer having capacitor holes includes: etching the initial mask layer with a first pattern identical to the capacitor hole pattern to form a mask layer with a first pattern; and etching the initial first sacrificial layer with the mask layer having the first pattern to form a first sacrificial layer having capacitor holes.

[0007] In some embodiments, etching the initial mask layer with a first pattern identical to the capacitor hole pattern to form a mask layer having the first pattern includes: forming a composite mask layer having a second pattern on the initial mask layer; and patterning the initial mask layer based on the composite mask layer with the second pattern to form a mask layer having the first pattern.

[0008] In some embodiments, etching the initial first sacrificial layer with the mask layer having the first pattern to form a first sacrificial layer having the capacitor hole includes: forming a first electrode flush with the mask layer in the aperture of the first pattern; etching the initial first sacrificial layer using a metal-assisted chemical etching process to form a first sacrificial layer having the capacitor hole, wherein the first electrode is connected to the capacitor contact pad to form a second electrode as the initial first sacrificial layer is consumed.

[0009] In some embodiments, forming a first electrode flush with the mask layer in the pores of the first pattern includes: depositing the electrode material in the pores of the first pattern to form an initial first electrode; and etching the initial first electrode using a dry etching process, a wet etching process, or a chemical mechanical polishing process to form the first electrode flush with the mask layer.

[0010] In some embodiments, after forming the second electrode, the lower electrode is formed by depositing electrode material in the capacitor hole, including: depositing the electrode material in the capacitor hole after forming the second electrode; removing excess electrode material using the dry etching process, wet etching process, or chemical mechanical polishing process to form a lower electrode flush with the mask layer.

[0011] In some embodiments, etching the first sacrificial layer to a predetermined first thickness to form a second sacrificial layer includes: removing the mask layer using a dry or wet etching process; and etching the first sacrificial layer using a dry or wet etching process to form a second sacrificial layer having a first predetermined thickness.

[0012] In some embodiments, forming an intermediate support layer on the second sacrificial layer includes: covering the second sacrificial layer and the lower electrode with an intermediate support material layer; forming a spin-coated hard mask layer on the intermediate support material layer; and simultaneously removing the intermediate support material layer and the spin-coated hard mask layer from the top and sidewalls of the lower electrode to form the intermediate support layer.

[0013] In some embodiments, forming an intermediate support layer and a top support layer on the second sacrificial layer to form a capacitor structure includes: forming a third sacrificial layer on the intermediate support layer; wherein the top surface of the third sacrificial layer is lower than the top surface of the lower electrode; forming the top support layer on the third sacrificial layer; patterning the top support layer and forming a first opening in the top support layer, removing the second sacrificial layer and the third sacrificial layer through the first opening; and sequentially forming a dielectric layer and an upper electrode on the lower electrode to obtain the capacitor structure.

[0014] In some embodiments, the second sacrificial layer is made of a different material than the third sacrificial layer; the material of the third sacrificial layer is an oxide.

[0015] In some embodiments, forming a third sacrificial layer on the intermediate support layer includes: forming an initial third sacrificial material layer on the intermediate support layer, wherein the top surface of the initial third sacrificial material layer is higher than the top surface of the lower electrode; removing a portion of the initial third sacrificial material layer using a chemical mechanical polishing process to form an initial third sacrificial layer flush with the top surface of the lower electrode; and etching the initial third sacrificial layer using a dry or wet etching process to form a third sacrificial layer lower than the top surface of the lower electrode.

[0016] In some embodiments, the top support layer is graphically represented, and a first opening is formed in the top support layer. Removing the second sacrificial layer and the third sacrificial layer through the first opening includes: etching the top support layer, the intermediate support layer, the second sacrificial layer, and the third sacrificial layer between any adjacent lower electrodes to form the first opening; and removing the second sacrificial layer and the third sacrificial layer through the first opening using a wet etching process.

[0017] Secondly, embodiments of this disclosure provide a semiconductor structure, including: a capacitor structure formed using the method described in any of the above embodiments.

[0018] In this embodiment, firstly, a first substrate is provided; wherein the first substrate sequentially includes: a bottom support layer, a first sacrificial layer with a lower electrode penetrating through it, and a mask layer; the surface of the lower electrode is flush with the mask layer and connected to the capacitor contact pad in the bottom support layer, which can reduce the possibility of short circuits between adjacent capacitor contact pads; secondly, the first sacrificial layer is etched to a preset first thickness to form a second sacrificial layer, which can provide a relatively flat surface for the subsequent formation of the intermediate support layer; finally, an intermediate support layer and a top support layer are formed on the second sacrificial layer to form a capacitor structure. As can be seen from the above, this embodiment first forms the lower electrode, and then forms the intermediate support layer and the top support layer, that is, this embodiment provides a new method for forming a capacitor structure; in addition, since the first substrate includes a first sacrificial layer and a mask layer with a lower electrode penetrating through it, it means that when etching the capacitor hole, only the first sacrificial layer of a single material needs to be etched, and it is not necessary to simultaneously etch the support layer and sacrificial layer of different materials. The capacitor hole formed in this way is more vertical and smooth, thereby obtaining a capacitor structure with excellent morphology, with a vertical cross-section and smooth sidewalls. Attached Figure Description

[0019] In the accompanying drawings (which are not necessarily drawn to scale), similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The drawings illustrate, by way of example and not limitation, the various embodiments discussed herein.

[0020] Figure 1 This is a schematic diagram illustrating the formation process of a capacitor structure in related technologies;

[0021] Figure 2 A schematic diagram illustrating the implementation process of a method for forming a capacitor structure according to an embodiment of this disclosure;

[0022] Figures 3 to 18 A schematic diagram illustrating the formation process of a capacitor structure provided for this disclosure. Detailed Implementation

[0023] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0024] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0025] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0026] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0027] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0028] A schematic diagram of the formation process of the capacitor structure in related technologies can be found in the following reference. Figure 1 The process of forming the capacitor structure includes the following steps:

[0029] First see Figure 1The left image shows a substrate comprising, from bottom to top: a stacked structure 10, a first mask layer 116, and a patterned second mask layer 117. The stacked structure 10 sequentially includes a bottom support layer 111, a first sacrificial layer 112, a middle support layer 113, a second sacrificial layer 114, and a top support layer 115. Next, the first mask layer 116 and the stacked structure 10 are etched through the patterned second mask layer 117 to form a capacitor aperture (not shown). Then, the remaining first mask layer 116 above the top support layer 115 is etched back, exposing the top support layer. Next, electrode material is deposited in the capacitor aperture, and the electrode material above the top surface of the top support layer 115 is etched back to form the lower electrode. Finally, between any adjacent lower electrodes, the top support layer 115, the second sacrificial layer 114, the middle support layer 113, and the first sacrificial layer 112 are etched to form a... Figure 1 The opening 118 is shown in the right figure; based on the opening 118, the first sacrificial layer 112 and the second sacrificial layer 114 are removed by wet etching; finally forming as shown in the figure. Figure 1 The supporting structure shown in the middle right figure is followed by the deposition of dielectric material and upper electrode material on the lower electrode and supporting structure to form a capacitor structure.

[0030] In related technologies, dry or wet etching processes are generally used to etch the stacked structure to form capacitor holes. Since the stacked structure includes sacrificial layers and intermediate support layers of different materials, the materials being etched during the etching process are different and there are many layers. In addition, the depth-to-width ratio of the capacitor holes is large, which makes it difficult for the outline of the capacitor holes to be perpendicular, and the sidewalls are always rough. Therefore, the resulting capacitor morphology is poor.

[0031] In view of this, embodiments of the present disclosure provide a method for forming a capacitor structure, with reference to... Figure 2 The method includes steps S201 to S203, wherein:

[0032] Step S201, providing a first substrate; wherein the first substrate sequentially includes: a bottom support layer, a first sacrificial layer with a lower electrode penetrating through it, and a mask layer; the surface of the lower electrode is flush with the mask layer and connected to the capacitive contact pad in the bottom support layer;

[0033] Here, the material of the bottom support layer may include at least one of the following: silicon oxide, silicon nitride, silicon carbide nitride, silicon oxynitride, and silicon boron nitride. The material of the first sacrificial layer may include silicon oxide, phosphoro silicate glass (PSG), borophosphorus silicate glass (BPSG), or fluorosilicone glass (FSG), polycrystalline silicon, silicon (Si), germanium (Ge), gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), gallium nitride (GaN), silicon carbide (SiC), etc.

[0034] The mask layer can be a single-layer structure or a double-layer structure; wherein, the material of each layer can be one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, amorphous carbon, polycrystalline silicon, hafnium oxide, titanium oxide, zirconium oxide, titanium nitride, tantalum nitride, and titanium. In the following embodiments, a single-layer structure of silicon oxide is used as an example for illustration.

[0035] The material of the lower electrode may include metal, metal nitride, or metal silicide, such as titanium nitride (TiN). In some embodiments, the lower electrode may be formed by depositing the lower electrode material in the capacitor aperture using any suitable deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), plasma-enhanced chemical vapor deposition (PECVD), spin coating, coating, or thin film processing.

[0036] In other embodiments, the lower electrode may be formed by forming a portion of the lower electrode simultaneously with the capacitor hole through a metal-assisted chemical etching process, and then depositing the lower electrode material in the capacitor hole. The present disclosure does not limit the method of forming the lower electrode.

[0037] Capacitor contact pads are used to electrically connect the drain of a transistor to a capacitor structure. Multiple capacitor holes formed subsequently can expose multiple capacitor contact pads, thereby forming multiple capacitor structures corresponding to the multiple capacitor contact pads.

[0038] Step S202: Etch the first sacrificial layer to a preset first thickness to form the second sacrificial layer;

[0039] Here, step S202 is the process of thinning the first sacrificial layer, which allows space to be reserved for the intermediate support layer and the top support layer. In implementation, the first sacrificial layer can be etched using a dry or wet etching process to form a second sacrificial layer with a first preset thickness, providing a relatively flat plane for the subsequent formation of the intermediate support layer on the second sacrificial layer. The preset first thickness can be set according to the thickness of the first sacrificial layer and the etching precision.

[0040] Here, the etching gases used in the dry etching process may include trifluoromethane (CHF3), carbon tetrafluoride (CF4), hydrogen bromide (HBr), and chlorine (Cl2). In other embodiments, the etching gases may also include one or more of other carbon-fluorine based gases, such as difluoromethane (CH2F2), octafluoropropane (C3F8), perfluorobutadiene (C4F6), octafluorocyclobutane (C4F8), and octafluorocyclopentene (C5F8). The etching solution used in the wet etching process may include a diluted hydrofluoric acid solution, wherein the volume ratio of hydrogen fluoride to deionized water in the diluted hydrofluoric acid solution is 1:150 to 1:250, for example, a volume ratio of hydrogen fluoride to deionized water of 1:200.

[0041] Step S203: An intermediate support layer and a top support layer are formed on the second sacrificial layer to form a capacitor structure;

[0042] Here, the bottom support layer, the middle support layer, and the top support layer are used to form a support structure for supporting the capacitor structure. In implementation, the materials of the middle support layer and the top support layer can be the same as the material of the bottom support layer, for example, all three are silicon nitride.

[0043] In practice, the intermediate support layer and the top support layer can be formed by any of the following suitable deposition processes, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, plasma chemical vapor deposition, spin coating, coating process, or thin film process.

[0044] After forming the intermediate support layer and the top support layer to form the support structure, it is necessary to deposit dielectric layer material and top electrode material on the bottom electrode and the support structure to form the dielectric layer and the top electrode to form the capacitor structure.

[0045] In this embodiment, firstly, a first substrate is provided; wherein the first substrate sequentially includes: a bottom support layer, a first sacrificial layer with a lower electrode penetrating through it, and a mask layer; the surface of the lower electrode is flush with the mask layer and connected to the capacitor contact pad in the bottom support layer, which can reduce the possibility of short circuits between adjacent capacitor contact pads; secondly, the first sacrificial layer is etched to a preset first thickness to form a second sacrificial layer, which can provide a relatively flat surface for the subsequent formation of the intermediate support layer; finally, an intermediate support layer and a top support layer are formed on the second sacrificial layer to form a capacitor structure. As can be seen from the above, this embodiment first forms the lower electrode, and then forms the intermediate support layer and the top support layer, that is, this embodiment provides a new method for forming a capacitor structure; in addition, since the first substrate includes a first sacrificial layer and a mask layer with a lower electrode penetrating through it, it means that when etching the capacitor hole, only the first sacrificial layer of a single material needs to be etched, and it is not necessary to simultaneously etch the support layer and sacrificial layer of different materials. The capacitor hole formed in this way is more vertical and smooth, thereby obtaining a capacitor structure with excellent morphology, with a vertical cross-section and smooth sidewalls.

[0046] The following will refer to Figures 3 to 18 The present disclosure provides a detailed description of a method for forming a capacitor structure according to embodiments.

[0047] First, refer to Figures 3 to 8 Step S201 is executed, providing a first substrate 20. The first substrate 20 sequentially includes: a bottom support layer 21, a first sacrificial layer 22 through which a lower electrode 26 penetrates, and a mask layer 23. The surface of the lower electrode 26 is flush with the mask layer 23 and connected to a capacitive contact pad 21a on the bottom support layer 21.

[0048] In some embodiments, the first substrate may be formed via steps S301 to S303, wherein:

[0049] Step S301, providing a second substrate; wherein the second substrate sequentially includes: a bottom support layer, an initial first sacrificial layer and an initial mask layer;

[0050] Step S302: Using a first pattern identical to the capacitor hole pattern, etch the initial mask layer and the initial first sacrificial layer to form a mask layer and the first sacrificial layer with capacitor holes;

[0051] Here, the capacitor aperture pattern can be multiple capacitor apertures arranged in an array, with the multiple capacitor apertures corresponding to the capacitor contact pads in the bottom support layer. Step S302 is the process of transferring the first pattern to the initial mask layer and the initial first sacrificial layer. In implementation, the transfer can be done in one step or in two steps. For example, the first pattern can be transferred to the initial mask layer first to form a mask layer with the first pattern, and then the first pattern in the mask layer can be transferred to the initial first sacrificial layer to form a first sacrificial layer with capacitor apertures.

[0052] Step S303: After depositing electrode material in the capacitor hole, the lower electrode is formed.

[0053] In some embodiments, the implementation of step S302 may include steps S3021 and S3022, wherein:

[0054] Step S3021: Etch the initial mask layer with a first pattern identical to the capacitor hole pattern to form a mask layer with the first pattern;

[0055] Step S3022: Etch the initial first sacrificial layer with a mask layer having a first pattern to form a first sacrificial layer with capacitor holes.

[0056] In some embodiments, the implementation of step S3021 may include steps S311 and S312, wherein:

[0057] Step S311: Form a composite mask layer with a second pattern on the initial mask layer;

[0058] Here, the composite mask layer may include a hard mask layer and an anti-reflection layer, etc. The anti-reflection layer may be one or a stack of two of the following: a bottom anti-reflection coating (BARC) and a dielectric anti-reflection coating (DARC).

[0059] Step S312: Based on the composite mask layer with the second pattern, the initial mask layer is patterned to form a mask layer with the first pattern.

[0060] Here, self-aligned double patterning (SADP) can be used to transfer the pattern in the composite mask layer to the initial mask layer, forming a mask layer with the first pattern. This allows for spatial frequency doubling of the lithographic pattern, resulting in smaller-pitched capacitor holes and thus enabling miniaturization.

[0061] First, refer to Figure 3A second substrate 20a is provided, which sequentially includes: a bottom support layer 21, an initial first sacrificial layer 22a, and an initial mask layer 23a. The bottom support layer includes a capacitor contact pad 21a. (See also...) Figure 3 and Figure 4 Using a first pattern identical to the capacitor hole pattern, an initial mask layer 23a is etched using a wet or dry etching process to form a mask layer 23 with the first pattern. Then, the initial first sacrificial layer 22a is etched using the mask layer 23 with the first pattern to form a first sacrificial layer 22 with a through-hole, exposing the capacitor contact pad 21a. This forms a... Figure 5 The capacitor hole 25 shown penetrates the mask layer 23 and the first sacrificial layer 22, thereby forming the first substrate 20.

[0062] Secondly, refer to Figure 5 Electrode material is deposited in capacitor aperture 25. During implementation, the deposited electrode material layer may be higher than mask layer 23 or the deposited electrode material may be uneven. Therefore, dry etching processes (such as plasma etching, reactive ion etching, or ion milling) or wet etching processes (such as etching with strong acids such as concentrated sulfuric acid, hydrofluoric acid, or concentrated nitric acid) can be used to etch the electrode material layer. Alternatively, chemical mechanical polishing (CMP) can be used to planarize the electrode material to form a surface like... Figure 6 The lower electrode 26 shown is connected to the capacitor contact pad 21a, from Figure 6 As can be seen, the top surface of the lower electrode 26 is flush with the top surface of the mask layer 23.

[0063] In some embodiments, the implementation of step S3022, "etching the initial first sacrificial layer with a mask layer having a first pattern to form a first sacrificial layer with a capacitor hole," may include steps S321 and S322, wherein:

[0064] Step S321: A first electrode flush with the mask layer is formed in the aperture of the first pattern;

[0065] Here, the first electrode can be used as a metal catalyst in a metal-assisted chemical etching process. Therefore, the material of the first electrode can include at least one of the following: silver, platinum, gold, titanium nitride, copper, plutonium, palladium, titanium oxide, titanium carbide, and tungsten. The formation process of the first electrode can be any suitable deposition process, and this disclosure is not limited thereto.

[0066] In some embodiments, the implementation of step S321 may include steps S3211 and S3212, wherein:

[0067] Step S3211: Deposit electrode material in the pores of the first pattern to form an initial first electrode;

[0068] Step S3212: The initial first electrode is etched using a dry etching process, a wet etching process, or a chemical mechanical polishing process to form a first electrode flush with the mask layer.

[0069] In this embodiment, electrode material is first deposited in the pores of the first pattern to form an initial first electrode. Then, the initial first electrode is etched using a dry etching process, a wet etching process, or a chemical mechanical polishing process to form a first electrode flush with the mask layer. This makes the top surface of the first electrode relatively flat, providing a flat surface for subsequent deposition of electrode material to form the lower electrode. This can improve the interfacial bonding force between the two deposited electrode materials and reduce the possibility of lower electrode breakage.

[0070] Step S322: The initial first sacrificial layer is etched using a metal-assisted chemical etching process to form a first sacrificial layer with a capacitor hole. The first electrode is connected to the capacitor contact pad as the initial first sacrificial layer is consumed to form the second electrode.

[0071] Here, metal-assisted chemical etching (MAE) differs from traditional dry etching techniques, leaning towards wet etching and capable of forming anisotropic semiconductor structures such as silicon. MAE uses conductive materials, such as metals, as catalysts to etch semiconductors, so the sidewall roughness is related to the roughness of the metal catalyst itself, while minimal roughness is generated during the etching process. MAE only reacts on the surface of the metal catalyst and the semiconductor, preventing over-etching. Therefore, the resulting pattern is identical to the shape of the metal catalyst, providing extremely high etching precision, and the pattern can be transferred perfectly. This minimizes the issues of non-perpendicularity and inner wall roughness in capacitor holes; it also protects the formation of capacitor holes from other influences, ultimately resulting in ideally shaped capacitor holes. Furthermore, MAE can form smaller capacitor holes, enabling miniaturization.

[0072] refer to Figure 4 In the pores of the first pattern, electrode material is deposited to form an initial first electrode (not shown). The initial first electrode is etched using a dry etching process (e.g., plasma etching, reactive ion etching, or ion milling) or a wet etching process (e.g., etching with strong acids such as concentrated sulfuric acid, hydrofluoric acid, or concentrated nitric acid). Alternatively, a chemical mechanical polishing process can be used to form a first electrode. Figure 7 The first electrode 261 is flush with the mask layer; then, the initial first sacrificial layer 22a is etched using a metal-assisted chemical etching process to form as shown. Figure 8 The first sacrificial layer 22 shown has a capacitor hole 25, wherein the first electrode 261 is connected to the capacitor contact pad 21a as the initial first sacrificial layer 22a is consumed, forming a connection as shown. Figure 8 The second electrode 262 is shown. In other words, during the formation of the capacitor hole 25 by the metal-assisted chemical etching process, the first electrode 261, which originally served as a metal catalyst, falls to the bottom of the capacitor hole 25 as the initial first sacrificial layer 22a is consumed, forming the second electrode 262, which serves as part of the subsequently formed lower electrode.

[0073] In this embodiment, a first electrode flush with the mask layer is formed in the gaps of the first pattern. Then, a metal-assisted chemical etching process is used to etch the initial first sacrificial layer to form a capacitor hole and a portion of the lower electrode, i.e., the second electrode, is formed at the same time. Therefore, the resulting capacitor hole is smaller and the sidewalls of the capacitor hole are more vertical and smoother. In other words, the morphology of the capacitor hole is better, which can further improve the morphology of the capacitor structure.

[0074] In some embodiments, after the formation of the second electrode, the implementation of step S303, "forming the lower electrode after depositing electrode material in the capacitor hole," may include steps S3031 and S3032, wherein:

[0075] Step S3031: Deposit electrode material in the capacitor hole after the second electrode is formed;

[0076] Step S3032: Use dry etching, wet etching or chemical mechanical polishing to remove excess electrode material and form a lower electrode flush with the mask layer.

[0077] refer to Figure 8 First, electrode material is deposited in the capacitor hole 25 forming the second electrode 262; then, excess electrode material is removed using a dry etching process, a wet etching process, or a chemical mechanical polishing process to form a electrode structure as shown in the figure. Figure 6 The lower electrode 26 shown is flush with the surface of the mask layer.

[0078] As can be seen from the above description, the lower electrode 26 can be formed in at least two ways: Method 1: Etching the initial first sacrificial layer 22a with a mask layer 23 having a first pattern to form a capacitor hole 25, and then depositing electrode material in the capacitor hole to form the lower electrode 26; Method 2: Depositing electrode material in the gaps of the first pattern to form a first electrode 261, using a metal-assisted chemical etching process to etch the initial first sacrificial layer 22a, and while forming the capacitor hole 25, the first electrode 261 falls to the bottom of the capacitor hole 25 to form a second electrode 262, and finally depositing electrode material again to form the lower electrode 26.

[0079] The following will refer to Figure 9 and Figure 10 In step S202, the first sacrificial layer 22 is etched to a preset first thickness to form the second sacrificial layer 27.

[0080] In some embodiments, the implementation of step S202, "etching the first sacrificial layer to a preset first thickness to form a second sacrificial layer," includes steps S2021 and S2022, wherein:

[0081] Step S2021: Remove the mask layer using a dry or wet etching process;

[0082] Step S2022: The first sacrificial layer is etched using a dry or wet etching process to form a second sacrificial layer with a first preset thickness.

[0083] In implementation, firstly, refer to Figure 9 The mask layer 23 is removed using either dry or wet etching processes (see reference). Figure 6 The first sacrificial layer 22 is exposed; then, the first sacrificial layer 22 is etched using a dry etching process (e.g., plasma etching, reactive ion etching, or ion milling) or a wet etching process (e.g., etching with strong acids such as concentrated sulfuric acid, hydrofluoric acid, or concentrated nitric acid) to form a layer as shown in the image. Figure 10 The second sacrificial layer 27 shown has a first preset thickness.

[0084] In this embodiment of the disclosure, the mask layer is removed only after the lower electrode is formed. Compared with the process of removing the mask layer immediately after forming the capacitor hole in the related technology, this can reduce the occurrence of by-products (such as polymers) generated during mask layer removal falling into the capacitor hole, thereby improving the quality of the subsequently formed lower electrode.

[0085] The following will refer to Figures 11 to 18 Step S203 is performed to form an intermediate support layer 28 and a top support layer 31 on the second sacrificial layer 27 to form a capacitor structure 35.

[0086] In some embodiments, the formation of an intermediate support layer on the second sacrificial layer may include steps S231 to S233, wherein:

[0087] Step S231: Cover the second sacrificial layer and the lower electrode with an intermediate support material layer;

[0088] Step S232: Form a spin-coated hard mask layer on the intermediate support material layer;

[0089] Step S233: Simultaneously remove the intermediate support material layer and spin-coated hard mask layer from the top and sidewalls of the lower electrode to form an intermediate support layer.

[0090] First, refer to Figure 11An intermediate support material layer 28a is applied to the second sacrificial layer 27 and the lower electrode 26; next, a spin-coated hard mask layer 29 is formed on the intermediate support material layer 28a; finally, the intermediate support material layer 28a and the spin-coated hard mask layer 29 on the top and sidewalls of the lower electrode 26 are simultaneously removed, forming a layer as shown in the image. Figure 12 The intermediate support layer 28 is shown.

[0091] In this embodiment, firstly, an intermediate support material layer is applied to the second sacrificial layer and the lower electrode. Then, a spin-coated hard mask layer is formed on the intermediate support material layer. This spin-coated hard mask layer supports the intermediate support material layer, reducing the likelihood of it collapsing and thus minimizing its impact on the subsequently formed intermediate support layer. Finally, the intermediate support material layer and the spin-coated hard mask layer on the top and sidewalls of the lower electrode are simultaneously removed to form the intermediate support layer. Therefore, the intermediate support layer formed in this embodiment has a good morphology and its thickness meets the preset thickness requirement.

[0092] In some embodiments, the implementation of step S203 may include steps S2031 to S2034, wherein:

[0093] Step S2031: A third sacrificial layer is formed on the intermediate support layer; wherein the top surface of the third sacrificial layer is lower than the top surface of the lower electrode;

[0094] Here, the material of the third sacrificial layer can be the same as the material of the second sacrificial layer. For example, both the third and second sacrificial layers are made of polycrystalline silicon. Alternatively, the material of the third sacrificial layer can be different from that of the second sacrificial layer. For example, the material of the third sacrificial layer is an oxide, while the material of the second sacrificial layer is polycrystalline silicon. This disclosure does not limit the materials of the second and third sacrificial layers.

[0095] In some embodiments, the thickness of the sacrificial layer can be controlled by controlling the deposition process parameters. For example, a third sacrificial layer of a predetermined thickness can be formed by controlling the deposition time and deposition rate; wherein the top surface of the third sacrificial layer of the predetermined thickness is lower than the top surface of the lower electrode. In other embodiments, an initial third sacrificial material layer that completely covers the lower electrode and the intermediate support layer can be deposited, and then the initial third sacrificial material layer can be etched back to form a third sacrificial layer of the predetermined thickness.

[0096] In some embodiments, the implementation of step S2031 may include steps S2311 to S2313, wherein:

[0097] Step S2311: An initial third sacrificial material layer is formed on the intermediate support layer, wherein the top surface of the initial third sacrificial material layer is higher than the top surface of the lower electrode;

[0098] Here, the material of the initial third sacrificial material layer may include one or a combination of silicon oxide, silicon carbide, and silicon oxynitride.

[0099] Step S2312: A portion of the initial third sacrificial material layer is removed using a chemical mechanical polishing process to form an initial third sacrificial layer flush with the top surface of the lower electrode.

[0100] Step S2313: The initial third sacrificial layer is etched using a dry or wet etching process to form a third sacrificial layer that is lower than the top surface of the lower electrode.

[0101] In this embodiment, an initial third sacrificial material layer with a top surface higher than the top surface of the lower electrode is first deposited on the intermediate support layer. Then, a portion of the initial third sacrificial material layer is removed using a chemical mechanical polishing (CMP) process, forming an initial third sacrificial layer flush with the top surface of the lower electrode. This results in an initial third sacrificial layer with a relatively flat top surface. Finally, the initial third sacrificial layer is etched using a dry or wet etching process to form a third sacrificial layer lower than the top surface of the lower electrode. Because the top surface of the initial third sacrificial layer is relatively flat, the top surface of the third sacrificial layer formed after etching is also relatively flat and of good quality, providing an excellent plane for the formation of the top support layer, thereby improving the support effect of the subsequently formed support structure.

[0102] Step S2032: A top support layer is formed on the third sacrificial layer;

[0103] Step S2033: Graphicalize the top support layer, form a first opening in the top support layer, and remove the second and third sacrificial layers through the first opening;

[0104] In some embodiments, the implementation of step S2033 may include steps S2331 and S2332, wherein:

[0105] Step S2331: Etch the top support layer, the middle support layer, the second sacrificial layer and the third sacrificial layer between any two adjacent lower electrodes to form a first opening;

[0106] Step S2332: The second sacrificial layer and the third sacrificial layer are etched through the first opening using a wet etching process.

[0107] It should be noted that since all the sacrificial layers between the bottom and top support layers are connected, the first opening can be formed by dry etching in one step and all the sacrificial layers can be removed by wet etching in one step during the subsequent removal of the sacrificial layers. This simplifies the capacitor formation process.

[0108] In step S2034, a dielectric layer and an upper electrode are sequentially formed on the lower electrode to obtain a capacitor structure.

[0109] refer to Figure 13 An initial third sacrificial material layer 30a is formed on the intermediate support layer 28, wherein the top surface of the initial third sacrificial material layer 30a is higher than the top surface of the lower electrode 26; secondly, simultaneously referencing Figure 13 and Figure 14 A portion of the initial third sacrificial material layer 30a is removed using a chemical mechanical polishing process to form an initial third sacrificial layer 30b flush with the top surface of the lower electrode 26; finally, with reference to... Figure 14 and Figure 15 The initial third sacrificial layer 30b is etched using a dry etching process (such as plasma etching, reactive ion etching, or ion milling) or a wet etching process (such as etching with strong acids such as concentrated sulfuric acid, hydrofluoric acid, or concentrated nitric acid) to form a third sacrificial layer 30 that is lower than the top surface of the lower electrode 26.

[0110] refer to Figure 16 A top support material is deposited on the third sacrificial layer 30 to form a top support layer 31. Here, the top surface of the top support layer 31 can be flush with or higher than the top surface of the lower electrode 26. Between any two adjacent lower electrodes 26, the top support layer 31, the intermediate support layer 28, the second sacrificial layer 27, and the third sacrificial layer 30 are etched to form a structure as follows: Figure 17 The first opening 32 is shown. The second sacrificial layer 27 and the third sacrificial layer 30 are etched through the first opening 32 using a wet etching process (e.g., using strong acids such as concentrated sulfuric acid, hydrofluoric acid, or concentrated nitric acid) to remove all of the second sacrificial layer 27 and the third sacrificial layer 30, forming as shown. Figure 17 The support structure shown includes a top support layer 31, a middle support layer 28, and a bottom support layer 21 remaining after the first opening is etched.

[0111] Continue to refer to Figure 17 After removing the second sacrificial layer 27 and the third sacrificial layer 30, a dielectric layer 33 and an upper electrode 34 are sequentially formed on the top support layer 31 and the middle support layer 28, resulting in the following: Figure 18 The capacitor structure 35 is shown.

[0112] This disclosure also provides a semiconductor structure, including a capacitor structure formed using the formation method described in any of the above embodiments. (Reference) Figure 18 The capacitor structure 35 includes a lower electrode 26, a dielectric layer 33, and an upper electrode 34. Because the capacitor structure is formed using the forming method provided in this embodiment, the capacitor structure has a vertical cross-section and smooth sidewalls, meaning that the capacitor structure has an excellent morphology.

[0113] In the several embodiments provided in this disclosure, it should be understood that the disclosed structures and methods can be implemented in a non-target manner. The structural embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not executed. In addition, the various components shown or discussed are coupled or directly coupled to each other.

[0114] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.

[0115] The features disclosed in the several method or structural embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or structural embodiments.

[0116] The above descriptions are merely some embodiments of this disclosure, but the protection scope of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this disclosure should be included within the protection scope of this disclosure. Therefore, the protection scope of this disclosure should be determined by the scope of the claims.

Claims

1. A method for forming a capacitor structure, characterized in that, The method includes: A first substrate is provided; wherein the first substrate sequentially comprises: a bottom support layer, a first sacrificial layer having a lower electrode penetrating through it, and a mask layer; the surface of the lower electrode is flush with the mask layer and connected to a capacitive contact pad in the bottom support layer; The first sacrificial layer is etched to a predetermined first thickness to form a second sacrificial layer; An intermediate support layer and a top support layer are formed on the second sacrificial layer to form a capacitor structure.

2. The forming method according to claim 1, characterized in that, The provision of the first substrate includes: A second substrate is provided; wherein the second substrate comprises, in sequence: the bottom support layer, the initial first sacrificial layer, and the initial mask layer; The initial mask layer and the initial first sacrificial layer are etched with a first pattern identical to the capacitor hole pattern to form a mask layer and a first sacrificial layer with capacitor holes; The lower electrode is formed after electrode material is deposited in the capacitor hole.

3. The forming method according to claim 2, characterized in that, Using a first pattern identical to the capacitor aperture pattern, the initial mask layer and the initial first sacrificial layer are etched to form a mask layer and a first sacrificial layer with capacitor apertures, including: The initial mask layer is etched with a first pattern identical to the capacitor hole pattern to form a mask layer with the first pattern; The initial first sacrificial layer is etched with the mask layer having the first pattern to form a first sacrificial layer having the capacitor hole.

4. The forming method according to claim 3, characterized in that, The initial mask layer is etched with a first pattern identical to the capacitor hole pattern to form a mask layer having the first pattern, including: A composite mask layer with a second pattern is formed in the initial mask layer; Based on the composite mask layer with the second pattern, the initial mask layer is patterned to form a mask layer with the first pattern.

5. The forming method according to claim 3, characterized in that, The initial first sacrificial layer is etched using the mask layer having the first pattern to form a first sacrificial layer having the capacitor aperture, comprising: A first electrode, flush with the mask layer, is formed in the pores of the first pattern; The initial first sacrificial layer is etched using a metal-assisted chemical etching process to form a first sacrificial layer with the capacitor hole, wherein the first electrode is connected to the capacitor contact pad as the initial first sacrificial layer is consumed to form a second electrode.

6. The forming method according to claim 5, characterized in that, A first electrode, flush with the mask layer, is formed in the pores of the first pattern, comprising: The electrode material is deposited in the pores of the first pattern to form an initial first electrode; The initial first electrode is etched using a dry etching process, a wet etching process, or a chemical mechanical polishing process to form a first electrode flush with the mask layer.

7. The forming method according to claim 6, characterized in that, After forming the second electrode, the lower electrode is formed by depositing electrode material in the capacitor hole, including: The electrode material is deposited in the capacitor hole after the second electrode is formed; Excess electrode material is removed using the dry etching process, wet etching process, or chemical mechanical polishing process to form a lower electrode flush with the mask layer.

8. The forming method according to any one of claims 1 to 7, characterized in that, Etching the first sacrificial layer to a predetermined first thickness to form a second sacrificial layer includes: The mask layer is removed using a dry or wet etching process. The first sacrificial layer is etched using a dry or wet etching process to form a second sacrificial layer with a first preset thickness.

9. The forming method according to claim 8, characterized in that, An intermediate support layer is formed on the second sacrificial layer, comprising: An intermediate support material layer is covered on the second sacrificial layer and the lower electrode; A spin-coated hard mask layer is formed on the intermediate support material layer; Simultaneously, the intermediate support material layer and the spin-coated hard mask layer on the top and sidewalls of the lower electrode are removed to form the intermediate support layer.

10. The forming method according to any one of claims 1 to 7, characterized in that, An intermediate support layer and a top support layer are formed on the second sacrificial layer to form a capacitor structure, including: A third sacrificial layer is formed on the intermediate support layer; wherein the top surface of the third sacrificial layer is lower than the top surface of the lower electrode; The top support layer is formed on the third sacrificial layer; The top support layer is graphically represented, and a first opening is formed in the top support layer, through which the second sacrificial layer and the third sacrificial layer are removed; A dielectric layer and an upper electrode are sequentially formed on the lower electrode to obtain the capacitor structure.

11. The forming method according to claim 10, characterized in that, The second sacrificial layer is made of a different material than the third sacrificial layer; The material of the third sacrificial layer is an oxide.

12. The forming method according to claim 10, characterized in that, A third sacrificial layer is formed on the intermediate support layer, comprising: An initial third sacrificial material layer is formed on the intermediate support layer, wherein the top surface of the initial third sacrificial material layer is higher than the top surface of the lower electrode; A portion of the initial third sacrificial material layer is removed using a chemical mechanical polishing process to form an initial third sacrificial layer flush with the top surface of the lower electrode; The initial third sacrificial layer is etched using a dry or wet etching process to form a third sacrificial layer that is lower than the top surface of the lower electrode.

13. The forming method according to claim 10, characterized in that, The top support layer is graphically represented, and a first opening is formed in the top support layer. The second sacrificial layer and the third sacrificial layer are removed through the first opening, including: The top support layer, the middle support layer, the second sacrificial layer, and the third sacrificial layer are etched between any two adjacent lower electrodes to form the first opening; The second sacrificial layer and the third sacrificial layer are etched through the first opening using a wet etching process.

14. A semiconductor structure, characterized in that, include: A capacitor structure formed using the forming method according to any one of claims 1 to 13.

Images