A SiC Schottky diode with wide process window and a manufacturing method thereof

Abstract

The present application relates to a SiC Schottky diode with wide process window and a manufacturing method thereof, wherein the SiC Schottky diode comprises a first conductive type semiconductor substrate, a first conductive type semiconductor epitaxial layer, a patterned silicon dioxide layer and a first metal layer; a first surface of the first conductive type semiconductor epitaxial layer is provided with a second conductive type main junction, a projection of the patterned silicon dioxide layer on the first conductive type semiconductor substrate is located within a projection of the second conductive type main junction on the first conductive type semiconductor substrate; and a projection of the first metal layer on the first conductive type semiconductor epitaxial layer overlaps with a projection of the patterned silicon dioxide layer on the first conductive type semiconductor epitaxial layer. The present application utilizes an angular dielectric layer structure to realize the lifting of the terminal metal, and can improve the overall reverse withstand voltage and reliability of the device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor power devices, and more specifically to a SiC Schottky diode with a wide process window and its manufacturing method. Background Technology

[0002] Silicon carbide (SiC), a third-generation semiconductor material, has a larger bandgap and a higher critical breakdown field strength than silicon. Compared to silicon power devices of the same voltage rating, SiC has a higher doping concentration and a smaller epitaxial layer thickness, thus significantly reducing forward on-resistance and power loss. Simultaneously, SiC possesses high thermal conductivity, high-temperature resistance, and a high electron saturation velocity, making it suitable for high-current, high-power applications. This reduces the requirements for heat dissipation equipment, shrinks device size, improves reliability, and lowers costs. Therefore, SiC is considered an important development direction for next-generation high-efficiency power electronic devices, with broad application prospects in new energy vehicles, rail transportation, locomotive traction, and smart grids.

[0003] Currently, in the design and fabrication of silicon carbide power devices, to improve the device's breakdown voltage performance, a good termination structure is required, such as a field plate (FP), field limiting ring (FLR), and junction termination extension (JTE). The field limiting ring (FLR) and junction termination extension (JTE) structures are the most widely used in existing SiC power device structures.

[0004] In silicon carbide (SiC) power devices, especially under high voltage conditions, a floating field-limiting ring (FCR) termination structure is commonly used. However, the sharp corners on the outer surface of the FCR (the side furthest from the main junction) are more prone to electric field spikes. Furthermore, due to the inherent characteristics of the material, the thermal growth of thick silicon dioxide films on the SiC surface is limited. Therefore, the passivation layer on the junction termination surface of SiC power devices is typically deposited silicon dioxide, which is of relatively poor quality. Compared to the high critical breakdown electric field of SiC, the passivation layer becomes a vulnerable point for breakdown. Thus, electric field spikes at sharp corners can reduce the breakdown voltage and reliability of SiC power devices. Summary of the Invention

[0005] In view of this, the present invention provides a SiC Schottky diode with a wide process window and a method for manufacturing the same. It adopts a combination of field ring and junction termination extension to give the device a very wide process window. The use of an angled dielectric layer structure to raise the terminal metal can improve the overall reverse breakdown voltage and reliability of the device.

[0006] To achieve the above objectives, the present invention adopts the following technical solution, providing a method for manufacturing a SiC Schottky diode with a wide process window, comprising the following steps:

[0007] Provide a semiconductor substrate of the first conductivity type.

[0008] A first conductivity type semiconductor epitaxial layer is formed on one side of the first conductivity type semiconductor substrate.

[0009] A second conductivity type main junction and a plurality of second conductivity type junction field rings are formed by high-temperature ion implantation on the side of the first conductivity type semiconductor epitaxial layer away from the first conductivity type semiconductor substrate.

[0010] A second conductivity type well region is formed on the first surface by high-temperature ion implantation, and at least a portion of the second conductivity type junction field ring is alternately arranged with the second conductivity type well region.

[0011] A polycrystalline silicon layer is deposited on the surface of the first conductivity type semiconductor substrate on the side away from the first conductivity type semiconductor epitaxial layer.

[0012] An etch barrier layer is deposited on the side of the polysilicon layer away from the first conductivity type semiconductor substrate, and the projection of the etch barrier layer on the first conductivity type semiconductor epitaxial layer overlaps with the second conductivity type main junction portion.

[0013] The exposed polysilicon layer is implanted with oxygen ions and then annealed to form an elevated patterned silicon dioxide layer.

[0014] The etching barrier layer and the masked polysilicon layer are removed sequentially.

[0015] A first metal layer is deposited on the side of the first conductivity type semiconductor epitaxial layer away from the first conductivity type semiconductor substrate, and the projection of the first metal layer on the first conductivity type semiconductor epitaxial layer overlaps with the projection of the patterned silicon dioxide layer on the first conductivity type semiconductor epitaxial layer.

[0016] Meanwhile, the present invention also provides a SiC Schottky diode with a wide process window, comprising: a first conductivity type semiconductor substrate; and a first conductivity type semiconductor epitaxial layer located on one side of the first conductivity type semiconductor substrate.

[0017] The first surface of the first conductivity type semiconductor epitaxial layer is provided with a second conductivity type main junction, wherein the first surface of the first conductivity type semiconductor epitaxial layer is the side surface of the first conductivity type semiconductor epitaxial layer away from the first conductivity type semiconductor substrate.

[0018] A patterned silicon dioxide layer located on the side of the second conductivity type main junction away from the first conductivity type semiconductor substrate, wherein the projection of the patterned silicon dioxide layer on the first conductivity type semiconductor substrate lies within the projection of the second conductivity type main junction on the first conductivity type semiconductor substrate.

[0019] A first metal layer is located on the side of the first conductivity type semiconductor epitaxial layer away from the first conductivity type semiconductor substrate, and the projection of the first metal layer on the first conductivity type semiconductor epitaxial layer overlaps with the projection of the patterned silicon dioxide layer on the first conductivity type semiconductor epitaxial layer.

[0020] Compared with the prior art, the beneficial effects of the present invention are:

[0021] The hybrid JTE scheme employing a field ring and junction termination extension provides the device with a very wide process window. Furthermore, utilizing an angled dielectric layer structure to raise the termination metal improves the overall reverse breakdown voltage of the device. This structure, which raises the termination metal, and the hybrid JTE scheme effectively suppress electric field spikes at the PN junction edge, enhancing overall device reliability and process window while simultaneously reducing the number of photomasks and lowering costs.

[0022] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures pointed out in the description, claims and drawings. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a cross-sectional schematic diagram of a SiC Schottky diode 100 with a wide process window according to the present invention;

[0025] Figure 2 for Figure 1 Enlarged view of region A in the middle;

[0026] Figure 3 This is a cross-sectional schematic diagram of a SiC Schottky diode 200 with a wide process window according to the present invention;

[0027] Figure 4 This is a cross-sectional schematic diagram of a SiC Schottky diode 300 with a wide process window according to the present invention;

[0028] Figure 5 This is a schematic diagram of the process steps for a SiC Schottky diode 400 with a wide process window according to the present invention. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0030] It should be noted that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" or "several" means two or more, unless otherwise explicitly specified.

[0031] The term "and / or" in this invention is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, B existing alone, and A and B existing simultaneously. Clearly, the described embodiments are only some, not all, of the embodiments of this invention.

[0032] As one implementation method, Figure 1 This is a cross-sectional schematic diagram of a SiC Schottky diode 100 with a wide process window according to the present invention. Figure 1 As shown, the present invention provides a SiC Schottky diode with a wide process window, comprising: a first conductivity type semiconductor substrate 101; a first conductivity type semiconductor epitaxial layer 102 located on one side of the first conductivity type semiconductor substrate 101; a second conductivity type main junction 1021 disposed on a first surface FS of the first conductivity type semiconductor epitaxial layer 102, wherein the first surface FS of the first conductivity type semiconductor epitaxial layer 102 is the side surface of the first conductivity type semiconductor epitaxial layer 102 away from the first conductivity type semiconductor substrate 101.

[0033] A patterned silicon dioxide layer 103 is located on the side of the second conductivity type main junction 1021 away from the first conductivity type semiconductor substrate 101. The projection of the patterned silicon dioxide layer 103 on the first conductivity type semiconductor substrate 101 is located within the projection of the second conductivity type main junction 1021 on the first conductivity type semiconductor substrate 101.

[0034] The first metal layer 104 is located on the side of the first conductive type semiconductor epitaxial layer 102 away from the first conductive type semiconductor substrate 101, and the projection of the first metal layer 104 on the first conductive type semiconductor epitaxial layer 102 overlaps with the projection of the patterned silicon dioxide layer 103 on the first conductive type semiconductor epitaxial layer 102.

[0035] Figure 2 for Figure 1 Enlarged diagram of region A in the middle. (See attached image.) Figure 2 As shown, the patterned silicon dioxide layer 103 will generate an angled slope 1031 during the molding process. The first metal layer 104 is manufactured after the patterned silicon dioxide layer 103. Therefore, the slope 1031 causes the vapor-deposited first metal layer 104 to form a metal elevation portion 1041 at the position where it contacts the slope 1031. The elevation of the terminal metal is achieved by using an angled dielectric layer structure, which can improve the overall reverse withstand voltage of the device.

[0036] Figure 3 This is a cross-sectional schematic diagram of a SiC Schottky diode 200 with a wide process window according to the present invention. Figure 3 As shown, the first conductivity type semiconductor epitaxial layer 202 includes a ring-assisted JTE region RA near the second conductivity type main junction 2021 and multiple floating JTE regions MFZ away from the second conductivity type main junction 2021. In the ring-assisted JTE region RA, the first surface FS of the first conductivity type semiconductor epitaxial layer 202 is provided with alternating second conductivity type junction field rings 2022 and second conductivity type well regions 2023. In the multiple floating JTE regions MFZ, the first surface FS of the first conductivity type semiconductor epitaxial layer 202 is provided with multiple second conductivity type well regions 2023 spaced apart. The hybrid JTE scheme using field rings and junction termination extension enables the device to have a very wide process window. The structure of raising the termination metal and the hybrid JTE scheme can improve the overall device reliability and process window while effectively suppressing electric field spikes appearing at the PN junction edge, and can also effectively reduce the number of photomasks and reduce costs.

[0037] The second conductivity type junction field ring 2022 can effectively suppress the electric field spikes of the second conductivity type main junction 2021. As an optional implementation, the number of the second conductivity type junction field ring 2022 is greater than or equal to three. For the sake of convenience in the following description, the embodiments of the present invention are all described with the number of the second conductivity type junction field ring 2022 being three. It can be understood that the number of the second conductivity type junction field ring 2022 can be set according to the specific voltage withstand requirements of the power device, and is not limited here.

[0038] In one implementation, along the first direction, the distance between the second conductivity type main junction 2021 and its adjacent second conductivity type junction field ring 2022 is d0, and the distance between two adjacent second conductivity type junction field rings 2022 gradually increases, but is not less than d0. In an optional implementation, 0.5μm ≤ d0 ≤ 5μm. Within the range allowed by the process, the smaller the value of d0, the higher the breakdown voltage of the device. However, if the value of d0 is too large, the second conductivity type junction field ring 2022 cannot effectively suppress the main junction electric field spike, and the device will be broken down before the edge of the depletion region reaches the next second conductivity type junction field ring 2022. The first direction is parallel to the first conductivity type semiconductor substrate and extends from the second conductivity type main junction to any second conductivity type junction field ring.

[0039] As an optional implementation, along the first direction, the width of each of the second conductivity type junction field rings 2022 can be the same or approximately the same to provide a more uniform peak electric field distribution. In this invention, "approximately the same" means that, within a certain allowable process error range, there are slight differences in the width between each of the second conductivity type junction field rings 2022. The specific difference depends on the precision of the mask and the degree of accurate control of the diffusion process. As a preferred implementation, along the first direction, the width of the second conductivity type junction field ring 2022 can be 3μm-6μm. It is understood that the specific width value of each of the second conductivity type junction field rings 2022 can be set according to the specific voltage withstand requirements of the power device, and is not limited here.

[0040] As an optional implementation, the doping concentration of the second conductive type junction field ring 2022 can be the same or approximately the same to provide a more uniform peak electric field, thereby improving the breakdown voltage of the junction termination structure. In this invention, "approximately the same" means that within a certain allowable process error range, there are slight differences in the doping concentration among the individual second conductive type junction field rings 2022. The specific differences depend on the precision of the mask and the degree of accurate control of the diffusion process. As a preferred implementation, when the number of second conductive type junction field rings 2022 is 3, the doping concentration ratio of each second conductive type junction field ring 2022 is 1:1:1.

[0041] As an optional implementation method, Figure 4 This is a cross-sectional schematic diagram of a SiC Schottky diode 300 with a wide process window according to the present invention. Figure 4As shown, along the first direction, the heights of two adjacent second conductivity type junction field rings 3022 gradually increase. The height of the second conductivity type junction field ring 3022 refers to its dimension h along the direction perpendicular to the first conductivity type semiconductor substrate 301. This incremental arrangement of field rings improves the uniformity of the electric field distribution and is more conducive to increasing the voltage breakdown value. In a preferred embodiment, when the number of second conductivity type junction field rings 3022 is 3, the ratio of h1:h2:h3 is 1:2:3.

[0042] As an optional implementation, the doping concentration of the second conductivity type well region is lower than that of the second conductivity type junction field ring. The second conductivity type well region can further adjust the electric field distribution. Under the same device area, the hybrid structure of junction field ring and well region can share more voltage, and the presence of the second conductivity type well region can, to some extent, eliminate the adverse effects of implanted ion diffusion and improve the overall stability of the device. At the same time, the first JTE structure located in the ring-assisted JTE region RA can improve the breakdown voltage of low doping, and the second JTE structure located in the multi-floating JTE region MFZ can improve the breakdown voltage of high doping. The present invention uses the above two hybrid structures to have a better process window while saving device area, and at the same time improves the breakdown voltage of low and high doping concentrations.

[0043] As an optional implementation method, such as Figure 3 As shown, along the first direction, the width of the second conductivity type well region 2023 located in the multi-floating JTE region MFZ gradually decreases.

[0044] As an optional implementation, the first conductivity type semiconductor is an N-type semiconductor, the second conductivity type semiconductor is a P-type semiconductor, the second conductivity type junction field ring is a P+ junction field ring, and the second conductivity type well region is a P-well. Alternatively, the first conductivity type semiconductor can also be a P-type semiconductor; in this case, the second conductivity type semiconductor should be an N-type semiconductor, and the corresponding device structure will be adjusted accordingly.

[0045] Figure 5 This is a schematic diagram of the process steps for a SiC Schottky diode 400 with a wide process window according to the present invention. Figure 5 As shown, the present invention also provides a method for manufacturing a SiC Schottky diode 400 with a wide process window, comprising the following steps:

[0046] like Figure 5 As shown in (a), a first conductivity type semiconductor substrate 401 is provided; a first conductivity type semiconductor epitaxial layer 402 is epitaxially formed on one side of the first conductivity type semiconductor substrate 401.

[0047] like Figure 5 As shown in (b), a second conductivity type main junction 4021 and a plurality of spaced second conductivity type junction field rings 4022 are formed on the surface FS of the first conductivity type semiconductor epitaxial layer 402 away from the first conductivity type semiconductor substrate 401 by high-temperature ion implantation. The second conductivity type main junction 4021 and the second conductivity type junction field rings 4022 are fabricated by the same process, which can reduce the number of process steps and reduce production costs.

[0048] like Figure 5 As shown in (c), a second conductivity type well region 4023 is formed on the first surface FS by high-temperature ion implantation, and at least a portion of the second conductivity type junction field ring 4022 is alternately disposed with the second conductivity type well region 4023. As an optional embodiment, the ion implantation concentration of the second conductivity type well region 4023 is lower than the ion implantation concentration of the second conductivity type junction field ring 4022 and the second conductivity type main junction 4021.

[0049] like Figure 5 As shown in (d), a polysilicon layer 405 is deposited on the surface of the first conductivity type semiconductor substrate 401 on the side away from the first conductivity type semiconductor epitaxial layer 402.

[0050] like Figure 5 As shown in (e), an etch stop layer 407 is deposited on the surface of the polysilicon layer 405 away from the first conductivity type semiconductor substrate 401. The projection of the etch stop layer 407 onto the first conductivity type semiconductor epitaxial layer 402 overlaps with the second conductivity type main junction portion. As an optional embodiment, the etch stop layer 407 can be made of silicon nitride (SiN). As an optional embodiment, the etch stop layer 407 is deposited using a mask 406.

[0051] like Figure 5 As shown in (f), the exposed polysilicon layer is implanted with oxygen ions and then annealed to form an elevated patterned silicon dioxide layer 403. Alternatively, oxygen can be introduced or oxygen ion implantation can be used to transform unprotected SiN into volume-expanded SiO2.

[0052] like Figure 5 As shown in (g), the etching barrier layer 407 and the partially obscured polysilicon layer are removed sequentially; as an optional implementation, Si and SiO2 can be removed by wet etching with HF of suitable concentration until Si is completely removed.

[0053] like Figure 5As shown in (h), a first metal layer 404 is deposited on the side of the first conductivity type semiconductor epitaxial layer 402 away from the first conductivity type semiconductor substrate 401. The projection of the first metal layer 404 onto the first conductivity type semiconductor epitaxial layer 402 overlaps with the projection of the patterned silicon dioxide layer 403 onto the first conductivity type semiconductor epitaxial layer 402. As an optional implementation, Figure 5 (e) the step of depositing an etch barrier layer on the surface of the polysilicon layer on the side away from the first conductivity type semiconductor substrate, and Figure 5 In step (h), the first metal layer is deposited on the side of the first conductivity type semiconductor epitaxial layer away from the first conductivity type semiconductor substrate, using the same mask 406.

[0054] Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for manufacturing a SiC Schottky diode with a wide process window, characterized in that, Includes the following steps: Provide a semiconductor substrate of the first conductivity type; A first conductivity type semiconductor epitaxial layer is formed on one side of the first conductivity type semiconductor substrate; A second conductivity type main junction and a plurality of second conductivity type junction field rings are formed by high-temperature ion implantation on the side of the first conductivity type semiconductor epitaxial layer away from the first conductivity type semiconductor substrate; A second conductivity type well region is formed on the first surface by high-temperature ion implantation, and at least a portion of the second conductivity type junction field ring is alternately disposed with the second conductivity type well region. The first surface is the side surface of the first conductivity type semiconductor epitaxial layer away from the first conductivity type semiconductor substrate. A polycrystalline silicon layer is deposited on the surface of the first conductivity type semiconductor substrate on the side away from the first conductivity type semiconductor epitaxial layer; An etch barrier layer is deposited on the surface of the polysilicon layer away from the first conductivity type semiconductor substrate, and the projection of the etch barrier layer on the first conductivity type semiconductor epitaxial layer overlaps with the second conductivity type main junction portion; Oxygen ion implantation was performed on the exposed polysilicon layer, followed by annealing to form an elevated patterned silicon dioxide layer. The etching barrier layer and the masked polysilicon layer are removed sequentially; A first metal layer is deposited on the side of the first conductivity type semiconductor epitaxial layer away from the first conductivity type semiconductor substrate, and the projection of the first metal layer on the first conductivity type semiconductor epitaxial layer overlaps with the projection of the patterned silicon dioxide layer on the first conductivity type semiconductor epitaxial layer.

2. The method for manufacturing a SiC Schottky diode with a wide process window as described in claim 1, characterized in that: The steps of depositing an etch barrier layer on the side of the polysilicon layer away from the first conductivity type semiconductor substrate and depositing a first metal layer on the side of the first conductivity type semiconductor epitaxial layer away from the first conductivity type semiconductor substrate share the same mask.

3. The method for manufacturing a SiC Schottky diode with a wide process window as described in claim 1, characterized in that, The step of sequentially removing the etch barrier layer and the masked polysilicon layer is performed using HF acid wet etching.

4. The method for manufacturing a SiC Schottky diode with a wide process window as described in claim 1, characterized in that, The ion implantation concentration in the second conductivity type well region is lower than the ion implantation concentration in the second conductivity type junction field ring and the second conductivity type main junction.

5. A SiC Schottky diode with a wide process window, characterized in that, include: First conductivity type semiconductor substrate; A first conductivity type semiconductor epitaxial layer located on one side of the first conductivity type semiconductor substrate; The first surface of the first conductivity type semiconductor epitaxial layer is provided with a second conductivity type main junction, wherein the first surface of the first conductivity type semiconductor epitaxial layer is the side surface of the first conductivity type semiconductor epitaxial layer away from the first conductivity type semiconductor substrate; A patterned silicon dioxide layer located on the side of the second conductivity type main junction away from the first conductivity type semiconductor substrate, wherein the projection of the patterned silicon dioxide layer on the first conductivity type semiconductor substrate is located within the projection of the second conductivity type main junction on the first conductivity type semiconductor substrate; A first metal layer located on the side of the first conductivity type semiconductor epitaxial layer away from the first conductivity type semiconductor substrate, wherein the projection of the first metal layer on the first conductivity type semiconductor epitaxial layer overlaps with the projection of the patterned silicon dioxide layer on the first conductivity type semiconductor epitaxial layer; The first conductivity type semiconductor epitaxial layer includes a ring-assisted JTE region close to the second conductivity type main junction and multiple floating JTE regions far from the second conductivity type main junction; in the ring-assisted JTE region, the first surface of the first conductivity type semiconductor epitaxial layer is provided with alternating second conductivity type junction field rings and second conductivity type well regions; in the multiple floating JTE regions, the first surface of the first conductivity type semiconductor epitaxial layer is provided with multiple second conductivity type well regions spaced apart.

6. A SiC Schottky diode with a wide process window as described in claim 5, characterized in that: The doping concentration of the well region of the second conductivity type is lower than the doping concentration of the junction field ring of the second conductivity type.

7. A SiC Schottky diode with a wide process window as described in claim 5, characterized in that: In the ring-assisted JTE region, along the first direction, the distance between the second conductivity type main junction and its adjacent second conductivity type junction field ring is d0, the distance between two adjacent second conductivity type junction field rings gradually increases and is not less than d0, the first direction is parallel to the first conductivity type semiconductor substrate and points from the second conductivity type main junction to any second conductivity type junction field ring.

8. A SiC Schottky diode with a wide process window as described in claim 5, characterized in that: In the multi-floating JTE region, along the first direction, the width of the second conductivity type well region gradually decreases, the first direction is parallel to the first conductivity type semiconductor substrate, and points from the second conductivity type main junction to any second conductivity type junction field ring.

9. A SiC Schottky diode with a wide process window as described in claim 5, characterized in that, The first type of semiconductor is an N-type semiconductor, the second type of semiconductor is a P-type semiconductor, the second type of junction field ring is a P+ junction field ring, and the second type of well region is a P-well.

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