A method for remotely updating FPGA firmware using CPU

Abstract

This invention discloses a method for remotely updating FPGA firmware using a CPU, characterized by the following steps: 1) locating the firmware; 2) splitting and transmitting the firmware; and 3) resolving conflicts between the FPGA and CPU reading and writing FLASH simultaneously. This method fully utilizes existing hardware connections, is simple to operate, and is portable.

Description

Technical Field

[0001] The present invention relates to a FLASH updating technology for FPGA firmware, in particular to a method for remotely updating FPGA firmware by using a CPU. Background Art

[0002] Traditional FPGA firmware updates require connecting to a programmer, but the FPGA programming interface is typically located on the motherboard. A single device may contain multiple boards, each housing a CPU, FPGA, and a flash memory chip that stores the FPGA firmware. Once the device is developed, the boards are assembled, a heat sink is added, and then installed in a chassis. To update the FPGA firmware, the chassis and heat sink must be disassembled. Disassembling the chassis and heat sink is time-consuming. A method that allows FPGA firmware updates without disassembling the chassis could significantly reduce this time. Summary of the Invention

[0003] The purpose of the present invention is to address the deficiencies of the prior art and provide a method for remotely updating FPGA firmware using a CPU. This method can fully utilize existing hardware connection methods, is simple to operate, and is portable.

[0004] The technical solution for achieving the purpose of the present invention is:

[0005] A method for remotely updating FPGA firmware using a CPU includes the following steps:

[0006] 1) Positioning: Assume that there are multiple circuit boards in the equipment chassis. Each circuit board has a CPU, FPGA, and a FLASH chip that stores the FPGA firmware. Apply the TCP / IP protocol to the positioning of the circuit board CPU and the FLASH chip. That is, the host computer identifies different circuit boards by their unique IP addresses and then determines the firmware data that needs to be upgraded. This allows the host computer to upgrade the FPGA firmware of multiple boards through a single network management interface. The process is as follows:

[0007] 1-1) The CPU creates a TCP network socket thread and waits for the network connection initiated by the host computer;

[0008] 1-2) The host computer initiates a TCP network connection to the board that needs to upgrade its firmware;

[0009] 1-3) The host computer sends a chip erase data frame to the CPU, and the CPU starts erasing the FLASH chip;

[0010] 1-4) After the CPU waits for the chip data to be erased, it sends an erase chip response frame to the host computer;

[0011] 2) Split the firmware and then transmit it: Split the firmware data into multiple 1024-byte data packets in ascending order of address and encapsulate them according to the data burning frame format. The data frame after packaging is less than 1500 bytes, which is less than the maximum packet length specified by the TCP / IP protocol. The CPU reads the address data from the burning data frame to determine the write location of the firmware data. The CPU obtains the address of the received firmware data from the data burning frame and writes the data into the FLASH chip. When the host computer sends a data readback frame to the CPU, it carries the address information of the readback firmware data and the read byte length. The CPU reads the firmware data from the FLASH according to the address and byte length, encapsulates it into a data readback reply frame, and sends it to the host computer. Splitting the firmware can save CPU memory space and reduce the memory usage of the upgrade module. The process is as follows:

[0012] 2-1) The host computer splits the FPGA firmware into multiple 1024-byte packets in sequence, repackages the split packets according to the programming data, and sends them to the CPU;

[0013] 2-2) The CPU parses the firmware data and the write address of the firmware data from the received firmware data packet, then writes the firmware data into the FLASH and returns a burning data reply frame to the host computer;

[0014] 2-3) After receiving the data burning reply frame, the host computer continues to send the next frame of firmware data, and repeats steps 2-1) and 2-2) until the firmware data burning is completed;

[0015] 2-4) After receiving the last programming data reply frame, the host computer sends a data readback frame to the CPU;

[0016] 2-5) After receiving the data readback frame, the CPU reads the firmware data of the specified byte length from the FLASH chip according to the address specified in the data frame, encapsulates the firmware data into the data readback reply frame, and sends it to the host computer;

[0017] 2-6) After receiving the readback data reply frame, the host computer compares the readback firmware data with the data stored locally on the host computer. If no error is found in the comparison, the host computer continues to send the next data readback frame.

[0018] 2-7) Loop through steps 2-5) and 2-6) until all firmware data in the FLASH chip are compared. If an error occurs during the comparison, the host computer stops sending readback data frames and displays a message indicating that the firmware data burning failed.

[0019] 2-8) If the burning fails, you need to erase the firmware data in the chip again and then start burning again, that is, start from step 1-3);

[0020] 3) Dealing with the conflict between FPGA and CPU reading and writing FLASH at the same time: Install a driver connected to the FLASH chip, and connect the SPI signal lines of the CPU and FPGA to the driver respectively. At any time, the driver only allows one SPI signal line to communicate with the FLASH chip. The driver is controlled by the CPU. When the CPU reads and writes FLASH, the FPGA is prohibited from operating the FLASH chip. The FPGA cannot prohibit the CPU from reading and writing the FLASH chip. The CPU controls the driver. When the CPU's SPI signal line is selected, the driver opens the channel from the CPU's SPI signal line to the FLASH, and the FPGA's SPI signal line will be shielded, thus avoiding signal conflicts.

[0021] The TCP / IP protocol is a connection-oriented, reliable communication protocol. The host computer and the CPU in the chassis establish a TCP / IP connection through Ethernet, ensuring that the host computer can accurately transmit firmware data to the CPU. The FPGA firmware of each circuit board is often different. Each circuit board in the device has a unique IP address, so the host computer can identify different boards by IP address. In this way, the firmware data of each board can be accurately updated through the IP address. The size of a firmware data is about 10M, and the memory space of the CPU is relatively limited. If the host computer transfers the entire firmware to the CPU at one time, then the CPU may not have enough space to store it.

[0022] In this technical solution, the host computer locates the CPU of the board to be upgraded through the IP address, and then establishes a TCP / IP connection with the CPU. The host computer splits the firmware to be upgraded and encapsulates it using a private protocol and transmits it to the CPU. The CPU updates the firmware data on the FLASH chip according to the instructions. After the writing is completed, the host computer sends a firmware data readback command to the CPU. The CPU reads the firmware data in the FLASH according to the protocol and returns it to the host computer. The host computer compares the data and confirms whether the update is successful or failed. In order to implement the firmware update in a limited memory space, in this technical solution, the firmware data is stored in the host computer. The firmware data is split up, then encapsulated according to the private protocol, and finally encapsulated into a TCP / IP data packet. The firmware data is then transmitted to the CPU in multiple times, and then the CPU writes the firmware data into the FLASH in a timely manner. After the writing is completed, the CPU sends a reply frame indicating that the data burning is completed to the host computer. After receiving the reply data frame, the host computer continues to send the next firmware data burning frame. Since the CPU does not get the complete firmware data, the CPU does not know which address of the FLASH the firmware data should be written to, so the host computer should add the firmware write address and the byte length data of the firmware data in the data frame into the burning data frame.

[0023] This method can make full use of existing hardware connection methods, is simple to operate, and is portable. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 Schematic diagram of the circuit principle between CPU, FPGA and FLASH in the embodiment. DETAILED DESCRIPTION

[0025] The present invention will be further described below with reference to the accompanying drawings and embodiments, but the present invention is not limited thereto.

[0026] Example:

[0027] A method for remotely updating FPGA firmware using a CPU includes the following steps:

[0028] 1) Positioning: There are multiple circuit boards in the equipment chassis. Each circuit board has a CPU, FPGA, and a FLASH chip that stores the FPGA firmware. The TCP / IP protocol is applied to the positioning of the circuit board CPU and the FLASH chip. That is, the host computer identifies different circuit boards by their unique IP addresses and then determines the firmware data that needs to be upgraded. This allows the host computer to upgrade the FPGA firmware of multiple boards through a single network management interface. The process is as follows:

[0029] 1-1) The CPU creates a TCP network socket thread and waits for the network connection initiated by the host computer;

[0030] 1-2) The host computer initiates a TCP network connection to the board that needs to upgrade its firmware;

[0031] 1-3) The host computer sends a chip erase data frame to the CPU, and the CPU starts erasing the FLASH chip;

[0032] 1-4) After the CPU waits for the chip data to be erased, it sends an erase chip response frame to the host computer;

[0033] 2) Split the firmware and then transmit it: Split the firmware data into multiple 1024-byte data packets in ascending order of address and encapsulate them according to the data burning frame format. The CPU reads the address data from the data burning frame to determine the write location of the firmware data. The CPU obtains the write address of the received firmware data from the data burning frame and writes the data into the FLASH chip. When the host computer sends a data readback frame to the CPU, it carries the address information of the readback firmware data and the read byte length. The CPU reads the firmware data from the FLASH according to the address and byte length, encapsulates it into a data readback reply frame, and sends it to the host computer. Splitting the firmware can save CPU memory space and reduce the memory usage of the upgrade module. The process is as follows:

[0034] 2-1) The host computer splits the FPGA firmware into multiple 1024-byte packets in sequence, repackages the split packets according to the programming data, and sends them to the CPU;

[0035] 2-2) The CPU parses the firmware data and the write address of the firmware data from the received firmware data packet, then writes the firmware data into the FLASH and returns a burning data reply frame to the host computer;

[0036] 2-3) After receiving the data burning reply frame, the host computer continues to send the next frame of firmware data, and repeats steps 2-1) and 2-2) until the firmware data burning is completed;

[0037] 2-4) After receiving the last programming data reply frame, the host computer sends a data readback frame to the CPU;

[0038] 2-5) After receiving the data readback frame, the CPU reads the firmware data of the specified byte length from the FLASH chip according to the address specified in the data frame, encapsulates the firmware data into the data readback reply frame, and sends it to the host computer;

[0039] 2-6) After receiving the readback data reply frame, the host computer compares the readback firmware data with the data stored locally on the host computer. If no error is found in the comparison, the host computer continues to send the next data readback frame.

[0040] 2-7) Loop through steps 2-5) and 2-6) until all firmware data in the FLASH chip are compared. If an error occurs during the comparison, the host computer stops sending readback data frames and displays a message indicating that the firmware data burning failed.

[0041] 2-8) If the burning fails, you need to erase the firmware data in the chip again and then start burning again, that is, start from step 1-3);

[0042] 3) Dealing with conflicts when the FPGA and CPU read and write FLASH at the same time: Install a driver connected to the FLASH chip. The SPI signal lines of the CPU and FPGA are connected to the driver respectively. At any time, the driver only allows one SPI signal line to communicate with the FLASH chip. The driver is controlled by the CPU. When the CPU reads and writes FLASH, the FPGA is prohibited from operating the FLASH chip. The FPGA cannot prohibit the CPU from reading and writing the FLASH chip. The CPU controls the driver. When the CPU's SPI signal line is selected, the driver opens the channel from the CPU's SPI signal line to the FLASH. The FPGA's SPI signal line will be shielded, thus avoiding signal conflicts.

[0043] The specific process of this example is:

[0044] 1) The host computer sends a chip erase frame to the CPU. The frame format of the chip erase frame is shown in Table 1:

[0045] Table 1

[0046] ;

[0047] 2) After receiving the chip erase frame, the CPU starts to erase the FLASH chip. After the FLASH chip is erased, it sends a chip erase response frame to the host computer software. The frame format of the response frame is shown in Table 2:

[0048] Table 2

[0049] ;

[0050] 3) After receiving the erase response frame, the host computer starts to split the firmware data and then load it into the data burning frame. The burning frame format is shown in Table 3:

[0051] Table 3

[0052] ;

[0053] 4) After receiving the burning frame, the CPU starts to write the firmware data into the FLASH. After the burning is completed, the CPU sends a burning response frame to the host computer. The response frame format is shown in Table 4:

[0054] Table 4

[0055] ;

[0056] 5) After receiving the burning response frame, the host computer continues to send the next frame of data burning frame. After the CPU burning is completed, it also sends a data burning response frame to the host computer. That is, steps 3) and 4) are repeated until the firmware data burning is completed;

[0057] 6) The host computer sends a data readback frame to the CPU, reading 1024 bytes of firmware data each time. The readback frame format is shown in Table 5:

[0058] Table 5

[0059] ;

[0060] 7) After receiving the data readback frame, the CPU reads the firmware data from the FLASH according to the requirements of the data readback frame, encapsulates the firmware data into the data readback response frame, and sends it to the host computer. The response frame format is shown in Table 6: Table 6

[0061] ;

[0062] 8) After receiving the readback data response frame, the host computer software compares the readback firmware data with the locally saved firmware data. If the data are the same, it indicates that there is no problem with the firmware data burning. The host computer continues to send the next frame of data readback frame to read the new firmware data, that is, looping through steps 6) and 7) until all firmware data is verified.

[0063] like Figure 1 As shown in the figure, in this example, the CPU is connected to the FLASH via the SPI bus, and after the FPGA is powered on, it also reads the firmware from the FLASH via the SPI protocol. If the SPI buses of the CPU and FPGA are connected to the FLASH at the same time, read and write conflicts may occur. To prevent the FPGA and CPU from reading the FLASH at the same time and causing signal conflicts, the SPI buses of the CPU and FPGA are both connected to the driver. When the en1 signal line is high and the en2 signal line is low, only the CPU's SPI bus signal can pass through the driver to read and write with the FLASH. When en1 is low and en2 is high, only the FPGA's SPI bus signal can pass through the driver to read and write with the FLASH. The driver selects one SPI signal to transmit to the FLASH, avoiding read and write conflicts by controlling the driver.

Claims

1. A method for remotely updating FPGA firmware using a CPU, characterized in that: The steps include: 1) Positioning: There are multiple circuit boards in the device chassis. Each circuit board has a CPU, FPGA, and a FLASH chip that stores the FPGA firmware. The TCP / IP protocol is applied to the positioning of the circuit board CPU and the FLASH chip. That is, the host computer identifies different circuit boards by their unique IP addresses and then determines the firmware data that needs to be upgraded for each circuit board. The process is as follows: 1-1) The CPU creates a TCP network socket thread and waits for the network connection initiated by the host computer; 1-2) The host computer initiates a TCP network connection to the board that needs to upgrade its firmware; 1-3) The host computer sends a chip erase data frame to the CPU, and the CPU starts erasing the FLASH chip; 1-4) After the CPU waits for the chip data to be erased, it sends an erase chip response frame to the host computer; 2) Split the firmware and then transmit it: Split the firmware data into multiple 1024-byte data packets in ascending address order and encapsulate them according to the data burning frame format. The CPU reads the address data from the burning data frame to determine the write location of the firmware data. The CPU obtains the address of the received firmware data from the data burning frame and writes the data into the FLASH chip. When the host computer sends a data readback frame to the CPU, it carries the address information of the readback firmware data and the read byte length. The CPU reads the firmware data from the FLASH according to the address and byte length, encapsulates it into a data readback reply frame, and sends it to the host computer. The process is as follows: 2-1) The host computer splits the FPGA firmware into multiple 1024-byte packets in sequence, repackages the split packets according to the programming data, and sends them to the CPU; 2-2) The CPU parses the firmware data and the write address of the firmware data from the received firmware data packet, then writes the firmware data into the FLASH and returns a burning data reply frame to the host computer; 2-3) After receiving the data burning reply frame, the host computer continues to send the next frame of firmware data, and repeats steps 2-1) and 2-2) until the firmware data burning is completed; 2-4) After receiving the last programming data reply frame, the host computer sends a data readback frame to the CPU; 2-5) After receiving the data readback frame, the CPU reads the firmware data of the specified byte length from the FLASH chip according to the address specified in the data frame, encapsulates the firmware data into the data readback reply frame, and sends it to the host computer; 2-6) After receiving the readback data reply frame, the host computer compares the readback firmware data with the data stored locally on the host computer. If no error is found in the comparison, the host computer continues to send the next data readback frame. 2-7) Loop through steps 2-5) and 2-6) until all firmware data in the FLASH chip are compared. If an error occurs during the comparison, the host computer stops sending readback data frames and displays a message indicating that the firmware data burning failed. 2-8) If the burning fails, you need to erase the firmware data in the chip again and then start burning again, that is, start from step 1-3); 3) Dealing with conflicts when the FPGA and CPU read and write FLASH at the same time: Install a driver connected to the FLASH chip. The SPI signal lines of the CPU and FPGA are connected to the driver respectively. At any time, the driver only allows one SPI signal line to communicate with the FLASH chip. The driver is controlled by the CPU. When the CPU reads and writes FLASH, the FPGA is prohibited from operating the FLASH chip. The FPGA cannot prohibit the CPU from reading and writing the FLASH chip. The CPU controls the driver. When the CPU's SPI signal line is selected, the driver opens the channel from the CPU's SPI signal line to the FLASH, and the FPGA's SPI signal line will be blocked.

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