Processor run-time clock cycle control error detection method and system

Abstract

The present application provides a processor error detection method and system for controlling the running clock cycle, and the time of a program segment running on a sequential processor core is linearly related to the number of instructions in the program segment. Therefore, the present application can classify the instructions in the program segment, and count the time required for the inspection core to run each type of instruction. During the running of the main core, the running time of the program segment on the inspection core is predicted according to the type and number of instructions, and when the predicted time is greater than a set value, the program segment is divided as a checkpoint, and the time for the inspection core to check the program segment is controlled, thereby reducing the delay of error detection.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of microprocessor reliability design, suspending the release of physical registers during the process of copying registers, and dividing the program segment by predicting the required runtime clock cycle, reducing the impact of heterogeneous parallel error detection on the performance of the main core and reducing the delay of error detection. BACKGROUND

[0002] Since the revolution of automotive semiconductor and vehicle information industry, the number of electronic control units (ECU) on each car has been increasing, and the requirement for automotive electronic reliability has also been increasing. However, automotive chips are faced with severe working environments such as high temperature and high humidity, which makes vehicle processors produce errors more frequently compared to general electronic systems, making the reliability of automotive chips face severe tests. Dual-core lockstep runs the same program on two processor cores and compares the outputs of the two cores to detect errors, which has a multiple area and power consumption overhead. Due to its high error detection speed and error coverage, it can meet the requirements of automotive chip reliability. Heterogeneous parallel error detection detects errors by using a series of low-performance check cores to run the program segment of the high-performance main core in parallel. In order to improve performance, the area and power consumption of the chip grow superlinearly, and the sum of the area and power consumption of these low-performance cores is less than that of the high-performance core, which can achieve similar error coverage to dual-core lockstep with lower power consumption and area overhead.

[0003] Each time the register state is copied, the submission of instructions needs to be suspended, which affects the performance of the main core. Heterogeneous parallel error detection requires the program of the high-performance main core to be divided into multiple program segments and assigned to check cores for repeated execution for error detection. Therefore, the current state of the main core needs to be copied to the check core at the beginning and end of each program segment, so that the check core can start running with the same state and compare the register states after running to achieve error detection. When copying the register stack state, due to the area and power consumption overhead, too many read ports cannot be set, so the main core needs to be suspended for multiple cycles to fill the register stack with the check core. The suspension of the submission of instructions by the main core affects its performance. The granularity of program segment division determines the frequency of main core suspension. In order to reduce the impact on the main core, a larger program segment is usually set to reduce the frequency of main core suspension, thereby reducing the impact of error detection on the performance of the main core. At the same time, for some errors, the check core needs to execute the program segment and compare the register states to detect them. Due to the low performance of the check core, a larger program segment requires a longer running time, which will bring a larger error detection delay.

[0004] The implementation of heterogeneous parallel error detection also requires consideration of how to divide program segments to set appropriate checkpoints. To enable the checking core to repeatedly run program segments, the main core saves the data and addresses of load / store instructions to a log. For load instructions, the checking core directly obtains data from the log as input; for store instructions, it compares the data in the log with the addresses for error detection. Whenever the current checking core's log is full or the main core submits enough instructions, the current state needs to be used as a checkpoint to divide the program segments. Because the frequency of load / store operations within a program segment varies, the number of instructions in each program segment when the log is full differs, and the execution time of each instruction within a program segment also varies. For example, multiplication and division instructions require more execution cycles than ordinary addition instructions, and floating-point arithmetic instructions require even more. Therefore, different program segments will require different execution times due to differences in the number and types of instructions. Because the performance of the checker core is much lower than that of the main core, for some errors, the checker core needs to run the entire program segment and then compare the register states at the end of the program segment before they can be detected. This results in excessive delays in error detection, which cannot meet the real-time requirements of critical systems. Summary of the Invention

[0005] To reduce the impact of heterogeneous parallel error detection on the performance of high-performance main cores and reduce error detection latency, this invention proposes a method to pause physical register release during register copying, storing the checkpoint state in the physical register file. This eliminates the need for the main core to pause commit instructions, allowing for smaller program segments. Furthermore, program segments can be divided based on the predicted program segment execution time, making error detection latency controllable.

[0006] To address the shortcomings of existing technologies, this invention proposes a processor runtime error detection method that controls the runtime clock cycle, including:

[0007] Step 1: Obtain a processing system with a main core and a check core, wherein the main core and the check core have the same instruction set architecture;

[0008] Step 2: When the main core is running the program to be executed, the program segment is predicted in the clock cycle of the check core according to the type and number of instructions submitted by the main core. If the clock cycle is greater than the threshold, the current state of the main core is used as the check point to divide the program segment.

[0009] Step 3, copying the state of the main core when the program segment starts to run to the checking core, so that the checking core starts to run in the same state as the main core, and in the process of running the program segment by the checking core, for the load instruction, directly accessing the load storage log to obtain the load data as the load result, and judging whether the address of the load result is the same as the load address in the load storage log, if not, it indicates that an error occurs; when the checking core ends running the program segment, judging whether the state of the checking core when ending running the program segment is the same as the state of the main core when ending running the program segment, if not, it indicates that an error occurs.

[0010] The processor running error detection method for controlling the running clock period, wherein step 2 further comprises:

[0011] Whenever a load instruction is submitted, the load address and load data corresponding to the load instruction are saved into the load storage log corresponding to the current checking core, and when the load storage log is full, the current state of the main core is taken as a checkpoint to divide the program segment.

[0012] The processor running error detection method for controlling the running clock period, wherein the renaming component of the main core comprises: a current state table, a checkpoint state table and a suspension queue.

[0013] The current state table is used to record the physical register corresponding to the current logical register, the checkpoint state table is used to save the correspondence between each logical register and physical register of the checkpoint, and the suspension queue is used to suspend releasing each physical register in the checkpoint state during the process of copying the state of the main core to the checking core, and save it in the suspension queue until the copying ends and then release.

[0014] The application further provides a processor running error detection system for controlling the running clock period, which comprises:

[0015] An initial module is used to obtain a processing system with a main core and a checking core, and the main core and the checking core have the same instruction set architecture.

[0016] A prediction module is used to predict the running clock period of the program segment in the checking core according to the type and quantity of instructions submitted by the main core when the main core runs the program to be executed, and when the running clock period is greater than a threshold, the current state of the main core is taken as a checkpoint to divide the program segment.

[0017] The detection module is used for copying the state of the main core when the program segment starts to run to the checking core, so that the checking core starts to run in the same state as the main core, and in the process of running the program segment by the checking core, for a load instruction, the load storage log is directly accessed to obtain the load data as a load result, and it is judged whether the address of the load result is the same as the load address in the load storage log, and if not, it indicates that an error occurs; when the checking core ends running the program segment, it is judged whether the state of the checking core when the program segment ends running is the same as the state of the main core when the program segment ends running, and if not, it indicates that an error occurs.

[0018] The processor running error detection system for controlling the running clock cycle, wherein the prediction module is further used for:

[0019] Whenever a load instruction is submitted, the load address and load data corresponding to the load instruction are saved into the load storage log corresponding to the current checking core, and when the load storage log is full, the current state of the main core is taken as a checkpoint to divide the program segment.

[0020] The processor running error detection method for controlling the running clock cycle, wherein the renaming component of the main core comprises: a current state table, a checkpoint state table and a suspension queue.

[0021] The current state table is used for recording the physical register corresponding to the current logical register; the checkpoint state table is used for saving the corresponding relationship between each logical register and physical register of the checkpoint; and the suspension queue is used for suspending the release of each physical register in the checkpoint state during the process of copying the state of the main core to the checking core, and saving the physical register in the suspension queue until the copying is completed and then the release is performed.

[0022] The application further provides a storage medium for storing a program for executing the processor running error detection method for controlling the running clock cycle.

[0023] The application further provides a data processing device comprising a storage medium, and when a processor of the data processing device calls and executes computer executable instructions in the computer readable storage medium, the data processing device performs the processor running error detection for controlling the running clock cycle.

[0024] The application further provides a client for the processor running error detection system for controlling the running clock cycle.

[0025] From the above scheme, it can be known that the application has the following advantages:

[0026] The application suspends the release of the physical register when copying the register, saves the checkpoint state in the physical register stack, so that the main core does not need to suspend the commit instruction, and the influence of the copied register on the high-performance main core is reduced. Therefore, a smaller granularity program segment can be divided, so as to reduce the error detection delay.

[0027] The application classifies the instructions, counts the execution time of each type of instruction, predicts the running time of the program segment in the checking core according to the type and quantity of the instructions, and divides the program segment according to the set time, so as to reduce the maximum error detection delay and guarantee the real-time performance of the system. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 It is a whole structure diagram of the application;

[0029] Figure 2 It is a matching process diagram of the throughput of the checking core and the main core;

[0030] Figure 3 It is a running time prediction diagram of the program segment in the checking core;

[0031] Figure 4 It is a current state table and checkpoint state diagram;

[0032] Figure 5 It is a process diagram of suspending the release of the physical register in the process of copying the register;

[0033] Figure 6 It is a data processing device diagram of the application. DETAILED DESCRIPTION

[0034] The out-of-order processor uses the register renaming technology to point the logical register to each physical register. For each instruction, the renaming component allocates a new physical register for its destination register to save the result of its operation, and the instructions dependent on the instruction directly obtain data from the physical register, which is distinguished from other instructions with the same logical register, so as to eliminate the register read-after-write correlation (WAR) and write-after-write correlation (WAW) between instructions, and improve the parallelism of instruction running. When an instruction is submitted, its destination logical register points to the new physical register allocated to it to represent the current state, and the original physical register can be released and allocated to other instructions, and the physical register can be modified only after the allocated instruction is written back. Therefore, when copying the register, the release of the physical register corresponding to the checkpoint state is suspended, so that the value of the physical register is prevented from being overwritten by the following instructions, and the checkpoint state is saved in the physical register stack without suspending the commit instruction.

[0035] In the research process, it is found that the time of a program segment running in a sequential processor core has a certain linear relationship with the number of various instructions in the program segment. Therefore, the present application can classify the instructions in the program segment and count the time required for each type of instruction to run in the check core. During the running of the main core, the running time of the program segment in the check core is predicted according to the type and number of instructions, and when the predicted time is greater than a set value, the program segment is divided as a checkpoint, and the time for the check core to check the program segment is controlled, thereby reducing the delay of error detection. In order to achieve the above technical effects, the present application includes the following key technical points:

[0036] Key point 1: The present application proposes a method of suspending the release of physical registers when copying registers, which completely saves the state of checkpoint registers in the physical register stack, so that there is no need to suspend the commit instruction in the copying of physical registers, thereby reducing the impact of heterogeneous parallel error detection on the performance of the main core, allowing a smaller program segment to be set and reducing the error detection delay.

[0037] Key point 2: The present application proposes a method of dividing the program segment according to the predicted running time, so that the running time of each program segment in the check core is relatively uniform, so that the maximum error detection delay is controllable to meet the real-time requirements of critical systems.

[0038] In order to make the above features and effects of the present application more clear and easy to understand, the following embodiments are described in detail below, together with the accompanying drawings.

[0039] The overall structure of the low-performance overhead heterogeneous parallel error detection proposed in this paper is shown in Figure 1 The main components include a high-performance out-of-order main core, multiple low-performance sequential check cores, a load forwarding unit, and a load-store log. In the renaming unit of the out-of-order main core, a current state table, a checkpoint state table, and a suspension queue are added.

[0040] The main core and the check core have the same instruction set architecture. The main core runs a normal program and divides the program into multiple program segments, which are handed over to the check core for repeated running and error detection. Each check core has its own L0 instruction cache and shares the L1 instruction cache with other check cores. The L1 instruction cache is connected to the L2 cache of the main core to obtain the required instructions from the L2 cache of the main core.

[0041] The load forwarding unit is used to copy the data taken by the load instruction, and when the load instruction is submitted, it is compared with the data in the load store queue to prevent the transmission of the load instruction error to the checking core. Specifically, for a load instruction, normally, the load instruction obtains the corresponding data from the data cache during execution and saves it in the load queue. The application saves the data from the data cache in the load forwarding unit at the same time. When the instruction is submitted, we need to take the data of the instruction in the load queue and compare it with the data in the load forwarding unit. When the two data are the same, save it in the load store log. Thus, the correctness of the data loaded in the load store log is ensured. Therefore, the load forwarding unit first saves the data obtained by the instruction from the cache, and when the instruction is submitted, the sequence number of the corresponding instruction is obtained, the saved data of the corresponding instruction is obtained according to the sequence number, and the data is compared with the data in the load queue, thereby ensuring the correctness of the data loaded in the load store log.

[0042] For the load instruction, after it is emitted, the load execution unit sends a read request to the data cache, and the data cache returns the data of the corresponding address to the processor and saves it in the load store queue. For the store instruction, when the data to be stored is ready, the store instruction is emitted. When the instruction is emitted, the data to be stored is saved in the load store queue.

[0043] The load store log is used to save the addresses and data corresponding to the load and store instructions submitted by the main core. Each checking core has its own partition and can be accessed in parallel. The checking core directly accesses the load store log during operation, compares the data and addresses to achieve error detection.

[0044] The current state table added in the main core renaming component is used to record the physical registers corresponding to the current logical registers. The checkpoint state table is used to save the physical registers corresponding to the logical registers in the checkpoint state. The pause queue is used to pause the release of each physical register in the checkpoint state during the process of copying the registers, and save the paused registers in the pause queue. After the copying of the registers is completed, the registers are released to be used by other instructions.

[0045] The main core runs the normal program and divides the program into multiple program segments to be run by each checking core repeatedly to achieve error detection. Since the performance of the checking core is low, multiple checking cores run in parallel, so the throughput of multiple checking cores can match the main core. The running process is as follows Figure 2The program segment is divided into a plurality of program segments. Each program segment is allocated a check core. At the beginning of the program segment, the current state is copied to the check core so that the check core can start running with the same state. At the end of the program segment, the current state is also assigned to the check core for the check core to check the state after the program segment runs. The current check core starts running, and a new check core is allocated for a new program segment.

[0046] When the main core runs, whenever a load or store instruction is submitted, the address and data of the load or store need to be saved to the load and store log partition corresponding to the current check core. If the current load and store log partition is full, the current state is taken as a checkpoint to divide the program segment. At the same time, the running clock cycle of the program segment is predicted according to the type and number of submitted instructions. When the running clock cycle is greater than a set value, the current state is taken as a checkpoint to divide the program segment.

[0047] Next, the process of dividing the program segment by predicting the running time of the program segment is described with examples.

[0048] We analyze the program segment, divide the instructions according to the required running clock cycle, and divide the instructions into fixed-point multiplication instructions, fixed-point division instructions, branch instructions, jump instructions, floating-point division square root instructions, floating-point addition multiplication instructions, floating-point miscellaneous instructions, and other instructions. Other instructions include arithmetic logic instructions, load instructions, and store instructions. The addition and subtraction, logic instructions only need one cycle. Since the load and store instructions directly obtain data from the load and store log and do not have a delay, they are divided together. Then, each instruction is taken as a program segment division to obtain the number and running clock cycle of various instructions in different program segments, obtain the time required for each instruction to run, and the predicted cycle number of each instruction is an integer.

[0049] For the load instruction in the check core, we need to make it have the same loaded data compared to the load instruction in the main core, so that the check core and the main core can run the same program segment. Therefore, directly obtaining data from the load and store log compared to making the check core directly obtain data from the cache has less impact on the performance of the main core. At the same time, this can also speed up the running speed of the program segment of the check core.

[0050] According to the time required by each instruction, the running time of the program segment in the check core is predicted as follows: Figure 3The running of the checking core for each program segment is divided into three stages: 1) at the beginning of the program segment, the program counter, general registers, state registers and other states of the main core are copied to the checking core, so that the checking core can start running in the same state as the main core; 2) in the process of running of the checking core, for a load instruction, the required data is obtained by directly accessing the load storage log, and the address is compared, and if they are different, an error is generated. For a store instruction, the data and address in the load storage log are compared, and if they are different, an error is generated; 3) when the program segment ends, the state of the checking core is compared with the state of the copied tail of the program segment, and if they are different, an error is generated.

[0051] The running of the checking core for each program segment is divided into three stages: 1) at the beginning of the program segment, the program counter, general registers, state registers and other states of the main core are copied to the checking core, so that the checking core can start running in the same state as the main core; 2) in the process of running of the checking core, for a load instruction, the required data is obtained by directly accessing the load storage log, and the address is compared, and if they are different, an error is generated. For a store instruction, the data and address in the load storage log are compared, and if they are different, an error is generated; 3) when the program segment ends, the state of the checking core is compared with the state of the copied tail of the program segment, and if they are different, an error is generated.

[0052] Next, the process of copying registers according to the present application is described with examples.

[0053] The present application adds a current state table and a checkpoint state table in the renaming component of the out-of-order main core, and the organization forms are as shown in Figure 4 The number of registers in the current state table is equal to the number of logical registers, and each register records the physical register corresponding to the logical register in the current state of the main core. The number of registers in the checkpoint state table is equal to the number of logical registers, and each register records the physical register corresponding to the logical register in the current state of the main core. When an instruction is submitted, the register in the target logical register of the current state table is modified to be the submitted physical register. When a checkpoint is encountered, the current state table is copied to the checkpoint state table.

[0054] In the process of copying registers, the checkpoint state table is queried to obtain the physical register corresponding to the checkpoint state logical register, and the corresponding physical register value in the register file is read to copy the register state of the checkpoint to the checking core. At the same time, the main core does not need to pause the submission of instructions, and when an instruction is submitted, the physical target register in the table is queried according to the logical target register of the instruction, and if they are equal, the release of the instruction is paused and the instruction is put into the pause queue to prevent it from being used by other instructions, so as to ensure that the checkpoint state is not overwritten. After the copying of registers is completed, the registers in the pause queue are released to the idle list for renaming. Since the submission of instructions does not need to be paused during the copying of registers, the present application can reduce the impact of the copying of registers on the performance of the main core, thereby allowing a smaller program segment to be set and reducing the delay of error detection.

[0055] Figure 5 An example process of releasing physical registers when copying registers is given. When the logical register L5 is released for the first time, the corresponding physical register P36 is released. According to the logical address lookup, the corresponding physical register of the checkpoint state logical register is found to be equal, and the release of the physical register is suspended. When L5 is released again, since a new physical register (P62) is allocated for it, the lookup finds that the physical register is not equal to the checkpoint state, and the physical register can be released. After the copying of the registers is completed, the physical registers in the suspension queue are released to the idle list for the next renaming.

[0056] When an error is detected, the checkpoint technology can be used to restore the state of the main core to the previous checkpoint state. The main core can also be restarted to run the program again. An interrupt handler can also be used to handle the error.

[0057] The application also provides a processor running error detection system for controlling the running clock period, comprising:

[0058] An initial module is configured to obtain a processing system having a main core and a checking core, and the main core and the checking core have the same instruction set architecture.

[0059] A prediction module is configured to predict the running clock period of a program segment in the checking core according to the type and number of instructions submitted by the main core when the main core runs the program to be executed, and divide the program segment by the checkpoint when the running clock period is greater than a threshold value.

[0060] A detection module is configured to copy the state of the main core when the program segment starts running to the checking core, so that the checking core starts running in the same state as the main core, and in the process of running the program segment in the checking core, for a load instruction, directly access the load storage log to obtain the load data as the load result, and judge whether the address of the load result is the same as the load address in the load storage log, if not, it indicates that an error occurs; when the checking core ends running the program segment, judge whether the state of the checking core when the program segment ends running is the same as the state of the main core when the program segment ends running, if not, it indicates that an error occurs.

[0061] The processor running error detection system for controlling the running clock period, wherein the prediction module is further configured to:

[0062] Whenever a load instruction is submitted, save the load address and load data corresponding to the load instruction in the load storage log corresponding to the current checking core, and when the load storage log is full, divide the program segment by the checkpoint with the current state of the main core.

[0063] The processor running error detection method for controlling the running clock cycle, wherein the renaming component of the main core comprises: a current state table, a checkpoint state table, and a suspension queue.

[0064] The current state table is used to record the physical register corresponding to the current logical register; the checkpoint state table is used to save the correspondence between the checkpointed logical register and the physical register; and the suspension queue is used to suspend the release of the physical register in the checkpointed state during the process of copying the state of the main core to the checking core, and save the physical register in the suspension queue until the copying is completed.

[0065] The application further provides a storage medium for storing a program for executing any of the processor running error detection methods for controlling the running clock cycle.

[0066] As shown in Figure 6 The application further provides a data processing apparatus comprising a storage medium, which executes the processor running error detection for controlling the running clock cycle when the processor of the data processing apparatus invokes and executes the computer executable instructions in the computer readable storage medium.

[0067] The computer readable storage medium of the application stores computer executable instructions, which, when executed by the processor of the data processing apparatus, implement the above-mentioned heterogeneous parallel error detection method for sharing the control flow information of the main core. Those skilled in the art can understand that all or part of the steps in the above-mentioned method can be instructed by a program to complete the relevant hardware (such as a processor, an FPGA, an ASIC, etc.), and the program can be stored in a readable storage medium, such as a read-only memory, a magnetic disk or an optical disk, etc. All or part of the steps of the above-mentioned embodiments can also be implemented by using one or more integrated circuits. Accordingly, each module in the above-mentioned embodiments can be implemented in the form of hardware, such as by an integrated circuit to implement its corresponding function, or in the form of a software function module, such as by a processor executing a program / instruction stored in a memory to implement its corresponding function. The embodiments of the application are not limited to any specific form of combination of hardware and software.

[0068] The application further provides a client for any of the processor running error detection systems for controlling the running clock cycle.

[0069] The following is a system embodiment corresponding to the above-mentioned method embodiment, and the present embodiment can be implemented in cooperation with the above-mentioned embodiments. The related technical details mentioned in the above-mentioned embodiments are still valid in the present embodiment, and in order to reduce repetition, they will not be described here again. Accordingly, the related technical details mentioned in the present embodiment can also be applied in the above-mentioned embodiments.

[0070] In summary, the application proposes a method for suspending the release of physical registers during the process of copying registers, so that the main core does not need to suspend the submission of instructions, reduces the influence of copying registers on the performance of the main core, and can allow smaller division of program segments, thereby reducing the delay of error detection. At the same time, the program segments are divided according to the predicted running clock cycles, so that the maximum error detection delay is controllable to meet the real-time requirements of critical systems.

Claims

1. A method for detecting processor runtime errors by controlling the clock cycle, characterized in that, The method comprises the following steps: Step 1, obtaining a processing system with a main core and a check core, and the main core and the check core have the same instruction set architecture; Step 2, when the main core runs a program to be executed, the running clock period of a program segment in the check core is predicted according to the type and quantity of instructions submitted by the main core, and when the running clock period is greater than a threshold value, the current state of the main core is taken as a checkpoint to divide the program segment; Step 3, the state of the main core when the program segment starts to run is copied to the check core, so that the check core starts to run in the same state as the main core, and in the process of running the program segment in the check core, for a load instruction, a load storage log is directly accessed to obtain load data as a load result, and it is judged whether the address of the load result is the same as the load address in the load storage log, if not, an error is generated; when the check core ends running the program segment, it is judged whether the state of the check core when the program segment ends to run is the same as the state of the main core when the program segment ends to run, if not, an error is generated.

2. The method of claim 1, wherein the number of clock cycles is determined by the number of instructions executed by the processor. The step 2 further comprises: Whenever a load instruction is submitted, the load address and load data corresponding to the load instruction are saved into the load storage log corresponding to the current check core, and when the load storage log is full, the current state of the main core is taken as a checkpoint to divide the program segment.

3. The method of claim 1, wherein the number of clock cycles is determined by the number of instructions executed by the processor. The renaming component of the main core comprises a current state table, a checkpoint state table and a pause queue; The current state table is used to record the physical register corresponding to the current logical register; the checkpoint state table is used to save the correspondence between each logical register and physical register of the checkpoint; and the pause queue is used to pause releasing each physical register in the checkpoint state during the process of copying the state of the main core to the check core, and save the physical register in the pause queue until the copying is completed.

4. A processor run-time clock cycle control error detection system, comprising: The method comprises the following steps: An initial module is used to obtain a processing system with a main core and a check core, and the main core and the check core have the same instruction set architecture; A prediction module is used to, when the main core runs a program to be executed, predict the running clock period of a program segment in the check core according to the type and quantity of instructions submitted by the main core, and when the running clock period is greater than a threshold value, take the current state of the main core as a checkpoint to divide the program segment; A detection module is used to copy the state of the main core when the program segment starts to run to the check core, so that the check core starts to run in the same state as the main core, and in the process of running the program segment in the check core, for a load instruction, a load storage log is directly accessed to obtain load data as a load result, and it is judged whether the address of the load result is the same as the load address in the load storage log, if not, an error is generated; when the check core ends running the program segment, it is judged whether the state of the check core when the program segment ends to run is the same as the state of the main core when the program segment ends to run, if not, an error is generated.

5. The processor run error detection system that controls a run clock cycle according to claim 4, wherein, The prediction module is further used to Whenever a load instruction is submitted, the load address and load data corresponding to the load instruction are saved into a load-store log corresponding to the checking core, and when the load-store log is full, the current state of the main core is taken as a checkpoint to divide a program segment.

6. The processor run error detection system that controls a run clock cycle according to claim 4, wherein, The renaming component of the main core comprises a current state table, a checkpoint state table, and a suspension queue. The current state table is used to record the physical registers corresponding to the current logical registers; the checkpoint state table is used to save the correspondence between the logical registers and the physical registers in the checkpoint; and the suspension queue is used to suspend the release of the physical registers in the checkpoint state during the process of copying the state of the main core to the checking core, and save them in the suspension queue until the copying is completed.

7. A storage medium for storing a program for executing the processor run error detection method for controlling the running clock period according to any one of claims 1 to 3.

8. A data processing apparatus comprising the storage medium according to claim 7, wherein the data processing apparatus performs the processor run error detection for controlling the running clock period when a processor of the data processing apparatus invokes and executes the computer executable instructions in the storage medium.

9. A client for the processor run error detection system for controlling the running clock period according to any one of claims 4 to 6.

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