Pixel circuit and display device including the same

Abstract

Disclosed are a pixel circuit and a display device including the pixel circuit. The pixel circuit of the present disclosure includes: a driving element including: a first electrode connected to a first node to which a pixel driving voltage is applied; a gate electrode connected to a second node; and a third electrode connected to a third node and configured to supply current to a light-emitting element; a light-emitting element including an anode electrode connected to the third node and a cathode electrode to which a pixel ground voltage is applied; a first switching element configured to supply a data voltage to the second node in response to a scan pulse; a second switching element configured to supply a first initialization voltage set to a negative voltage lower than the pixel ground voltage to the third node in response to a first initialization pulse; a third switching element configured to supply a second initialization voltage higher than the first initialization voltage to the second node in response to a second initialization pulse; and a capacitor connected between the second node and the third node.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2021-0089955, filed on July 8, 2021, and Korean Patent Application No. 10-2021-0174570, filed on December 8, 2021, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to a pixel circuit and a display device including the pixel circuit. Background Art

[0004] According to the material of the emission layer, electroluminescent display devices can be divided into inorganic light-emitting display devices and organic light-emitting display devices. Active matrix organic light-emitting display devices include organic light-emitting diodes (hereinafter referred to as "OLEDs") that emit light by themselves, and have the advantages of fast response speed, high luminous efficiency, high brightness and viewing angle. In an organic light-emitting display device, an OLED (organic light-emitting diode) is formed in each pixel. The organic light-emitting display device has a fast response speed, excellent luminous efficiency, brightness and viewing angle, and also has excellent contrast and color reproducibility because the grayscale of black can be expressed as completely black.

[0005] The pixel circuit of an organic light-emitting display device includes a light-emitting element, a driver element for driving the light-emitting element, and one or more switching elements. The switching element is turned on / off according to the gate voltage to connect or block the main node of the pixel circuit. The driver element and the switching element can be implemented as transistors.

[0006] The pixel circuit of an organic light-emitting display device may include an initialization phase. During this initialization phase, the source node voltage of the driving element may be initialized to a positive voltage greater than 0V, for example. In this case, the pixel ground voltage applied to the cathode electrode of the light-emitting element needs to be equal to or greater than the source node voltage. This can increase the power consumption of the display device.

[0007] A pixel ground voltage is typically applied to a pixel of an organic light-emitting display device. When the data voltage is changed or the voltage of the source node is changed by the parasitic capacitance of the display panel and the capacitance of the light-emitting element, ripple may appear in the pixel ground voltage. In this case, the current flowing through the light-emitting element may change, which in turn may cause a change in the brightness of the pixel. For example, when an input image including a crosstalk pattern is displayed on the screen of the display panel, and when ripple appears in the pixel ground voltage, dark lines or dark blocks may become visible. When the voltage of the source node and the pixel ground voltage are set to, for example, 0 V or a higher voltage, the ripple of the pixel ground voltage may increase. Summary of the Invention

[0008] The present disclosure has been made to address at least one of the above-mentioned needs and / or disadvantages.

[0009] The present disclosure provides a pixel circuit capable of preventing image quality degradation due to ripples of a pixel ground voltage commonly applied between pixels, and a display device including the pixel circuit.

[0010] The disadvantages solved by the present disclosure are not limited to the above-mentioned disadvantages, but other disadvantages that can be solved by the present disclosure will become apparent to those skilled in the art from the following description.

[0011] A pixel circuit according to one embodiment of the present disclosure includes: a driving element, which includes: a first electrode, the first electrode is connected to a first node to which a pixel driving voltage is applied; a gate electrode connected to a second node; and a third electrode connected to a third node, and the driving element is configured to supply current to the light-emitting element; a light-emitting element, which includes an anode electrode connected to the third node, and a cathode electrode to which a pixel ground voltage is applied; and a switching element, which is configured to supply a first initialization voltage set to a negative voltage lower than the pixel ground voltage to the third node in response to a first initialization pulse.

[0012] A pixel circuit according to one embodiment of the present disclosure includes: a driving element, which includes: a first electrode connected to a first node to which a pixel driving voltage is applied; a gate electrode connected to a second node; and a third electrode connected to a third node and supplies current to the light-emitting element; a light-emitting element, which includes an anode electrode connected to the third node and a cathode electrode to which a pixel ground voltage is applied; a first switching element, which supplies a data voltage to the second node in response to a scan pulse; a second switching element, which supplies a first initialization voltage set to a negative voltage lower than the pixel ground voltage to the third node in response to a first initialization pulse; a third switching element, which supplies a second initialization voltage higher than the first initialization voltage to the second node in response to a second initialization pulse; and a capacitor connected between the second node and the third node.

[0013] A display device according to one embodiment of the present disclosure includes a pixel circuit.

[0014] According to one embodiment of the present disclosure, for example, by initializing the source node of the driving element to a negative voltage, the pixel ground voltage can be set to 0V or the ground voltage (GND). Therefore, according to the present disclosure, the power consumption of the display panel can be reduced, and the ripple of the pixel ground voltage can be minimized. In addition, according to the present disclosure, the data voltage Vdata can be reduced, so that power consumption can be reduced.

[0015] According to one embodiment of the present disclosure, a negative voltage may be generated in a display panel without adding a negative voltage generating circuit to a power supply.

[0016] The effects of the present disclosure are not limited to the above-mentioned effects, and other effects not mentioned above will be clearly understood by those skilled in the art from the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and other objects, features and advantages of the present invention will become more apparent to those skilled in the art by describing in detail exemplary embodiments thereof with reference to the accompanying drawings, in which:

[0018] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present disclosure;

[0019] Figure 2 It shows Figure 1 A cross-sectional view of the cross-sectional structure of the display panel shown in ;

[0020] Figure 3 is a circuit diagram showing a pixel circuit according to a first embodiment of the present disclosure;

[0021] Figure 4 is shown applied to Figure 3 A waveform diagram of a gate signal of a pixel circuit shown in ;

[0022] Figure 5 is a circuit diagram showing a pixel circuit according to a second embodiment of the present disclosure;

[0023] Figure 6 is shown applied to Figure 5 A waveform diagram of a gate signal of a pixel circuit shown in ;

[0024] Figure 7 is a diagram showing a path in which a first initialization voltage is applied to a pixel according to an embodiment of the present disclosure;

[0025] Figure 8 is a circuit diagram showing a negative voltage generating circuit according to an embodiment of the present disclosure;

[0026] Figure 9 yes Figure 8 The amplifying circuit diagram of the negative voltage generating circuit shown in ;

[0027] Figure 10 is shown as input to Figure 8 : a waveform diagram of an example of an N-1th gate pulse and an Nth gate pulse of the negative voltage generating circuit shown in ; and

[0028] Figure 11and Figure 12 It is shown in different stages Figure 8 The operation of the negative voltage generating circuit is shown in the circuit diagram. DETAILED DESCRIPTION

[0029] The advantages and features of the present disclosure and the methods for achieving the same will be more clearly understood from the embodiments described below with reference to the accompanying drawings. However, the present disclosure is not limited to the following embodiments, but can be implemented in a variety of different forms. Moreover, the present embodiments will complete the disclosure of the present disclosure and allow those skilled in the art to fully understand the scope of the present disclosure. The present disclosure is limited only within the scope of the appended claims.

[0030] The shapes, sizes, ratios, angles, numbers, etc. shown in the drawings used to describe the embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. Throughout this specification, similar reference numerals generally represent similar elements. In addition, when describing the present disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure.

[0031] Terms such as "comprising," "including," "having," and "consisting of" used herein are generally intended to allow the addition of other components unless these terms are used with the term "only." Any reference to a singular form may include a plural form unless expressly stated otherwise.

[0032] Even if not explicitly stated, the components are interpreted as including the ordinary error range.

[0033] When terms such as "on," "over," "below," and "immediately" are used to describe the positional relationship between two components, one or more components may be located between the two components unless these terms are used together with the term "immediately" or "directly."

[0034] Terms such as “first” and “second” may be used to distinguish components from one another, but the function or structure of the components is not limited by the ordinal numbers preceding the components or the names of the components.

[0035] Like reference numerals may substantially refer to like elements throughout this disclosure.

[0036] The following embodiments may be partially or entirely joined or combined with each other, and may be coupled and operated in technically different ways. The embodiments may be performed independently or in association with each other.

[0037] Each pixel may include multiple sub-pixels with different colors to reproduce the colors of the image on the screen of the display panel. Each sub-pixel includes a transistor that acts as a switching element or driving element. Such a transistor can be implemented as a TFT (thin film transistor).

[0038] The display device's driver circuit writes pixel data of an input image to pixels on the display panel. To this end, the display device's driver circuit may include a data driver circuit configured to supply data signals to data lines, a gate driver circuit configured to supply gate signals to gate lines, and the like.

[0039] In the display device of the present disclosure, the pixel circuit and the gate driver circuit may include a plurality of transistors. The transistors may be implemented as oxide thin film transistors (oxide TFTs) including oxide semiconductors, low temperature polysilicon (LTPS) TFTs including low temperature polysilicon, and the like. In the embodiment, a description will be given based on an example in which the transistors of the pixel circuit and the gate driver circuit are implemented as n-channel oxide TFTs, but the present disclosure is not limited thereto.

[0040] A transistor is a three-electrode component consisting of a gate, a source, and a drain. The source is the electrode that supplies carriers to the transistor. In a transistor, carriers begin flowing from the source. The drain is the electrode from which carriers exit the transistor. In a transistor, carriers flow from the source to the drain. In the case of an n-channel transistor, since the carriers are electrons, the source voltage is lower than the drain voltage, allowing electrons to flow from the source to the drain. An n-channel transistor has a current flow direction from the drain to the source. In the case of a p-channel transistor (p-channel metal oxide semiconductor (PMOS)), since the carriers are holes, the source voltage is higher than the drain voltage, allowing holes to flow from the source to the drain. In a p-channel transistor, since holes flow from the source to the drain, current flows from the source to the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain can be changed depending on the applied voltage. Therefore, the present disclosure is not limited by the source and drain of a transistor. In the following description, a source and a drain of a transistor will be referred to as a first electrode and a second electrode.

[0041] The gate signal varies between a gate-on voltage and a gate-off voltage. The gate-on voltage is set to a voltage higher than a threshold voltage of the transistor, and the gate-off voltage is set to a voltage lower than the threshold voltage of the transistor.

[0042] The transistor is turned on in response to a gate-on voltage and turned off in response to a gate-off voltage. In the case of an n-channel transistor, the gate-on voltage may be a gate-high voltage and the gate-off voltage may be a gate-low voltage.

[0043] Hereinafter, various embodiments of the present disclosure will be described with reference to the accompanying drawings. In the following embodiments, the display device will be described primarily with respect to an organic light-emitting display device, but the present disclosure is not limited thereto. In addition, the scope of the present disclosure is not intended to be limited by the names of components or signals in the following embodiments and claims.

[0044] Reference Figure 1 and Figure 2 , a display device according to an embodiment of the present disclosure includes: a display panel 100; a display panel driver for writing pixel data into pixels of the display panel 100; and a power supply 140 for generating power required to drive the pixels and the display panel driver.

[0045] The display panel 100 may be a panel having a rectangular structure having a length in the X-axis direction, a width in the Y-axis direction, and a thickness in the Z-axis direction. The display panel 100 includes a pixel array that displays an input image on a screen. The pixel array includes a plurality of data lines 102, a plurality of gate lines 103 that intersect the data lines 102, and pixels arranged in a matrix form. The display panel 100 may also include power lines commonly connected to the pixels. The power lines supply the constant voltage required to drive the pixels 101 to the pixels 101. For example, the display panel 100 may include a VDD line that applies a pixel drive voltage ELVDD, and a VSS line that applies a pixel ground voltage ELVSS. In addition, the power lines may also include a REF line that applies a reference voltage Vref, an INIT1 line that applies a first initialization voltage -Vx, an INIT2 line that applies a second initialization voltage Vinit, and the like.

[0046] like Figure 2 As shown in , the cross-sectional structure of the display panel 100 may include a circuit layer 12 , a light emitting element layer 14 , and an encapsulation layer 16 stacked on a substrate 10 .

[0047] Circuit layer 12 may include: a TFT array comprising pixel circuits connected to circuits such as data lines, gate lines, and power lines; a demultiplexer array 112; a gate driver 120; and the like. The circuits and circuit elements of circuit layer 12 may include: multiple insulating layers; two or more metal layers separated by an insulating layer therebetween; and an active layer comprising a semiconductor material. All transistors formed in circuit layer 12 may be implemented as n-channel oxide TFTs.

[0048] The light-emitting element layer 14 may include a light-emitting element EL driven by a pixel circuit. The light-emitting element EL may include a red (Red, R) light-emitting element, a green (Green, G) light-emitting element, and a blue (Blue, B) light-emitting element. In another embodiment, the light-emitting element layer 14 may include a white light-emitting element and a color filter. The light-emitting element EL of the light-emitting element layer 14 may be covered by a multi-layer protective layer including an organic film and an inorganic protective film.

[0049] The encapsulation layer 16 covers the light-emitting element layer 14 to seal the circuit layer 12 and the light-emitting element layer 14. The encapsulation layer 16 may also have a multi-insulating film structure in which organic films and inorganic films are alternately stacked. The inorganic films block the penetration of moisture and oxygen. The organic films flatten the surface of the inorganic films. When the organic and inorganic layers are stacked in multiple layers, the movement path of moisture or oxygen becomes longer than that of a single layer, making it possible to effectively block the penetration of moisture and oxygen that affects the light-emitting element layer 14.

[0050] A touch sensor layer (omitted from the figures) can be formed on the encapsulation layer 16, and a polarizer or color filter layer can be disposed thereon. The touch sensor layer can include capacitive touch sensors that sense touch input based on changes in capacitance before and after a touch input. The touch sensor layer can include an insulating layer and a metal line pattern that form the touch sensor's capacitance. The insulating layer can insulate the intersections of the metal line pattern and flatten the surface of the touch sensor layer. The polarizer can improve visibility and contrast by converting the polarization of external light reflected by the metal and circuit layers of the touch sensor layer. The polarizer can be implemented as a polarizer that combines a linear polarizer and a phase retardation film, or as a circular polarizer. The cover glass may be bonded to the polarizer. The color filter layer can include a red filter, a green filter, and a blue filter. The color filter layer may also include a black matrix pattern. The color filter layer absorbs a portion of the wavelength of light reflected from the circuit layer and the touch sensor layer, allowing it to replace the polarizer and increase the color purity of the image reproduced in the pixel array.

[0051] The pixel array includes a plurality of pixel rows L1 to Ln. Each of the pixel rows L1 to Ln comprises a pixel row arranged along the row direction (X-axis direction) in the pixel array of the display panel 100. The pixels arranged in a pixel row share a gate line 103. Subpixels are arranged along the data line direction in the column direction Y and share the same data line 102. One horizontal period is the time obtained by dividing one frame period by the total number of pixel rows L1 to Ln.

[0052] The display panel 100 can be implemented as a non-transmissive display panel or a transmissive display panel. The transmissive display panel can be applied to a transparent display device that displays an image on a screen with the actual background visible. The display panel 100 can be manufactured as a flexible display panel.

[0053] Each of the pixels 101 can be divided into a red sub-pixel, a green sub-pixel, and a blue sub-pixel to achieve color. Each of the pixels can further include a white sub-pixel. Each of the sub-pixels includes a pixel circuit. Hereinafter, a pixel can be interpreted as having the same meaning as a sub-pixel. Each of the pixel circuits is connected to a data line, a gate line, and a power line.

[0054] Pixels can be arranged as true color pixels and pentile pixels. Pentile pixels can achieve higher resolution than true color pixels by driving two sub-pixels with different colors as one pixel 101 using a preset pixel rendering algorithm. The pixel rendering algorithm may compensate for insufficient color representation in each pixel by using the color of light emitted from adjacent pixels.

[0055] The power supply 140 generates the direct current (DC) voltage (or constant voltage) required to drive the pixel array and display panel driver of the display panel 100 using a DC-DC converter. The DC-DC converter may include a charge pump, a regulator, a buck converter, a boost converter, etc. The power supply 140 can generate DC voltages (or constant voltages) such as a gamma reference voltage VGMA, a gate-on voltage VGH, a gate-off voltage VGL, a pixel driving voltage ELVDD, a pixel ground voltage ELVSS, a first initialization voltage -Vx, a second initialization voltage Vinit, a reference voltage Vref, etc. by adjusting the level of a DC input voltage applied from a host system (not shown). The gamma reference voltage VGMA is supplied to the data driver 110. The gate-on voltage VGH and the gate-off voltage VGL are supplied to the gate driver 120. Constant voltages such as the pixel driving voltage ELVDD, the pixel ground voltage ELVSS, the first initialization voltage -Vx, the second initialization voltage Vinit, and the reference voltage Vref are supplied to the pixels 101 via power lines commonly connected to the pixels 101. The constant voltage applied to the pixel circuit may have different voltage levels.

[0056] The first initialization voltage -Vx may be generated from a negative voltage generating circuit. The negative voltage generating circuit may be disposed on the display panel 100 without being added to the power supply 140.

[0057] The display panel driver writes pixel data of an input image into pixels of the display panel 100 under the control of the timing controller 130 .

[0058] The display panel driver includes a data driver 110 and a gate driver 120. The display panel driver may further include a demultiplexer array 112 disposed between the data driver 110 and the data lines 102.

[0059] The demultiplexer array 112 sequentially supplies data voltages output from the channels of the data driver 110 to the data lines 102 using a plurality of demultiplexers (DEMUX). The demultiplexer may include a plurality of switching elements disposed on the display panel 100. When the demultiplexer is disposed between the output terminal of the data driver 110 and the data lines 102, the number of channels of the data driver 110 may be reduced. The demultiplexer array 112 may be omitted.

[0060] The display panel driver may further include a touch sensor driver for driving the touch sensor. Figure 1 The touch sensor driver is omitted. The data driver 110 and the touch sensor driver can be integrated into one driver IC (integrated circuit). In a mobile device or wearable device, the timing controller 130, the power supply 140, the data driver 110, etc. can be integrated into one driver IC.

[0061] The display panel driver can operate in a low-speed drive mode under the control of the timing controller 130. When the input image does not change a preset number of frames by analyzing the input image, the low-speed drive mode can be set to reduce the power consumption of the display device. In the low-speed drive mode, when a still image is input for a predetermined time or longer, the power consumption of the display panel driver and the display panel 100 can be reduced by reducing the refresh rate of the pixels. The low-speed drive mode is not limited to when a still image is input. For example, when the display device is operating in standby mode or when a user command or input image is not input to the display panel driver for a predetermined time or more, the display panel driver can operate in a low-speed drive mode.

[0062] The data driver 110 receives pixel data of an input image as a digital signal from the timing controller 130 and outputs a data voltage. The data driver 110 generates a data voltage Vdata by converting the pixel data of the input image into a gamma compensation voltage every frame period using a digital-to-analog converter (DAC). The gamma reference voltage VGMA is divided into a gamma compensation voltage for each grayscale by a voltage divider circuit. The gamma compensation voltage for each grayscale is supplied to the DAC of the data driver 110. The data voltage Vdata is output from each channel of the data driver 110 through an output buffer.

[0063] The gate driver 120 can be implemented as a gate-in-panel (GIP) circuit in the circuit layer 12 on the display panel 100, together with the lines of the TFT array and the pixel array. The gate driver 120 can be arranged on the bezel BZ, which is the non-display area of ​​the display panel 100, or can be distributedly arranged in the pixel array that reproduces the input image. The gate driver 120 sequentially outputs gate signals to the gate lines 103 under the control of the timing controller 130. The gate driver 120 can sequentially supply gate signals to the gate lines 103 while shifting the gate signals using a shift register. The gate signal may include various gate pulses, such as a scan pulse, a sensing pulse, an initialization pulse, a light emitting control pulse (hereinafter referred to as an "EM pulse"), etc.

[0064] The timing controller 130 receives digital video data DATA of an input image and timing signals synchronized with the digital video data DATA from the host system. The timing signals may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a clock CLK, and a data enable signal DE. Since the vertical and horizontal periods can be determined by counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync can be omitted. The data enable signal DE has a period of one horizontal period (1H).

[0065] The host system may be any one of a TV (television) system, a tablet computer, a laptop computer, a navigation system, a personal computer (PC), a home theater system, a mobile device, a wearable device, and a vehicle system. The host system may scale the image signal from the video source to fit the resolution of the display panel 100 and may send it along with the timing signal to the timing controller 130.

[0066] The timing controller 130 can multiply the input frame frequency by i (i is a natural number) in the normal driving mode so that it can control the operation timing of the display panel driver at a frame frequency of input frame frequency×i Hz. The input frame frequency is 60 Hz in the NTSC (National Television Standards Committee) scheme, and 50 Hz in the PAL (Phase Alternating Line) scheme.

[0067] Compared to the normal drive mode, the timing controller 130 reduces the frequency of the frame rate at which pixel data is written to the pixel in the low-speed drive mode. For example, in the normal drive mode, the data refresh frame frequency at which pixel data is written to the pixel can occur at a frequency of 60 Hz or higher, for example, at a refresh rate of any one of 60 Hz, 120 Hz, and 144 Hz, and the data refresh frame DRF in the low-speed drive mode can occur at a refresh rate lower than the refresh rate of the normal drive mode. The timing controller 130 can reduce the drive frequency of the display panel driver by reducing the frame frequency to a frequency between 1 Hz and 30 Hz, so as to reduce the refresh rate of the pixel in the low-speed drive mode.

[0068] The timing controller 130 generates data timing control signals for controlling the operation timing of the data driver 110, control signals for controlling the operation timing of the demultiplexer array 112, and gate timing control signals for controlling the operation timing of the gate driver 120 based on the timing signals Vsync, Hsync, and DE received from the host system. The timing controller 130 controls the operation timing of the display panel driver to synchronize the data driver 110, the demultiplexer array 112, the touch sensor driver, and the gate driver 120.

[0069] The gate timing control signal generated from the timing controller 130 may be input to the shift register of the gate driver 120 through a level shifter (not shown). The level shifter may receive the gate timing control signal, generate a start pulse and a shift clock, and provide them to the shift register of the gate driver 120.

[0070] Figure 3 is a circuit diagram showing a pixel circuit according to a first embodiment of the present disclosure. Figure 4 is shown applied to Figure 3 : The waveform diagram of the gate signal of the pixel circuit shown in FIG.

[0071] Reference Figure 3 and Figure 4 The pixel circuit includes a light emitting element EL, a driving element DT for supplying current to the light emitting element EL, a plurality of switching elements M01 to M03, and a capacitor Cst. In the pixel circuit, the driving element DT and the switching elements M01 to M03 may be implemented as n-channel oxide TFTs.

[0072] Constant voltages, such as a pixel driving voltage ELVDD, a pixel ground voltage ELVSS, a first initialization voltage -Vx, and a second initialization voltage Vinit, are applied to the pixel circuit. The pixel driving voltage ELVDD is higher than the pixel ground voltage ELVSS. The pixel ground voltage ELVSS is set to 0V or the ground voltage GND. The second initialization voltage Vinit is set to a voltage higher than the first initialization voltage -Vx. The first initialization voltage -Vx can be set to a negative voltage lower than the pixel ground voltage ELVSS. The gate-on voltage VGH can be set to a voltage higher than the pixel driving voltage ELVDD. The gate-off voltage VGL can be set to a voltage lower than the pixel ground voltage ELVSS.

[0073] The pixel circuit can be driven in an internal compensation mode. In this mode, the pixel circuit's driving period can be divided into an initialization phase (INIT), a sensing phase (SEN), an addressing phase (WR), a boost phase (BOOST), and an emission phase (EMIS). In the initialization phase (INIT), the second and third nodes DRG and DRS of the pixel circuit, as well as the capacitor Cst, are initialized, and the driving element DT is turned on. In the sensing phase (SEN), when the voltage of the third node DRS rises and the gate-source voltage Vgs of the driving element DT falls below the threshold voltage Vth, the driving element DT is turned off. The threshold voltage Vth of the driving element DT, which was sampled when the driving element DT was turned off in the sensing phase (SEN), is stored. When the data voltage Vdata is applied to the second node DRG in the addressing phase (WR), the gate voltage of the driving element DT becomes the data voltage Vdata compensated by the threshold voltage Vth. In the boost phase (BOOST), the floating voltages of the second and third nodes DRG and DRS rise, charging the capacitor connected between the two ends of the light-emitting element EL. The capacitor connected between the two ends of the light-emitting element EL is omitted from the drawings. In the light emitting period EMIS, the driving element DT generates a current for driving the light emitting element EL according to the gate-source voltage Vgs.

[0074] The gate driver 120 may include a first shift register that sequentially outputs a first initialization pulse SINIT, a second shift register that sequentially outputs a second initialization pulse INIT, and a third shift register that sequentially outputs a scan pulse SCAN.

[0075] The first initialization pulse SINIT is generated as the gate-on voltage VGH during the initialization phase INIT, and is the gate-off voltage VGL during the sensing phase SEN, the address phase WR, the boost phase BOOST, and the emission phase EMIS. The second initialization pulse INIT is generated as the gate-on voltage VGH during the initialization phase INIT and the sensing phase SEN. The second initialization pulse INIT is the gate-off voltage VGL during the address phase WR, the boost phase BOOST, and the emission phase EMIS. The scan pulse SCAN is synchronized with the data voltage Vdata of the pixel data and is generated as the gate-on voltage VGH during the address phase WR. The scan pulse SCAN is the gate-off voltage VGL during the initialization phase INIT, the sensing phase SEN, the boost phase BOOST, and the emission phase EMIS.

[0076] The light-emitting element EL can be implemented as an OLED including an anode electrode, a cathode electrode, and an organic composite layer connected between these electrodes. The organic composite layer includes, but is not limited to, a hole injection layer HIL, a hole transport layer HTL, an emission layer EML, an electron transport layer ETL, and an electron injection layer EIL. When voltage is applied to the anode electrode and the cathode electrode, holes passing through the hole transport layer HTL and electrons passing through the electron transport layer ETL move to the emission layer EML to form excitons. At this time, visible light can be emitted from the emission layer EML. The anode electrode of the light-emitting element EL can be connected to a third node DRS, and its cathode electrode can be connected to a VSS line to which a pixel ground voltage ELVSS is applied. The OLED used as the light-emitting element EL can have a series structure in which multiple emission layers are stacked. The series structure of the OLED can improve the brightness and lifespan of the pixel.

[0077] The driving element DT generates a current for driving the light-emitting element EL based on the gate-source voltage Vgs. The driving element DT includes a gate electrode connected to a second node DRG; a first electrode connected to a first node DRD to which a pixel driving voltage ELVDD is applied; and a third electrode connected to a third node DRS. A capacitor Cst is connected between the second node DRG and the third node DRS.

[0078] The first switching element M01 is turned on according to the gate-on voltage VGH of the scan pulse SCAN to supply the data voltage Vdata to the second node DRG during the address phase WR. The first switching element M01 includes: a gate electrode connected to the first gate line to which the scan pulse SCAN is applied; a first electrode connected to the data line to which the data voltage Vdata is applied; and a second electrode connected to the second node DRG.

[0079] The second switching element M02 is turned on in response to the gate-on voltage VGH of the first initialization pulse SINIT to supply the first initialization voltage -Vx to the third node DRS during the initialization phase INIT. The second switching element M02 includes a gate electrode connected to the second gate line to which the first initialization pulse SINIT is applied; a first electrode connected to the third node DRS; and a second electrode connected to the INIT1 line to which the first initialization voltage -Vx is applied.

[0080] The third switching element M03 is turned on according to the gate-on voltage VGH of the second initialization pulse INIT to supply the second initialization voltage Vinit to the second node DRG during the initialization phase INIT and the sensing phase SEN. The third switching element M03 includes: a gate electrode connected to the third gate line to which the second initialization pulse INIT is applied; a first electrode connected to the line to which the second initialization voltage Vinit is applied; and a second electrode connected to the second node DRG.

[0081] In the present disclosure, by initializing the third node DRS of the pixel circuit to a negative voltage, that is, a first initialization voltage -Vx, the pixel ground voltage ELVSS can be set to 0V or the ground voltage GND. Therefore, according to the present disclosure, the power consumption of the display panel 100 can be reduced, and the ripple of the pixel ground voltage ELVSS can be minimized. When the data voltage Vdata and the gate pulse change, the parasitic capacitance and ripple components generated by the capacitor connected to both ends of the light-emitting element EL are released to the VSS line with low resistance, thereby minimizing the ripple of the pixel ground voltage (ELVSS). In addition, according to the present disclosure, since the data voltage Vdata can be used as a voltage lower than the data voltage when the pixel ground voltage ELVSS is higher than 0V, power consumption can be further reduced.

[0082] Due to device characteristic variations and process variations caused during the manufacturing process of the display panel 100, there may be differences in the electrical characteristics of the driving elements between pixels, and such differences may increase as the driving time of the pixels passes. In order to compensate for the variations in the electrical characteristics of the driving elements between pixels, an internal compensation circuit may be embedded in the pixel circuit, or an external compensation circuit may be connected to the pixel circuit. The internal compensation circuit is used in applications such as Figure 3 The internal compensation circuit implemented in each pixel circuit shown in FIG5 samples the electrical characteristics of the driving element of each sub-pixel and compensates the gate-source voltage Vgs of the driving element based on such electrical characteristics. The external compensation circuit compensates for changes in the electrical characteristics of the driving element by generating a compensation value based on the result of sensing the electrical characteristics of the driving element using an external compensation circuit connected to the pixel circuit.

[0083] The external compensation circuit includes: a REF line (or sensing line) connected to the pixel circuit; and an analog-to-digital converter (ADC) that converts the sensing voltage stored in the REF line into digital data. The sensing voltage may include electrical characteristics of the driving element DT, such as threshold voltage and / or mobility. An integrator may be connected to the input terminal of the ADC. The timing controller 130 applying the external compensation circuit may generate a compensation value for compensating for changes in the electrical characteristics of the driving element DT based on the sensing data input from the ADC, and may compensate for changes in the electrical characteristics of the driving element DT by adding or multiplying the compensation value with the pixel data of the input image. The ADC may be embedded in the data driver 110.

[0084] According to the present disclosure, a pixel circuit can be driven by a hybrid drive method that combines internal compensation and external compensation. In this case, the normal drive mode may include an internal compensation mode and an external compensation mode. As the cumulative drive time of the pixel becomes longer, the threshold voltage of the driving element shifts, so that compensation of the threshold voltage of the driving element by internal compensation alone may be insufficient.

[0085] The timing controller 130 can drive the pixel in the internal compensation drive mode until the cumulative drive time of the pixel reaches the preset compensation mode change time point according to the preset prediction model, and it can apply the internal compensation drive mode and the external compensation mode at the same time after the compensation mode change time point. For example, after the compensation mode change time point, the pixel in the preset sensing mode can be driven in the external compensation mode, and the pixel in the display mode other than the sensing mode can be driven in the internal compensation mode. The sensing mode can be set to a power-on sequence immediately after the power of the display device is turned on, a power-off sequence immediately after the power of the display device is turned off, and a vertical blank period in which pixel data of the input image is not received between the frame periods of the display mode. In addition, the sensing mode can be arbitrarily activated according to user selection. The display mode can be set to an effective period for writing pixel data into the pixel excluding the vertical blank period from the frame period. In the display mode, during the effective period in each frame period, the pixel rows are scanned sequentially to write pixel data into the pixel.

[0086] Figure 5 is a circuit diagram showing a pixel circuit according to a second embodiment of the present disclosure. Figure 6 is shown applied to Figure 5 The waveform diagram of the gate signal of the pixel circuit shown in FIG. Figure 6 In , "NBD" is the internal compensation mode, and "YBD" is the external compensation mode. Figure 5 In the pixel circuit shown in , a detailed description of a circuit configuration substantially the same as that of the pixel circuit of the above-described embodiment will be omitted.

[0087] Reference Figure 5 and Figure 6 The pixel circuit includes a light emitting element EL, a driving element DT for supplying current to the light emitting element EL, a plurality of switching elements M01 to M04, and a capacitor Cst. In this pixel circuit, the driving element DT and the switching elements M01 to M04 may be implemented as n-channel oxide TFTs.

[0088] Constant voltages such as a pixel driving voltage ELVDD, a pixel ground voltage ELVSS, a first initialization voltage -Vx, a second initialization voltage Vinit, and a reference voltage Vref are applied to the pixel circuit. The pixel driving voltage ELVDD is higher than the pixel ground voltage ELVSS. The pixel ground voltage ELVSS is set to 0V or the ground voltage GND. The second initialization voltage Vinit is set to a voltage higher than the first initialization voltage -Vx and the pixel ground voltage ELVSS. The first initialization voltage -Vx can be set to a negative voltage lower than the pixel ground voltage ELVSS. The reference voltage Vref can be set to a voltage higher than the pixel ground voltage ELVSS and lower than the second initialization voltage Vinit. The gate-on voltage VGH can be set to a voltage higher than the pixel driving voltage ELVDD. The gate-off voltage VGL can be set to a voltage lower than the pixel ground voltage ELVSS.

[0089] The gate driver 120 may include a first shift register that sequentially outputs a first initialization pulse SINIT, a second shift register that sequentially outputs a second initialization pulse INIT, a third shift register that sequentially outputs a scan pulse SCAN, and a fourth shift register that sequentially outputs a sensing pulse SENSE.

[0090] The pixel circuit can be driven in an internal compensation mode NBD and an external compensation mode YBD.

[0091] In the internal compensation mode (NBD), the driving period of the pixel circuit can be divided into an initialization phase (INIT), a sensing phase (SEN), an addressing phase (WR), a boosting phase (BOOST), and an emission phase (EMIS). In the initialization phase (INIT), the second and third nodes DRG and DRS of the pixel circuit, as well as the capacitor Cst, are initialized, and the driving element DT is turned on. In the sensing phase (SEN), when the voltage of the third node DRS rises and the gate-source voltage (Vgs) of the driving element DT falls below the threshold voltage (Vth), the driving element DT is turned off. The threshold voltage (Vth) of the driving element DT, which was sampled when the driving element DT was turned off in the sensing phase (SEN), is stored. When the data voltage (Vdata) is applied to the second node DRG in the addressing phase (WR), the gate voltage of the driving element DT becomes the data voltage (Vdata) compensated by the threshold voltage (Vth). In the boosting phase (BOOST), the floating voltages of the second and third nodes DRG and DRS rise, charging the capacitor connected across the light-emitting element EL. In the emission phase (EMIS), the driving element DT generates a current based on the gate-source voltage (Vgs) to drive the light-emitting element EL.

[0092] The first initialization pulse SINIT is generated as the gate-on voltage VGH during the address phase WR, and is the gate-off voltage VGL during the initialization phase INIT, the sensing phase SEN, the boost phase BOOST, and the emission phase EMIS. The second initialization pulse INIT is generated as the gate-on voltage VGH during the initialization phase INIT and the sensing phase SEN. The second initialization pulse INIT is the gate-off voltage VGL during the address phase WR, the boost phase BOOST, and the emission phase EMIS. The scan pulse SCAN is synchronized with the data voltage Vdata of the pixel data and is generated as the gate-on voltage VGH during the address phase WR. The scan pulse SCAN is the gate-off voltage VGL during the initialization phase INIT, the sensing phase SEN, the boost phase BOOST, and the emission phase EMIS.

[0093] The anode electrode of the light-emitting element EL may be connected to a third node DRS, and its cathode electrode may be connected to a VSS line to which a pixel ground voltage ELVSS is applied. The driving element DT includes a gate electrode connected to a second node DRG; a first electrode connected to a first node DRD to which a pixel driving voltage ELVDD is applied; and a third electrode connected to a third node DRS. A capacitor Cst is connected between the second node DRG and the third node DRS.

[0094] The first switching element M01 includes a gate electrode connected to a first gate line to which a scan pulse SCAN is applied; a first electrode connected to a data line DL to which a data voltage Vdata is applied; and a second electrode connected to a second node DRG. The second switching element M02 includes a gate electrode connected to a second gate line to which a first initialization pulse SINIT is applied; a first electrode connected to a third node DRS; and a second electrode connected to an INIT1 line to which a first initialization voltage -Vx is applied. The third switching element M03 includes a gate electrode connected to a third gate line to which a second initialization pulse INIT is applied; a first electrode connected to an INIT2 line to which a second initialization voltage Vinit is applied; and a second electrode connected to a second node DRG.

[0095] The fourth switching element M04 includes a gate electrode connected to a fourth gate line to which a sense pulse SENSE is applied; a first electrode connected to a third node DRS; and a second electrode connected to a REF line RL to which a reference voltage Vref is applied. In the internal compensation mode NBD, the sense pulse SENSE maintains the gate-off voltage VGL. Therefore, the fourth switching element M04 is in an off state in the internal compensation mode. Consequently, in the internal compensation mode NBD, the third node DRS is electrically isolated from the REF line RL.

[0096] In the external compensation mode (YBD), the driving period of the pixel circuit can be divided into an initialization phase (INIT), a sensing phase (SEN), a sampling phase (SMPL), and an emission phase (EMIS). A boost phase can be provided between the sampling phase (SMPL) and the emission phase (EMIS). During the boost phase, the gate signals (SCAN, SINIT, INIT, and SENSE) are the gate-off voltage (VGL).

[0097] The first initialization pulse SINIT and the second initialization pulse INIT maintain the gate-off voltage VGL in the external compensation mode YBD. Therefore, in the external compensation mode YBD, since the second switching element M02 and the third switching element M03 remain in the off state, the second node DRG is electrically isolated from the INIT2 line, and the third node (DRS) is electrically isolated from the INIT1 line.

[0098] The scan pulse SCAN is generated as the gate-on voltage VGH in the initialization phase INIT, the sensing phase SEN, and the sampling phase SMPL in the external compensation mode YBD, and is the gate-off voltage VGL in the emission phase EMIS in the external compensation mode YBD.

[0099] The sensing pulse SENSE is generated at the gate-on voltage VGH during the initialization phase INIT and the sensing phase SEN in the external compensation mode YBD. The sensing pulse SENSE is the gate-off voltage during the sampling phase SMPL and the light-emission phase EMIS in the external compensation mode YBD. The sensing pulse SENSE rises to the gate-on voltage VGH after the rising edge of the scan pulse SCAN inverts to the gate-on voltage VGH, and then falls to the gate-off voltage VGL before the falling edge of the scan pulse SCAN inverts to the gate-off voltage VGL. Therefore, the fourth switching element M04 is turned on during the initialization phase INIT and the sensing phase SEN in the external compensation mode YBD to supply the reference voltage Vref to the third node DRS.

[0100] The reference voltage switching element SPRE and the sampling switching element SAM can be connected to a REF line RL to which a reference voltage Vref is applied. The reference voltage switching element SPRE and the sampling switching element SAM are turned on and off under the control of the timing controller 130. The reference voltage switching element SPRE is turned on during the initialization phase INIT to supply the reference voltage Vref to the REF line RL. After the reference voltage switching element SPRE is turned off during the initialization phase INIT, the fourth switching element M04 can be turned on in response to a sense pulse SENSE. The sampling switching element SAM is turned on during the sampling phase SMPL to connect the REF line RL to the ADC.

[0101] The reference voltage switching element SPRE, the sampling switching element SAM, and the ADC may be embedded in a driving integrated circuit (IC) in which the data driver 110 is integrated.

[0102] Figure 7 is a diagram illustrating a path in which a first initialization voltage -Vx is applied to a pixel according to an embodiment of the present disclosure.

[0103] Reference Figure 7 The data driver 110 may be integrated into each of one or more driver ICs (SICs). A chip on film (COF) may be bonded to the display panel (PNL). The driver IC (SIC) is mounted on the COF. The COF is connected between a source PCB (printed circuit board, SPCB) and the display panel (PNL), and the output terminals of the driver IC (SIC) are electrically connected to the display panel 100.

[0104] The timing controller 130 and the power supply 140 may be mounted on a control PCB (CPCB). The control PCB (CPCB) may be connected to the source PCB (SPCB) via a flexible circuit film, such as a flexible printed circuit (FPC). At least a portion of the power supply 140 may be arranged on the source PCB (SPCB).

[0105] The constant voltage output from the power supply 140 can be supplied to the display panel PNL via the source PCB (SPCB) and the dummy line of the COF. The first initialization voltage -Vx can be generated by the negative voltage generation circuit of the power supply 140 formed on the control PCB (CPCB) or the source PCB (SPCB) and supplied to the pixels of the display panel PNL via the dummy line of the COF. The dummy line of the COF is a line formed on the COF outside the driver IC (SIC).

[0106] Figure 8 、 Figure 9 、 Figure 11 and Figure 12 is a circuit diagram showing a negative voltage generating circuit VXC according to an embodiment of the present disclosure. Figure 10 : is a waveform diagram showing an example of an N-1th (N is a positive integer) gate pulse and an Nth gate pulse input to the negative voltage generating circuit.

[0107] Reference Figures 8 to 12 , the negative voltage generating circuit VXC generates the first initialization voltage -Vx in response to the N-1th gate pulse and the Nth gate pulse. Here, the gate pulse may be a gate pulse that controls the switching element that applies the first initialization voltage -Vx to the third node DRS of the pixel circuit. For example, Figure 3 and Figure 5 In the pixel circuit shown in , the gate pulse may be the first initialization pulse SINIT, or a separate gate pulse synchronized with the first initialization pulse SINIT. Figure 10 As shown in , the N-1th gate pulse and the N-th gate pulse may be sequentially generated from the shift register of the gate driver 120. Hereinafter, the "N-1th gate pulse" and the "N-th gate pulse" are described as the "N-1th initialization pulse [SINIT(N-1)]" and the "N-th initialization pulse [SINIT(N)]," respectively, but are not limited thereto.

[0108] The negative voltage generating circuit VXC is formed in the circuit layer 12 of the display panel PNL and can be arranged in a border area outside the pixel array or in the pixel array. In addition, the negative voltage generating circuit VXC can be embedded in a driver IC (SIC). The negative voltage generating circuit VXC can be connected to two or more pixel circuits in common. The pixel circuits connected to the negative voltage generating circuit VXC can be arranged on the same pixel row to share the gate line and the INIT1 line. In other words, a plurality of pixels can be connected to one negative voltage generating circuit VXC so that they can receive a first initialization voltage -Vx generated from the negative voltage generating circuit VXC.

[0109] The negative voltage generating circuit VXC includes first to fourth switching elements T1 to T4 and a capacitor C. When the negative voltage generating circuit VXC is formed in the circuit layer 12 of the display panel PNL, the switching elements T1 to T4 may be implemented as n-channel oxide TFTs.

[0110] The pixel ground voltage ELVSS and the reference voltage Vref are supplied to the negative voltage generating circuit VXC. The pixel ground voltage ELVSS is 0V or the ground voltage GND. The reference voltage Vref can be a positive voltage higher than the pixel ground voltage ELVSS, for example, 1V.

[0111] Capacitor C is connected between node A (a) and node B (b). The first switching element T1 is turned on by the gate-on voltage VGH of the N-1th initialization pulse [SINIT(N-1)] and connects the VSS node, to which the pixel ground voltage ELVSS is applied, to node A (a). The VSS node can be connected to a VSS line VSS. The first switching element T1 includes: a gate electrode to which the N-1th initialization pulse [SINIT(N-1)] is applied; a first electrode connected to the VSS node; and a second electrode connected to node A (a).

[0112] The second switching element T2 is turned on in response to the gate-on voltage VGH of the N-1th initialization pulse [SINIT(N-1)], thereby connecting the B node (b) to the REF node to which the reference voltage Vref is applied. The REF node can be connected to the REF line. The second switching element T2 includes: a gate electrode to which the N-1th initialization pulse [SINIT(N-1)] is applied; a first electrode connected to the B node (b); and a second electrode connected to the REF node.

[0113] The third switching element T3 is turned on according to the gate-on voltage VGH of the Nth initialization pulse [SINIT(N)] to connect the VSS node, to which the pixel ground voltage ELVSS is applied, to the B node (b). The third switching element T3 includes: a gate electrode to which the Nth initialization pulse [SINIT(N)] is applied; a first electrode connected to the VSS node; and a second electrode connected to the B node (b).

[0114] The fourth switching element T4 is turned on by the gate-on voltage VGH of the Nth initialization pulse [SINIT(N)] to connect node A (a) to the INIT1 line. The negative voltage output by the fourth switching element T4, namely the first initialization voltage -Vx, is supplied to the pixel via the INIT1 line. The fourth switching element T4 includes a gate electrode that applies the Nth initialization pulse [SINIT(N)]; a first electrode connected to node A (a); and a second electrode connected to the INIT1 line.

[0115] When the N-1th initialization pulse [SINIT(N-1)] is input to the negative voltage generating circuit VXC, as shown in FIG. Figure 11 As shown in FIG, the first switching element T1 and the second switching element T2 are turned on, while the third switching element T3 and the fourth switching element T4 are turned off. At this time, ELVSS=0V is applied to the A node (a), for example, VREF=1V is applied to the B node (b), and thus 1V is stored in the capacitor C.

[0116] Then, when the Nth initialization pulse [SINIT(N)] is input to the negative voltage generating circuit VXC, as shown in FIG. Figure 12 As shown in FIG, the third switching element T3 and the fourth switching element T4 are turned on, while the first switching element T1 and the second switching element T2 are turned off. At this time, since ELVSS = 0 V is applied to the B node (b), the A node (a) becomes, for example, -1 V. Therefore, when the Nth initialization pulse [SINIT(N)] is generated as the gate-on voltage VGH, the negative first initialization voltage -Vx is applied to the pixel through the INIT1 line.

[0117] The objects to be achieved by the present disclosure, means for achieving the objects, and the effects of the present disclosure described above do not specify essential features of the claims, and therefore, the scope of the claims is not limited to the disclosure of the present disclosure.

[0118] Although the embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be embodied in many different forms without departing from the technical concept of the present disclosure. Therefore, the embodiments disclosed in the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above-mentioned embodiments are illustrative in all aspects and do not limit the present disclosure. The scope of protection of the present disclosure should be interpreted based on the attached claims, and all technical concepts within their equivalent scope should be interpreted as falling within the scope of the present disclosure.

Claims

1. A pixel circuit, comprising: a driving element comprising: a first electrode connected to a first node to which a pixel driving voltage is applied; a gate electrode connected to a second node; and a third electrode connected to a third node, the driving element being configured to supply current to the light emitting element; The light emitting element includes an anode electrode connected to the third node and a cathode electrode to which a pixel ground voltage is applied; a first switching element configured to supply a data voltage to the second node in response to a scan pulse; a second switching element configured to supply a first initialization voltage to the third node in response to a first initialization pulse, the first initialization voltage being set to a negative voltage lower than the pixel ground voltage; a third switching element configured to supply a second initialization voltage higher than the first initialization voltage to the second node in response to a second initialization pulse; a capacitor connected between the second node and the third node; and A fourth switching element is configured to supply a reference voltage to the third node in response to a sensing pulse, the reference voltage being set to a voltage higher than the pixel ground voltage and lower than the second initialization voltage.

2. The pixel circuit according to claim 1, wherein: The pixel ground voltage is 0V.

3. The pixel circuit according to claim 1, wherein: The first switching element includes a gate electrode to which the scan pulse is applied, a first electrode to which the data voltage is applied, and a second electrode connected to the second node. The second switching element includes a gate electrode to which the first initialization pulse is applied, a first electrode connected to the third node, and a second electrode to which the first initialization voltage is applied, and The third switching element includes a gate electrode to which the second initialization pulse is applied, a first electrode to which the second initialization voltage is applied, and a second electrode connected to the second node. The pixel circuit according to claim 3 , wherein: The driving period of the pixel circuit includes an initialization phase, a sensing phase, an addressing phase, a boosting phase and a light emitting phase. wherein the first to third switching elements are turned on according to a gate-on voltage and turned off according to a gate-off voltage, The first initialization pulse is generated as the gate-on voltage in the initialization phase, and is generated as the gate-off voltage in the sensing phase, the addressing phase, the boosting phase, and the light-emitting phase. wherein the second initialization pulse is generated as the gate-on voltage in the initialization phase and the sensing phase, and is generated as the gate-off voltage in the addressing phase, the boosting phase, and the light-emitting phase, and The scan pulse is generated as the gate-on voltage in the addressing phase, and is generated as the gate-off voltage in the initialization phase, the sensing phase, the boosting phase, and the light-emitting phase.

5. The pixel circuit according to claim 1, wherein: The fourth switching element includes a gate electrode to which the sensing pulse is applied, a first electrode connected to the third node, and a second electrode to which the reference voltage is applied. The pixel circuit according to claim 5 , wherein: In the internal compensation mode, the driving period of the pixel circuit includes a first initialization phase, a first sensing phase, an addressing phase, a voltage boosting phase and a first light emitting phase. wherein the first to third switching elements are turned on according to a gate-on voltage and turned off according to a gate-off voltage, The first initialization pulse is generated as the gate-on voltage in the first initialization phase, and is generated as the gate-off voltage in the first sensing phase, the addressing phase, the boost phase, and the first light-emitting phase. wherein the second initialization pulse is generated as the gate-on voltage in the first initialization phase and the first sensing phase, and is generated as the gate-off voltage in the addressing phase, the boosting phase, and the first light-emitting phase; and The scan pulse is generated as the gate-on voltage in the addressing phase, and is generated as the gate-off voltage in the first initialization phase, the first sensing phase, the boosting phase, and the first light-emitting phase.

7. The pixel circuit according to claim 6, wherein: In the external compensation mode, the driving period of the pixel circuit includes a second initialization phase, a second sensing phase, a sampling phase, and a second light emitting phase. Wherein, the first initialization pulse and the second initialization pulse maintain the gate cut-off voltage in the external compensation mode, The scanning pulse is generated as the gate-on voltage in the second initialization phase, the second sensing phase, and the sampling phase, and is generated as the gate-off voltage in the second light-emitting phase, and The sensing pulse is generated as the gate-on voltage in the second initialization phase and the second sensing phase, and is generated as the gate-off voltage in the sampling phase and the second light-emitting phase.

8. A display device comprising: a display panel, in which a plurality of data lines, a plurality of gate lines crossing the data lines, a plurality of power lines, and a plurality of pixel circuits connected to the plurality of data lines, the plurality of gate lines, and the plurality of power lines are arranged; a data driver configured to supply data voltages of pixel data to the plurality of data lines; as well as a gate driver configured to supply gate signals to the plurality of gate lines, The gate signal includes a first initialization pulse, a second initialization pulse and a scan pulse, and Wherein, each of the plurality of pixel circuits comprises: a driving element comprising: a first electrode connected to a first node to which a pixel driving voltage is applied; a gate electrode connected to a second node; and a third electrode connected to a third node, the driving element being configured to supply current to the light emitting element; The light emitting element includes an anode electrode connected to the third node, and a cathode electrode to which a pixel ground voltage is applied; a first switching element configured to supply the data voltage to the second node in response to the scan pulse; a second switching element configured to supply a first initialization voltage to the third node in response to the first initialization pulse, the first initialization voltage being set to a negative voltage lower than the pixel ground voltage; a third switching element configured to supply a second initialization voltage higher than the first initialization voltage to the second node in response to the second initialization pulse; a capacitor connected between the second node and the third node; and A fourth switching element is configured to supply a reference voltage to the third node in response to a sensing pulse, the reference voltage being set to a voltage higher than the pixel ground voltage and lower than the second initialization voltage.

9. The display device according to claim 8, wherein The pixel ground voltage is 0V.

10. The display device according to claim 8, wherein The driving period of the pixel circuit includes an initialization phase, a sensing phase, an addressing phase, a boosting phase and a light emitting phase. wherein the first to third switching elements are turned on according to a gate-on voltage and turned off according to a gate-off voltage, The first initialization pulse is generated as the gate-on voltage in the initialization phase, and is generated as the gate-off voltage in the sensing phase, the addressing phase, the boosting phase, and the light-emitting phase. wherein the second initialization pulse is generated as the gate-on voltage in the initialization phase and the sensing phase, and is generated as the gate-off voltage in the addressing phase, the boosting phase, and the light-emitting phase, and The scan pulse is generated as the gate-on voltage in the addressing phase, and is generated as the gate-off voltage in the initialization phase, the sensing phase, the boosting phase, and the light-emitting phase.

11. The display device according to claim 8, wherein In the internal compensation mode, the driving period of the pixel circuit includes a first initialization phase, a first sensing phase, an addressing phase, a voltage boosting phase and a first light emitting phase. wherein the first to third switching elements are turned on according to a gate-on voltage and turned off according to a gate-off voltage, The first initialization pulse is generated as the gate-on voltage in the first initialization phase, and is generated as the gate-off voltage in the first sensing phase, the addressing phase, the boost phase, and the first light-emitting phase. wherein the second initialization pulse is generated as the gate-on voltage in the first initialization phase and the first sensing phase, and is generated as the gate-off voltage in the addressing phase, the boosting phase, and the first light-emitting phase; and The scan pulse is generated as the gate-on voltage in the addressing phase, and is generated as the gate-off voltage in the first initialization phase, the first sensing phase, the boosting phase, and the first light-emitting phase.

12. The display device according to claim 11, wherein In the external compensation mode, the driving period of the pixel circuit includes a second initialization phase, a second sensing phase, a sampling phase, and a second light emitting phase. Wherein, the first initialization pulse and the second initialization pulse maintain the gate cut-off voltage in the external compensation mode, The scanning pulse is generated as the gate-on voltage in the second initialization phase, the second sensing phase, and the sampling phase, and is the gate-off voltage in the second light-emitting phase, and The sensing pulse is generated as the gate-on voltage in the second initialization phase and the second sensing phase, and is generated as the gate-off voltage in the sampling phase and the second light-emitting phase.

13. The display device according to claim 8, further comprising a negative voltage generating circuit for generating the first initialization voltage, in, The negative voltage generating circuit is disposed on the display panel.

14. The display device according to claim 13, wherein: The negative voltage generating circuit comprises: a second capacitor connected between the fourth node and the fifth node; a first switching element comprising a gate electrode to which an N-1th gate pulse is applied, a first electrode to which the pixel ground voltage is applied, and a second electrode connected to the fourth node, where N is a positive integer; a second switching element including a gate electrode to which the (N-1)th gate pulse is applied, a first electrode connected to the fifth node, and a second electrode to which a reference voltage set to a positive voltage higher than the pixel ground voltage is applied; a third switching element including a gate electrode to which an Nth gate pulse is applied, a first electrode to which the pixel ground voltage is applied, and a second electrode connected to the fifth node; and A fourth switching element includes a gate electrode to which the Nth gate pulse is applied, a first electrode connected to the fourth node, and a second electrode connected to two or more pixel circuits to be connected to a power line to which the first initialization voltage is applied.

15. The display device according to claim 14, wherein The gate pulse is the first initialization pulse.

16. The display device according to claim 14, wherein: Each of the driving element and the switching element of each pixel circuit and the switching element of the negative voltage generating circuit includes an n-channel transistor.

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