Gate driver and display device using the same

Abstract

A gating driver according to an embodiment and a display device using the same are disclosed. The gating driver is configured to output a gating signal to a pixel circuit having a driving element connected between a first power line and a first node, a light-emitting element connected between the first node and a second power line, and a switching element connected between the first node and a third power line and driven by the gating signal. The gating driver includes: a first circuit unit configured to receive a carry signal from a previous signal transmission unit to charge or discharge a first control node and a second control node; and a second circuit unit having a first buffer transistor and a second buffer transistor, configured to output the gating signal based on a first clock signal and a first low-potential voltage according to the potentials of the first control node and the second control node, wherein the first low-potential voltage has a high-level voltage when driven in a sensing mode.

Description

Technical Field

[0001] This disclosure relates to gating drivers and display devices using them. Background Technology

[0002] Display devices include liquid crystal display (LCD) devices, electroluminescent display devices, field emission display (FED) devices, plasma display panels (PDP), etc.

[0003] Electroluminescent display devices are classified into inorganic light-emitting display devices and organic light-emitting display devices based on the material of the light-emitting layer. Active-matrix organic light-emitting display devices use self-emissive elements (e.g., organic light-emitting diodes, hereinafter referred to as "OLEDs") to reproduce input images. The advantages of organic light-emitting display devices include fast response time, high luminous efficiency, brightness, and wide viewing angle.

[0004] Some display devices, such as liquid crystal displays or organic light-emitting displays, include: a display panel comprising a plurality of subpixels; a driver outputting drive signals for driving the display panel; a power supply generating power to be supplied to the display panel or the driver, etc. The driver includes a gating driver that provides scan signals or gating signals to the display panel, and a data driver that provides data signals to the display panel.

[0005] In such a display device, when drive signals such as scan signals, EM signals and data signals are provided to multiple sub-pixels formed in the display panel, the selected sub-pixels transmit light or emit light directly to display an image.

[0006] Each sub-pixel includes a driving thin-film transistor (TFT) that controls the current flowing through the light-emitting element, and one or more switching TFTs that switch the current. In this case, degradation occurs due to the long-term driving of the driving TFTs, and a current-sensing-based compensation method is applied to compensate for this degradation. However, although the current-sensing-based compensation method operates when the user is not viewing the device, it has the disadvantage that the organic light-emitting diode (OLED) is perceived as a light-emitting structure. Summary of the Invention

[0007] This disclosure aims to address all the aforementioned needs and problems.

[0008] This disclosure is intended to provide a gating driver and a display device using the same.

[0009] It should be noted that the purpose of this disclosure is not limited to the above-described purposes, and other purposes of this disclosure will be apparent to those skilled in the art from the following description.

[0010] The gating driver according to this disclosure is configured to output a gating signal to a pixel circuit having a driving element connected between a first power line and a first node, a light-emitting element connected between the first node and a second power line, and a switching element connected between the first node and a third power line to be driven by the gating signal. The gating driver includes: a first circuit unit configured to receive a carry signal from a previous signal transmission unit to charge or discharge a first control node and a second control node; and a second circuit unit having a first buffer transistor and a second buffer transistor, configured to output the gating signal based on a first clock signal and a first low-potential voltage according to the potentials of the first control node and the second control node, wherein the first low-potential voltage has a high-level voltage when driven in sensing mode.

[0011] The display device according to this disclosure includes: a data driver configured to output a data voltage; a gating driver including a first circuit unit and a second circuit unit, the first circuit unit being configured to receive a carry signal from a previous signal transmission unit and charge a first control node or a second control node, the second circuit unit being configured to output a gating signal based on a clock signal and a low-potential voltage according to the potentials of the first control node and the second control node; and a plurality of pixel circuits configured to receive the data voltage and the gating signal to reproduce an input image, wherein, when driven in a sensing mode, the second circuit unit outputs the gating signal based on a first clock signal and a first low-potential voltage having a high-level voltage, and the pixel circuits include a driving element connected between a first power line and a first node, a light-emitting element connected between the first node and a second power line, and a switching element connected between the first node and a third power line to be driven by the gating signal. Attached Figure Description

[0012] The above and other objects, features, and advantages of this disclosure will become more apparent to those skilled in the art from the detailed description of exemplary embodiments thereof with reference to the accompanying drawings, wherein:

[0013] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the present disclosure;

[0014] Figure 2 This is a circuit diagram illustrating a pixel circuit connected to an external compensation circuit according to the present disclosure;

[0015] Figures 3 to 7 It is a diagram used to illustrate the operating principle of the sensing circuit according to the embodiment;

[0016] Figure 8 This is a diagram that schematically illustrates a gating driver according to an embodiment of the present disclosure;

[0017] Figure 9 This is an example Figure 8 The waveforms of the input / output signals and voltages of the control node of the gating driver are shown.

[0018] Figure 10 This is a diagram used to describe a pattern-based driving method according to an embodiment of the present disclosure;

[0019] Figure 11 This is a diagram illustrating the input and output signals of a level shifter according to an embodiment;

[0020] Figure 12 This is a diagram illustrating the signal transmission unit of a gating driver according to an embodiment;

[0021] Figure 13 This is an example Figure 12 The waveform diagram of the input signal of the signal transmission unit shown;

[0022] Figure 14 This is a diagram illustrating the signal transmission unit of the gating driver according to the first embodiment;

[0023] Figure 15 This is an example Figure 14 The waveform diagram of the input signal of the signal transmission unit shown;

[0024] Figure 16 This is an example Figure 14 The figure shows the simulation results of the gating driver;

[0025] Figure 17 This is a diagram illustrating the signal transmission unit of the gating driver according to the second embodiment;

[0026] Figure 18 This is an example Figure 17 The waveform diagram of the input signal of the signal transmission unit shown;

[0027] Figure 19 This is a diagram illustrating the signal transmission unit of the gating driver according to the third embodiment;

[0028] Figure 20 This is an example Figure 19 The waveform diagram of the input signal of the signal transmission unit shown;

[0029] Figure 21 This is a circuit diagram illustrating a pixel circuit according to another embodiment of the present disclosure;

[0030] Figure 22 This is an example Figure 21 Waveform diagram of the driving method of the pixel circuit shown;

[0031] Figure 23 This is an example Figure 21 The circuit diagram shown illustrates the initialization operation of the pixel circuit.

[0032] Figure 24 This is an example Figure 21 The circuit diagram shown illustrates the sampling operation of the pixel circuit.

[0033] Figure 25 This is an example Figure 21 The circuit diagram showing the addressing operation of the pixel circuit is shown.

[0034] Figure 26 This is an example Figure 21 The circuit diagram shown illustrates the sensing operation of the pixel circuit.

[0035] Figure 27 This is a circuit diagram illustrating a pixel circuit according to yet another embodiment of the present disclosure; and

[0036] Figure 28 This is an example Figure 27 The waveform diagram shows the driving method of the pixel circuit. Detailed Implementation

[0037] The advantages and features of this disclosure, and its implementation methods, will become clearer from the embodiments described below with reference to the accompanying drawings. However, this disclosure is not limited to the following embodiments, but can be implemented in various different forms. Rather, these embodiments will make the disclosure complete and allow those skilled in the art to fully understand its scope. This disclosure is limited only by the scope of the appended claims.

[0038] The shapes, dimensions, ratios, angles, quantities, etc., shown in the accompanying drawings to describe embodiments of this disclosure are merely examples, and this disclosure is not limited thereto. Throughout this specification, similar reference numerals generally denote similar elements. Furthermore, in describing this disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of this disclosure.

[0039] Terms such as “including,” “containing,” “having,” and “consisting of” as used herein are generally intended to allow for the addition of other components, unless these terms are used in conjunction with the term “only.” Unless otherwise expressly stated, any reference to the singular may include the plural.

[0040] Even if not explicitly stated, components are interpreted as including the normal error range.

[0041] When using terms such as “on,” “above,” “below,” and “next to” to describe the positional relationship between two components, one or more components may be located between the two components, unless these terms are used with the terms “immediately” or “directly.”

[0042] The terms “first”, “second”, etc., can be used to distinguish components from each other, but the function or structure of a component is not limited by the serial number or component name preceding the component.

[0043] Throughout this disclosure, the same reference numerals may refer to substantially the same elements.

[0044] The following implementations can be partially or wholly combined or integrated with each other, and can be linked and operated in various technical ways. These implementations can be performed independently of each other or in relation to each other.

[0045] In the following, various embodiments of this disclosure will be described in detail with reference to the accompanying drawings.

[0046] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0047] Reference Figure 1 The display device according to the embodiments of the present disclosure includes a display panel 100 and a display panel driving circuit.

[0048] The display panel 100 includes a pixel array AA for displaying an input image. Pixel data of the input image is displayed on pixels 101 of the pixel array AA. The pixel array AA includes multiple data lines 102, multiple gate lines 103 intersecting the data lines 102, and pixels arranged in a matrix. Besides a matrix arrangement, the arrangement of the pixels 101 can also include various forms such as sharing pixels emitting the same color, stripes, diamonds, etc.

[0049] When the resolution of the pixel array AA is n*m, the pixel array AA consists of n pixel columns and m pixel rows L1 to Lm intersecting the pixel columns. Pixel columns include pixels arranged in the y-axis direction. Pixel rows include pixels arranged in the x-axis direction. A horizontal time interval 1H is the number of times a frame time interval is divided into m pixel rows L1 to Lm. Pixel data is written to the pixels of a pixel row within a horizontal time interval 1H.

[0050] To achieve color, each pixel can be divided into red sub-pixels (hereinafter referred to as "R sub-pixels"), green sub-pixels (hereinafter referred to as "G sub-pixels"), and blue sub-pixels (hereinafter referred to as "B sub-pixels"). Each pixel may also include a white sub-pixel. Each sub-pixel 101 includes pixel circuitry. The pixel circuitry includes pixel electrodes, multiple thin-film transistors (TFTs), and capacitors. The pixel circuitry is connected to data line DL and gate line GL.

[0051] A touch sensor can be disposed on the display panel 100 to realize a touch screen. Touch input can be sensed using a separate touch sensor, or it can be sensed by pixels. The touch sensor can be disposed on the screen of the display panel as an on-cell type or an add-on type, or it can be implemented as an in-cell type touch sensor embedded in the pixel array AA.

[0052] The display panel driving circuit includes a data driver 110, a gating driver 120, and a timing controller 130 for controlling the operating timing of the drivers 110 and 120. Under the control of the timing controller (TCON) 130, the display panel driving circuit writes the pixel data (digital data) of the input image to the pixels of the display panel 100.

[0053] Data driver 110 converts the pixel data V-DATA of the input image received as a digital signal from timing controller 130 for each frame into analog gamma-compensated voltages to output data signals Vdata1 to Vdata3. Data driver 110 provides data signals Vdata1 to Vdata3 to data lines DL. Data driver 110 uses a digital-to-analog converter (hereinafter referred to as "DAC") that converts digital signals into analog gamma-compensated voltages to output data signals Vdata1 to Vdata3.

[0054] A gating driver 120 may be formed in a border area BZ of the display panel 100 where no image is displayed. The gating driver 120 receives a gating timing control signal from a level shifter 140 to generate gating signals (or scan signals) GATE1 to GATE3 and provides these gating signals to gating lines GL. The gating signals GATE1 to GATE3 applied to gating lines GL turn on the switching elements of sub-pixels to select the pixels to which the voltages of data signals Vdata1 to Vdata3 are charged. The gating signals GATE1 to GATE3 may be generated as pulse signals oscillating between a gating high voltage VGH and a gating low voltage VGL. The gating driver 120 uses a shift register to shift the gating signals.

[0055] The timing controller 130 multiplies the input frame frequency by i and uses the frame frequency of input frame frequency × i (i is a positive integer greater than 0) Hz to control the timing of the operation of the display panel drive circuit. The input frame frequency is 60 Hz in the NTSC (National Television Standards Committee) scheme and 50 Hz in the PAL (Phase Alternating Line) scheme.

[0056] The timing controller 130 receives pixel data of the input image and timing signals synchronized with it from the host system (not shown). The pixel data of the input image received by the timing controller 130 is a digital signal. The timing controller 130 sends the pixel data to the data driver 110. The timing signals include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a master clock CLK, a data enable signal DE, etc. Because the vertical and horizontal time periods can be determined by counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync can be omitted. The data enable signal DE has a period of one horizontal time period (1H).

[0057] The display panel driving circuit may also include a demultiplexer (DEMUX) 112 disposed between the data driver 110 and the strobe driver 120. The demultiplexer 112 sequentially connects one channel of the data driver 110 to multiple data lines 102 and distributes the data voltage output from one channel of the data driver 110 to the data lines 102 in a time-division manner, thereby reducing the number of channels of the data driver 110.

[0058] The timing controller 130 can generate data timing control signals for controlling the data driver 110, gating timing control signals for controlling the gating driver 120, and MUX control signals for controlling the switching elements of the demultiplexer array (demultiplexer) 112, etc., based on timing signals received from the host system 200. The gating timing control signals may include a start pulse (gating start pulse) VST, a shift clock GCLK, etc. The start pulse VST controls the start timing of the gating driver 120 in each frame period. The shift clock GCLK controls the shift timing of the gating signal output from the gating driver 120. The timing controller 130 can generate control signals for controlling the level shifter 140.

[0059] The host system 200 can be any of a television (TV), set-top box, navigation system, personal computer (PC), home theater, mobile system, and wearable system. In mobile devices and wearable devices, data driver 110, timing controller 130, level shifter 140, etc., can be integrated into a single driver IC (not shown).

[0060] In the mobile system, the host system 200 can be implemented as an application processor (AP). The host system 200 can send pixel data of the input image to the driver IC via a Mobile Industrial Processor Interface (MIPI). The host system 200 can be connected to the driver IC via a flexible printed circuit (e.g., a flexible printed circuit (FPC)).

[0061] Level shifter 140 converts the voltage of the control signal received from timing controller 130. For example, level shifter 140 converts a high logic voltage (or high potential input voltage) of an input signal received as a digital signal voltage level into a gating high voltage VGH, and converts a low logic voltage (or low potential input voltage) of the input signal into a gating low voltage VGL.

[0062] The output signal of the level shifter 140 can be applied to at least one of the demultiplexer array 112, the gating driver 120, the data driver 110, the touch sensor driver, and the power supply unit 400.

[0063] The display device disclosed herein also includes a power supply unit 400.

[0064] The power supply unit 400 generates the DC power required to drive the pixel array AA and display panel driving circuitry of the display panel 100 using a DC-DC converter. The DC-DC converter may include a charge pump, rectifier, buck converter, boost converter, buck-boost converter, etc. The power supply unit 400 adjusts the DC input voltage from the host system 200 to generate DC voltages such as the gamma reference voltage VGMA, gating high voltages VGH and VEH, gating low voltages VGL and VEL, half-VDD (HVDD), and the common voltage of the pixels. The gamma reference voltage VGMA is provided to the data driver 110. The half-VDD voltage is half the voltage of VDD and can be used as the output buffer drive voltage of the source driver IC. The gamma reference voltage VGMA is divided for each grayscale level by a voltage divider circuit and provided to the DAC of the data driver 110.

[0065] Figure 2 This is a circuit diagram illustrating a pixel circuit connected to an external compensation circuit according to the present disclosure.

[0066] Reference Figure 2 The pixel circuit includes a light-emitting element EL, a driving element DT that provides current to the light-emitting element EL, a first switching element M01 that connects to the data line 40 in response to the scan pulse SCAN, a capacitor Cst connected to the gate electrode of the driving element DT, and a second switching element M02 that connects to the reference voltage line 43 in response to the sensing pulse SENSE.

[0067] A pixel driving voltage (i.e., a high-potential voltage EVDD) is applied to the first electrode of the driving element DT through a high-potential voltage line 41. The driving element DT drives the light-emitting element OLED by providing current to the light-emitting element OLED according to the gate-source voltage Vgs. The light-emitting element OLED turns on and emits light when the forward voltage between the anode and cathode is greater than or equal to the threshold voltage. A low-potential voltage EVSS is applied to the cathode of the light-emitting element EL. A capacitor Cst is connected between the gate electrode and the second electrode of the driving element DT to maintain the gate-source voltage Vgs of the driving element DT.

[0068] The first switching element M01 is turned on according to the gating voltage of the scan pulse SCAN applied from the gating line, and connects the data line 40 to the gate electrode of the driving element DT and the capacitor Cst.

[0069] The second switching element M02 applies a reference voltage Vref in response to a scan pulse SCAN or a separate sensing pulse SENSE. The reference voltage Vref is applied to the pixel circuit through reference voltage line 43.

[0070] The light-emitting element (EL) can be implemented as an OLED. An OLED comprises an organic compound layer formed between the anode and cathode. This organic compound layer may include, but is not limited to, a hole injection layer (HIL), a hole transport layer (HTL), an emissive layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). The switching elements M01 and M02 can be implemented as n-channel oxide thin-film transistors (TFTs).

[0071] Organic light-emitting diodes (OLEDs) used as light-emitting elements can have a series structure with multiple light-emitting layers stacked on top of each other. OLEDs with a series structure can improve pixel brightness and lifespan.

[0072] In sensing mode, the current flowing through the channel of the driving element DT or the voltage between the driving element DT and the light-emitting element OLED is sensed via reference voltage line 43. The current flowing through reference voltage line 43 is converted into voltage by an integrator and then into digital data by an analog-to-digital converter (ADC). This digital data is sensing data that includes threshold voltage or mobility information of the driving element DT. The sensing data is sent to the data operation unit. The data operation unit can receive the sensing data from the ADC to compensate for pixel drive deviations and degradation by adding or multiplying a compensation value selected based on the sensing data to the pixel data.

[0073] Figures 3 to 7 This is a diagram used to illustrate the operating principle of the sensing circuit according to the embodiment.

[0074] Reference Figure 3This allows the chip-on-film (COF) to be adhered to the display panel PNL. The COF includes a driver IC (SIC) and connects the source PCB (SPCB) to the display panel PNL. The driver IC (SIC) includes a data driver.

[0075] The timing controller 130 and the power supply unit 150 can be mounted on the control PCB CPCB. The control PCB CPCB can be connected to the source PCB SPCB via a flexible circuit film (e.g., flexible printed circuit (FPC)).

[0076] The timing controller 130 can adjust the reference voltage Vref output from the power supply unit 150 based on the result of comparing the reference voltage Vref_sensed from the display panel PNL with the reference voltage Vref output from the power supply unit 150, by including the aforementioned reference voltage controller.

[0077] The reference voltage Vref output from the power supply unit 150 can be supplied to the display panel PNL via the FPC, source PCB SPCB, and COF. Therefore, in the display panel PNL, the portion IN of the reference voltage Vref is located close to the driver IC SIC.

[0078] Reference voltage lines REFL on the display panel PNL can be connected to the power supply unit 150 via COF, SPCB, and FPC. Reference voltage lines REFL can be grouped by short bars (SB). The short bars can be formed on one side of the display panel PNL and can be formed as glass overlay (LOG) lines on the display panel instead of being formed in the driver IC SIC. Reference voltage lines REFL connected to all pixels on the display panel PNL can be connected to the short bars.

[0079] When the sensing unit 160 is driven in sensing mode after the power is turned off, it senses the current flowing through the pixel power line to which a high potential voltage EVDD is applied. The sensing unit 160 provides the sensed current to the timing controller 130.

[0080] Reference Figure 5 The sensing unit may include a resistor connected to the pixel power line and an analog-to-digital converter (ADC) connected to the resistor. The sensing unit may also include a switch connected between the pixel power line and the resistor. The switch is turned off in display mode and turned on in sensing mode.

[0081] When switch SW is off in display mode, a high-potential voltage EVDD is applied to pixel PXL through the pixel power line. When switch SW is on in sensing mode, a high-potential voltage is applied to the pixel through the pixel power line and resistor R, and the current flowing through the resistor is sensed.

[0082] Reference Figure 4 The sensing unit senses current in units of blocks comprising a predetermined number of pixels. Here, the block can be a square shape in which the number of pixels in the row direction X is the same as the number of pixels in the column direction Y, for example, a square shape of 30 pixels × 30 pixels. The block is not limited to a square shape and can be implemented in various shapes.

[0083] The sensing unit senses current in blocks, and senses the current flowing through each block in a predetermined order. Different currents are sensed based on the characteristics and degradation level of the pixels included in each block.

[0084] Compared to methods that sense current on a pixel-by-pixel basis, methods that sense current on a block-by-block basis can reduce the total sensing time and can be implemented with a simpler structure.

[0085] Reference Figure 6A In this embodiment, when driven in sensing mode, a gate voltage of the sensing pulse SENSE is applied to the second switching element. When the gate voltage is applied, the second switching element is turned on to form a current path that flows through the pixel driving voltage line (high potential voltage line) 41 through the reference voltage line 43 instead of the current path to the light-emitting element. Therefore, current sensing can be performed without emitting light from the light-emitting element.

[0086] Reference Figure 6B In the comparative example, in sensing mode, a gate cutoff voltage of the sensing pulse is applied to the second switching element. Since the second switching element is turned off when the gate cutoff voltage is applied, current flowing through the pixel drive voltage line 41 is applied to the light-emitting element, causing the light-emitting element to emit light. When the light-emitting element emits light after the power is turned off, the user may notice the light.

[0087] Therefore, when driven in sensing mode, the current flowing through the pixel power line can be measured by driving the sensing transistor and changing the current path without making the light-emitting element emit light.

[0088] Reference Figure 7 The embodiment illustrates a pixel structure for sensing current on a block-by-block basis. Reference voltage lines and high-potential voltage lines are connected to all pixels on the display panel for sharing, and data voltage lines are connected to each of the pixels in the column direction Y.

[0089] Therefore, even if the reference voltage and high potential voltage are applied to all pixels on the display panel, the block to be sensed can be selected based on whether data is applied. For example, white data can be applied to all pixels in the first block ONBLK where sensing is performed, and black data can be applied to all pixels in the second block OFFBLK where sensing is not performed.

[0090] Here, while white data is applied to one block on the display panel, black data is applied to the remaining blocks.

[0091] When white data is applied to all pixels in the first block to be sensed, the sensing unit senses the current flowing through the pixel drive voltage lines. In this case, since the current flowing through the pixel drive voltage lines has a large value on a block-by-block basis, an integrator is not required in the sensing unit.

[0092] Figure 8 This is a diagram that schematically illustrates a gating driver according to an embodiment of the present disclosure. Figure 9 This is an example Figure 8 The diagram shows the voltage and input / output signal waveforms of the control node of the gating driver.

[0093] Reference Figure 8 and Figure 9 According to the embodiment, the gating driver 120 includes a plurality of signal processing units ST1, ST2, ST3, ST4 and ST5 cascaded together via carry lines that transmit carry signals.

[0094] The timing controller 130 can use the start pulse Vst input to the gating driver 120 to adjust the width and multiple outputs of the gating driver's output signal SC_OUT.

[0095] Each of the signal processing units STG1, STG2, STG3, STG4, and STG5 receives a start pulse or carry signal and clock signals CLK1, CLK2, CLK3, and CLK4 from the previously odd- or even-numbered signal processing units. The first signal processing unit STG1 is driven starting from the start pulse Vst, and the other signal processing units STG2, STG3, STG4, and STG5 receive carry signals from the previously odd- or even-numbered signal processing units and are then driven.

[0096] Each of the signal processing units STG1, STG2, STG3, STG4, and STG5 outputs a scan signal sequentially by shifting the start pulse or carry signal output from the previously odd-numbered or even-numbered signal processing units according to the timing of the clock signal.

[0097] Figure 10 This is a diagram used to describe a pattern-based driving method according to an embodiment of the present disclosure.

[0098] Reference Figure 10 When driven in display mode, the strobe driver outputs scan signals and sensing signals in sequence, and the data driver outputs image data to display the image.

[0099] When driven in sensing mode after the power is turned off, the strobe driver outputs a high-level voltage sensing signal while sequentially outputting scan signals, and the data driver outputs white data to the block to be sensed and black data to the block not to be sensed to sense current without making the block to be sensed light up.

[0100] Figure 11 This is a diagram illustrating the input / output signals of a level shifter according to an embodiment. Figure 12 This is a diagram illustrating the signal transmission unit of a gating driver according to an embodiment, and Figure 13 This is an example Figure 12 The waveform diagram of the input signal of the signal transmission unit shown.

[0101] Reference Figure 11 According to the embodiment, the level shifter 140 can be mounted on each of the source printed circuit boards (PCBs) SPCB1 and SPCB2. In this case, the level shifter 140 includes a first level shifter 141 mounted on the first source PCB SPCB1 and a second level shifter 142 mounted on the second source PCB SPCB2. The input terminals of level shifters 141 and 142 are connected to the timing controller 130 via lines connecting the control board CPCB, FPC 151, and the source PCBs SPCB1 and SPCB2. The output terminals of level shifters 141 and 142 are connected to the gating driver 120 via lines connecting the source PCBs SPCB1 and SPCB2, the chip-on-film (COF), and the gating driver 120 on the display panel 100.

[0102] Although an example in which the level shifter 140 is mounted on source PCBs SPCB1 and SPCB2 is described herein, this disclosure is not limited thereto, and the level shifter 140 may be mounted on the control board CPCB.

[0103] Reference Figure 12 and Figure 13 Each signal transmission unit of the gating driver according to the embodiment includes a first circuit unit 10 and a second circuit unit 20. The first circuit unit 10 charges or discharges a first control node (hereinafter referred to as the "Q node") and a second control node (hereinafter referred to as the "Qb node").

[0104] In this configuration, the first circuit unit 10 includes a control circuit for controlling the charging and discharging of Q node Q and Qb node Qb, and an inverter circuit for inverting the voltage of Q node Q and applying the voltage to Qb node Qb. The inverter circuit includes a Qb node charging unit and a Qb node discharging unit.

[0105] The second circuit unit 20 outputs a gating signal G_OUT(n) in response to the potentials of Q node Q and Qb node Qb.

[0106] The second circuit unit 20 includes first buffer transistors T1 and T2 that output a gating signal G_OUT(n). The first buffer transistors T1 and T2 are classified as a first pull-up transistor T1 that conducts based on the potential of node Q, and a first pull-down transistor T2 that conducts based on the potential of node Qb. In the first pull-up transistor T1, the gate electrode is connected to node Q, the first electrode is connected to the clock signal line CLK(n), and the second electrode is connected to the first output terminal 70. In the first pull-down transistor T2, the gate electrode is connected to node Qb, the first electrode is connected to the first output terminal 70, and the second electrode is connected to the low-potential voltage line 90. The first buffer transistors T1 and T2 output the gating signal G_OUT(n) based on a clock signal applied through clock signal line 80 and a low-potential voltage applied through low-potential voltage line 90.

[0107] In this configuration, the clock signal voltage and low-potential voltage can vary depending on the pixel circuit mode (e.g., display mode or sensing mode). That is, while sensing the electrical characteristics of the pixel circuit, the clock signal voltage and low-potential voltage can be maintained at the voltages required to turn on the switching elements of the pixel circuit.

[0108] For example, in a display mode where the pixel circuit emits light according to pixel data, the clock signal can swing between high and low voltages and the low potential voltage can be low voltage, while in a sensing mode where the electrical characteristics of the pixel circuit are sensed, the voltage of the clock signal can be maintained at high voltage and the low potential voltage can be high voltage.

[0109] Reference Figure 14 and Figure 15 Each signal transmission unit of the gating driver according to the first embodiment includes a first circuit unit 10 and a second circuit unit 20. The first circuit unit 10 charges or discharges a first control node (hereinafter referred to as the "Q node") and a second control node (hereinafter referred to as the "Qb node").

[0110] In this configuration, the first circuit unit 10 includes a control circuit for controlling the charging and discharging of Q node Q and Qb node Qb, and an inverter circuit for inverting the voltage of Q node Q and applying the voltage to Qb node Qb. The inverter circuit includes a Qb node charging unit and a Qb node discharging unit.

[0111] The second circuit unit 20 includes a second a circuit unit, a second b circuit unit, and a second c circuit unit. The second c circuit unit outputs a carry signal C(n) in response to the potentials of Q node Q and Qb node Qb. The second b circuit unit outputs a scan signal SC_OUT(n) in response to the potentials of Q node Q and Qb node Qb. The second a circuit unit outputs a sensing signal SE_OUT(n) in response to the potentials of Q node Q and Qb node Qb.

[0112] The second c-circuit unit includes third buffer transistors T5 and T6 that output a carry signal C(n). The third buffer transistors T5 and T6 are classified as a third pull-up transistor T5, which conducts based on the potential of node Q, and a third pull-down transistor T6, which conducts based on the potential of node Qb. In the third pull-up transistor T5, the gate electrode is connected to node Q and one end of capacitor C, the first electrode is connected to the first clock signal line 83, and the second electrode is connected to the third output terminal 73 and the other end of capacitor C. In the third pull-down transistor T6, the gate electrode is connected to node Qb, the first electrode is connected to the third output terminal 73 and the other end of capacitor C, and the second electrode is connected to the third low-potential voltage line 93. The third buffer transistors T5 and T6 output the carry signal C(n) based on a first clock signal applied through the first clock signal line 83 and a third low-potential voltage applied through the third low-potential voltage line 93.

[0113] The second b circuit unit includes second buffer transistors T3 and T4 that output scan signals. The second buffer transistors T3 and T4 are classified as a second pull-up transistor T3 that conducts based on the potential of node Q, and a second pull-down transistor T4 that conducts based on the potential of node Qb. In the second pull-up transistor T3, the gate electrode is connected to node Q, the first electrode is connected to the second clock signal line 82, and the second electrode is connected to the second output terminal 72. In the second pull-down transistor T4, the gate electrode is connected to node Qb, the first electrode is connected to the second output terminal 72, and the second electrode is connected to the second low-potential voltage line 92. The second buffer transistors T3 and T4 output scan signals based on a second clock signal applied through the second clock signal line 82 and a second low-potential voltage applied through the second low-potential voltage line 92.

[0114] The second circuit unit a includes first buffer transistors T1 and T2 that output the sensing signal SE_OUT(n). The first buffer transistors T1 and T2 are classified as a first pull-up transistor T1 that conducts based on the potential of node Q, and a first pull-down transistor T2 that conducts based on the potential of node Qb. In the first pull-up transistor T1, the gate electrode is connected to node Q, the first electrode is connected to the third clock signal line 81, and the second electrode is connected to the first output terminal 71. In the first pull-down transistor T2, the gate electrode is connected to node Qb, the first electrode is connected to the first output terminal 71, and the second electrode is connected to the first low-potential voltage line 91. The first buffer transistors T1 and T2 output the sensing signal SE_OUT(n) based on a third clock signal applied through the third clock signal line 81 and a first low-potential voltage applied through the first low-potential voltage line 91.

[0115] In this configuration, since the second b circuit unit and the second a circuit unit share the Q node and Qb node, the third clock signal line 81 and the first low-potential voltage line 91 are set to always output a high-level voltage when outputting SC_OUT(n) and the sensing signal SE_OUT(n). Therefore, the sensing signal SE_OUT(n) is always a high-level voltage during sensing drive.

[0116] Figure 16 This is an example Figure 14 The figure shows the simulation results of the gating driver.

[0117] Reference Figure 16 When the third clock signal line 81 and the first low-potential voltage line 91 are always at a high level, it can be seen that the sensing signal becomes a high level voltage after a predetermined time (e.g., 200μs). That is to say, when driven in sensing mode after the power is turned off, the sensing signal normally outputs a high-level voltage.

[0118] Furthermore, it can be seen that the effective value of the current flowing through the first low-potential voltage line 91, i_rms, is 18mA. The effective value of the current, i_rms, results in minimal power loss in the pixel circuit and therefore is not problematic when measured below 30mA.

[0119] Figure 17 This is a diagram illustrating the signal transmission unit of the gating driver according to the second embodiment, and Figure 18 This is an example Figure 17 The waveform diagram of the input signal of the signal transmission unit shown.

[0120] Reference Figure 17 and Figure 18Each signal transmission unit of the gating driver according to the second embodiment includes a first circuit unit 10 and a second circuit unit 20. The first circuit unit 10 includes a first a circuit unit 21 and a first b circuit unit 11. The first a circuit unit 21 charges or discharges the first a control node (hereinafter referred to as the "SE_Q node") and the second a control node (hereinafter referred to as the "SE_Qb node"). The first b circuit unit 11 charges or discharges the first b control node (hereinafter referred to as the "SC_Q node") and the second b control node (hereinafter referred to as the "SC_Qb node").

[0121] The second circuit unit 20 includes a second a circuit unit 22 and a second b circuit unit 12. The second b circuit unit 12 includes a second b1 circuit unit and a second b2 circuit unit. The second b1 circuit unit outputs a first b carry signal SC_C(n) in response to the potentials of the first b Q node SC_Q and the second b Qb node SC_Qb. The second b2 circuit unit outputs a scan signal SC_OUT(n) in response to the potentials of the first b Q node SC_Q and the second b Qb node SC_Qb.

[0122] The second b1 circuit unit includes third b buffer transistors T5b and T6b that output the first b carry signal SC_C(n). The third b buffer transistors T5b and T6b are classified as a third b pull-up transistor T5b that conducts based on the potential of the first b Q node SC_Q and a third b pull-down transistor T6b that conducts based on the potential of the second b Qb node SC_Qb. In the third b pull-up transistor T5b, the gate electrode is connected to the first b Q node SC_Q and one end of the capacitor C, the first electrode is connected to the third b clock signal line 83b, and the second electrode is connected to the first b output terminal 73b and the other end of the capacitor C. In the third b pull-down transistor T6b, the gate electrode is connected to the second b Qb node SC_Qb, the first electrode is connected to the first b output terminal 73b and the other end of the capacitor C, and the second electrode is connected to the second b low-potential voltage line 93b. The third b buffer transistors T5b and T6b output the first b carry signal SC_C(n) based on the third b clock signal applied through the third b clock signal line 83b and the second b low potential voltage applied through the second b low potential voltage line 93b.

[0123] The second b2 circuit unit includes second buffer transistors T3 and T4 that output the scan signal SC_OUT(n). The second buffer transistors T3 and T4 are classified as a second pull-up transistor T3 that conducts based on the potential of the first bQ node SC_Q and a second pull-down transistor T4 that conducts based on the potential of the second bQb node SC_Qb. In the second pull-up transistor T3, the gate electrode is connected to the first bQ node SC_Q, the first electrode is connected to the second clock signal line 82, and the second electrode is connected to the second output terminal 72. In the second pull-down transistor T4, the gate electrode is connected to the second bQb node SC_Qb, the first electrode is connected to the second output terminal 72, and the second electrode is connected to the first b low-potential voltage line 92. The second buffer transistors T3 and T4 output the scan signal SC_OUT(n) based on a second clock signal applied through the second clock signal line 82 and a first b low-potential voltage applied through the first b low-potential voltage line 92.

[0124] The second a circuit unit 22 includes a second a1 circuit unit and a second a2 circuit unit. The second a2 circuit unit outputs a first a carry signal SE_C(n) in response to the potentials of the first a Q node SE_Q and the second a Qb node SE_Qb. The second a1 circuit unit outputs a sensing signal SE_OUT(n) in response to the potentials of the first b Q node SE_Q and the second b Qb node SE_Qb.

[0125] The second a2 circuit unit includes third a buffer transistors T5b and T6b that output the first a carry signal SE_C(n). The third a buffer transistors T5b and T6b are classified as a third a pull-up transistor T5b that conducts based on the potential of the first a Q node SE_Q and a third a pull-down transistor T6b that conducts based on the potential of the second a Qb node SE_Qb. In the third a pull-up transistor T5b, the gate electrode is connected to the first a Q node SE_Q and one end of the capacitor C, the first electrode is connected to the third a clock signal line 83a, and the second electrode is connected to the third a output terminal 73b and the other end of the capacitor C. In the third a pull-down transistor T6b, the gate electrode is connected to the second a Qb node SE_Qb, the first electrode is connected to the third a output terminal 73b and the other end of the capacitor C, and the second electrode is connected to the second a low-potential voltage line 93a. The third a buffer transistors T5b and T6b output the first a carry signal SE_C(n) based on the third a clock signal applied through the third a clock signal line 83a and the second a low potential voltage applied through the second a low potential voltage line 93a.

[0126] The second a1 circuit unit includes first buffer transistors T1 and T2 that output a sensing signal SE_OUT(n). The first buffer transistors T1 and T2 are classified as a first pull-up transistor T1 that conducts based on the potential of the first aQ node SE_Q and a first pull-down transistor T2 that conducts based on the potential of the second aQb node SE_Qb. In the first pull-up transistor T1, the gate electrode is connected to the first aQ node SE_Q, the first electrode is connected to the first clock signal line 81, and the second electrode is connected to the first output terminal 71. In the first pull-down transistor T2, the gate electrode is connected to the second aQb node SE_Qb, the first electrode is connected to the first output terminal 71, and the second electrode is connected to the first a low-potential voltage line 91. The first buffer transistors T1 and T2 output the sensing signal SE_OUT(n) based on a first clock signal applied through the first clock signal line 81 and a first low-potential voltage applied through the first low-potential voltage line 91.

[0127] In this configuration, since the second a1 circuit unit is in a state where the second aQb node maintains a high-level voltage after the power is turned off, the first low-level voltage line 91 is set to always maintain a high-level voltage. On the other hand, the first clock signal line 81 can be any of a high-level voltage, a low-level voltage, or a clock signal. In terms of power consumption, the first clock signal line 81 can have a low-level voltage. Therefore, during the sensing drive, the sensing signal SE_OUT(n) is always a high-level voltage, regardless of the first clock signal line 81.

[0128] Figure 19 This is a diagram illustrating the signal transmission unit of the gating driver according to the third embodiment. Figure 20 This is an example Figure 19 The waveform diagram of the input signal of the signal transmission unit shown.

[0129] Reference Figure 19 and Figure 20 The gating driver according to the third embodiment includes a first circuit unit 10 and a second circuit unit 20. The first circuit unit 10 includes a first a circuit unit 21 and a first b circuit unit 11. The first a circuit unit 21 charges or discharges the first a control node (hereinafter referred to as the "SE_Q node") and the second a control node (hereinafter referred to as the "SE_Qb node"). The first b circuit unit 11 charges or discharges the first b control node (hereinafter referred to as the "SC_Q node") and the second b control node (hereinafter referred to as the "SC_Qb node").

[0130] The second circuit unit 20 includes a second a circuit unit 22 and a second b circuit unit 12. The second b circuit unit 12 outputs a scan signal SC_OUT(n) in response to the potentials of the first b Q node SC_Q and the second b Qb node SC_Qb. These scan signals SC_OUT(n) also serve as the first b carry signal. The second a circuit unit 22 outputs a sensing signal SE_OUT(n) in response to the potentials of the first a Q node SE_Q and the second aQb node SE_Qb. These sensing signals SE_OUT(n) also serve as the first a carry signal.

[0131] The second b circuit unit 12 includes second buffer transistors T3 and T4 that output a scan signal SC_OUT(n). The second buffer transistors T3 and T4 are classified as a second pull-up transistor T3 that conducts based on the potential of the first b Q node SC_Q and a second pull-down transistor T4 that conducts based on the potential of the second b Qb node SC_Qb. In the second pull-up transistor T3, the gate electrode is connected to the first b Q node SC_Q, the first electrode is connected to the second clock signal line 82, and the second electrode is connected to the second output terminal 72. In the second pull-down transistor T4, the gate electrode is connected to the second b Qb node SC_Qb, the first electrode is connected to the second output terminal 72, and the second electrode is connected to the first b low-potential voltage line 92. The second buffer transistors T3 and T4 output the scan signal SC_OUT(n) based on a second clock signal applied through the second clock signal line 82 and a first b low-potential voltage applied through the first b low-potential voltage line 92.

[0132] The second a circuit unit 22 includes first buffer transistors T1 and T2 that output a sensing signal SE_OUT(n). The first buffer transistors T1 and T2 are classified as a first pull-up transistor T1 that conducts based on the potential of the first a Q node SE_Q and a first pull-down transistor T2 that conducts based on the potential of the second a Qb node SE_Qb. In the first pull-up transistor T1, the gate electrode is connected to the first a Q node SE_Q, the first electrode is connected to the first clock signal line 81, and the second electrode is connected to the first output terminal 71. In the first pull-down transistor T2, the gate electrode is connected to the second a Qb node SE_Qb, the first electrode is connected to the first output terminal 71, and the second electrode is connected to the first a low-potential voltage line 91. The first buffer transistors T1 and T2 output the sensing signal SE_OUT(n) based on a first clock signal applied through the first clock signal line 81 and a first a low-potential voltage applied through the first a low-potential voltage line 91.

[0133] In this configuration, since the carry signal and the sensing signal are integrated, and therefore the first clock signal is used as the first carry signal when the second a circuit unit outputs the sensing signal SE_OUT(n), the first clock signal line 81 and the first a low-potential voltage line 91 are set to always output a high-level voltage. Therefore, the sensing signal SE_OUT(n) is always a high-level voltage during sensing drive.

[0134] Figure 21 This is a circuit diagram illustrating a pixel circuit according to another embodiment of the present disclosure. Figure 21 The pixel circuit shown includes an internal compensation circuit that compensates for changes in the threshold voltage of the driving element DT by sampling the threshold voltage of the driving element DT. Figure 22 This is an example Figure 21 The waveform diagram shows the driving method of the pixel circuit.

[0135] Reference Figure 21 and Figure 22 The pixel circuit includes a light-emitting element EL, a driving element DT, a first capacitor C1 and a second capacitor C2, and first switching elements T1 to eighth switching elements T8. The driving element DT and the switching elements T1 to T8 can be implemented as an n-channel oxide TFT.

[0136] DC voltages such as pixel drive voltage VDD, low-potential supply voltage VSS, reference voltage Vref, and initialization voltage Vinit; data voltage Vdata that varies according to the grayscale level of the pixel data; scan pulses SC1, SC2, and SC3; and EM pulses EM1 and EM2 are supplied to the pixel circuit. The voltages of scan pulses SC1, SC2, and SC3, and the voltages of EM pulses EM1 and EM2, oscillate between gating on voltages VGH and VEH and gating off voltages VGL and VEL.

[0137] The voltage relationship applied to the pixel can typically be set as VDD > Vref > Vinit > VSS. The data voltage Vdata can be generated as a gamma compensation voltage selected based on the grayscale level of the pixel data from the data driver 110, within a voltage range below the pixel drive voltage VDD and above the low-potential supply voltage VSS. The initialization voltage Vinit can be set to a voltage below or equal to the threshold voltage of the light-emitting element EL. The reference voltage Vref can be set to a voltage greater than the initialization voltage Vinit, such that a negative reverse bias is applied to the driving element DT during the sampling operation SMPL. The gating on voltages VGH and VEH can be set to be greater than the pixel drive voltage VDD. The gating off voltages VGL and VEL can be set to be lower than the low-potential supply voltage VSS.

[0138] Scan pulses SC1, SC2, and SC3 may include a first scan pulse SC1 applied to a first gate line GL1, a second scan pulse SC2 applied to a second gate line GL2, and a third scan pulse SC3 applied to a third gate line GL3. EM pulses EM1 and EM2 may include a first EM pulse EM1 applied to a fourth gate line GL4 and a second EM pulse EM2 applied to a fifth gate line GL5.

[0139] The driving period of the pixel circuit can be divided into the initialization operation INIT, the sampling operation SMPL, the addressing operation ADDR, the charging operation ADDR, and the sensing operation SENS, which senses the electrical characteristics of the pixel circuit (i.e., the current flowing through the pixel power line).

[0140] The first scan pulse SC1 can be the turn-on voltage VGH in the addressing operation ADDR. The first scan pulse SC1 can be the turn-off voltage VGL in the initialization operation INIT, sampling operation SMPL, and sensing operation SENS. The first scan pulse SC1 can be generated as a pulse of horizontal duration 1H less than or equal to the data voltage Vdata of the pixel data. In the addressing operation ADDR synchronized with the first scan pulse SC1, the data voltage Vdata is supplied to the pixel circuit via the data line DL.

[0141] The second scan pulse SC2 can rise to the gating on-state voltage VGH before the third scan pulse SC3, and can fall to the gating off-state voltage VGL before the falling edge of the third scan pulse SC3. The second scan pulse SC2 can be the gating on-state voltage VGH in the initialization operation INIT and the sampling operation SMPL. The second scan pulse SC2 can be the gating off-state voltage VGL in the addressing operation ADDR and the sensing operation SENS.

[0142] The third scan pulse SC3 can be generated as the gating voltage VGH in the sampling operation SMPL and the addressing operation ADDR. In the addressing operation ADDR, the gating voltage segment of the third scan pulse SC3 can overlap with the gating voltage segment of the first scan pulse SC1. The third scan pulse SC3 can rise to the gating voltage VGH after the rising edge of the second scan pulse SC2, and then fall to the gating cutoff voltage after the falling edge of the second scan pulse SC2VGL. The third scan pulse SC3 can be the gating cutoff voltage VGL in the initialization operation INIT and the sensing operation SENS.

[0143] The first EM pulse EM1 can be generated as a gating on-state voltage VGH in the initialization operation INIT, and can be generated as a gating on-state voltage VEH in at least a portion of the sensing operation SENS. The first EM pulse EM1 can be a gating off-state voltage VEL in the sampling operation INIT and the addressing operation ADDR. The first EM pulse EM1 can drop to the gating off-state voltage VEL after the falling edge of the second EM pulse EM2, and can rise to the gating on-state voltage VEH before the rising edge of the second EM pulse EM2.

[0144] The second EM pulse EM2 can be generated as a gating on-state voltage VEH in at least a portion of the sensing operation SENS. The second EM pulse EM2 can be a gating off-state voltage VEL in the initialization operation INIT, the sampling operation INIT, and the addressing operation ADDR.

[0145] In at least a portion of the sensing operation SENS, the third EM pulse EM3 can be generated as a gating on-state voltage VEH. The third EM pulse EM3 can also be a gating off-state voltage VEL in the initialization operation INIT, the sampling operation INIT, and the addressing operation ADDR.

[0146] The light-emitting element EL can be implemented as an organic light-emitting diode (OLED). The anode of the light-emitting element EL can be connected to the fourth node n4, and a low-potential power supply voltage VSS can be applied to the cathode of the light-emitting element EL.

[0147] The first capacitor C1 can be connected between the second node n2 and the fifth node n5. The first capacitor C1 stores the threshold voltage Vth of the driving element DT during the sampling operation SMPL. During the addressing operation ADDR, the data voltage Vdata is sent to the first gate electrode of the driving element DT through the first capacitor C1.

[0148] The second capacitor C2 is connected between the third node n3 and the fifth node n5. The second capacitor C2 stores the second electrode voltage (i.e., the source voltage) of the driving element DT at the beginning of the sensing operation SENS, and maintains the gate-source voltage Vgs of the driving element during the sensing operation SENS.

[0149] The driving element DT can be a metal-oxide-semiconductor field-effect transistor (MOSFET) with a dual-gate structure. The driving element DT includes a first gate electrode connected to a second node n2, a second gate electrode connected to a fourth node n4, a first electrode connected to a first node n1, and a second electrode connected to a third node n3. The first and second gate electrodes of the driving element DT can overlap each other, and a semiconductor active pattern ACT is located therebetween.

[0150] The first switching element T1 includes a first electrode connected to a first node n1, a second electrode connected to a second node n2, and a gate electrode to which a second scan pulse SC2 is applied. The first switching element T1 is turned on in response to the gating voltage VGH of the second scan pulse SC2 during the initialization operation INIT and the sampling operation SMPL to connect the first node n1 and the second node n2. When the first switching element T1 is turned on, the driving element DT operates as a diode due to the connection between the first gate electrode and the second electrode.

[0151] The second switching element T2 includes a first electrode connected to the third node n3, a second electrode connected to the fourth node n4, and a gate electrode to which a second EM pulse EM2 is applied. The second switching element T2 is turned on in at least a portion of the sensing operation SENS in response to the gate voltage VEH of the second EM pulse EM2, thereby forming a current path between the driving element DT and the light-emitting element EL. During the initialization operation INIT, sampling operation SMPL, and addressing operation ADDR, when the second switching element T2 is in the off state, the light-emitting element EL does not emit light because the current path between the driving element DT and the light-emitting element EL is cut off.

[0152] The third switching element T3 includes a first electrode connected to a second power supply line INL to which an initialization voltage Vinit is applied, a second electrode connected to a fifth node n5, and a gate electrode to which a second scan pulse SC2 is applied. The third switching element T3 is turned on in response to the gating voltage VGH of the second scan pulse SC2 during the initialization operation INIT and the sampling operation SMPL, to provide the initialization voltage Vinit to the fifth node n5. During the addressing operation ADDR and the sensing operation SENS, in which the third switching element T3 is turned off, the current path between the second power supply line INL and the fifth node n5 is interrupted.

[0153] The fourth switching element T4 includes a first electrode connected to a data line DL to which a data voltage Vdata is applied, a second electrode connected to a fifth node n5, and a gate electrode to which a first scan pulse SC1 is applied. The fourth switching element T4 is turned on in addressing operation ADDR in response to the gating voltage VGH of the first scan pulse SC1, to provide the data voltage Vdata to the fifth node n5. During the initialization operation INIT, sampling operation SMPL, and sensing operation SENS, when the fourth switching element T4 is turned off, the current path between the data line DL and the fifth node n5 is interrupted.

[0154] The fifth switching element T5 includes a first electrode connected to a first power line VDDL to which a pixel driving voltage VDD is applied, a second electrode connected to a first node n1, and a gate electrode to which a first EM pulse EM1 is applied. The fifth switching element T5 is turned on in the initialization operation INIT and the sensing operation SENS in response to the gating voltage VEH of the first EM pulse EM1, to provide the pixel driving voltage VDD to node n1. In the sampling operation SMPL and the addressing operation ADDR, where the fifth switching element T5 is turned off, the current path between the first power line VDDL and the first node n1 is cut off.

[0155] The sixth switching element T6 includes a first electrode connected to the third node n3, a second electrode connected to the third power supply line (reference voltage line) REFL to which a reference voltage Vref is applied, and a gate electrode to which a third scan pulse SC3 is applied. The sixth switching element T6 is turned on in the sampling operation SMPL and the addressing operation ADDR in response to the gating voltage VGH of the third scan pulse SC3, so as to provide the reference voltage Vref to the third node n3. In the initialization operation INIT and the sensing operation SENS, in which the sixth switching element T6 is turned off, the current path between the third power supply line REFL and the third node n3 is interrupted.

[0156] The seventh switching element T7 includes a first electrode connected to a second power supply line INL to which an initialization voltage Vinit is applied, a second electrode connected to a fourth node n4, and a gate electrode to which a third scan pulse SC3 is applied. The seventh switching element T7 is turned on in response to the gating voltage VGH of the third scan pulse SC3 during the sampling operation SMPL and the addressing operation ADDR, to provide the initialization voltage Vinit to the fourth node n4. When the seventh switching element T7 is on, the reference voltage Vref is applied to the third node n3 through the sixth switching element T6. During the initialization operation INIT and the sensing operation SENS when the seventh switching element T7 is off, the current path between the second power supply line INL and the fourth node n4 is interrupted.

[0157] The eighth switching element T8 includes a first electrode connected to the fourth node n4, a second electrode connected to the fourth power line VSSL which is supplied with a low-potential power supply voltage VSS, and a gate electrode supplied with a third EM pulse EM3. The eighth switching element T8 is turned on in sensing operation SENS in response to the gate voltage VEH of the third EM pulse EM3, so as to form a current path between the fourth node n4 and the fourth power line VSSL.

[0158] In this disclosure, the threshold voltage Vth of the driving element DT is sampled by applying a reference voltage Vref to the third node n3 in the sampling operation SMPL, and the data voltage Vdata is applied to the fifth node n5 in the addressing operation ADDR. Therefore, according to this disclosure, the offset of the threshold voltage Vth' of the driving element DT can be accurately sensed by ensuring that the sampling operation SMPL lasts for a sufficiently long time (e.g., two or more horizontal time periods).

[0159] In the following text, reference will be made to Figures 23 to 26 Describe in detail the driving method used for the operation of pixel circuits.

[0160] Figure 23 This is an example Figure 21 The circuit diagram shown is for the initialization operation INIT of the pixel circuit.

[0161] Reference Figure 23 In the initialization operation INIT, the second scan pulse SC2 and the first EM pulse EM1 are generated as the gating voltages VGH and VEH, and the other gating signals SC1, SC3, and EM2 are the gating cutoff voltages VGL and VEL. In the initialization operation INIT, the second switching element T2, the fourth switching element T4, the sixth switching element T6, and the seventh switching element T7 are turned off. Therefore, in the initialization operation INIT, the first switching element T1, the third switching element T3, the fifth switching element T5, and the drive element DT are turned on. In this case, the first gate electrode and the first electrode of the drive element DT are connected via a diode connection.

[0162] In the initialization operation INIT, the voltages of the first node n1 and the second node n2 are initialized to the pixel driving voltage VDD, and the voltage of the third node n3 becomes VDD-Vth0. Here, Vth0 is the initial threshold voltage before Vbs are applied to the driving element DT. The voltage of the fifth node n5 is the initialization voltage Vinit. The voltage of the fourth node n4 remains at the initialization voltage Vinit applied to the previous frame.

[0163] Figure 24 This is an example Figure 21 The circuit diagram shown is for the sampling operation SMPL of the pixel circuit.

[0164] Reference Figure 24In the sampling operation SMPL, the third scan pulse SC3 is inverted to become the gating on-state voltage VGH, and the first EM pulse EM1 is inverted to become the gating off-state voltage VEL. The second scan pulse SC2 maintains the gating on-state voltage VGH during the sampling operation SMPL. During the sampling operation SMPL, the second scan pulse SC2 and the third scan pulse SC3 are the gating on-state voltage VGH, while the other gating signals SC1, EM1, and EM2 are the gating off-state voltages VGL and VEL, respectively. Therefore, during the sampling operation SMPL, the first switching element T1, the third switching element T3, the sixth switching element T6, the seventh switching element T7, and the drive element DT are turned on.

[0165] In the sampling operation SMPL, the initialization voltage Vinit is applied to the second gate electrode G2 of the drive element DT through the switched-on seventh switch element T7, and a reference voltage Vref greater than the initialization voltage Vinit is applied to the second electrode of the drive element DT through the switched-on sixth switch element T6. Therefore, since Vbs can be applied to the drive element, the threshold voltage of the drive element DT can be shifted to a positive voltage greater than zero.

[0166] In the sampling operation SMPL, the voltages of the first node n1 and the second node n2 become Vref + Vth0 + α. Here, α equals β(Vref - Vinit), and β equals Cbuf / Cgi. The voltage of the third node n3 is the reference voltage Vref, and the voltages of the fourth node n4 and the fifth node n5 are maintained at the initialization voltage Vinit.

[0167] Figure 25 This is an example Figure 21 The circuit diagram shown is for the addressing operation ADDR of the pixel circuit.

[0168] Reference Figure 25 In the addressing operation ADDR, the first scan pulse SC1, synchronized with the pixel data voltage Vdata, is generated as the gating voltage VGH. In the addressing operation ADDR, the third scan pulse SC3 is maintained at the gating voltage VGH and then inverted to become the gating voltage VGL. In the addressing operation ADDR, the first EM pulse EM1 is maintained at the gating voltage VEL and then inverted to become the gating voltage after the falling edge of the first scan pulse SC1. In the addressing operation ADDR, the second scan pulse SC2 is inverted to become the gating voltage VGL. In the addressing operation ADDR, the voltages of the first EM pulse EM1 and the second EM pulse EM2 can be the gating voltage VEL. Therefore, in the addressing operation ADDR, the fourth switching element T4, the sixth switching element T6, the seventh switching element T7, and the drive element DT are turned on.

[0169] In the addressing operation ADDR, the voltage of the first node n1 is maintained at Vref + Vth0 + α, while the voltage of the second node n2 becomes Vref + Vth0 + α + C'(Vdata - Vinit). Here, C' can be expressed as C' = C1 / (C1 + Cpar). "Cpar" is the parasitic capacitance connected to the first gate electrode of the driving element DT. When Cpar is 0, the data transmission rate is high because C' is 1, and the data transmission rate decreases as Cpar increases. The voltage of the third node n3 is the reference voltage Vref, and the voltages of the fourth node n4 and the fifth node n5 are maintained at the initialization voltage Vinit.

[0170] Figure 26 This is an example Figure 21 The diagram shows the sensor operation (SENS) circuit of the pixel circuit.

[0171] Reference Figure 26 When driven in sensing mode after the power is turned off, the voltages of the scan pulses SC1, SC2, and SC3 in the sensing operation SENS are the gate cutoff voltage VGL. In at least some sections of the sensing operation SENS, the first EM pulse EM1 and the second EM pulse EM2 are generated as the gate turn-on voltage VEH. Therefore, in the sensing operation SENS that senses the electrical characteristics of the pixel circuit, the driving element DT and the second switching element T2, the fifth switching element T5, and the eighth switching element T8 are turned on, and the first switching element T1, the third switching element T3, the fourth switching element T4, the sixth switching element T6, and the seventh switching element T7 are turned off.

[0172] In this case, since the current flowing through the pixel voltage line forms a current path through the low voltage line and not through the light-emitting element EL, the light-emitting element EL can be turned off.

[0173] Figure 27 This is a circuit diagram illustrating a pixel circuit according to yet another embodiment of the present disclosure. Figure 28 This is an example Figure 27 The waveform diagram shows the driving method of the pixel circuit.

[0174] Reference Figure 27 and Figure 28 The pixel circuit includes a light-emitting element EL, a driving element DT, a first capacitor C1 and a second capacitor C2, and first switching elements T1 to eighth switching elements T8. The driving element DT and the switching elements T1 to T8 can be implemented as an n-channel oxide TFT.

[0175] In addition to the eighth switching element, the pixel circuit here can have the same... Figure 21 The pixel circuit shown has the same switching element configuration and can have the same... Figure 21 The pixel circuit shown has the same function.

[0176] The eighth switching element T8 includes a first electrode connected to the third node n3, a second electrode connected to the current sensing line VSC, and a gate electrode to which a fourth scan pulse SC4 is applied. The eighth switching element T8 is turned on in sensing operation SENS in response to the gating voltage VEH of the fourth scan pulse SC4, so as to form a current path between the third node n3 and the current sensing line VSC.

[0177] Here, as Figure 5 The sensing unit shown can be connected to the current sensing line VSC in addition to the pixel power line, so that the current flowing through the current sensing line VSC can be sensed.

[0178] In this disclosure, when the display device is driven in sensing mode after the power is turned off, the light emission of the light-emitting element can be suppressed by sensing the current flowing through the pixel driving voltage line while the current flowing through the power line to which the pixel driving voltage is applied forms a path bypassing the light-emitting element as a current path.

[0179] In this disclosure, when driven in sensing mode, the visibility problem can be solved because the light emission of the light-emitting element is suppressed.

[0180] Although embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited thereto and may be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the embodiments disclosed herein are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above embodiments are illustrative in all respects and are not limiting of the present disclosure. The scope of protection of the present disclosure should be interpreted based on the appended claims, and all technical concepts within the equivalent scope thereof should be interpreted as falling within the scope of the present disclosure.

[0181] Cross-references to related applications

[0182] This application claims priority and benefit to Korean Patent Application No. 10-2021-0090008, filed on July 8, 2021, and Korean Patent Application No. 10-2021-0171603, filed on December 3, 2021, the entire disclosure of which is incorporated herein by reference.

Claims

1. A gate driver comprising: a first circuit unit configured to charge or discharge voltages of a first control node and a second control node in accordance with an input signal; and a second circuit unit configured to transmit a first clock signal and a first potential voltage to a first output node in accordance with the voltages of the first control node and the second control node to output a gate signal to the first output node, wherein the voltage of the first clock signal and the first potential voltage vary in accordance with a mode of a pixel circuit, and wherein the voltage of the first clock signal and the first potential voltage are maintained at voltages set to conditions in which a switching element of the pixel circuit is turned on in a sensing mode in which electrical characteristics of the pixel circuit are sensed.

2. The gate driver of claim 1, wherein, the switching element of the pixel circuit includes a first electrode connected to an anode of a light emitting element of the pixel circuit, a second voltage to which a preset voltage is applied, and a gate electrode connected to the first output node.

3. The gated driver of claim 2, wherein, the preset voltage is a reference voltage or a low potential power voltage.

4. The gated driver of claim 1, wherein, in a display mode in which the pixel circuit emits light in accordance with pixel data, the first clock signal oscillates between a high voltage and a low voltage, and the first potential voltage is the low voltage, and in the sensing mode in which the electrical characteristics of the pixel circuit are sensed, the voltage of the first clock signal is maintained at the high voltage and the first potential voltage is the high voltage.

5. The gated driver of claim 1, wherein, the second circuit unit includes: a first buffer transistor including a gate connected to the first control node, a first electrode to which the first clock signal is applied, and a second electrode connected to the first output node; and a second buffer transistor including a gate connected to the second control node, a first electrode connected to the first output node, and a second electrode to which the first potential voltage is applied.

6. The gated driver of claim 1, wherein, the gate signal includes a sensing signal and a scan signal, and the second circuit unit includes: a second a circuit unit configured to transmit the first clock signal and the first potential voltage to the first output node in accordance with the voltages of the first control node and the second control node to output the sensing signal to the first output node; a second b circuit unit configured to transmit a second clock signal and a second low potential voltage to a second output node in accordance with the voltages of the first control node and the second control node to output the scan signal to the second output node; and a second c circuit unit configured to transmit a third clock signal and a third low potential voltage to a third output node in accordance with the voltages of the first control node and the second control node to output a carry signal to the third output node.

7. The gated driver of claim 6, wherein, in the sensing mode in which the electrical characteristics of the pixel circuit are sensed, the voltage of the first clock signal is maintained at a high voltage and the first potential voltage is the high voltage.

8. The gated driver of claim 1, wherein, the first control node includes a first a control node and a first b control node, The second control nodes include a second a control node and a second b control node, and The first circuit unit includes: a first a circuit unit configured to charge or discharge the first a control node and the second a control node; and a first b circuit unit configured to charge or discharge the first b control node and the second b control node.

9. The gate driver of claim 8, wherein, The selection signal includes a sensing signal and a scan signal, and The second circuit unit includes: a second a circuit unit having a second a1 circuit unit configured to transmit the first clock signal and the first potential voltage to the first output node to output the sensing signal to the first output node according to voltages of the first a control node and the second a control node, and a second a2 circuit unit configured to transmit a third a clock signal and a third a low potential voltage to a third a output node to output a first a carry signal to the third a output node; and a second b circuit unit having a second b1 circuit unit configured to transmit a second clock signal and a second low potential voltage to a second output node to output the scan signal to the second output node according to voltages of the first b control node and the second b control node, and a second b2 circuit unit configured to transmit a third b clock signal and a third b low potential voltage to a third b output node to output a first b carry signal to the third b output node.

10. The gate driver of claim 9, wherein, In the sensing mode in which the electrical characteristics of the pixel circuit are sensed, the first potential voltage is a high voltage.

11. The gated driver of claim 8, wherein, The selection signal includes a sensing signal and a scan signal, and The second circuit unit includes: a second a circuit unit configured to transmit the first clock signal and the first potential voltage to the first output node to output the sensing signal and a first a carry signal to the first output node according to voltages of the first a control node and the second a control node; and a second b circuit unit configured to transmit a second clock signal and a second low potential voltage to a second output node to output the scan signal and a first b carry signal to the second output node according to voltages of the first b control node and the second b control node.

12. The gate driver of claim 11, wherein, In the sensing mode in which the electrical characteristics of the pixel circuit are sensed, a voltage of the first clock signal is maintained at a high voltage and the first potential voltage is the high voltage.

13. A display device comprising: a data driver configured to output a data voltage; a gate driver including a first circuit unit configured to charge or discharge voltages of first and second control nodes according to an input signal, and a second circuit unit configured to transmit a first clock signal and a first potential voltage to a first output node according to the voltages of the first and second control nodes to output a gate signal to the first output node; and a plurality of pixel circuits configured to receive the data voltage and the gate signal to reproduce an input image, wherein the voltage of the first clock signal and the first potential voltage vary according to a mode of the pixel circuit, and wherein the voltage of the first clock signal and the first potential voltage maintain voltages set as conditions in which a switching element of the pixel circuit is turned on in a sensing mode in which electrical characteristics of the pixel circuit are sensed.

14. The display device according to claim 13, further comprising: a sensing unit configured to sense a current flowing through a pixel power line in the sensing mode in which the electrical characteristics of the pixel circuit are sensed.

15. The display device of claim 14, wherein, The sensing unit includes: a resistor connected to the pixel power line; an analog-to-digital converter (ADC) connected to the resistor; and a switch connected between the pixel power line and the resistor.

16. The display device of claim 15, wherein, The switch is turned off in a display mode in which the pixel circuit emits light according to pixel data, and is turned on in the sensing mode.

17. The display device of claim 14, wherein, The plurality of pixel circuits are grouped into two or more blocks, and the sensing unit is configured to sense the current in units of blocks.

18. The display device of claim 17, wherein, White data is applied to all pixels in one block in which sensing is performed among the two or more blocks, and black data is applied to all pixels in a remaining block in which the sensing is not performed.

19. The display device of claim 13, wherein, The switching element of the pixel circuit includes a first electrode connected to an anode of a light emitting element of the pixel circuit, a second voltage to which a preset voltage is applied, and a gate electrode connected to the first output node.

20. The display device of claim 19, wherein, The preset voltage is a reference voltage or a low potential power voltage.

21. The display device of claim 13, wherein, In the display mode in which the pixel circuit emits light according to pixel data, the first clock signal swings between a high voltage and a low voltage, and the first potential voltage is the low voltage, and In the sensing mode in which the electrical characteristics of the pixel circuit are sensed, the voltage of the first clock signal maintains the high voltage and the first potential voltage is the high voltage.

22. The display device of claim 13, wherein, The second circuit unit includes: a first buffer transistor including a gate connected to the first control node, a first electrode to which the first clock signal is applied, and a second electrode connected to the first output node; and a second buffer transistor including a gate connected to the second control node, a first electrode connected to the first output node, and a second electrode to which the first potential voltage is applied.

23. The display device of claim 13, wherein, The gate signal includes a sensing signal and a scan signal, and The second circuit unit includes: a second a circuit unit configured to transmit, according to voltages of the first control node and the second control node, the first clock signal and the first potential voltage to the first output node to output the sensing signal to the first output node; a second b circuit unit configured to transmit, according to voltages of the first control node and the second control node, a second clock signal and a second low potential voltage to a second output node to output the scan signal to the second output node; and a second c circuit unit configured to transmit, according to voltages of the first control node and the second control node, a third clock signal and a third low potential voltage to a third output node to output a carry signal to the third output node.

24. The display device of claim 23, wherein, In the sensing mode in which the electrical characteristics of the pixel circuit are sensed, the voltage of the first clock signal is maintained at a high voltage and the first potential voltage is the high voltage.

25. The display device of claim 13, wherein, The first control node includes a first a control node and a first b control node, The second control node includes a second a control node and a second b control node, and The first circuit unit includes: a first a circuit unit configured to charge or discharge the first a control node and the second a control node; and a first b circuit unit configured to charge or discharge the first b control node and the second b control node.

26. The display device of claim 25, wherein, The selection signal includes a sensing signal and a scan signal, and The second circuit unit includes: a second a circuit unit having a second a1 circuit unit configured to transmit, according to voltages of the first a control node and the second a control node, the first clock signal and the first potential voltage to the first output node to output the sensing signal to the first output node, and a second a2 circuit unit configured to transmit a third a clock signal and a third a low potential voltage to a third a output node to output a first a carry signal to the third a output node; and a second b circuit unit having a second b1 circuit unit configured to transmit, according to voltages of the first b control node and the second b control node, a second clock signal and a second low potential voltage to a second output node to output the scan signal to the second output node, and a second b2 circuit unit configured to transmit a third b clock signal and a third b low potential voltage to a third b output node to output a first b carry signal to the third b output node.

27. The display device of claim 26, wherein, In the sensing mode in which the electrical characteristics of the pixel circuit are sensed, the first potential voltage is a high voltage.

28. The display device of claim 25, wherein, The selection signal includes a sensing signal and a scan signal, and The second circuit unit includes: a second a circuit unit configured to transmit the first clock signal and the first potential voltage to the first output node according to voltages of the first a control node and the second a control node to output the sensing signal and a first a carry signal to the first output node; and a second b circuit unit configured to transmit a second clock signal and a second low potential voltage to a second output node according to voltages of the first b control node and the second b control node to output the scan signal and a first b carry signal to the second output node.

29. The display device of claim 28, wherein, In the sensing mode in which the electrical characteristics of the pixel circuit are sensed, the voltage of the first clock signal is maintained at a high voltage and the first potential voltage is the high voltage.

30. The display device of claim 13, wherein, The pixel circuit includes: a drive element having a gate connected to a first node, a first electrode to which a high potential voltage is applied, and a second electrode connected to a second node; a light emitting element including an anode connected to the second node and a cathode to which a low potential power supply voltage is applied to be driven according to a current from the drive element; a first switching element including a first electrode to which a data voltage is applied, a second electrode connected to the first node, and a gate electrode to which a scan pulse is applied; and a second switching element including a first electrode connected to the second node, a second electrode connected to a reference voltage, and a gate electrode to which a sensing pulse is applied.

31. A display device according to claim 30, wherein, The second switching element is turned on in the sensing mode in which the electrical characteristics of the pixel circuit are sensed.

32. The display device of claim 13, wherein, The pixel circuit includes: a drive element including a first electrode connected to a first node, a first gate electrode connected to a second node, a second electrode connected to a third node, and a second gate electrode to which a preset voltage is applied; a light emitting element including an anode connected to a fourth node and a cathode to which a low potential power supply voltage is applied to be driven according to a current from the drive element; a first switching element connected between the first node and the second node; a second switching element connected between the third node and the fourth node; a third switching element including a first electrode to which an initialization voltage is applied, a second electrode connected to a fifth node, and a gate electrode to which a second scan pulse is applied; a fourth switching element including a first electrode to which the data voltage is applied, a second electrode connected to the fifth node, and a gate electrode to which a first scan pulse is applied; a fifth switching element including a first electrode to which a pixel drive voltage is applied, a second electrode connected to the first node, and a gate electrode to which a first EM pulse is applied; a sixth switching element including a first electrode to which a reference voltage is applied, a second electrode connected to the third node, and a gate electrode to which a third scan pulse is applied; a seventh switching element including a first electrode to which the initialization voltage is applied, a second electrode connected to the fourth node, and a gate electrode to which the third scan pulse is applied; an eighth switching element including a first electrode connected to the fourth node, a second electrode to which the low potential power supply voltage is applied, and a gate electrode to which a third EM pulse is applied; a first capacitor including a first electrode connected to the fifth node and a second electrode connected to the second node; and a second capacitor including a first electrode connected to the fifth node and a second electrode connected to the third node.

33. The display device of claim 13, wherein, The pixel circuit includes: a drive element including a first electrode connected to a first node, a first gate electrode connected to a second node, a second electrode connected to a third node, and a second gate electrode to which a predetermined voltage is applied; a light emitting element including an anode connected to a fourth node and a cathode to which a low potential power supply voltage is applied to be driven by a current from the drive element; a first switching element connected between the first node and the second node; a second switching element connected between the third node and the fourth node; a third switching element including a first electrode to which an initialization voltage is applied, a second electrode connected to a fifth node, and a gate electrode to which a second scan pulse is applied; a fourth switching element including a first electrode to which a data voltage is applied, a second electrode connected to the fifth node, and a gate electrode to which a first scan pulse is applied; a fifth switching element including a first electrode to which a pixel drive voltage is applied, a second electrode connected to the first node, and a gate electrode to which a first EM pulse is applied; a sixth switching element including a first electrode to which a reference voltage is applied, a second electrode connected to the third node, and a gate electrode to which a third scan pulse is applied; a seventh switching element including a first electrode to which the initialization voltage is applied, a second electrode connected to the fourth node, and a gate electrode to which the third scan pulse is applied; an eighth switching element including a first electrode connected to the third node, a second electrode connected to a current sensing line, and a gate electrode to which a fourth scan pulse is applied; a first capacitor including a first electrode connected to the fifth node and a second electrode connected to the second node; and a second capacitor including a first electrode connected to the fifth node and a second electrode connected to the third node.

34. A display device according to either one of claims 32 and 33, wherein, The first switching element includes a first electrode connected to the first node, a second electrode connected to the second node, and a gate electrode to which the second scan pulse is applied, and The second switching element includes a first electrode connected to the third node, a second electrode connected to the fourth node, and a gate electrode to which a second EM pulse is applied.

35. A display device according to either one of claims 32 and 33, wherein, The second gate electrode of the drive element is connected to the fourth node.

36. The display device of claim 32, wherein, The second switching element, the fifth switching element, and the eighth switching element are turned on in the sensing mode in which an electrical characteristic of the pixel circuit is sensed.

37. The display device of claim 33, wherein, The fifth switching element and the eighth switching element are turned on in the sensing mode in which an electrical characteristic of the pixel circuit is sensed.

38. The display device of claim 13, wherein, All transistors in a panel including the data driver, the gate driver, and the pixel circuit are implemented using oxide thin film transistors (TFTs) including n-channel oxide semiconductors.

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